Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. 7
1Publication Order Number:
CAT5132/D
CAT5132
16 Volt Digital
Potentiometer (POT)
with 128 Taps
and I2C Interface
Description
The CAT5132 is a high voltage digital POT with non-volatile wiper
setting memory, operating like a mechanical potentiometer. The tap
points between the 127 equal resistive elements are connected to the
wiper output via CMOS switches. The switches are controlled by a
7-bit Wiper Control Register (WCR). The wiper setting can be stored
in a 7-bit non-volatile Data Register (DR). The WCR is accessed via
the I2C serial bus.
Upon power-up, the WCR is set to mid-scale (1000000). After the
power supply is stable, the contents of the DR are transferred to the
WCR and the wiper is returned to the memorized setting.
The CAT5132 has two voltage supplies: VCC, the digital supply and
V+, the analog supply. V+ can be much higher than VCC, allowing for
16 V analog operations.
The CAT5132 can be used as a potentiometer or as a two-terminal
variable resistor.
Features
Single Linear Digital Potentiometer with 128 Taps
End-to-end Resistance of 10 kW, 50 kW or 100 kW
I2C Interface
Fast Up/Down Wiper Control Mode
Non-volatile Wiper Setting Storage
Automatic Wiper Setting Recall at Power−up
Digital Supply Range (VCC): 2.7 V to 5.5 V
Analog Supply Range (V+): +8 V to +16 V
Low Standby Current: 15 mA
100 Year Wiper Setting Memory
Industrial Temperature Range: −40C to +85C
10-pin MSOP Package
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
LCD Screen Adjustment
Volume Control
Mechanical Potentiometer Replacement
Gain Adjustment
Line Impedance Matching
VCOM Setting Adjustments
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PIN CONFIGURATION
MSOP−10
Z SUFFIX
CASE 846AE
RH
RL
V+
SCL
A0
VCC
GND
SDA 1
(Top View)
RW
A1
Device Package Shipping†
ORDERING INFORMATION
CAT5132ZI−10−GT3
MSOP
(Pb−Free)
3,000 /
Tape & Reel
CAT5132ZI−50−GT3
CAT5132ZI−00−GT3
MARKING DIAGRAM
ANBU = CAT5132ZI-10-GT3
ANBK = CAT5132ZI-50-GT3
ANBP = CAT5132ZI-00-GT3
Y = Production Year (Last Digit)
M = Production Month (1-9, A, B, C)
R = Production Revision
ANBx
YMR
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications Bro-
chure, BRD8011/D.
1. For detailed information and a breakdown of
device nomenclature and numbering systems,
please see the ON Semiconductor Device No-
menclature document, TND310/D, available at
www.onsemi.com.
2. The standard lead finish is NiPdAu.
3. For additional package and temperature options,
please contact your nearest ON Semiconductor
Sales office.
CAT5132
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2
Figure 1. Block Diagram
SDA
SCL CONTROL LOGIC AND
ADDRESS DECODE
7−BIT WIPER
CONTROL
REGISTER
(WCR)
(DR)
V+
127 RESISTIVE
ELEMENTS
127
0
A0
A1
VCC
7−BIT
NONVOLATILE
MEMORY
REGISTER
128 TAP POSITION
DECODE CONTROL
RH
RL
RW
Table 1. PIN FUNCTION DESCRIPTION
Pin No. Pin Name Description
1 SDA Serial Data Input/Output − Bidirectional Serial Data pin used to transfer data into and out of the CAT5132.
This is an Open-Drain I/O and can be wire OR’d with other Open-Drain (or Open Collector) I/Os.
2 GND Ground
3 VCC Digital Supply Voltage (2.7 V to 5.5 V)
4 A1 Address Select Input to select slave address for I2C bus.
5 A0 Address Select Input to select slave address for I2C bus.
6 RHHigh Reference Terminal for the potentiometer
7 RWWiper Terminal for the potentiometer
8 RLLow Reference Terminal for the potentiometer
9 V+ Analog Supply Voltage for the potentiometer (+8.0 V to 16.0 V)
10 SCL Serial Bus Clock input for the I2C Serial Bus. This clock is used to clock all data transfers into and out of
the CAT5132
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating Value Unit
Temperature Under Bias −55 to +125 C
Storage Temperature −65 to +150 C
Voltage on any SDA, SCL, A0 & A1 pins with respect to Ground (Note 4) −0.3 to VCC + 0.3 V
Voltage on RH, RL & RW pins with respect to Ground V+
VCC with respect to Ground −0.3 to +6 V
V+ with respect to Ground −0.3 to +16.5 V
Wiper Current (10 sec) 6 mA
Lead Soldering temperature (10 sec) +300 C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. Latch-up protection is provided for stresses up to 100 mA on address and data pins from −0.3 V to VCC +0.3 V.
Table 3. RECOMMENDED OPERATING CONDITIONS
Rating Value Unit
VCC +2.7 to +5.5 V
V+ +8.0 to +16 V
Operating Temperature Range −40 to +85 C
CAT5132
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3
Table 4. POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol Parameter Test Conditions
Limits
Units
Min Typ Max
RPOT Potentiometer Resistance (100 kW)100 kW
RPOT Potentiometer Resistance (50 kW)50 kW
RPOT Potentiometer Resistance (10 kW)10 kW
RTOL Potentiometer Resistance Tolerance 20 %
Power Rating 25C 50 mW
IWWiper Current 3 mA
RWWiper Resistance IW = 1 mA @ V+ = 12 V 70 150 W
IW = 1 mA @ V+ = 8 V 110 200 W
VTERM Voltage on RW, RH or RLGND = 0 V; V+ = 8 V to 16 V GND V+ V
RES Resolution 0.78 %
ALIN Absolute Linearity (Note 6) VW(n)(actual) − VW(n)(expected) (Notes 9, 10) 1 LSB
(Note 8)
RLIN Relative Linearity (Note 7) VW(n+1) − [VW(n) + LSB] (Notes 9, 10) 0.5 LSB
(Note 8)
TCRPOT Temperature Coefficient of RPOT (Note 5) 300 ppm/C
TCRatio Ratiometric Temperature Coefficient (Note 5) 30 ppm/C
CH/CL/CWPotentiometer Capacitances (Note 5) 10/10/25 pF
fc Frequency Response RPOT = 50 kW0.4 MHz
5. This parameter is tested initially and after a design or process change that affects the parameter.
6. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
7. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.
8. LSB = (RHM − RLM)/127; where RHM and RLM are the highest and lowest measured values on the wiper terminal.
9. n = 1, 2, ..., 127
10.V+ @ RH; 0 V @ RL; VW measured @ RW with no load.
Table 5. D.C. ELECTRICAL CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol Parameter Test Conditions Min Max Units
ICC1 Power Supply Current
(Volatile Write/Read)
FSCL = 400 kHz, SDA Open,
VCC = 5.5 V, Input = GND
1 mA
ICC2 Power Supply Current
(Nonvolatile WRITE)
FSCL = 400 kHz, SDA Open,
VCC = 5.5 V, Input = GND
3.0 mA
ISB(VCC) Standby Current (VCC = 5 V) VIN = GND or VCC, SDA = VCC 5mA
ISB(V+) V+ Standby Current VCC = 5 V, V+ = 16 V 10 mA
ILI Input Leakage Current VIN = GND to VCC 10 mA
ILO Output Leakage Current VOUT = GND to VCC 10 mA
VIL Input Low Voltage −1 VCC x 0.3 V
VIH Input High Voltage VCC x 0.7 VCC + 1.0 V
VOL1 Output Low Voltage (VCC = 3.0) IOL = 3 mA 0.4 V
Table 6. CAPACITANCE (TA = 25C, f = 1.0 MHz, VCC = 5.0 V)
Symbol Parameter Test Conditions Min Max Units
CI/O Input/Output Capacitance (SDA) VI/O = 0 V (Note 11) 8 pF
CIN Input Capacitance (A0, A1, SCL) VIN = 0 V (Note 11) 6 pF
CAT5132
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Table 7. A.C. CHARACTERISTICS
Symbol Parameter (see Figure 6)
VCC = 2.7 − 5.5 V
Units
Min Max
FSCL Clock Frequency 400 kHz
TI (Note 11) Noise Suppression Time Constant at SCL & SDA Inputs 50 ns
tAA SLC Low to SDA Data Out and ACK Out 1ms
tBUF (Note 11) Time the bus must be free before a new transmission can start 1.2 ms
tHD:STA Start Condition Hold Time 0.6 ms
tLOW Clock Low Period 1.2 ms
tHIGH Clock High Period 0.6 ms
tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 0.6 ms
tHD:DAT Data in Hold Time 0 ns
tR (Note 11) SDA and SCL Rise Time 0.3 ms
tF (Note 11) SDA and SCL Fall Time 300 ns
tSU:STO Stop Conditions Setup Time 0.6 ms
tDH Data Out Hold Time 100 ns
11. This parameter is tested initially and after a design or process change that affects the parameter.
Table 8. POWER UP TIMING (Notes 12, 13)
Symbol Parameter Min Max Units
tPUR Power-up to Read Operation 1 ms
tPUW Power-up to Write Operation 1 ms
Table 9. WIPER TIMING
Symbol Parameter Min Max Units
tWRPO Wiper Response Time After Power Supply Stable 5 10 ms
tWRL Wiper Response Time After Instruction Issued 5 10 ms
Table 10. WRITE CYCLE LIMITS
Symbol Parameter Min Max Units
tWR Write Cycle Time (see Figure 7) 5 ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
Table 11. RELIABILITY CHARACTERISTICS
Symbol Parameter Reference Test Method Min Max Units
NEND (Note 12) Endurance MIL−STD−883, Test Method 1033 100,000 Cycles
TDR (Note 12) Data Retention MIL−STD−883, Test Method 1008 100 Years
12.This parameter is tested initially and after a design or process change that affects the parameter.
13.tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
CAT5132
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5
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 2. Resistance between RW and RLFigure 3. ICC2 (NV Write) vs. Temperature
TAP POSITION TEMPERATURE (C)
1129680644832160
0
2
4
6
8
10
12
11090703010−10−30−50
0
50
100
200
250
300
350
400
Figure 4. Absolute Linearity Error per Tap
Position
Figure 5. Relative Linearity Error
TAP POSITION TAP POSITION
1129680644832160
−1.0
−0.8
−0.4
−0.2
0.2
0.4
0.8
1.0
1129680644832160
−0.5
−0.4
−0.2
−0.1
0.1
0.2
0.4
0.5
RWL (KW)
ICC2 (mA)
ALIN ERROR (LSB)
ALIN ERROR (LSB)
128 50 130
150
VCC = 5.5 V
VCC = 2.7 V
128
−0.6
0
0.6
Tamb = 25C
Rtotal = 10 K
128
Tamb = 25C
Rtotal = 10 K
−0.3
0
0.3
VCC = 2.7 V; V+ = 8 V
VCC = 5.5 V; V+ = 16 V
VCC = 2.7 V; V+ = 8 V
VCC = 5.5 V; V+ = 16 V
VCC = 2.7 V; V+ = 8 V
VCC = 5.5 V; V+ = 16 V
CAT5132
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Figure 6. Bus Timing
Figure 7. Write Cycle Timing
SCL
SDA IN
SDA OUT
CONDITION
ADDRESS
ACK
SCL
SDA 8TH BIT
BYTE n
STOP
tWR
CONDITION
START
tBUF
tSU:STO
tSU:DAT
tDH
tR
tLOW
tLOW
tHIGH
tHD:DAT
tAA
tHD:STA
tF
tSU:STA
CAT5132
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7
SERIAL BUS PROTOCOL
The following defines the features of the I2C bus protocol:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock is high
will be interpreted as a START or STOP condition.
The device controlling the transfer is a master, typically a
processor or controller, and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations.
Therefore, the CAT5132 will be considered a slave device
in all applications.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT5132 monitors the SDA and
SCL lines and will not respond until this condition is met
(see Figure 8).
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition (see Figure 8).
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data (see Figure 9).
The CAT5132 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8-bit
byte.
When the CAT5132 is in a READ mode it transmits 8 bits
of data, releases the SDA line, and monitors the line for an
acknowledge. Once it receives this acknowledge, the
CAT5132 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the STOP condition is
issued to indicate the end of the write operation, the
CAT5132 initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the START
condition followed by the slave address. If the CAT5132 is
still busy with the write operation, no ACK will be returned.
If the CAT5132 has completed the write operation, an ACK
will be returned and the host can then proceed with the next
instruction operation.
Figure 8. Start/Stop Condition
SDA
SCL
START
CONDITION
STOP
CONDITION
Figure 9. Acknowledge Condition
START
SCL FROM
MASTER
ACK SETUP ( tSU:DAT)
BUS RELEASE DELAY (RECEIVER)
98
ACK DELAY ( tAA)
1
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
BUS RELEASE DELAY (TRANSMITTER)
CAT5132
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DEVICE DESCRIPTION
Access Control Register
The volatile register WCR and the non-volatile register
DR are accessed only by addressing the volatile Access
Register AR first, using the 3 byte I2C protocol for all read
and write operations (see Table 12). The first byte is the slave
address/instruction byte (see details below). The second
byte contains the address (02h) of the AR register. The data
in the third byte controls which register WCR (80h) or DR
(00h) is being addressed (see Figure 10).
Slave Address Instruction Byte Description
The first byte sent to the CAT5132 from the master
processor is called the Slave Address Byte. The most
significant five bits of the slave address are a device type
identifier. For the CAT5132 these bits are fixed at 01010
(refer to Table 13).
The next two bits, A1 and A0, are the internal slave
address and must match the physical device address which
is defined by the state of the A1 and A0 input pins. Only the
device with slave address matching the input byte will be
accessed by the master. This allows up to 4 devices to reside
on the same bus. The A1 and A0 inputs can be actively
driven by CMOS input signals or tied to VCC or Ground.
The last bit is the READ/WRITE bit and determines the
function to be performed. If it is a “1” a read command is
initiated and if it is a “0” a write is initiated. For the AR
register only write is allowed.
After the Master sends a START condition and the slave
address byte, the CAT5132 monitors the bus and responds
with an acknowledge when its address matches the
transmitted slave address.
Table 12. ACCESS CONTROL REGISTER
000000ST 11A00000010A ASP00000000
000000ST 11A00000010A ASP10000000
ACK
STOP
ACK
ACK
START
ID4
ID3
ID2
ID1
ID0
A1
A0
Wb
1st byte 2nd byte
AR address − 02h
3rd byte
WCR(80h) / DR(00h) selection
Table 13. BYTE 1 SLAVE ADDRESS AND INSTRUCTION BYTE
Device Type Identifier Slave Address
ID4
(MSB)
0
ID3
1
ID2
0
ID1
1
ID0
0
A1
X
A0
XX
R/W
Read/Write
(LSB)
Figure 10. Access Register Addressing Using 3 Bytes
& INSTRUCTION
S
C
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
R
TFIXED
VARIABLE
AR REGISTER
ADDRESS
K
A
C
K
A
C
K
A
T
O
S
T
A
ADDRESS
SLAVE
WCR/DR
SELECTION
CAT5132
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Wiper Control Register (WCR) Description
The CAT5132 contains a 7-bit Wiper Control Register
which is decoded to select one of the 128 switches along its
resistor array. The WCR is a volatile register and is written
with the contents of the nonvolatile Data Register (DR) on
power-up. The Wiper Control Register loses its contents
when the CAT5132 is powered-down. The contents of the
WCR may be read or changed directly by the host using a
READ/WRITE command after addressing the WCR (see
Table 12 to access WCR). Since the CAT5132 will only
make use of the 7 LSB bits (The first data bit, or MSB, is
ignored) on write instructions and will always come back as
a “0” on read commands.
A write operation (see Table 14) requires a Start condition,
followed by a valid slave address byte, a valid address byte
00h, a data byte and a STOP condition. After each of the
three bytes the CAT5132 responds with an acknowledge. At
this time the data is written only to volatile registers, then the
device enters its standby state.
Table 14. WCR WRITE OPERATION
000000ST 11A00000010A ASP10000000
ACK
STOP
ACK
ACK
START
ID4
ID3
ID2
ID1
ID0
A1
A0
Wb
1st byte 2nd byte
AR address − 02h
3rd byte
WCR(80h) selection
000000ST 11A00000000A ASPxxxxxxxx
ACK
STOP
ACK
ACK
START
slave address byte WCR address − 00h data byte
An increment operation (see Table 15) requires a Start
condition, followed by a valid increment address byte
(01011), a valid address byte 00h. After each of the two
bytes, the CAT5132 responds with an acknowledge. At this
time if the data is high then the wiper is incremented or if the
data is low the wiper is decremented at each clock. Once the
stop is issued then the device enters its standby state with the
WCR data as being the last inc/dec position. Also, the wiper
position does not roll over but is limited to min and max
positions.
Table 15. WCR INCREMENT/DECREMENT OPERATION
000000ST 11A00000010A ASP10000000
ACK
STOP
ACK
ACK
START
ID4
ID3
ID2
ID1
ID0
A1
A0
Wb
1st byte 2nd byte
AR address − 02h
3rd byte
WCR(80h) selection
001000ST 11A00000000A SP11110000
STOP
ACK
ACK
START
slave address byte WCR address − 00h increment (1) / decrement (0) bits
A read operation (see Table 16) requires a Start condition,
followed by a valid slave address byte for write, a valid
address byte 00h, a second START and a second slave
address byte for read. After each of the three bytes, the
CAT5132 responds with an acknowledge and then the
device transmits the data byte. The master terminates the
read operation by issuing a STOP condition following the
last bit of Data byte.
Table 16. WCR READ OPERATION
000000ST 11A00000010A ASP10000000
ACK
STOP
ACK
ACK
START
ID4
ID3
ID2
ID1
ID0
A1
A0
Wb
1st byte 2nd byte
AR address − 02h
3rd byte
WCR(80h) selection
000000ST 11A00000000
ACK
START
slave address byte WCR address − 00h
000001ST 11A0XXXXXXXSP
STOP
START
slave address byte data byte
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Data Register (DR)
The Data Register (DR) is a nonvolatile register and its
contents are automatically written to the Wiper Control
Register (WCR) on power-up. It can be read at any time
without effecting the value of the WCR. The DR, like the
WCR, only stores the 7 LSB bits and will report the MSB bit
as a “0”. Writing to the DR is performed in the same fashion
as the WCR except that a time delay of up to 5 ms is
experienced while the nonvolatile store operation is being
performed. During the internal non-volatile write cycle, the
device ignores transitions at the SDA and SCL pins, and the
SDA output is at a high impedance state. The WCR is also
written during a write to DR. After a DR WRITE is complete
the DR and WCR will contain the same wiper position.
To write or read to the DR, first the access to DR is
selected, see table 1 then the data is written or read using the
following sequences.
A write operation (see Table 17) requires a Start condition,
followed by a valid slave address byte, a valid address byte
00h, a data byte and a STOP condition. After each of the
three bytes the CAT5132 responds with an acknowledge. At
this time the data is written both to volatile and non-volatile
registers, then the device enters its standby state.
Table 17. DR WRITE OPERATION
000000ST 11A00000010A ASP00000000
ACK
STOP
ACK
ACK
START
ID4
ID3
ID2
ID1
ID0
A1
A0
Wb
1st byte 2nd byte
AR address − 02h
3rd byte
DR(00h) selection
000000ST 11A00000000A ASPXXXX X XXX
ACK
STOP
ACK
ACK
START
slave address byte DR address − 00h data byte
A read operation (see Table 18) requires a Start condition,
followed by a valid slave address byte, a valid address byte
00h, a second Start and a second slave address byte for read.
After each of the three bytes the CAT5132 responds with an
acknowledge and then the device transmits the data byte.
The master terminates the read operation by issuing a STOP
condition following the last bit of Data byte.
Table 18. DR READ OPERATION
000000ST 11A00000010A ASP00000000
ACK
STOP
ACK
ACK
START
ID4
ID3
ID2
ID1
ID0
A1
A0
Wb
1st byte 2nd byte
AR address − 02h
3rd byte
DR(00h) selection
000000ST 11A00000000
ACK
START
slave address byte DR address − 00h
000001ST 11A0XXXXXXXSP
STOP
START
slave address byte data byte
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11
POTENTIOMETER OPERATION
Power-On
The CAT5132 is a 128-position, digital controlled
potentiometer. When applying power to the CAT5132, VCC
must be supplied prior to or simultaneously with V+. At the
same time, the signals on RH, RW and RL terminals should
not exceed V+. If V+ is applied before VCC, the electronic
switches are powered in the absence of the switch control
signals, that could result in multiple switches being turned
on. This causes unexpected wiper settings and possible
current overload of the potentiometer. When VCC is applied
the device turns on at the mid-point wiper location (64) until
the wiper register can be loaded with the nonvolatile
memory location previously stored in the device. After the
nonvolatile memory data is loaded into the wiper register the
wiper location will change to the previously stored wiper
position.
At power-down, it is recommended to turn-off first the
signals on RH, RW and RL, followed by V+ and, after that,
VCC, in order to avoid unexpected transmissions of the
wiper and uncontrolled current overload of the
potentiometer.
The end-to-end nominal resistance of the potentiometer
has 128 contact points linearly distributed across the total
resistor. Each of these contact points is addressed by the 7 bit
wiper register which is decoded to select one of these 128
contact points.
Each contact point generates a linear resistive value
between the 0 position and the 127 position. These values
can be determined by dividing the end-to-end value of the
potentiometer by 127. In the case of the 10 kW potentiometer
~79 W is the resistance between each wiper position.
However in addition to the ~79 W for each resistive segment
of the potentiometer, a wiper resistance offset must be
considered. Table 19 shows the effect of this value and how
it would appear on the wiper terminal.
This offset will appear in each of the CAT5132 end-to-end
resistance values in the same way as the 10 kW example.
However resistance between each wiper position for the
50 kW version will be ~395 W and for the 100 kW version
will be ~790 W.
Table 19. POTENTIOMETER RESISTANCE AND
WIPER RESISTANCE OFFSET EFFECTS
Position Typical RW to RL Resistance for 10 kW
Digital POT
00 70 W or 0 W + 70 W
01 149 W or 79 W + 70 W
63 5,047 W or 4,977 W + 70 W
127 10,070 W or 10,000 W + 70 W
Position Typical RW to RH Resistance for 10 kW
Digital POT
00 10,070 W or 10,000 W + 70 W
64 5,047 W or 4,977 W + 70 W
126 149 W or 79 W + 70 W
127 70 W or 0 W + 70 W
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12
PACKAGE DIMENSIONS
MSOP 10, 3x3
CASE 846AE
ISSUE O
E1E
A2
A1 e b
D
c
A
TOP VIEW
SIDE VIEW
END VIEW
L1
L2
L
DETAIL A
DETAIL A
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
q
SYMBOL MIN NOM MAX
θ
A
A1
A2
b
c
D
E
E1
e
L
0º 8º
L2
0.00
0.75
0.17
0.13
0.40
2.90
4.75
2.90
0.50 BSC
0.25 BSC
1.10
0.15
0.95
0.27
0.23
0.80
3.10
5.05
3.10
0.60
3.00
4.90
3.00
L1 0.95 REF
0.05
0.85
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