LOW SKEW, 1-TO-4 LVCMOS/LVTTL
F ANOUT BUFFER ICS8304I
IDT™ / ICS™ L VCMOS/LVTTL F ANOUT BUFFER 1 ICS8304AMI REV. D OCTOBER 29, 2010
GENERAL DESCRIPTION
The ICS8304I is a low skew, 1-to-4 Fanout Buffer. The
ICS8304I is characterized at full 3.3V for input VDD, and
mixed 3.3V and 2.5V for output operating supply modes
(VDDO). Guaranteed output and part-to-part skew character-
istics make the ICS8304I ideal for those clock distribution
applications demanding well defined performance and re-
peatability.
FEATURES
•Four LVCMOS / LVTTL outputs
•LVCMOS clock input
•CLK can accept the following input levels: LVCMOS, LVTTL
•Maximum output frequency: 166MHz
•Output skew: 60ps (maximum)
•Part-to-part skew: 650ps (maximum)
•Small 8 lead SOIC package saves board space
•3.3V input, outputs may be either 3.3V or 2.5V supply modes
•-40°C to 85°C ambient operating temperature
•Available in both standard (RoHS 5) and lead-free (RoHS 6)
compliant packages
BLOCK DIAGRAM PIN ASSIGNMENT
ICS8304I
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
VDDO
VDD
CLK
GND
1
2
3
4
Q3
Q2
Q1
Q0
8
7
6
5
Q0
Q1
Q2
Q3
CLK Pulldown
IDT™ / ICS™ L VCMOS/LVTTL F ANOUT BUFFER 2 ICS8304AMI REV. D OCTOBER 29, 2010
ICS8304I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
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C
NI
ecnaticapaCtupnI 4Fp
C
DP
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)tuptuorep( V
DD
V,
ODD
V564.3=51Fp
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
R
TUO
ecnadepmItuptuO 7 Ω
rebmuNemaNepyTnoitpircseD
1V
ODD
rewoP.V5.2roV3.3ottcennoC.nipylppustuptuO
2V
DD
rewoP.V3.3ottcennoC.nipylppusevitisoP
3KLCtupnInwodlluP.tupnikcolcLTTVL/SOMCVL
4DNGrewoP.dnuorgottcennoC.dnuorg
ylppusrewoP
50QtuptuO .slevelecafretniLTTVL/SOMCVL.tuptuokcolcelgniS
61QtuptuO .slevelecafretniLTTVL/SOMCVL.t
uptuokcolcelgniS
72QtuptuO .slevelecafretniLTTVL/SOMCVL.tuptuokcolcelgniS
83QtuptuO .slevelecafretniLTTVL/SOM
CVL.tuptuokcolcelgniS
:ETON
nwodlluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
IDT™ / ICS™ L VCMOS/LVTTL F ANOUT BUFFER 3 ICS8304AMI REV. D OCTOBER 29, 2010
ICS8304I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSrewoP531.33.3564.3V
V
ODD
egatloVylppuSrewoPtuptuO531.33.3564.3V
I
DD
tnerruCylppuSrewoP 81Am
I
ODD
tnerruCylppuStuptuO 11Am
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI2V
DD
3.0+V
V
LI
egatloVwoLtupnI3.0-3.1V
I
HI
tnerruChgiHtupnIV
DD
V=
NI
V564.3=051Aµ
I
LI
tnerruCwoLtupnIV
DD
V,V564.3=
NI
V0=5-Aµ
V
HO
egatloVhgiHtuptuO
1ETONotrefeR6.2V
I
HO
Am61-=9.2V
I
HO
Au001-=3 V
V
LO
egatloVwoLtuptuO
1ETONotrefeR5.0V
I
LO
Am61=52.0V
I
LO
Au001=51.0V
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ODD
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5 V
Outputs, V
O-0.5V to VDDO + 0.5V
Package Thermal Impedance, θ
JA 112.7°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSevitisoP 531.33.3564.3V
V
ODD
egatloVylppuStuptuO 573.25.2526.2V
I
DD
tnerruCylppuSrewoP 81Am
I
ODD
tnerruCylppuStuptuO 11Am
IDT™ / ICS™ L VCMOS/LVTTL F ANOUT BUFFER 4 ICS8304AMI REV. D OCTOBER 29, 2010
ICS8304I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C
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f
XAM
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HL
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VmorfderusaeM:1ETON
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Vta
ODD
.2/
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI2V
DD
3.0+V
V
LI
egatloVwoLtupnI3.0-3.1V
I
HI
tnerruChgiHtupnIV
DD
V=
NI
V564.3=051Aµ
I
LI
tnerruCwoLtupnIV
DD
V,V564.3=
NI
V0=5-Aµ
V
HO
1ETON;egatloVhgiHtuptuO1.2V
V
LO
1ETON;egatloVwoLtuptuO 5.0V
05htiwdetanimretstuptuO:1ETON ΩVot
ODD
,noitceStnemerusaeMretemaraPeeS.2/
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IDT™ / ICS™ L VCMOS/LVTTL F ANOUT BUFFER 5 ICS8304AMI REV. D OCTOBER 29, 2010
ICS8304I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuO 661zHM
pt
HL
1ETON;hgiH-ot-woL,yaleDnoitagaporPIJzHM6613.27.3sn
t
)o(ks4,2ETON;wekStuptuOzHM331=ƒ06sp
t
)pp(ks4,3ETON;wekStraP-ot-traP 056sp
t
R
emiTesiRtuptuO%07ot%03052005sp
t
F
emiTllaFtuptuO%07ot%03052005sp
cdoelcyCytuDtuptuO 0406%
dehsilbatsesihcihw,egnarerutarepmetgnitarepotneibmadeif
icepsehtrevodeetnaraugerasretemaraplacirtcelE:ETON
teemlliwecivedehT.mpfl005nahtretaergwolfriaesrevsna
rtdeniatniamhtiwtekcostsetanidetnuomsiecivedehtnehw
.snoitidnocesehtrednudehcaerneebsahmuirbiliuqelamr
ehtretfasnoitacificeps
.esiwrehtodetonsselnuzHM661taderusaemsretemarapllA
VmorfderusaeM:1ETON
DD
Vottupniehtfo2/
ODD
.tuptuoehtfo2/
.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON
Vtade
rusaeM
ODD
.2/
segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
derusaemerastup
tuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna
Vta
ODD
.2/
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
IDT™ / ICS™ L VCMOS/LVTTL F ANOUT BUFFER 6 ICS8304AMI REV. D OCTOBER 29, 2010
ICS8304I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a
dBc
value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
Additive Phase Jitter @
125MHz (12kHz to 20MHz) = 0.17ps typical
IDT™ / ICS™ L VCMOS/LVTTL F ANOUT BUFFER 7 ICS8304AMI REV. D OCTOBER 29, 2010
ICS8304I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
LVCMOS
GND
1.65V±5%
SCOPE
Qx
LVCMOSGND
2.05V±5%
-1.25V±5%
OUTPUT SKEW
OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
30%
70% 70%
30%
tRtF
tsk(o)
V
DD
2
V
DD
2
Qx
Qy
tsk(pp)
V
DD
2
V
DD
2
Qx
Qy
PART 1
PART 2
Q0:Q3
t
PD
V
DD
2
V
DDO
2
PROPAGATION DELAY
tPERIOD
tPW
tPERIOD
odc =
V
DDO
2
x 100%
tPW
Q0:Q3
CLK
VDD,
VDDO
-1.65V±5%
VDD
VDDO
1.25V±5%
PART-TO-PART SKEW
Q0:Q3
IDT™ / ICS™ L VCMOS/LVTTL F ANOUT BUFFER 8 ICS8304AMI REV. D OCTOBER 29, 2010
ICS8304I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
TRANSISTOR COUNT
The transistor count for ICS8304I is: 416
TABLE 5. θJAVS. AIR FLOW TABLE
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
RELIABILITY INFORMATION
TABLE 6. PACKAGE DIMENSIONS - SUFFIX M
Reference Document: JEDEC Publication 95, MS-012
PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC
LOBMYS sretemilliM
NUMINIMMUMIXAM
N8
A53.157.1
1A01.052.0
B33.015.0
C91.052.0
D08.400.5
E08.300.4
eCISAB72.1
H08.502.6
h52.005.0
L04.07
2.1
α°0°8
PACKAGE OUTLINE AND DIMENSIONS
IDT™ / ICS™ L VCMOS/LVTTL F ANOUT BUFFER 9 ICS8304AMI REV. D OCTOBER 29, 2010
ICS8304I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
TABLE 7. ORDERING INFORMATION
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IDT™ / ICS™ L VCMOS/LVTTL F ANOUT BUFFER 10 ICS8304AMI REV. D OCTOBER 29, 2010
ICS8304I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
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ICS8304I
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
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Corporate Headquarters
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800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
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