ICS8304I LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8304I is a low skew, 1-to-4 Fanout Buffer. The ICS8304I is characterized at full 3.3V for input VDD, and mixed 3.3V and 2.5V for output operating supply modes (VDDO). Guaranteed output and par t-to-par t skew characteristics make the ICS8304I ideal for those clock distribution applications demanding well defined performance and repeatability. * Four LVCMOS / LVTTL outputs * LVCMOS clock input * CLK can accept the following input levels: LVCMOS, LVTTL * Maximum output frequency: 166MHz * Output skew: 60ps (maximum) * Part-to-part skew: 650ps (maximum) * Small 8 lead SOIC package saves board space * 3.3V input, outputs may be either 3.3V or 2.5V supply modes * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) compliant packages BLOCK DIAGRAM PIN ASSIGNMENT Q0 VDDO VDD CLK GND Q1 CLK Pulldown Q2 8 7 6 5 Q3 Q2 Q1 Q0 ICS8304I 8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View Q3 IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER 1 2 3 4 1 ICS8304AMI REV. D OCTOBER 29, 2010 ICS8304I LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VDDO Power Type Description Output supply pin. Connect to 3.3V or 2.5V. 2 VDD Power 3 CLK Input 4 GN D Power Power supply ground. Connect to ground. Positive supply pin. Connect to 3.3V. Pulldown LVCMOS / LVTTL clock input. 5 Q0 Output Single clock output. LVCMOS / LVTTL interface levels. 6 Q1 Output Single clock output. LVCMOS / LVTTL interface levels. 7 Q2 Output Single clock output. LVCMOS / LVTTL interface levels. 8 Q3 Output Single clock output. LVCMOS / LVTTL interface levels. NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN RPULLDOWN Input Capacitance Power Dissipation Capacitance (per output) Input Pulldown Resistor ROUT Output Impedance CPD IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER Test Conditions Minimum Typical VDD, VDDO = 3.465V 2 Maximum Units 4 pF 15 pF 51 k 7 ICS8304AMI REV. D OCTOBER 29, 2010 ICS8304I LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, JA 112.7C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40C TO 85C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Power Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 18 mA IDDO Output Supply Current 11 mA Maximum Units TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C Symbol Parameter Test Conditions Minimum Typical VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 18 mA IDDO Output Supply Current 11 mA TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40C TO 85C Symbol Parameter VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 1.3 V IIH Input High Current VDD = VIN = 3.465V 150 A IIL Input Low Current VDD = 3.465V, VIN = 0V -5 A Refer to NOTE 1 2.6 V IOH = -16mA 2.9 V IOH = -100uA 3 VOH VOL Output High Voltage Output Low Voltage Test Conditions Minimum Typical Maximum Units V Refer to NOTE 1 0.5 V IOL = 16mA 0.25 V IOL = 100uA 0.15 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Section, "3.3V Output Load Test Circuit". IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER 3 ICS8304AMI REV. D OCTOBER 29, 2010 ICS8304I LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C Symbol Parameter VIH Input High Voltage Test Conditions Minimum Typical 2 VIL Input Low Voltage IIH Input High Current VDD = VIN = 3.465V -0.3 IIL Input Low Current VDD = 3.465V, VIN = 0V VOH Output High Voltage; NOTE 1 Maximum Units VDD + 0.3 V 1.3 V 150 A -5 A 2.1 V Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Section, "3.3V/2.5V Output Load Test Circuit". 0.5 V TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40C TO 85C Symbol Parameter fMAX tpLH tjit Output Frequency Propagation Delay, Low-to-High; NOTE 1 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Test Conditions 166MHz Minimum 2 125MHz, Integration Range 12kHz - 20MHz = 133MHz tsk(o) Output Skew; NOTE 2, 4 tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 tR Output Rise Time 30% to 70% tF Output Fall Time 30% to 70% Typical Maximum Units 166 MHz 3.3 ns 0.17 ps 50 ps 600 ps 250 500 ps 25 0 500 ps odc Output Duty Cycle 40 60 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at 166MHz unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER 4 ICS8304AMI REV. D OCTOBER 29, 2010 ICS8304I LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C Symbol Parameter Test Conditions Minimum 2.3 Typical Maximum Units 166 MHz 3. 7 ns 60 ps fMAX Output Frequency tpLH Propagation Delay, Low-to-High; NOTE 1 166MHz tsk(o) Output Skew; NOTE 2, 4 = 133MHz tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 650 ps tR Output Rise Time 30% to 70% 250 500 ps tF Output Fall Time 30% to 70% 25 0 500 ps odc Output Duty Cycle 40 60 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at 166MHz unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER 5 ICS8304AMI REV. D OCTOBER 29, 2010 ICS8304I LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER ADDITIVE PHASE JITTER band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz Additive Phase Jitter @ 125MHz (12kHz to 20MHz) = 0.17ps typical As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. 6 ICS8304AMI REV. D OCTOBER 29, 2010 ICS8304I LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2.05V5% 1.65V5% 1.25V5% SCOPE VDD, VDDO SCOPE VDD VDDO Qx LVCMOS Qx GND LVCMOS GND -1.65V5% -1.25V5% 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V OUTPUT LOAD AC TEST CIRCUIT PART 1 V DD Qx Qx 2 PART 2 V DD 2 V DD DD Qy V Qy 2 tsk(o) OUTPUT SKEW 2 tsk(pp) PART-TO-PART SKEW V DDO 2 Q0:Q3 70% 70% t PW t PERIOD 30% 30% Q0:Q3 tR tF odc = t PW x 100% t PERIOD OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD VDD 2 CLK VDDO 2 Q0:Q3 t PD PROPAGATION DELAY IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER 7 ICS8304AMI REV. D OCTOBER 29, 2010 ICS8304I LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER RELIABILITY INFORMATION TABLE 5. JAVS. AIR FLOW TABLE JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 200 153.3C/W 112.7C/W 500 128.5C/W 103.3C/W 115.5C/W 97.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8304I is: 416 PACKAGE OUTLINE PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC AND DIMENSIONS TABLE 6. PACKAGE DIMENSIONS - SUFFIX M SYMBOL Millimeters MINIMUN N MAXIMUM 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BASIC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0 8 Reference Document: JEDEC Publication 95, MS-012 IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER 8 ICS8304AMI REV. D OCTOBER 29, 2010 ICS8304I LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package 8304AMI 8304AMI 8 lead SOIC 8304AMIT 8304AMI 8 lead SOIC 8304AMILF 8304AMIL 8 lead "Lead Free" SOIC 8304AMILFT 8304AMIL 8 lead "Lead Free" SOIC Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER 9 ICS8304AMI REV. D OCTOBER 29, 2010 ICS8304I LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER REVISION HISTORY SHEET Rev Table Page B 3B 3 B T7 1 8 T4A C T7 D T1 T2 4 6 9 1 2 2 Description of Change Date LVCMOS/LVTTL DC Characteristics Table, added IOH and IOL Test Conditions to VOH and VOL rows. Features Section - added lead-free bullet. Ordering Information Table - added lead-free par t number, marking and note. Updated datasheet format. 3.3V AC Characteristics Table - added Buffer Additive Phase Jitter spec. Added Buffer Additive Phase Jitter Plot. Ordering Information - Deleted "ICS" from the Par t/Order number column. Pin Assignment - corrected "pullup" label to "pulldown" label. Pin Description Table - deleted pullup from note. Pin Characteristics Table - deleted Rpullup row. IDT TM / ICSTM LVCMOS/LVTTL FANOUT BUFFER 10 4/4/02 11/09/06 2/11/09 10/29/10 ICS8304AMI REV. D OCTOBER 29, 2010 ICS8304I LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support Corporate Headquarters 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT netcom@idt.com +480-763-2056 Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) (c) 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. 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