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This circuit, connected to the collectors of Q8 and Q9, uses
a differentiating network (R4, C1) to discriminate between
the normally relatively slow fall time of the voltage pulse on
the DUT, and the exceedingly fast fall time when the device
fails. Thus, the R4-C1 time constant (5 ns) will only generate
a negative going trigger to PNP transistor Q12 when the DUT
voltage collapses during device failure. The positive going
output from Q12 resets the flip-flop (gates 4A and 4B), which
turns on the NPN transistor Q14. This transistor supplies
drive to the two PNP clamp transistors (Q5 and Q7) placed
respectively across the emitter-bases of the high, constant
current stages Q6 and Q8 and Q9. Propagation delay is thus
minimized, providing greater protection to the power stages
of the tester. As an added safety feature, the positive going
output from Gate 3C when Short Detector #1 is activated is
also used to trigger the flip-flop.
On the few occasions when the DUT fails open, then the
Open Detector consisting of comparator U5B and SCR Q17
comes into play. This circuit measures the DUT integrity
during the sense time. For a good DUT (VF < −1 V), U5B
output remains low (see Figures 4L and 4M). However for
an open DUT, VF switches to the negative rail and U5B goes
high, turning on Q17. As in the Short Detector, Q2 clamps
off the IZ power amplifier.
All of the circuitry including the +15 V and −15 V
regulated power supplies are self-contained, with the
exception of the V+ supply. For high current, narrow pulse
width testing, this external supply should have 10 to 15 A
capability. If not, additional energy storing capacitors across
the supply output may be required.
CIRCUIT OPERATION FOR THE
EXPONENTIAL SURGE CURRENT TESTER
To generate the surge current curve of peak current versus
exponential discharge pulse width, the test circuit of
Figure 5 was designed. This tester is an implementation of
the simplified capacitor discharge circuit shown in
Figure 1A, with the PNP high voltage transistor Q2
allowing the capacitor C to charge through limiting resistor
R1 and a triggered SCR discharging the capacitor. As shown
in Figure 5, the DUTs can be of any technology, although the
device connected to the capacitor and discharge limiting
resistor RS is shown as an MOS SCR. It could just as well
have been an SCR as the DUT or as the switch for the zener
diode, rectifier, SIDAC, etc., DUTs.
System timing for this Exponential Surge Current Tester
is derived from a CMOS quad 2 input NOR gate with gates
1A and 1B comprising a non-symmetrical astable MV of
about 13 seconds on and about one second off (switch S3
open). The positive On pulse from gate 1B turns on the 500
V power MOSFET Q1 and the following PNP transistor Q2.
The extremely high current gain FET allows for the large
base current variation of Q2 with varying supply voltage
(V+). This capacitor charging circuit has a 400 V blocking
capability (limited by the VCEO of Q2) and thus the capacitor
C1 used should be comparably rated. When operating with
high voltage (V+ = 200 to 350 V) and large capacitors
(>3000 μF), the power dissipated in the current limiting
resistor R1 can be substantial, thus necessitating the
illustrated 20 W rating. For longer charging times, switch S3
is closed, doubling the timing capacitor and the astable MV
on time.
To discharge capacitor C1 and thereby generate the
exponential surge current, the SCR must be fired. This
trigger is generated by the positive going one second pulse
from gate 1A being integrated by the R2C2 network, and
then shaped by gates 1C and 1D. The net result of about 100
μs time delay from gate 1D ensures noncoincident timing
conditions. This pulse output is then differentiated by C3-R3
with the positive going leading edge turning on Q3, Q4 and
finally the SCR with about a 4 ms wide, 15 mA gate pulse.
Consequently, the DUT is subjected to a surge current pulse
whose magnitude is dictated by the voltage on the capacitor
C1 and value of resistor RS, and also whose pulse width to
the 10% point is 2.3 RSC1. For a fixed pulse width, the DUT
is then stressed with increasing charge (by increasing V+)
until failure occurs, usually a shorted device.
If the DUT is the SCR (or MOS SCR), the failed condition
is obvious as the capacitor C1 will not be allowed to charge
for subsequent timing cycles. However, when the DUT is the
zener, rectifier, SIDAC or even an MOV, and the SCR is an
adequately rated switch, the circuit will still discharge
through the shorted DUT, but now the SCR alone will be
stressed by the surge current. A shorted DUT can be detected
by noting the voltage across the device during testing.
One problem encountered when stressing SCRs with high
voltage is when the DUT fails short. The limiting resistor
R1, which is only rated for 20 W, would now experience
continuous power dissipation for the full On time − as much
as 123 W ([350 V]2/1K). To prevent this occurrence, the PR1
Short Protection Circuit is incorporated. Since this is only a
problem when high V+’s (>100 V) are used, the circuit can
be switched in or out by means of switch S2. When
activated, this circuit monitors the voltage on capacitor C1
some time after the charging cycle begins. If the capacitor is
charging, normal operation occurs. However, if the SCR
DUT is shorted, the absence of voltage on the capacitor is
detected and the system is disabled.
The circuit consists of one CMOS IC with NAND gates
2A and 2B comprising a one second monostable time delay
MV and gates 2C and 2D forming a comparator and NAND
gate, respectively.
The negative going, trailing edge of gate 2A is
differentiated by R4-C4, and amplified by Q5 to form a
positive, 10 ms wide pulse (delayed by 1 sec) to gate 2D
input. If the capacitor C1 is shorted, gate 2C output is high,
allowing the now negative pulse from gate 2D to turn on
PNP transistor Q6 and SCR Q7. This latches the input to the
astable MV gate 1A low, disabling the timing and
consequently removing the power from R1. Resetting the
tester for a new device is accomplished by depressing the
pushbutton switch S1.