FemtoClock(R) NG Octal Universal Frequency Translator 8T49N287 DATA SHEET General Description Features The 8T49N287 has two independent, fractional-feedback PLLs that can be used as jitter attenuators and frequency translators. It is equipped with six integer and two fractional output dividers, allowing the generation of up to 8 different output frequencies, ranging from 8kHz to 1GHz. Four of these frequencies are completely independent of each other and the inputs. The other four are related frequencies. The eight outputs may select among LVPECL, LVDS, HCSL or LVCMOS output levels. * Supports SDH/SONET and Synchronous Ethernet clocks including all FEC rate conversions * * * * <0.3ps RMS Typical jitter (including spurs), 12kHz to 20MHz The 8T49N287 accepts up to two differential or single-ended input clocks and a crystal input. Each of the two internal PLLs can lock to different input clocks which may be of independent frequencies. Each PLL can use the other input for redundant backup of the primary clock, but in this case, both input clocks must be related in frequency. Operates from a 10MHz to 40MHz fundamental-mode crystal Applications Output frequencies ranging from 8kHz to 250MHz (LVCMOS) Four General Purpose I/O pins with optional support for status & control: * Four Output Enable control inputs may be mapped to any of the eight outputs * Lock, Holdover & Loss-of-Signal status outputs Open-drain Interrupt pin Nine programmable loop bandwidth settings for each PLL from 1.4Hz to 360Hz. Optional Fast Lock function Programmable output phase delays in steps as small as 16ps * * -40C to 85C ambient operating temperature The device supports Output Enable inputs and Lock, Holdover and LOS status outputs. The device is programmable through an I2C interface. It also supports I2C master capability to allow the register configuration to be read from an external EEPROM. Output frequencies ranging from 8kHz up to 1.0GHz (diff) * * * * Each output supports individual phase delay settings to allow output-output alignment. * * * * Generates 8 LVPECL / LVDS / HCSL or 16 LVCMOS output clocks * Each PLL has a register-selectable loop bandwidth from 1.4Hz to 360Hz. Clock input monitoring, including support for gapped clocks * * * * The device places no constraints on input to output frequency conversion, supporting all FEC rates, including the new revision of ITU-T Recommendation G.709 (2009), most with 0ppm conversion error. Auto and manual input clock selection with hitless switching Phase-Slope Limiting and Fully Hitless Switching options to control output phase transients * The 8T49N287 supports holdover for each PLL. The holdover has an initial accuracy of 50ppB from the point where the loss of all applicable input reference(s) has been detected. It maintains a historical average operating point for each PLL that may be returned to in holdover at a limited phase slope. Accepts frequencies ranging from 8kHz up to 875MHz * * * The device supports hitless reference switching between input clocks. The device monitors all input clocks for Loss of Signal (LOS), and generates an alarm when an input clock failure is detected. Automatic and manual hitless reference switching options are supported. LOS behavior can be set to support gapped or un-gapped clocks. * * Accepts up to two LVPECL, LVDS, LVHSTL, HCSL or LVCMOS input clocks * * * This makes it ideal to be used in any frequency translation application, including 1G, 10G, 40G and 100G Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T G.709 (2009) FEC rates. The device may also behave as a frequency synthesizer. * Operating modes: locked to input signal, holdover and free-run Initial holdover accuracy of 50ppb Register programmable through I2C or via external I2C EEPROM Bypass clock paths for system tests Power supply modes VCC / VCCA / VCCO 3.3V / 3.3V / 3.3V 3.3V / 3.3V / 2.5V 3.3V / 3.3V / 1.8V (LVCMOS) 2.5V / 2.5V / 3.3V 2.5V / 2.5V / 2.5V 2.5V / 2.5V / 1.8V (LVCMOS) Package: 56QFN, lead-free (RoHS 6) OTN or SONET / SDH equipment Line cards (up to OC-192, and supporting FEC ratios) OTN de-mapping (Gapped Clock and DCO mode) Gigabit and Terabit IP switches / routers including support of Synchronous Ethernet SyncE (G.8262) applications Wireless base station baseband Data communications 100G Ethernet 8T49N287 REVISION 5 07/09/15 1 (c)2015 Integrated Device Technology, Inc. 8T49N287 DATA SHEET 8T49N287 Block Diagram XTAL Fractional Feedback APLL 0 OSC CLK0 / P0 CLK1 / P1 Input Clock Monitoring, Priority, & Selection Lock 0 Holdover 0 Fractional Feedback APLL 1 Lock 1 Holdover 1 nRST Reset Logic I2C Master SCLK SDATA LOS OTP Status Registers Q0 IntN Output Divider Q1 FracN Output Divider Q2 FracN Output Divider Q3 GPIO Logic Control Registers IntN Q4 IntN Q5 IntN Q6 IntN Q7 4 I2C Slave Serial EEPROM IntN Output Divider SA0 GPIO nINT PLL_BYP Figure 1. 8T49N287 Functional Block Diagram FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 2 REVISION 5 07/09/15 8T49N287 DATA SHEET GPIO[3] nQ7 Q7 VCCO7 nQ6 Q6 VCCO6 nQ5 Q5 VCCO5 nQ4 Q4 VCCO4 GPIO[2] Pin Assignment nQ1 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Q1 44 27 Q2 VCCO1 45 26 VCCO2 nRST 46 25 GPIO[0] nQ0 47 24 nQ3 Q0 48 23 Q3 VCCO0 49 22 VCCO3 nINT 50 21 GPIO[1] VCCA 51 20 VCCA CAP0_REF 52 19 CAP1_REF CAP0 53 18 CAP1 PLL_BYP 54 17 VCC VCCA 55 16 VCCA VCCA 56 15 VCCA 6 7 8 9 VCCA OSCI OSCO S_A0 VEE CLK0 nCLK0 CLK1 10 11 12 13 14 VCCA 5 SCLK 4 SDATA 3 VCC 2 nCLK1 1 VCCA 8T49N287 nQ2 56-pin, 8mm x 8mm VFQFN Package Figure 2. Pinout Drawing REVISION 5 07/09/15 3 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 3 OSCI I Crystal Input. Accepts a 10MHz-40MHz reference from a clock oscillator or a 12pF fundamental mode, parallel-resonant crystal. 4 OSCO O Crystal Output. This pin should be connected to a crystal. If an oscillator is connected to OSCI, then this pin must be left unconnected. 5 S_A0 I Pulldown 12 SDATA I/O Pullup I2C interface bi-directional Data. 13 SCLK I/O Pullup I2C interface bi-directional Clock. 7 CLK0 I Pulldown Non-inverting differential clock input. Inverting differential clock input. VCC/2 when left floating (set by the internal pullup and pulldown resistors.) I2C lower address bit A0. 8 nCLK0 I Pullup / Pulldown 9 CLK1 I Pulldown Non-inverting differential clock input. Inverting differential clock input. VCC/2 when left floating (set by the internal pullup and pulldown resistors.) 10 nCLK1 I Pullup / Pulldown 48, 47 Q0, nQ0 O Universal Output Clock 0. Please refer to the Output Drivers section for more details. 44, 43 Q1, nQ1 O Universal Output Clock 1. Please refer to the Output Drivers section for more details. 27, 28 Q2, nQ2 O Universal Output Clock 2. Please refer to the Output Drivers section for more details. 23, 24 Q3, nQ3 O Universal Output Clock 3. Please refer to the Output Drivers section for more details. 40, 39 Q4, nQ4 O Universal Output Clock 4. Please refer to the Output Drivers section for more details. 37, 36 Q5, nQ5 O Universal Output Clock 5. Please refer to the Output Drivers section for more details. 34, 33 Q6, nQ6 O Universal Output Clock 6. Please refer to the Output Drivers section for more details. 31, 30 Q7, nQ7 O Universal Output Clock 7. Please refer to the Output Drivers section for more details. 46 nRST I Pullup 50 nINT O 29, 42, 21, 25 GPIO[3:0] I/O Pullup 54 PLL_BYP I Pulldown 6, ePad VEE Power Negative supply voltage. All VEE pins and EPAD must be connected before any positive supply voltage is applied. 11 VCC Power Core and digital functions supply voltage. 17 VCC Power Core and digital functions supply voltage. 2 VCCA Power Analog functions supply voltage for core analog functions. 14, 15, 16, 20 VCCA Power Analog functions supply voltage for analog functions associated with PLL1. 1, 51, 55, 56 VCCA Power Analog functions supply voltage for analog functions associated with PLL0. 49 VCCO0 Power High-speed output supply voltage for output pair Q0, nQ0. 45 VCCO1 Power High-speed output supply voltage for output pair Q1, nQ1. 26 VCCO2 Power High-speed output supply voltage for output pair Q2, nQ2. 22 VCCO3 Power High-speed output supply voltage for output pair Q3, nQ3. Master Reset input. LVTTL / LVCMOS interface levels: 0 = All registers and state machines are reset to their default values 1 = Device runs normally Open-drain with pullup Interrupt output. General-purpose input-outputs. LVTTL / LVCMOS Input levels Open-drain output. Pulled-up with 5.1k resistor to VCC. Bypass Selection. Allow input references to bypass both PLLs. LVTTL / LVCMOS interface levels. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 4 REVISION 5 07/09/15 8T49N287 DATA SHEET Number Name Type Description 41 VCCO4 Power High-speed output supply voltage for output pair Q4, nQ4. 38 VCCO5 Power High-speed output supply voltage for output pair Q5, nQ5. 35 VCCO6 Power High-speed output supply voltage for output pair Q6, nQ6. 32 VCCO7 Power High-speed output supply voltage for output pair Q7, nQ7. 53 52 CAP0, CAP0_REF Analog PLL0 External Capacitance. 18 19 CAP1, CAP1_REF Analog PLL1 External Capacitance. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics, VCC = VCCOX = 3.3V5% or 2.5V5% Symbol Parameter Test Conditions CIN Input Capacitance; NOTE 1 Minimum Typical Maximum Units 3.5 pF nRST, SDATA, SCLK 51 k nINT 50 k RPULLUP Internal Pullup Resistor GPIO[3:0] 5.1 k RPULLDOWN Internal Pulldown Resistor 51 k CPD ROUT Power Dissipation Capacitance (per output pair) Output Impedance LVCMOS; Q[0:1], Q[4:7] VCCOX = 3.465V 14.5 pF LVCMOS Q[2:3] VCCOX = 3.465V 18.5 pF LVCMOS; Q[0:1], Q[4:7] VCCOX = 2.625V 13 pF LVCMOS; Q[2:3] VCCOX = 2.625V 17.5 pF LVCMOS; Q[0:1], Q[4:7] VCCOX = 1.89V 12.5 pF LVCMOS; Q[2:3] VCCOX = 1.89V 17 pF LVDS, HCSL or LVPECL; Q[0:1], Q[4:7] VCCOx = 3.465V or 2.625V 2 pF LVDS, HCSL or LVPECL; Q[2:3] VCCOx = 3.465V or 2.625V 4.5 pF Output HIGH 5.1 k Output LOW 25 20 GPIO [3:0] LVCMOS; Q[0:7], nQ[0:7] NOTE: VCCOX denotes: VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE 1: This specification does not apply to OSCI and OSCO pins. REVISION 5 07/09/15 5 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Principles of Operation Crystal Input The 8T49N287 has two PLLs that can each independently be locked to any of the input clocks and generate a wide range of synchronized output clocks. The crystal input on the 8T49N287 is capable of being driven by a parallel-resonant, fundamental mode crystal with a frequency range of 10MHz - 40MHz. It incorporates two completely independent PLLs. These could be used for example in the transmit and receive path of Synchronous Ethernet equipment. Either of the input clocks can be selected as the reference for either PLL. From the output of the two PLLs a wide range of output frequencies can be simultaneously generated. The oscillator input also supports being driven by a single-ended crystal oscillator or reference clock. The initial holdover frequency offset is set by the device, but the long term drift depends on the quality of the crystal or oscillator attached to this port. The 8T49N287 accepts up to two differential input clocks ranging from 8kHz up to 875MHz. It generates up to eight output clocks ranging from 8kHz up to 1.0GHz. Bypass Path Each PLL path within the 8T49N287 supports three states: Lock, Holdover and Free-run. Lock & holdover status may be monitored on register bits and pins. Each PLL also supports automatic and manual hitless reference switching. In the locked state, the PLL locks to a valid clock input and its output clocks have a frequency accuracy equal to the frequency accuracy of the input clock. In the Holdover state, the PLL will output a clock which is based on the selected holdover behavior. Each of the PLL paths within the 8T49N287 has an initial holdover frequency offset of 50ppb. In the Free-run state, the PLL outputs a clock with the same frequency accuracy as the external crystal. For system test purposes, each of PLL0 and PLL1 may be bypassed. When PLL_BYP is asserted the CLK0 input reference will be presented directly on the Q4 output. The CLK1 input reference will be presented directly on the Q5 output. Additionally, CLK0 or CLK1 may be used as a clock source for the output dividers of Q[4:7]. This may only be done for input frequencies of 250MHz or less. Input Clock Selection The 8T49N287 accepts up to two input clocks with frequencies ranging from 8kHz up to 875MHz. Each input can accept LVPECL, LVDS, LVHSTL, HCSL or LVCMOS inputs using 1.8V, 2.5V or 3.3V logic levels. To use LVCMOS inputs, refer to the Application Note, Wiring the Differential Input to Accept Single-Ended Levels for biasing instructions. Upon power up, each PLL will enter Free-run state, in this state it generates output clocks with the same frequency accuracy as the external crystal. The 8T49N287 continuously monitors each input for activity (signal transitions). In automatic reference switching, when an input clock has been validated the PLL will transition to the locked state. If the selected input clock fails and there are no other valid input clocks, the PLL will quickly detect that and go into holdover. In the Holdover state, the PLL will output a clock which is based on the selected holdover behavior. If the selected input clock fails and another input clock is available then the 8T49N287 will hitlessly switch to that input clock. The reference switch can be either revertive or non-revertive. The device has independent input clock selection control for each PLL. In Manual mode, only one of these inputs may be chosen per PLL and if that input fails that PLL will enter holdover. Manual mode may be operated by directly selecting the desired input reference in the REFSEL register field. It may also operate via pin-selection of the desired input clock by selecting that mode in the REFSEL register field. In that case, GPIOs must be used as Clock Select inputs (CSELn). CSEL0 = 0 will select the CLK0 input and CSEL0 = 1 will select the CLK1 input for PLL0. CSEL1 will perform the same function for PLL1. The device supports conversion of any input frequency to four different, independent output frequencies on the Q[0:3]outputs. Additionally, a further four output frequencies may be generated that are integer-related to the four independent frequencies. These additional four frequencies are on the Q[4:7] outputs. In addition, the crystal frequency may be passed directly to the output dividers for Q[4:7] for use as a reference. The 8T49N287 has a programmable loop bandwidth from 1.4Hz to 360Hz. Inputs do not support transmission of spread-spectrum clocking sources. Since this family is intended for high-performance applications, it will assume input reference sources to have stabilities of +100ppm or better, except where gapped clock inputs are used. The device monitors all input clocks and generates an alarm when an input clock failure is detected. The device supports programmable individual output phase adjustments in order to allow control of input to output phase adjustments and output to output phase alignment. If the PLL is working in automatic mode, then each of the input reference sources is assigned a priority of 1-2. At power-up or if the currently selected input reference fails, the PLL will switch to the highest priority input reference that is valid at that time (see section Input Clock Monitor for details). The device is programmable through an I2C and may also autonomously read its register settings from an internal One-Time Programmable (OTP) memory or an external serial I2C EEPROM. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 6 REVISION 5 07/09/15 8T49N287 DATA SHEET Automatic mode has two sub-options: revertive or non-revertive. In revertive mode, the PLL will switch to a reference with a higher priority setting whenever one becomes valid. In non-revertive mode the PLL remains with the currently selected source as long as it remains valid. clock edges on that input reference. If another error condition on the same input clock is detected during the validation time then the alarm remains asserted and the validation time starts over. Each LOS flag may also be reflected on one of the GPIO[3:0] outputs. Changes in status of any reference can also generate an interrupt if not masked. The clock input selection is based on the input clock priority set by the Clock Input Priority control registers. It is recommended that all input references for a PLL be given different priority settings in the Clock Input Priority control registers for that PLL. Holdover 8T49N287 supports a small initial holdover frequency offset for each PLL path in non-gapped clock mode. When the input clock monitor is set to support gapped clock operation, this initial holdover frequency offset is indeterminate since the desired behavior with gapped clocks is for the PLL to continue to adjust itself even if clock edges are missing. In gapped clock mode, the PLL will not enter holdover until the input is missing for two LOS monitor periods. Input Clock Monitor Each clock input is monitored for Loss of Signal (LOS). If no activity has been detected on the clock input within a user-selectable time period then the clock input is considered to be failed and an internal Loss-of-Signal status flag is set, which may cause an input switchover depending on other settings. The user-selectable time period has sufficient range to allow a gapped clock missing many consecutive edges to be considered a valid input. The holdover performance characteristics of a clock are referred as its accuracy and stability, and are characterized in terms of the fractional frequency offset. The 8T49N287 can only control the initial frequency accuracy. Longer-term accuracy and stability are determined by the accuracy and stability of the external oscillator. User-selection of the clock monitor time-period is based on a counter driven by a monitor clock. The monitor clock is fixed at the frequency of PLL0's VCO divided by 8. With a VCO range of 3GHz - 4GHz, the monitor clock has a frequency range of 375MHz to 500MHz. When a PLL loses all valid input references, it will enter the holdover state. In non-gapped clock mode, the PLL will initially maintain its most recent frequency offset setting and then transition at a rate dictated by its selected phase-slope limit setting to a frequency offset setting that is based on historical settings. The monitor logic for each input reference will count the number of monitor clock edges indicated in the appropriate Monitor Control register. If an edge is received on the input reference being monitored, then the count resets and begins again. If the target edge count is reached before an input reference edge is received, then an internal soft alarm is raised and the count re-starts. During the soft alarm period, the PLL(s) tracking this input will not be adjusted. If an input reference edge is received before the count expires for the second time, then the soft alarm status is cleared and the PLL(s) will resume adjustments. If the count expires again without any input reference edge being received, then a Loss-of-Signal alarm is declared. This behavior is intended to compensate for any frequency drift that may have occurred on the input reference before it was detected to be lost. The historical holdover value will have three options: It is expected that for normal (non-gapped) clock operation, users will set the monitor clock count for each input reference to be slightly longer than the nominal period of that input reference. A margin of 2-3 monitor clock periods should give a reasonably quick reaction time and yet prevent false alarms. For gapped clock operation, the user will set the monitor clock count to a few monitor clock periods longer than the longest expected clock gap period. The monitor count registers support 17-bit count values, which will support at least a gap length of two clock periods for any supported input reference frequency, with longer gaps being supported for faster input reference frequencies. Since gapped clocks usually occur on input reference frequencies above 100MHz, gap lengths of thousands of periods can be supported. Return to center of tuning range within the VCO band. * Instantaneous mode - the holdover frequency will use the DPLL current frequency 100msec before it entered holdover. The accuracy is shown in the AC Electrical Characteristics, Table 11A. * Fast average mode - an internal IIR (Infinite Impulse Response) filter is employed to get the frequency offset. The IIR filter gives a 3 dB attenuation point corresponding to a nominal period of 20 minutes. The accuracy is shown in the AC Electrical Characteristics, Table 11A. When entering holdover, each PLL will set a separate internal HOLD alarm internally. This alarm may be read from internal status register, appear on the appropriate GPIO pin and/or assert the nINT output. While a PLL is in holdover, its frequency offset is now relative to the crystal input and so the output clocks derived from that PLL will be tracing their accuracy to the local oscillator or crystal. At some point in time, depending on the stability & accuracy of that source, the clock(s) derived from that PLL will have drifted outside of the limits of the holdover state and the system will be considered to be in a free-run state. Since this borderline is defined outside the PLL and dictated by the accuracy and stability of the external local crystal or oscillator, the 8T49N287 cannot know or influence when that transition occurs. As a result, the 8T49N287 will remain in the holdover state internally. Using this configuration for a gapped clock, the PLL will continue to adjust while the normally expected gap is present, but will freeze once the expected gap length has been exceeded and alarm after twice the normal gap length has passed. Once a LOS on any of the input clocks is detected, the appropriate internal LOS alarm will be asserted and it will remain asserted until that input clock returns and will be validated by the receipt of 8 rising REVISION 5 07/09/15 * 7 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Input to Output Clock Frequency Table 3. Q[0:1], Q[4:7] Output Divide Ratios The 8T49N287 is designed to accept any frequency in its input range and generate eight different output frequencies that are independent from each other and from the input frequencies. The internal architecture of the device ensures that most such translations will result in the exact output frequency specified. Where exact frequency translation is not possible, the frequency translation error will be minimized.Please contact IDT for configuration software or other assistance in determining if a desired configuration will be supported exactly. 1st-Stage Divide 2nd-Stage Divide Total Divide Minimum FOUT MHz Maximum FOUT MHz 4 1 4 750 1000 5 1 5 600 800 6 1 6 500 666.7 4 2 8 375 500 5 2 10 300 400 Synthesizer Mode Operation 6 2 12 250 333.3 The device may also act as a frequency synthesizer with either or both PLL's generating their operating frequency from just the crystal input. By setting the SYN_MODEn register bit and setting the STATEn[1:0] field to Freerun, no input clock references are required to generate the desired output frequencies. 4 4 16 187.5 250 5 4 20 150 200 6 4 24 125 166.7 ... 4 131,070 524,280 0.0057 0.0076 Loop Filter and Bandwidth 5 131,070 655,350 0.0046 0.0061 When operating in Synthesizer Mode as described above, the 8T49N287 has a fixed loop bandwidth of approximately 200kHz. When operating in all other modes, the following information applies: 6 131,070 786,420 0.0038 0.0051 NOTE: Above frequency ranges for Q[4:7] apply when driven directly from PLL0 or PLL1. The 8T49N287 uses no external components to support a range of loop bandwidths: 1.40625Hz, 2.8125Hz, 5.625Hz, 11.25Hz, 22.5Hz, 45Hz, 90Hz, 180Hz or 360Hz. Each PLL shall support separate loop filter settings. Fractional Output Divider Programming (Q[2:3] only) For the FracN output dividers Q[2:3], the output divide ratio is given by: The device supports two different loop bandwidth settings for each PLL: acquisition and locked. These loop bandwidths are selected from the list of options described above. If enabled, the acquisition bandwidth is used while lock is being acquired to allow the PLL to "fast-lock". Once locked the PLL will use the locked bandwidth setting. If the acquisition bandwidth setting is not used, the PLL will use the locked bandwidth setting at all times. Output Divide Ratio = (N.F)x2 N = Integer Part: 4, 5, ...(218-1) F = Fractional Part: [0, 1, 2, ...(228-1)]/(228) For integer operation of these outputs dividers, N = 3 is also supported. Output Divider Frequency Sources Output Dividers and Mapping to PLLs Output dividers associated with the Q[0:3] outputs can take their input frequencies from either PLL0 or PLL1. The 8T49N287 will support eight output dividers that may be mapped to either PLL. Six of the output dividers will have IntN capability only (see Table 3) and the other two will support FracN division. Output dividers associated with the Q[4:7] outputs can take their input frequencies from PLL0, PLL1, Q2 or Q3 output dividers, CLK0 or CLK1 input frequencies or the crystal frequency. Integer Output Divider Programming (Q[0:1], Q[4:7] only) Each integer output divider block consists of two divider stages in a series to achieve the desired total output divider ratio. The first stage divider may be set to divide by 4, 5 or 6. The second stage of the divider may be bypassed (i.e. divide-by-1) or programmed to any even divider ratio from 2 to 131,070. The total divide ratios, settings and possible output frequencies are shown in Table 3. Output Banks Outputs of the 8T49N287 are divided into three banks for purposes of output skew measurement: * Q0, nQ0, Q1, nQ1 In addition, the first divider stage for the Q[4:7] outputs supports a bypass (i.e. divide-by-1) operation for some clock sources. * Q4, nQ4, Q5, nQ5 * Q6, nQ6, Q7, nQ7 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8 REVISION 5 07/09/15 8T49N287 DATA SHEET Output Phase Control on Switchover 3) For integer dividers where the 1st-stage divider is bypassed (only Q[4:7] support this), coarse delay adjustments can't be performed. The output phase will be one step earlier than in Case 2. When the 8T49N287 switches between input references, enters or leaves the holdover state for either PLL, there are two options on how the output phase can be controlled in these events: phase-slope limiting or fully hitless switching (sometimes called phase build-out) may be selected. The SWMODEn bit selects which behavior is to be followed for PLLn. 4) Fractional output dividers (Q2 or Q3) do not guarantee any specific phase on power-up or after a synchronization event. 5) Integer dividers using Q2 or Q3 as a source (Q[4:7] support this option) will be aligned to their source divider's output (Q2 or Q3). Note that the output skews described above are not included in any of the phase adjustments described here. If fully hitless switching is selected, then the output phase will remain unchanged under any of these conditions. Note that fully hitless switching is not supported when external loopback is being used. Fully hitless switching should not be used unless all input references are in the same clock domain. Note that use of this mode may prevent an output frequency and phase from being able to trace its alignment back to a primary reference source. Once the device is in operation, the outputs associated with each PLL may have their phase adjustments re-synced in one of two ways: 1) If the PLL becomes unlocked, the coarse phase adjustments will be reset and the fine phase adjustments will be re-loaded once it becomes locked again. If phase-slope limiting is selected, then the output phase will adjust from its previous value until it is tracking the new condition at a rate dictated by the SLEWn[1:0] bits. Phase-slope limiting should be used if all input references are not in the same clock domain or users wish to retain traceability to a primary reference source. 2) Toggling of a register bit for either PLL (PLLn_SYN bits in register 00A8h) may also be used to force a re-sync / re-load for outputs associated with that PLL. The user may apply adjustments that are proportional to the period of the clock source each output divider is operating from. For example, if the divider associated with Output Q3 is running off PLL0, which has a VCO frequency of 4GHz, then the appropriate period would be 250ps. The output phase may be adjusted in these steps across the full period of the output. Input-Output Delay Control When using the 8T49N285 in external loopback or in a situation where input-output delay needs to be known and controlled, it is necessary to examine the exact signal path through the device. Due to the flexibility of the device, there are a large number of potential signal paths from input to output through it that depend on the desired configuration. Each of those potential paths may include or exclude logic blocks from the path and change the absolute value of the delay (Static Phase Offset or SPO) through the device. Considering the range of SPO values to cover all those potential paths would not be useful in achieving the target delays for any specific user configuration. Please contact IDT for the specific SPO value associated with a desired input-output path. Note that events such as switchovers, entering or leaving holdover or re-configuring the signal path can result in one-time changes to the SPO due to that path re-configuration. The AC Electrical Characteristics, (Table 11A) indicates the maximum variation in SPO that could be expected for a particular path through the device. Output Phase Alignment The device has a programmable output to output phase alignment for each of the eight output dividers. After power-up and the PLLs have achieved lock, the device will be in a state where the outputs are synchronized with a deterministic offset relative to each other.After synchronization, the output alignment will depend on the particular configuration of each output according to the following rules. The step size is defined as the period of the clock to that divider: Coarse Adjustment: all Output Dividers may have their phase adjusted in steps of the source clock period. For example a 4GHz VCO gives a step size of 250ps. The user may request an adjustment of phase of up to 31 steps using a single register write. The phase will be adjusted by lengthening the period of the output by 250ps at a time. This process will be repeated every four output clock periods until the full requested adjustment has been achieved. A busy signal will remain asserted in the phase delay register until the requested adjustment is complete. Then a further adjustment may be setup and triggered by toggling the trigger bit. * Fine Adjustment: For the Fractional Output Dividers associated with the Q2 and Q3 outputs, the phase of those outputs may be further adjusted with a granularity of 1/16th of the VCO period. For example a 4GHz VCO frequency gives a granularity of 16ps. This is performed by directly writing the required offset (from the nominal rising edge position) in units of 1/16th of the output period into a register. Then the appropriate PLLn_SYN bit must be toggled to load the new value. Note that toggling this bit will clear all Coarse Delays for all outputs associated with that PLL, so Fine Delays should be set first, before Coarse Delays. The output will then jump directly to that new offset value. For this reason, this adjustment should be made as the input is initially programmed or in High-Impedance. Each output has the capability of being inverted (180 phase shift). 1) Only outputs derived from the same source will be aligned with each other. 'Source' means the reference selected to drive the output divider as controlled by the CLK_SELn bit for each output. Jitter and Wander Tolerance The 8T49N287 can be used as a line card device and therefore is expected to tolerate the jitter and wander output of a timing card PLL (e.g 82P33714). 2) For integer dividers (Q[0:1], Q[4:7]) when both divider stages are active, edges are aligned. This case is used as a baseline to compare the other cases here. REVISION 5 07/09/15 * 9 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Output Drivers Table 4. GPIO Configuration Configured as Input The Q0 to Q7 clock outputs are provided with register-controlled output drivers. By selecting the output drive type in the appropriate register, any of these outputs can support LVCMOS, LVPECL, HCSL or LVDS logic levels. Configured as Output Fixed Function The operating voltage ranges of each output is determined by its independent output power pin (VCCO) and thus each can have different output voltage levels. Output voltage levels of 2.5V or 3.3V are supported for differential operation and LVCMOS operation. In addition, LVCMOS output operation supports 1.8V VCCO. Fixed Function GPIO Pin Output Enable (default) Output Enable Clock Select General Purpose 3 OE[3] OE[7] CSEL1 GPI[3] 2 OE[2] OE[6] CSEL0 GPI[2] 1 OE[1] OE[5] - GPI[1] 0 OE[0] OE[4] - GPI[0] LOL[0] General Purpose - - GPO[3] LOS[0] LOS[1] GPO[2] HOLD[0] HOLD[1] GPO[1] LOL[1] GPO[0] If used in the Fixed Function mode of operation, the GPIO bits will reflect the real-time status of their respective status bits as shown in Table 4. Note that the LOL signal represents the lock status of the PLL. It does not account for the process of synchronization of the output dividers associated with that PLL. The output dividers programmed to operate from that PLL will automatically go through a re-synchronization process when the PLL locks or re-locks, or if the user triggers a re-sync manually via register bit PLLn_SYN. This synchronization process may result in a period of instability on the affected outputs for a duration of up to 350ns after the re-lock (LOL de-asserts) or the PLLn_SYN bit is de-asserted. Each output may be enabled or disabled by register bits and/or GPIO pins configured as Output Enables. The outputs will be enabled if the register bit and the associated OE pin are both asserted (high). When disabled an output will be in a high impedance state. LVCMOS Operation When a given output is configured to provide LVCMOS levels, then both the Q and nQ outputs will toggle at the selected output frequency. All the previously described configuration and control apply equally to both outputs. Frequency, phase alignment, voltage levels and enable / disable status apply to both the Q and nQ pins. When configured as LVCMOS, the Q and nQ outputs can be selected to be phase-aligned with each other or inverted relative to one another. Phase-aligned outputs will have increased simultaneous switching currents which can negatively affect phase noise performance and power consumption. It is recommended that use of this selection be kept to a minimum. Interrupt Functionality Interrupt functionality includes an interrupt status flag for each of PLL Loss-of-Lock Status (LOL[1:0]), PLL Holdover Status (HOLD[1:0]) and Input Reference Status (LOS[1:0]) that is set whenever there is an alarm on any of those signals. The Status Flag will remain set until the alarm has been cleared and a `1' has been written to the Status Flag's register location or if a reset occurs. Each Status Flag will also have an Interrupt Enable bit that will determine if that Status Flag is allowed to cause the Interrupt Status to be affected (enabled) or not (disabled). All Interrupt Enable bits will be in the disabled state after reset. The Device Interrupt Status flag and nINT output pin are asserted if any of the enabled Interrupt Status flags are set. Power-Saving Modes To allow the device to consume the least power possible for a given application, the following functions are included under register control: * PLL1 may be shut down. * Any unused output, including all output divider and phase adjustment logic, can be individually powered-off. Device Hardware Configuration * Clock gating on logic that is not being used. The 8T49N287 supports an internal One-Time Programmable (OTP) memory that can be pre-programmed at the factory with 1 complete device configuration. If the device is set to read a configuration from an external, serial EEPROM, then the values read will overwrite the OTP-defined values. Status / Control Signals and Interrupts General-Purpose I/Os & Interrupts This configuration can be over-written using the serial interface once reset is complete. Any configuration written via the programming interface needs to be re-written after any power cycle or reset. Please contact IDT if a specific factory-programmed configuration is desired. The 8T49N287 provides 4 General Purpose Input / Output (GPIO) pins for miscellaneous status & control functions. Each GPIO may be configured as an input or an output. Each GPIO may be directly controlled from register bits or be used as a predefined function as shown in Table 4. Note that the default state prior to configuration being loaded from internal OTP or external EEPROM will be to set each GPIO to function as an Output Enable. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 10 REVISION 5 07/09/15 8T49N287 DATA SHEET Device Start-up & Reset Behavior Serial Control Port Description The 8T49N287 has an internal power-up reset (POR) circuit and a Master Reset input pin nRST. If either is asserted, the device will be in the Reset State. Serial Control Port Configuration Description The device has a serial control port capable of responding as a slave in an I2C compatible configuration, to allow access any of the internal registers for device programming or examination of internal status. All registers are configured to have default values. See the specifics for each register for details. For highly programmable devices, it's common practice to reset the device immediately after the initial power-on sequence. IDT recommends connecting the nRST input pin to a programmable logic source for optimal functionality. It is recommended that a minimum pulse width of 10ns be used to drive the nRST input pin. The device has the additional capability of becoming a master on the I2C bus only for the purpose of reading its initial register configurations from a serial EEPROM on the I2C bus. Writing of the configuration to the serial EEPROM must be performed by another device on the same I2C bus or pre-programmed into the device prior to assembly. While in the reset state (nRST input asserted or POR active), the device will operate as follows: * All registers will return to & be held in their default states as indicated in the applicable register description. * All internal state machines will be in their reset conditions. I2C Mode Operation * The serial interface will not respond to read or write cycles. The I2C interface is designed to fully support v1.2 of the I2C Specification for Normal and Fast mode operation. The device acts as a slave device on the I2C bus at 100kHz or 400kHz using the address defined in the Status Interface Control register (0006h), as modified by the S_A0 input pin setting. The interface accepts byte-oriented block write and block read operations. Two address bytes specify the register address of the byte position of the first register to write or read. Data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first). Read and write block transfers can be stopped after any complete byte transfer. During a write operation, data will not be moved into the registers until the STOP bit is received, at which point, all data received in the block write will be written simultaneously. * The GPIO signals will be configured as General-Purpose inputs. * All clock outputs will be disabled. * All interrupt status and Interrupt Enable bits will be cleared, negating the nINT signal. Upon the later of the internal POR circuit expiring or the nRST input negating, the device will exit reset and begin self-configuration. The device will load an initial block of its internal registers using the configuration stored in the internal One-Time Programmable (OTP) memory. Once this step is complete, the 8T49N287 will check the register settings to see if it should load the remainder of its configuration from an external I2C EEPROM at a defined address or continue loading from OTP. See the section on I2C Boot Initialization for details on how this is performed. For full electrical I2C compliance, it is recommended to use external pull-up resistors for SDATA and SCLK. The internal pull-up resistors have a size of 51k typical. Once the full configuration has been loaded, the device will respond to accesses on the serial port and will attempt to lock both PLLs to the selected sources and begin operation. Once the PLLs are locked, all the outputs derived from a given PLL will be synchronized and output phase adjustments can then be applied if desired. Current Read S Dev Addr + R A Data 0 A Data 1 A A Data n A P Sequential Read S Dev Addr + W A Offset Addr MSB A Offset Addr LSB A A Offset Addr MSB A Offset Addr LSB A Sr Dev Addr + R A Data 0 Data 1 A A Data 1 A A Data n A P Sequential Write S Dev Addr + W from master to slave from slave to master Data 0 A A Data n A P S = start Sr = repeated start A = acknowledge A = none acknowledge P = stop Figure 3. I2C Slave Read and Write Cycle Sequencing REVISION 5 07/09/15 11 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET I2C Master Mode When operating in I2C mode, the 8T49N287 has the capability to become a bus master on the I2C bus for the purposes of reading its configuration from an external I2C EEPROM. Only a block read cycle will be supported. * Fixed-period cycle response timer to prevent permanently hanging the I2C bus. * Read will abort with an alarm (BOOTFAIL) if any of the following conditions occur: Slave NACK, Arbitration Fail, Collision during Address Phase, CRC failure, Slave Response time-out As an I2C bus master, the 8T49N287 will support the following functions: * The 8T49N287 will not support the following functions: * 7-bit addressing mode * I2C General Call * Base address register for EEPROM * Slave clock stretching * Validation of the read block via CCITT-8 CRC check against value stored in last byte (E0h) of EEPROM * I2C Start Byte protocol * EEPROM Chaining * Support for 100kHz and 400kHz operation with speed negotiation. If bit d0 is set at Byte address 05h in the EEPROM, this will shift from 100kHz operation to 400kHz operation. * CBUS compatibility * Responding to its own slave address when acting as a master * Support for 1 or 2-byte addressing mode * Writing to external I2C devices including the external EEPROM used for booting * Master arbitration with programmable number of retries Sequential Read (1byte offset address) S Dev Addr + W A Offset Addr A Sr Dev Addr + R A Offset Addr LSB A Data 0 A Sr Dev Addr + R Data 1 A A Data n A P Sequential Read (2byte offset address) S Dev Addr + W A from master to slave from slave to master Offset Addr MSB A A Data 0 A Data 1 A A Data n A P S = start Sr = repeated start A = acknowledge A = none acknowledge P = stop Figure 4. I2C Master Read Cycle Sequencing I2C Boot-up Initialization Mode If enabled (via the BOOT_EEP bit in the Startup register), once the nRST input has been deasserted (high) and its internal power-up reset sequence has completed, the device will contend for ownership of the I2C bus to read its initial register settings from a memory location on the I2C bus. The address of that memory location is kept in non-volatile memory in the Startup register. During the boot-up process, the device will not respond to serial control port accesses. Once the initialization process is complete, the contents of any of the device's registers can be altered. It is the responsibility of the user to make any desired adjustments in initial values directly in the serial bus memory. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR If a NACK is received to any of the read cycles performed by the device during the initialization process, or if the CRC does not match the one stored in address E0h of the EEPROM the process will be aborted and any uninitialized registers will remain with their default values. The BOOTFAIL bit (021Eh) in the Global Interrupt Status register will also be set in this event. If the BOOTFAIL bit is set, then both LOL[n] indicators will be set. Contents of the EEPROM should be as shown in Table 5. 12 REVISION 5 07/09/15 8T49N287 DATA SHEET Table 5. External Serial EEPROM Contents Contents EEPROM Offset (Hex) D7 D6 D5 D4 D3 D2 D1 D0 00 1 1 1 1 1 1 1 1 01 1 1 1 1 1 1 1 1 02 1 1 1 1 1 1 1 1 03 1 1 1 1 1 1 1 1 04 1 1 1 1 1 1 1 1 1 Serial EEPROM Speed Select 0 = 100kHz 1 = 400kHz 0 1 0 0 05 1 06 1 07 0 1 1 1 1 1 8T49N287 Device I2C Address [6:2] 0 0 0 0 0 08 - DF Desired contents of Device Registers 08h - DFh E0 Serial EEPROM CRC E1 - FF Unused REVISION 5 07/09/15 13 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Register Descriptions Table 6A.Register Blocks Register Ranges Offset (Hex) Register Block Description 0000 - 0001 Startup Control Registers 0002 - 0005 Device ID Control Registers 0006 - 0007 Serial Interface Control Registers 0008 - 003A Digital PLL0 Control Registers 003B - 006D Digital PLL1 Control Registers 006E - 0076 GPIO Control Registers 0077 - 00AB Output Clock Control Registers 00AC - 00AF Analog PLL0 Control Registers 00B0 - 00B3 Analog PLL1 Control Registers 00B4 - 00B8 Power-Down Control Registers 00B9 - 00C6 Input Monitor Control Registers 00C7 Interrupt Enable Register 00C8 - 00CB Digital Phase Detector Control Registers 00CC - 01FF Reserved1 0200 - 0203 Interrupt Status Registers 0204 Output Phase Adjustment Status Register 0205 - 020E Digital PLL0 Status Registers 020F - 0218 Digital PLL1 Status Registers 0219 General-Purpose Input Status Register 021A - 21F Global Interrupt and Boot Status Register 0220 - 3FF Reserved1 NOTE 1: Reserved. Always write 0 to this bit location. Read values are not defined. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 14 REVISION 5 07/09/15 8T49N287 DATA SHEET Table 6B. Startup Control Register Bit Field Locations and Descriptions Startup Control Register Block Field Locations Address (Hex) D7 D6 D5 0000 0001 D4 D3 EEP_RTY[4:0] D2 Rsvd EEP_A15 D1 D0 nBOOT_OTP nBOOT_EEP EEP_ADDR[6:0] Startup Control Register Block Field Descriptions Bit Field Name Field Type Default Value Description EEP_RTY[4:0] R/W 00001b Select number of times arbitration for the I2C bus to read the serial EEPROM will be retried before being aborted. Note that this number does not include the original try. nBOOT_OTP R/W NOTE 1 Internal One-Time Programmable (OTP) memory usage on power-up: 0 = Load power-up configuration from OTP 1 = Only load 1st eight bytes from OTP nBOOT_EEP R/W NOTE 1 External EEPROM usage on power-up: 0 = Load power-up configuration from external serial EEPROM (overwrites OTP values) 1 = Don't use external EEPROM EEP_A15 R/W NOTE 1 Serial EEPROM supports 15-bit addressing mode (multiple pages). EEP_ADDR[6:0] R/W NOTE 1 I2C base address for serial EEPROM. Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined. NOTE 1: These values are specific to the device configuration and can be customized when ordering. Refer to the FemtoClock NG Universal Frequency Translator Ordering Product Information guide for more details. Table 6C. Device ID Control Register Bit Field Locations and Descriptions Device ID Control Register Block Field Locations Address (Hex) D7 0002 D6 D5 D4 D3 D2 REV_ID[3:0] D1 D0 DEV_ID[15:12] 0003 DEV_ID[11:4] 0004 DEV_ID[3:0] 0005 DASH_CODE [10:7] DASH_CODE [6:0] 1 Device ID Control Register Block Field Descriptions Bit Field Name Field Type Default Value REV_ID[3:0] R/W 0000b Device revision. DEV_ID[15:0] R/W 605h Device ID code. DASH CODE [10:0] R/W NOTE 1 Description Device Dash Code: Decimal value assigned by IDT to identify the configuration loaded at the factory. May be over-written by users at any time. Refer to FemtoClock NG Universal Frequency Translator Ordering Product Information guide to identify major configuration parameters associated with this Dash Code value. NOTE 1: These values are specific to the device configuration and can be customized when ordering. Refer to the FemtoClock NG Universal Frequency Translator Ordering Product Information guide or custom datasheet addendum for more details. REVISION 5 07/09/15 15 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Table 6D. Serial Interface Control Register Bit Field Locations and Descriptions Serial Interface Control Block Field Locations Address (Hex) D7 0006 Rsvd D6 D5 D4 D3 D2 UFTADD[6:2] 0007 D1 D0 UFTADD[1] UFTADD[0] Rsvd 1 Serial Interface Control Register Block Field Descriptions Bit Field Name Field Type Default Value Description UFTADD[6:2] R/W NOTE 1 UFTADD[1] R/O 0b I2C Base Address bit 1. This bit is fixed at 0. UFTADD[0] R/O 0b I2C base address bit 0. This address bit reflects the status of the S_A0 external input pin. See Table 1, Pin Description. Rsvd R/W - Configurable portion of I2C Base Address (bits 6:2) for this device. Reserved. Always write 0 to this bit location. Read values are not defined. NOTE 1: These values are specific to the device configuration and can be customized when ordering. Generic dash codes -900 through -908, -998 and-999 are available and programmed with the default I2C address of 1111100b. Please refer to the FemtoClock NG Universal Frequency Translator Ordering Product Information guide for more details. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 16 REVISION 5 07/09/15 8T49N287 DATA SHEET Table 6E. Digital PLL0 Input Control Register Bit Field Locations and Descriptions Digital PLL0 Input Control Register Block Field Locations Address (Hex) D7 0008 D6 D5 D4 D3 REFSEL0[2:0] 0009 11 000A 10 1 1 000B D2 FBSEL0[1:0] REFDIS0_1 D0 SWMODE0 PRI0_1[1:0] REFDIS0_0 Rsvd Rsvd Rsvd PRI0_0[1:0] STATE0[1:0] PRE0_0[20:16] 000C PRE0_0[15:8] 000D PRE0_0[7:0] 000E D1 RVRT0 Rsvd PRE0_1[20:16] 000F PRE0_1[15:8] 0010 PRE0_1[7:0] 0011 Rsvd Rsvd 0012 Rsvd 0013 Rsvd 0014 Rsvd Rsvd 0015 Rsvd 0016 Rsvd Digital PLL0 Input Control Register Block Field Descriptions Bit Field Name REFSEL0[2:0] Field Type R/W Default Value Description 000b Input reference selection for Digital PLL0: 000 = Automatic selection 001 = Manual selection by GPIO inputs 010 through 011 = Reserved 100 = Force selection of Input Reference 0 101 = Force selection of Input Reference 1 110 = Do not use 111 = Do not use Feedback mode selection for Digital PLL0: 000 through 011 = internal feedback divider 100 = external feedback from Input Reference 0 101 = external feedback from Input Reference 1 110 = do not use 111 = do not use FBSEL0[2:0] R/W 000b RVRT0 R/W 1b Automatic switching mode for Digital PLL0: 0 = non-revertive switching 1 = revertive switching 1b Controls how Digital PLL0 adjusts output phase when switching between input references: 0 = Absorb any phase differences between old and new input references at the PLL output. Recommended for use when both input references are in the same clock domain. 1 = Limit the maximum rate of phase change at the PLL output when adjusting to a new input reference's phase/frequency using phase-slope limiting as set in the SLEWn bits. Recommended for use when the input references are not in the same clock domain. 00b Switchover priority for Input Reference 0 when used by Digital PLL0: 00 = 1st priority 01 = 2nd priority 10 = do not use 11 = do not use SWMODE0 PRI0_0[1:0] REVISION 5 07/09/15 R/W R/W 17 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Digital PLL0 Input Control Register Block Field Descriptions Bit Field Name Field Type Default Value Description PRI0_1[1:0] R/W 01b Switchover priority for Input Reference 1 when used by Digital PLL0: 00 = 1st priority 01 = 2nd priority 10 = do not use 11 = do not use REFDIS0_0 R/W 0b Input Reference 0 Switching Selection Disable for Digital PLL0: 0 = Input Reference 0 is included in the switchover sequence for Digital PLL0 1 = Input Reference 0 is not included in the switchover sequence for Digital PLL0 REFDIS0_1 R/W 0b Input Reference 1 Switching Selection Disable for Digital PLL0: 0 = Input Reference 1 is included in the switchover sequence for Digital PLL0 1 = Input Reference 1 is not included in the switchover sequence for Digital PLL0 Digital PLL0 State Machine Control: 00 = Run automatically 01 = Force FREERUN state - set this if in Synthesizer Mode for PLL0 10 = Force NORMAL state 11 = Force HOLDOVER state STATE0[1:0] R/W 00b PRE0_0[20:0] R/W 000000h Pre-divider ratio for Input Reference 0 when used by Digital PLL0. PRE0_1[20:0] R/W 000000h Pre-divider ratio for Input Reference 1 when used by Digital PLL0. Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 18 REVISION 5 07/09/15 8T49N287 DATA SHEET Table 6F. Digital PLL0 Feedback Control Register Bit Field Locations and Descriptions Digital PLL0 Feedback Control Register Block Field Locations Address (Hex) D7 D6 D5 D4 D3 0017 M1_0_0[23:16] 0018 M1_0_0[15:8] 0019 M1_0_0[7:0] 001A M1_0_1[23:16] 001B M1_0_1[15:8] 001C M1_0_1[7:0] 001D Rsvd 001E Rsvd 001F Rsvd 0020 Rsvd 0021 Rsvd 0022 Rsvd 0023 LCKBW0[3:0] 0024 LCKDAMP0[2:0] 0025 Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd 0029 Rsvd 002A Rsvd 002B FFh 002C FFh 002D FFh 002E FFh SLEW0[1:0] Rsvd HOLD0[1:0] 0030 Rsvd HOLDAVG0 FASTLCK0 LOCK0[7:0] 0031 Rsvd 0032 DSM_INT0[8] DSM_INT0[7:0] Rsvd DSMFRAC0[20:16] 0034 DSMFRAC0[15:8] 0035 DSMFRAC0[7:0] 0036 Rsvd 0037 01h 0038 Rsvd 0039 Rsvd REVISION 5 07/09/15 PLLGAIN0[1:0] Rsvd 0028 003A D0 ACQBW0[3:0] 0027 0033 D1 ACQDAMP0[2:0] 0026 002F D2 DSM_ORD0[1:0] DCXOGAIN0[1:0] 19 Rsvd DITHGAIN0[2:0] FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Digital PLL0 Feedback Configuration Register Block Field Descriptions Bit Field Name Field Type Default Value M1_0_0[23:0] R/W 070000h M1 Feedback divider ratio for Input Reference 0 when used by Digital PLL0. M1_0_1[23:0] R/W 070000h M1 Feedback divider ratio for Input Reference 1 when used by Digital PLL0. LCKBW0[3:0] ACQBW0[3:0] LCKDAMP0[2:0] ACQDAMP0[2:0] PLLGAIN0[1:0] R/W R/W R/W R/W R/W Description 0111b Digital PLL Loop Bandwidth while locked: 0000 = Reserved 0001 = Reserved 0010 = Reserved 0011 = 1.40625Hz 0100 = 2.8125Hz 0101 = 5.625Hz 0110 = 11.25Hz 0111 = 22.5Hz 1000 = 45Hz 1001 = 90Hz 1010 = 180Hz 1011 = 360Hz 1100 through 1111 = Reserved 0111b Digital PLL0 Loop Bandwidth while in acquisition (not-locked): 0000 = Reserved 0001 = Reserved 0010 = Reserved 0011 = 1.40625Hz 0100 = 2.8125Hz 0101 = 5.625Hz 0110 = 11.25Hz 0111 = 22.5Hz 1000 = 45Hz 1001 = 90Hz 1010 = 180Hz 1011 = 360Hz 1100 through 1111 = Reserved 011b Damping factor for Digital PLL0 while locked: 000 = Reserved 001 = 1 010 = 2 011 = 5 100 = 10 101 = 20 110 = Reserved 111 = Reserved 011b Damping factor for Digital PLL0 while in acquisition (not locked): 000 = Reserved 001 = 1 010 = 2 011 = 5 100 = 10 101 = 20 110 = Reserved 111 = Reserved 01b Digital Loop Filter Gain Settings for Digital PLL0: 00 = 0.5 01 = 1 10 = 1.5 11 = 2 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 20 REVISION 5 07/09/15 8T49N287 DATA SHEET Digital PLL0 Feedback Configuration Register Block Field Descriptions Bit Field Name SLEW0[1:0] Field Type R/W Default Value Description 00b Phase-slope control for Digital PLL0: 00 = no limit - controlled by loop bandwidth of Digital PLL0 (NOTE 1) 01 = 83 sec/sec 10 = 13 sec/sec 11 = Reserved HOLD0[1:0] R/W 00b Holdover Averaging mode selection for Digital PLL0: 00 = Instantaneous mode - uses historical value 100ms prior to entering holdover 01 = Fast Average Mode 10 = Reserved 11 = Set VCO control voltage to VCC/2 HOLDAVG0 R/W 0b Holdover Averaging Enable for Digital PLL0: 0 = Holdover averaging disabled 1 = Holdover averaging enabled as defined in HOLD0[1:0] Enables Fast Lock operation for Digital PLL0: 0 = Normal locking using LCKBW0 & LCKDAMP0 fields in all cases 1 = Fast Lock mode using ACQBW0 & ACQDAMP0 when not phase locked and LCKBW0 & LCKDAMP0 once phase locked FASTLCK0 R/W 0b LOCK0[7:0] R/W 3Fh Lock window size for Digital PLL0. Unsigned 2's complement binary number in steps of 2.5ns, giving a total range of 640ns. Do not program to 0. DSM_INT0[8:0] R/W 02Dh Integer portion of the Delta-Sigma Modulator value. Do not set higher than FFh. This implies that for crystal frequencies lower than 16MHz, the doubler circuit must be enabled. DSMFRAC0[20:0] R/W 000000h DSM_ORD0[1:0] DCXOGAIN0[1:0] R/W R/W Fractional portion of Delta-Sigma Modulator value. Divide this number by 221 to determine the actual fraction. 11b Delta-Sigma Modulator Order for Digital PLL0: 00 = Delta-Sigma Modulator disabled 01 = 1st order modulation 10 = 2nd order modulation 11 = 3rd order modulation 01b Multiplier applied to instantaneous frequency error before it is applied to the Digitally Controlled Oscillator in Digital PLL0: 00 = 0.5 01 = 1 10 = 2 11 = 4 Dither Gain setting for Digital PLL0: 000 = no dither 001 = Least Significant Bit (LSB) only 010 = 2 LSBs 011 = 4 LSBs 100 = 8 LSBs 101 = 16 LSBs 110 = 32 LSBs 111 = 64 LSBs DITHGAIN0[2:0] R/W 000b Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined. NOTE 1: Settings other than "00" may result in a significant increase in initial lock time. REVISION 5 07/09/15 21 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Table 6G. Digital PLL1 Input Control Register Bit Field Locations and Descriptions Digital PLL1 Input Control Register Block Field Locations Address (Hex) D7 003B 003C 003D D6 D5 D4 D3 REFSEL1[2:0] 11 10 1 1 003E D2 FBSEL1[1:0] REFDIS1_1 D0 SWMODE1 PRI1_1[1:0] REFDIS1_0 Rsvd Rsvd Rsvd PRI1_0[1:0] STATE1[1:0] PRE1_0[20:16] 003F PRE1_0[15:8] 0040 PRE1_0[7:0] 0041 D1 RVRT1 Rsvd PRE1_1[20:16] 0042 PRE1_1[15:8] 0043 PRE1_1[7:0] 0044 Rsvd Rsvd 0045 Rsvd 0046 Rsvd 0047 Rsvd Rsvd 0048 Rsvd 0049 Rsvd Digital PLL1 Input Control Register Block Field Descriptions Bit Field Name REFSEL1[2:0] Field Type R/W Default Value Description 000b Input reference selection for Digital PLL1: 000 = Automatic selection 001 = Manual selection by GPIO inputs 010 through 011 = Reserved 100 = Force selection of Input Reference 0 101 = Force selection of Input Reference 1 110 = do not use 111 = do not use Feedback mode selection for Digital PLL1: 000 through 011 = internal feedback divider 100 = external feedback from Input Reference 0 101 = external feedback from Input Reference 1 110 = do not use 111 = do not use FBSEL1[2:0] R/W 000b RVRT1 R/W 1b Automatic switching mode for Digital PLL1: 0 = non-revertive switching 1 = revertive switching 1b Controls how Digital PLL1 adjusts output phase when switching between input references: 0 = Absorb any phase differences between old and new input references at the PLL output. Recommended for use when both input references are in the same clock domain. 1 = Limit the maximum rate of phase change at the PLL output when adjusting to a new input reference's phase/frequency using phase-slope limiting as set in the SLEWn bits. Recommended for use when the input references are not in the same clock domain. 00b Switchover priority for Input Reference 0 when used by Digital PLL1: 00 = 1st priority 01 = 2nd priority 10 = do not use 11 = do not use SWMODE1 PRI1_0[1:0] R/W R/W FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 22 REVISION 5 07/09/15 8T49N287 DATA SHEET Digital PLL1 Input Control Register Block Field Descriptions Bit Field Name Field Type Default Value Description PRI1_1[1:0] R/W 01b Switchover priority for Input Reference 1 when used by Digital PLL1: 00 = 1st priority 01 = 2nd priority 10 = do not use 11 = do not use REFDIS1_0 R/W 0b Input Reference 0 Switching Selection Disable for Digital PLL1: 0 = Input Reference 0 is included in the switchover sequence for Digital PLL1 1 = Input Reference 0 is not included in the switchover sequence for Digital PLL1 REFDIS1_1 R/W 0b Input Reference 1 Switching Selection Disable for Digital PLL1: 0 = Input Reference 1 is included in the switchover sequence for Digital PLL1 1 = Input Reference 1 is not included in the switchover sequence for Digital PLL1 Digital PLL1 State Machine Control: 00 = Run automatically 01 = Force FREERUN state - set this if in Synthesizer Mode for PLL1 10 = Force NORMAL state 11 = Force HOLDOVER state STATE1[1:0] R/W 00b PRE1_0[20:0] R/W 000000h Pre-divider ratio for Input Reference 0 when used by Digital PLL1. PRE1_1[20:0] R/W 000000h Pre-divider ratio for Input Reference 1 when used by Digital PLL1. Rsvd R/W - REVISION 5 07/09/15 Reserved. Always write 0 to this bit location. Read values are not defined. 23 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Table 6H. Digital PLL1 Feedback Control Register Bit Field Locations and Descriptions Digital PLL1 Feedback Control Register Block Field Locations Address (Hex) D7 D6 D5 D4 D3 004A M1_1_0[23:16] 004B M1_1_0[15:8] 004C M1_1_0[7:0] 004D M1_1_1[23:16] 004E M1_1_1[15:8] 004F M1_1_1[7:0] 0050 Rsvd 0051 Rsvd 0052 Rsvd 0053 Rsvd 0054 Rsvd 0055 Rsvd 0056 LCKBW1[3:0] 0057 LCKDAMP1[2:0] 0058 Rsvd Rsvd PLLGAIN1[1:0] Rsvd Rsvd Rsvd Rsvd 005B Rsvd Rsvd 005C Rsvd 005D Rsvd 005E FFh 005F FFh 0060 FFh 0061 FFh SLEW1[1:0] Rsvd HOLD1[1:0] 0063 Rsvd HOLDAVG1 FASTLCK1 LOCK1[7:0] 0064 Rsvd 0065 DSM_INT1[8] DSM_INT1[7:0] Rsvd DSMFRAC1[20:16] 0067 DSMFRAC1[15:8] 0068 DSMFRAC1[7:0] 0069 Rsvd 006A 01h 006B Rsvd 006C Rsvd 006D D0 ACQBW1[3:0] 005A 0066 D1 ACQDAMP1[2:0] 0059 0062 D2 DSM_ORD1[1:0] DCXOGAIN1[1:0] FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 24 Rsvd DITHGAIN1[2:0] REVISION 5 07/09/15 8T49N287 DATA SHEET Digital PLL1 Feedback Configuration Register Block Field Descriptions Bit Field Name Field Type Default Value M1_1_0[23:0] R/W 070000h M1 Feedback divider ratio for Input Reference 0 when used by Digital PLL1. M1_1_1[23:0] R/W 070000h M1 Feedback divider ratio for Input Reference 1 when used by Digital PLL1. LCKBW1[3:0] ACQBW1[3:0] LCKDAMP1[2:0] ACQDAMP1[2:0] PLLGAIN1[1:0] REVISION 5 07/09/15 R/W R/W R/W R/W R/W Description 0111b Digital PLL1 Loop Bandwidth while locked: 0000 = Reserved 0001 = Reserved 0010 = Reserved 0011 = 1.40625Hz 0100 = 2.8125Hz 0101 = 5.625Hz 0110 = 11.25Hz 0111 = 22.5Hz 1000 = 45Hz 1001 = 90Hz 1010 = 180Hz 1011 = 360Hz 1100 through 1111 = Reserved 0111b Digital PLL1 Loop Bandwidth while in acquisition (not-locked): 0000 = Reserved 0001 = Reserved 0010 = Reserved 0011 = 1.40625Hz 0100 = 2.8125Hz 0101 = 5.625Hz 0110 = 11.25Hz 0111 = 22.5Hz 1000 = 45Hz 1001 = 90Hz 1010 = 180Hz 1011 = 360Hz 1100 through 1111 = Reserved 011b Damping factor for Digital PLL1 while locked: 000 = Reserved 001 = 1 010 = 2 011 = 5 100 = 10 101 = 20 110 = Reserved 111 = Reserved 011b Damping factor for Digital PLL1 while in acquisition (not locked): 000 = Reserved 001 = 1 010 = 2 011 = 5 100 = 10 101 = 20 110 = Reserved 111 = Reserved 01b Digital Loop Filter Gain Settings for Digital PLL1: 00 = 0.5 01 = 1 10 = 1.5 11 = 2 25 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Digital PLL1 Feedback Configuration Register Block Field Descriptions Bit Field Name SLEW1[1:0] Field Type R/W Default Value Description 00b Phase-slope control for Digital PLL1: 00 = no limit - controlled by loop bandwidth of Digital PLL0 (NOTE 1) 01 = 83 sec/sec 10 = 13 sec/sec 11 = Reserved HOLD1[1:0] R/W 00b Holdover Averaging mode selection for Digital PLL1: 00 = Instantaneous mode - uses historical value 100ms prior to entering holdover 01 = Fast Average Mode 10 = Reserved 11 = Set VCO control voltage to VCC/2 HOLDAVG1 R/W 0b Holdover Averaging Enable for Digital PLL1: 0 = Holdover averaging disabled 1 = Holdover averaging enabled as defined in HOLD1[1:0] Enables Fast Lock operation for Digital PLL1: 0 = Normal locking using LCKBW1 & LCKDAMP1 fields in all cases 1 = Fast Lock mode using ACQBW1 & ACQDAMP1 when not phase locked and LCKBW1 & LCKDAMP1 once phase locked FASTLCK1 R/W 0b LOCK1[7:0] R/W 3Fh Lock window size for Digital PLL1. Unsigned 2's complement binary number in steps of 2.5ns, giving a total range of 640ns. Do not program to 0. DSM_INT1[8:0] R/W 02Dh Integer portion of the Delta-Sigma Modulator value. Do not set higher than FFh. This implies that for crystal frequencies lower than 16MHz, the doubler circuit must be enabled. DSMFRAC1[20:0] R/W 000000h DSM_ORD1[1:0] DCXOGAIN1[1:0] R/W R/W Fractional portion of Delta-Sigma Modulator value. Divide this number by 221 to determine the actual fraction. 11b Delta-Sigma Modulator Order for Digital PLL1: 00 = Delta-Sigma Modulator disabled 01 = 1st order modulation 10 = 2nd order modulation 11 = 3rd order modulation 01b Multiplier applied to instantaneous frequency error before it is applied to the Digitally Controlled Oscillator in Digital PLL1: 00 = 0.5 01 = 1 10 = 2 11 = 4 Dither Gain setting for Digital PLL1: 000 = no dither 001 = Least Significant Bit (LSB) only 010 = 2 LSBs 011 = 4 LSBs 100 = 8 LSBs 101 = 16 LSBs 110 = 32 LSBs 111 = 64 LSBs DITHGAIN1[2:0] R/W 000b Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined. NOTE 1: Settings other than "00" may result in a significant increase in initial lock time. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 26 REVISION 5 07/09/15 8T49N287 DATA SHEET Table 6I. GPIO Control Register Bit Field Locations and Descriptions The values observed on any GPIO pins that are used as general purpose inputs are visible in the GPI[3:0] register that is located at location 0219h near a number of other read-only registers. GPIO Control Register Block Field Locations Address (Hex) D7 D6 D5 D4 D3 D2 D1 D0 006E Rsvd GPIO_DIR[3:0] 006F Rsvd GPI3SEL[2] GPI2SEL[2] GPI1SEL[2] GPI0SEL[2] 0070 Rsvd GPI3SEL[1] GPI2SEL[1] GPI1SEL[1] GPI0SEL[1] 0071 Rsvd GPI3SEL[0] GPI2SEL[0] GPI1SEL[0] GPI0SEL[0] 0072 Rsvd GPO3SEL[2] GPO2SEL[2] GPO1SEL[2] GPO0SEL[2] 0073 Rsvd GPO3SEL[1] GPO2SEL[1] GPO1SEL[1] GPO0SEL[1] 0074 Rsvd GPO3SEL[0] GPO2SEL[0] GPO1SEL[0] GPO0SEL[0] 0075 Rsvd 0076 Rsvd GPO[3:0] GPIO Control Register Block Field Descriptions Bit Field Name Field Type Default Value GPIO_DIR[3:0] R/W 00h Direction control for General-Purpose I/O Pins GPIO[3:0]: 0 = input mode 1 = output mode 000b Function of GPIO[0] pin when set to input mode by GPIO_DIR[0] register bit: 000 = General Purpose Input (value on GPIO[0] pin directly reflected in GPI[0] register bit) 001 = Output Enable control for output Q0 010 = Output Enable control for output Q4 011 = reserved 100 through 111 = reserved 000b Function of GPIO[1] pin when set to input mode by GPIO_DIR[1] register bit: 000 = General Purpose Input (value on GPIO[1] pin directly reflected in GPI[1] register bit) 001 = Output Enable control for output Q1 010 = Output Enable control for output Q5 011 through 111 = reserved 000b Function of GPIO[2] pin when set to input mode by GPIO_DIR[2] register bit: 000 = General Purpose Input (value on GPIO[2] pin directly reflected in GPI[2] register bit) 001 = Output Enable control for output Q2 010 = Output Enable control for output Q6 011 = reserved 100 = reserved 101 = CSEL0: Manual Clock Select Input for PLL0 110 through 111 = reserved 000b Function of GPIO[3] pin when set to input mode by GPIO_DIR[3] register bit: 000 = General Purpose Input (value on GPIO[3] pin directly reflected in GPI[3] register bit) 001 = Output Enable control for output Q3 010 = Output Enable control for output Q7 011 = reserved 101 = CSEL1: Manual Clock Select Input for PLL1 100, 110, 111 = reserved GPI0SEL[2:0] GPI1SEL[2:0] GPI2SEL[2:0] GPI3SEL[2:0] REVISION 5 07/09/15 R/W R/W R/W R/W Description 27 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET GPIO Control Register Block Field Descriptions Bit Field Name GPO0SEL[2:0] GPO1SEL[2:0] GPO2SEL[2:0] Field Type R/W R/W R/W Default Value Description 000b Function of GPIO[0] pin when set to output mode by GPIO_DIR[0] register bit: 000 = General Purpose Output (value in GPO[0] register bit driven on GPIO[0] pin 001 = Loss-of-Lock Status Flag for Digital PLL0 reflected on GPIO[0] pin 010 = Loss-of-Lock Status Flag for Digital PLL1 reflected on GPIO[0] pin 011 = reserved 100 = reserved 101 = reserved 110 through 111 = reserved 000b Function of GPIO[1] pin when set to output mode by GPIO_DIR[1] register bit: 000 = General Purpose Output (value in GPO[1] register bit driven on GPIO[1] pin 001 = Holdover Status Flag for Digital PLL0 reflected on GPIO[1] pin 010 = Holdover Status Flag for Digital PLL1 reflected on GPIO[1] pin 011 = reserved 100 = reserved 101 = reserved 110 = reserved 111 = reserved 000b Function of GPIO[2] pin when set to output mode by GPIO_DIR[2] register bit: 000 = General Purpose Output (value in GPO[2] register bit driven on GPIO[2] pin 001 = Loss-of-Signal Flag for Input Reference 0 reflected on GPIO[2] pin 010 = Loss-of-Signal Flag for Input Reference 1 reflected on GPIO[2] pin 011 = reserved 100 = reserved 101 through 111 = reserved GPO3SEL[2:0] R/W 000b Function of GPIO[3] pin when set to output mode by GPIO_DIR[3] register bit: 000 = General Purpose Output (value in GPO[3] register bit driven on GPIO[3] pin 001 = Loss-of-Lock Status Flag for Digital PLL1 reflected on GPIO[3] pin 010 = Loss-of-Signal Status Flag for Input Reference 1 reflected on GPIO[3] pin 011 = reserved 100 = reserved 101 through 111 = reserved GPO[3:0] R/W 00h Output Values reflect on pin GPIO[3:0] when General-Purpose Output Mode selected. Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 28 REVISION 5 07/09/15 8T49N287 DATA SHEET Table 6J. Output Driver Control Register Bit Field Locations and Descriptions Output Driver Control Register Block Field Locations Address (Hex) D7 D6 D5 D4 D3 0077 OUTEN[7:0] 0078 POL_Q[7:0] D2 D1 D0 0079 OUTMODE7[2:0] SE_MODE7 OUTMODE6[2:0] SE_MODE6 007A OUTMODE5[2:0] SE_MODE5 OUTMODE4[2:0] SE_MODE4 007B OUTMODE3[2:0] SE_MODE3 OUTMODE2[2:0] SE_MODE2 007C OUTMODE1[2:0] SE_MODE1 OUTMODE0[2:0] SE_MODE0 Output Driver Control Register Block Field Descriptions Bit Field Name Field Type Default Value OUTEN[7:0] R/W 00h Output Enable control for Clock Outputs Q[7:0], nQ[7:0]: 0 = Qn is in a high-impedance state 1 = Qn is enabled as indicated in appropriate OUTMODEn[2:0] register field POL_Q[7:0] R/W 00h Polarity of Clock Outputs Q[7:0], nQ[7:0]: 0 = normal polarity 1 = inverted polarity 001b Output Driver Mode of Operation for Clock Output Pair Qm, nQm: 000 = High-impedance 001 = LVPECL 010 = LVDS 011 = LVCMOS 100 = HCSL 101 - 111 = reserved OUTMODEm[2:0] SE_MODEm REVISION 5 07/09/15 R/W R/W 0b Description Behavior of Output Pair Qm, nQm when LVCMOS operation is selected: (Must be 0 if LVDS, HCSL or LVPECL output style is selected) 0 = Qm and nQm are both the same frequency but inverted in phase 1 = Qm and nQm are both the same frequency and phase 29 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Table 6K. Output Divider Control Register Bit Field Locations and Descriptions Output Divider Control Register Block Field Locations Address (Hex) D7 D6 D5 007D D4 D3 Rsvd NS2_Q0[15:8] 007F NS2_Q0[7:0] Rsvd NS2_Q1[15:8] 0082 NS2_Q1[7:0] Rsvd N_Q2[17:16] 0084 N_Q2[15:8] 0085 N_Q2[7:0] 0086 Rsvd N_Q3[17:16] 0087 N_Q3[15:8] 0088 N_Q3[7:0] 0089 Rsvd NS1_Q4[1:0] 008A NS2_Q4[15:8] 008B NS2_Q4[7:0] 008C Rsvd NS1_Q5[1:0] 008D NS2_Q5[15:8] 008E NS2_Q5[7:0] 008F Rsvd NS1_Q6[1:0] 0090 NS2_Q6[15:8] 0091 NS2_Q6[7:0] 0092 Rsvd NS1_Q7[1:0] 0093 NS2_Q7[15:8] 0094 NS2_Q7[7:0] 0095 Rsvd NFRAC_Q2[27:24] 0096 NFRAC_Q2[23:16] 0097 NFRAC_Q2[15:8] 0098 NFRAC_Q2[7:0] 0099 D0 NS1_Q1[1:0] 0081 0083 D1 NS1_Q0[1:0] 007E 0080 D2 Rsvd NFRAC_Q3[27:24] 009A NFRAC_Q3[23:16] 009B NFRAC_Q3[15:8] 009C NFRAC_Q3[7:0] FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 30 REVISION 5 07/09/15 8T49N287 DATA SHEET Output Divider Control Register Block Field Descriptions Bit Field Name NS1_Qm[1:0] (m = 0, 1) Field Type R/W Default Value Description 10b 1st Stage Output Divider Ratio for Output Clock Qm, nQm: (m = 0, 1): 00 = /5 01 = /6 10 = /4 11 = Output Qm, nQm not switching 1st Stage Output Divider Ratio for Output Clock Qm, nQm (m = 4, 5, 6, 7): 00 = /5 01 = /6 10 = /4 11 = /1 (Do not use this selection if PLL0 or PLL1 are the source since the 2nd-stage divider has a limit of 1GHz.) NS1_Qm[1:0] (m = 4, 5, 6, 7) R/W 10b NS2_Qm[15:0] R/W 0002h 2nd Stage Output Divider Ratio for Output Clock Qm, nQm (m = 0, 1, 4, 5, 6, 7): Actual divider ratio is 2x the value written here. A value of 0 in this register will bypass the second stage of the divider. N_Qm[17:0] R/W 00008h Integer Portion of Output Divider Ratio for Output Clock Qm, nQm (m = 2, 3): Values of 0, 1 or 2 cannot be written to this register. Actual divider ratio is 2x the value written here. NFRAC_Qm[27:0] R/W 0000000h Rsvd R/W - REVISION 5 07/09/15 Fractional Portion of Output Divider Ratio for Output Clock Qm, nQm (m = 2, 3): Actual fractional portion is 2x the value written here. Fraction = (NFRAC_Qm * 2) * 2-28 Reserved. Always write 0 to this bit location. Read values are not defined. 31 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Table 6L. Output Clock Phase Adjustment Control Register Bit Field Locations and Descriptions Output Clock Phase Adjustment Control Control Register Block Field Locations Address (Hex) D7 D6 D5 D4 009D D3 D2 D1 D0 CRSE_TRG[7:0] 009E Rsvd COARSE0[4:0] 009F Rsvd COARSE1[4:0] 00A0 Rsvd COARSE2[4:0] 00A1 Rsvd COARSE3[4:0] 00A2 Rsvd COARSE4[4:0] 00A3 Rsvd COARSE5[4:0] 00A4 Rsvd COARSE6[4:0] 00A5 Rsvd COARSE7[4:0] 00A6 Rsvd FINE2[3:0] 00A7 Rsvd FINE3[3:0] Output Clock Phase Adjustment Control Control Register Block Field Descriptions Bit Field Name Field Type Default Value Description CRSE_TRG[7:0] R/W 00h Trigger Coarse Phase Adjustment for output Qm, nQm by amount specified in COARSEm[4:0] register upon 01 transition of this Trigger register bit. Please ensure the PA_BUSYm status bit is 0 before triggering another adjustment cycle on that particular output. Trigger bit must be returned to 0 before another delay cycle can be triggered. COARSEm[4:0] R/W 00000b Number of periods to be inserted when Trigger happens. Relevant clock period is determined by the clock source selected for output Qm, nQm in its CLK_SELm register field. Number of 1/16ths of the relevant clock period to add to the phase of output Qm, nQm (m = 2,3). Relevant clock period is determined by the clock source selected for output Qm, nQm in its CLK_SELm register field. The PLLn_SYN bit for the PLL driving the output divider for the output in question must be toggled to make this value take effect. Note that toggling the PLLn_SYN bit will clear all Coarse delay values and so Fine delay should be set first. FINEm[3:0] R/W 0000b Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 32 REVISION 5 07/09/15 8T49N287 DATA SHEET Table 6M. Output Clock Source Control Register Bit Field Locations and Descriptions Output Clock Source Control Register Block Field Locations Address (Hex) D7 00A8 D6 Rsvd D5 D4 D3 D2 D1 D0 PLL1_SYN PLL0_SYN CLK_SEL3 CLK_SEL2 CLK_SEL1 CLK_SEL0 00A9 Rsvd CLK_SEL5[2:0] Rsvd CLK_SEL4[2:0] 00AA Rsvd CLK_SEL7[2:0] Rsvd CLK_SEL6[2:0] 00AB 11 11 Rsvd Rsvd Output Clock Source Control Register Block Field Descriptions Bit Field Name PLL1_SYN Field Type R/W Default Value Description 0b Output Synchronization Control for Outputs Derived from PLL1: Setting this bit from 01 will cause the output divider(s) for the affected outputs to be held in reset. Setting this bit from 10 will release all the output divider(s) for the affected outputs to run from the same point in time with the coarse output phase adjustment reset to 0. PLL0_SYN R/W 0b Output Synchronization Control for Outputs Derived from PLL0: Setting this bit from 01 will cause the output divider(s) for the affected outputs to be held in reset. Setting this bit from 10 will release all the output divider(s) for the affected outputs to run from the same point in time with the coarse output phase adjustment reset to 0. CLK_SEL0 R/W 0b Clock Source Selection for output Q0, nQ0: 0 = PLL0 1 = PLL1 CLK_SEL1 R/W 1b Clock Source Selection for output Q1, nQ1: 0 = PLL0 1 = PLL1 CLK_SEL2 R/W 0b Clock Source Selection for output Q2, nQ2: 0 = PLL0 1 = PLL1 CLK_SEL3 R/W 1b Clock Source Selection for output Q3, nQ3: 0 = PLL0 1 = PLL1 CLK_SEL4[2:0] CLK_SEL5[2:0] REVISION 5 07/09/15 R/W R/W 000b Clock Source Selection for output Q4, nQ4: Do not select Input Reference 0 or 1 if that input is faster than 250MHz: 000 = PLL0 001 = PLL1 010 = Output Q2, nQ2 011 = Output Q3, nQ3 100 = Input Reference 0 (CLK0) 101 = Input Reference 1 (CLK1) 110 = Reserved 111 = Crystal input 010b Clock Source Selection for output Q5, nQ5: Do not select Input Reference 0 or 1 if that input is faster than 250MHz: 000 = PLL0 001 = PLL1 010 = Output Q2, nQ2 011 = Output Q3, nQ3 100 = Input Reference 0 (CLK0) 101 = Input Reference 1 (CLK1) 110 = Reserved 111 = Crystal input 33 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Output Clock Source Control Register Block Field Descriptions Bit Field Name CLK_SEL6[2:0] Field Type R/W Default Value Description 000b Clock Source Selection for output Q6, nQ6: Do not select Input Reference 0 or 1 if that input is faster than 250MHz: 000 = PLL0 001 = PLL1 010 = Output Q2, nQ2 011 = Output Q3, nQ3 100 = Input Reference 0 (CLK0) 101 = Input Reference 1 (CLK1) 110 = Reserved 111 = Crystal input Clock Source Selection for output Q7, nQ7: Do not select Input Reference 0 or 1 if that input is faster than 250MHz: 000 = PLL0 001 = PLL1 010 = Output Q2, nQ2 011 = Output Q3 nQ3 100 = Input Reference 0 (CLK0) 101 = Input Reference 1 (CLK1) 110 = Reserved 111 = Crystal input CLK_SEL7[2:0] R/W 101b Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 34 REVISION 5 07/09/15 8T49N287 DATA SHEET Table 6N. Analog PLL0 Control Register Bit Field Locations and Descriptions Please contact IDT through one of the methods listed on the last page of this datasheet for details on how to set these fields for a particular user configuration. Analog PLL0 Control Register Block Field Locations Address (Hex) D7 D6 00AC D5 CPSET_0[2:0] 00AD 00AE D4 00AF D2 RS_0[1:0] Rsvd Rsvd D3 SYN_MODE0 VCOMAN_0 D1 CP_0[1:0] Rsvd DLCNT_0 D0 WPOST_0 DBITM_0 DBIT1_0[4:0] Rsvd DBIT2_0[4:0] Analog PLL0 Control Register Block Field Descriptions Bit Field Name CPSET_0[2:0] RS_0[1:0] Field Type R/W R/W Default Value Description 100b Charge Pump Current Setting for Analog PLL0: 000 = 110A 001 = 220A 010 = 330A 011 = 440A 100 = 550A 101 = 660A 110 = 770A 111 = 880A 01b Internal Loop Filter Series Resistor Setting for Analog PLL0: 00 = 330 01 = 640 10 = 1.2k 11 = 1.79k CP_0[1:0] R/W 01b Internal Loop Filter Parallel Capacitor Setting for Analog PLL0: 00 = 40pF 01 = 80pF 10 = 140pF 11 = 200pF WPOST_0 R/W 1b Internal Loop Filter 2nd-Pole Setting for Analog PLL0: 0 = Rpost = 497, Cpost = 40pF 1 = Rpost = 1.58k, Cpost = 40pF DLCNT_0 R/W 1b Digital Lock Count Setting for Analog PLL0: Value should be set to 0 (1ppm accuracy) if external capacitor value is >95nF, otherwise set to 1. 0 = 1ppm accuracy 1 = 16ppm accuracy DBITM_0 R/W 0b Digital Lock Manual Override Setting for Analog PLL0: 0 = Automatic Mode 1 = Manual Mode VCOMAN_0 R/W 1b Manual Lock Mode VCO Selection Setting for Analog PLL0: 0 = VCO2 1 = VCO1 DBIT1_0[4:0] R/W 01011b Manual Mode Digital Lock Control Setting for VCO1 in Analog PLL0. DBIT2_0[4:0] R/W 00000b Manual Mode Digital Lock Control Setting for VCO2 in Analog PLL0. SYN_MODE0 R/W 0b Rsvd R/W - REVISION 5 07/09/15 Frequency Synthesizer Mode Control for PLL0: 0 = PLL0 jitter attenuates and translates one or more input references 1 = PLL0 synthesizes output frequencies using only the crystal as a reference Note that the STATE0[1:0] field in the Digital PLL0 Control Register must be set to Force Freerun state. Reserved. Always write 0 to this bit location. Read values are not defined. 35 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Table 6O. Analog PLL1 Control Register Bit Field Locations and Descriptions Please contact IDT through one of the methods listed on the last page of this datasheet for details on how to set these fields for a particular user configuration. Analog PLL1 Control Register Block Field Locations Address (Hex) D7 D6 00B0 D5 CPSET_1[2:0] 00B1 00B2 D4 00B3 D2 RS_1[1:0] Rsvd Rsvd D3 SYN_MODE1 VCOMAN_1 D1 D0 CP_1[1:0] Rsvd WPOST_1 DLCNT_1 DBITM_1 DBIT1_1[4:0] Rsvd DBIT2_1[4:0] Analog PLL1 Control Register Block Field Descriptions Bit Field Name CPSET_1[2:0] RS_1[1:0] Field Type R/W R/W Default Value Description 100b Charge Pump Current Setting for Analog PLL1: 000 = 110A 001 = 220A 010 = 330A 011 = 440A 100 = 550A 101 = 660A 110 = 770A 111 = 880A 01b Internal Loop Filter Series Resistor Setting for Analog PLL1: 00 = 330 01 = 640 10 = 1.2k 11 = 1.79k CP_1[1:0] R/W 01b Internal Loop Filter Parallel Capacitor Setting for Analog PLL1: 00 = 40pF 01 = 80pF 10 = 140pF 11 = 200pF WPOST_1 R/W 1b Internal Loop Filter 2nd-Pole Setting for Analog PLL1: 0 = Rpost = 497, Cpost = 40pF 1 = Rpost = 1.58k, Cpost = 40pF DLCNT_1 R/W 1b Digital Lock Count Setting for Analog PLL1: Value should be set to 0 (1ppm accuracy) if external capacitor value is >95nF, otherwise set to 1. 0 = 1ppm accuracy 1 = 16ppm accuracy DBITM_1 R/W 0b Digital Lock Manual Override Setting for Analog PLL1: 0 = Automatic Mode 1 = Manual Mode VCOMAN_1 R/W 1b Manual Lock Mode VCO Selection Setting for Analog PLL1: 0 = VCO2 1 = VCO1 DBIT1_1[4:0] R/W 01011b Manual Mode Digital Lock Control Setting for VCO1 in Analog PLL1. DBIT2_1[4:0] R/W 00000b Manual Mode Digital Lock Control Setting for VCO2 in Analog PLL1. SYN_MODE1 R/W 0b Rsvd R/W - Frequency Synthesizer Mode Control for PLL1: 0 = PLL1 jitter attenuates and translates one or more input references 1 = PLL1 synthesizes output frequencies using only the crystal as a reference Note that the STATE1[1:0] field in the Digital PLL1 Control Register must be set to Force Freerun state. Reserved. Always write 0 to this bit location. Read values are not defined. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 36 REVISION 5 07/09/15 8T49N287 DATA SHEET Table 6P. Power Down Control Register Bit Field Locations and Descriptions Power Down Control Register Block Field Locations Address (Hex) D7 D6 D5 00B4 D3 D2 D1 Rsvd 00B5 1 Rsvd Q7_DIS 00B8 1 PLL1_DIS Q6_DIS Q5_DIS CLK1_DIS CLK0_DIS Rsvd Q4_DIS Rsvd D0 DBL_DIS Rsvd 00B6 00B7 D4 Q3_DIS Q2_DIS Q1_DIS Q0_DIS DPLL1_DIS DPLL0_DIS CALRST1 CALRST0 Power Down Control Register Block Field Descriptions Bit Field Name Field Type Default Value DBL_DIS R/W 0b Controls whether Crystal Input Frequency is Doubled before Being used in PLL0 or PLL1: 0 = 2x Actual Crystal Frequency Used 1 = Actual Crystal Frequency Used CLKm_DIS R/W 0b Disable Control for Input Reference m: 0 = Input Reference m is Enabled 1 = Input Reference m is Disabled PLL1_DIS R/W 0b Disable Control for Analog PLL1: 0 = PLL1 Enabled 1 = Analog PLL1 Disabled Description Qm_DIS R/W 0b Disable Control for Output Qm, nQm: 0 = Output Qm, nQm functions normally 1 = All logic associated with Output Qm, nQm is Disabled & Driver in High-Impedance state DPLLm_DIS R/W 0b Disable Control for Digital PLLm: 0 = Digital PLLm Enabled 1 = Digital PLLm Disabled CALRSTm R/W 0b Reset Calibration Logic for APLLm: 0 = Calibration Logic for APLLm Enabled 1 = Calibration Logic for APLLm Disabled Rsvd R/W - REVISION 5 07/09/15 Reserved. Always write 0 to this bit location. Read values are not defined. 37 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Table 6Q. Input Monitor Control Register Bit Field Locations and Descriptions Input Monitor Control Register Block Field Locations Address (Hex) D7 D6 D5 00B9 D4 D3 D2 D1 D0 Rsvd LOS_0[16] 00BA LOS_0[15:8] 00BB LOS_0[7:0] 00BC Rsvd LOS_1[16] 00BD LOS_1[15:8] 00BE LOS_1[7:0] 00BF Rsvd 00C0 Rsvd Rsvd 00C1 Rsvd 00C2 Rsvd Rsvd 00C3 Rsvd 00C4 Rsvd 00C5 Rsvd 00C6 Rsvd Input Monitor Control Register Block Field Descriptions Bit Field Name Field Type Default Value LOS_m[16:0] R/W 1FFFFh Rsvd R/W - Description Number of Input Monitoring clock periods before Input Reference m is considered to be missed (soft alarm). Minimum setting is 3. Reserved. Always write 0 to this bit location. Read values are not defined. Table 6R. Interrupt Enable Control Register Bit Field Locations and Descriptions Interrupt Enable Control Register Block Field Locations Address (Hex) D7 D6 D5 D4 D3 D2 D1 D0 00C7 LOL1_EN LOL0_EN HOLD1_EN HOLD0_EN Rsvd Rsvd LOS1_EN LOS0_EN Bit Field Name Field Type Default Value LOLm_EN R/W 0b Interrupt Enable Control for Loss-of-Lock Interrupt Status Bit for PLLm: 0 = LOLm_INT register bit will not affect status of nINT output signal 1 = LOLm_INT register bit will affect status of nINT output signal HOLDm_EN R/W 0b Interrupt Enable Control for Holdover Interrupt Status Bit for PLLm: 0 = HOLDm_INT register bit will not affect status of nINT output signal 1 = HOLDm_INT register bit will affect status of nINT output signal LOSm_EN R/W 0b Interrupt Enable Control for Loss-of-Signal Interrupt Status Bit for Input Reference m: 0 = LOSm_INT register bit will not affect status of nINT output signal 1 = LOSm_INT register bit will affect status of nINT output signal Interrupt Enable Control Register Block Field Descriptions Description FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 38 REVISION 5 07/09/15 8T49N287 DATA SHEET Table 6S. Digital Phase Detector Control Register Bit Field Locations and Descriptions Digital Phase Detector Control Register Block Field Locations Address (Hex) D7 D6 D5 D4 00C8 D3 D2 D1 D0 Rsvd 1 Rsvd Rsvd Rsvd 1 Rsvd Rsvd 27h 00C9 Rsvd 1 00CA 27h 00CB Rsvd 1 Digital Phase Detector Control Register Block Field Descriptions Bit Field Name Field Type Rsvd R/W Default Value Description - Reserved. Always write 0 to this bit location. Read values are not defined. Table 6T. Interrupt Status Register Bit Field Locations and Descriptions This register contains "sticky" bits for tracking the status of the various alarms. Whenever an alarm occurs, the appropriate Interrupt Status bit will be set. The Interrupt Status bit will remain asserted even after the original alarm goes away. The Interrupt Status bits remain asserted until explicitly cleared by a write of a `1' to the bit over the serial port. This type of functionality is referred to as Read / Write-1-to-Clear (R/W1C). Interrupt Status Register Block Field Locations Address (Hex) D7 D6 D5 D4 D3 D2 D1 D0 0200 LOL1_INT LOL0_INT HOLD1_INT HOLD0_INT Rsvd Rsvd LOS1_INT LOS0_INT 0201 Rsvd 0202 Rsvd 0203 Rsvd Interrupt Status Register Block Field Descriptions Bit Field Name LOLm_INT HOLDm_INT Field Type R/W1C R/W1C Default Value 0b Interrupt Status Bit for Loss-of-Lock on PLLm: 0 = No Loss-of-Lock alarm flag on PLLm has occurred since the last time this register bit was cleared 1 = At least one Loss-of-Lock alarm flag on PLLm has occurred since the last time this register bit was cleared 0b Interrupt Status Bit for Holdover on PLLm: 0 = No Holdover alarm flag on PLLm has occurred since the last time this register bit was cleared 1 = At least one Holdover alarm flag on PLLm has occurred since the last time this register bit was cleared Interrupt Status Bit for Loss-of-Signal on Input Reference m: 0 = No Loss-of-Signal alarm flag on Input Reference m has occurred since the last time this register bit was cleared 1 = At least one Loss-of-Signal alarm flag on Input Reference m has occurred since the last time this register bit was cleared LOSm_INT R/W1C 0b Rsvd R/W - REVISION 5 07/09/15 Description Reserved. Always write 0 to this bit location. Read values are not defined. 39 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Table 6U. Output Phase Adjustment Status Register Bit Field Locations and Descriptions Output Phase Adjustment Status Register Block Field Locations Address (Hex) D7 D6 D5 D4 D3 D2 D1 D0 0204 PA_BUSY7 PA_BUSY6 PA_BUSY5 PA_BUSY4 PA_BUSY3 PA_BUSY2 PA_BUSY1 PA_BUSY0 Output Phase Adjustment Status Register Block Field Descriptions Bit Field Name PA_BUSYm Field Type Default Value R/O - Description Phase Adjustment Event Status for output Qm, nQm: 0 = No phase adjustment is currently in progress on output Qm, nQm 1 = Phase adjustment still in progress on output Qm, nQm. Do not initiate any new phase adjustment at this time Table 6V. Digital PLL0 Status Register Bit Field Locations and Descriptions Digital PLL0 Status Register Block Field Locations Address (Hex) D7 D6 D5 D4 D3 0205 Rsvd EXTLOS0 Rsvd 0206 Rsvd Rsvd Rsvd 0207 D2 D1 D0 CURR_REF0[2:0] Rsvd Rsvd Rsvd 0208 Rsvd Rsvd 0209 Rsvd 020A Rsvd Rsvd 020B Rsvd 020C Rsvd 020D Rsvd 020E Rsvd Digital PLL0 Status Register Block Field Descriptions Bit Field Name Field Type Default Value Description CURR_REF0[2:0] R/O - Currently Selected Reference Status for Digital PLL0: 000 - 011 = No reference currently selected 100 = Input Reference 0 (CLK0, nCLK0) selected 101 = Input Reference 1 (CLK1, nCLK1) selected 110 = Reserved 111 = Reserved EXTLOS0 R/O - External Loopback signal lost for PLL0: 0 = PLL0 has a valid feedback reference signal 1 = PLL0 has lost the external feedback reference signal and is no longer locked Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 40 REVISION 5 07/09/15 8T49N287 DATA SHEET Table 6W. Digital PLL1 Status Register Bit Field Locations and Descriptions Digital PLL1 Status Register Block Field Locations Address (Hex) D4 D3 020F D7 Rsvd D6 D5 EXTLOS1 Rsvd 0210 Rsvd Rsvd Rsvd 0211 D2 D1 D0 CURR_REF1[2:0] Rsvd Rsvd Rsvd 0212 Rsvd Rsvd 0213 Rsvd 0214 Rsvd Rsvd 0215 Rsvd 0216 Rsvd 0217 Rsvd 0218 Rsvd Digital PLL1 Status Register Block Field Descriptions Bit Field Name Field Type Default Value Description CURR_REF1[2:0] R/O - Currently Selected Reference Status for Digital PLL1: 000 - 011 = No reference currently selected 100 = Input Reference 0 (CLK0, nCLK0) selected 101 = Input Reference 1 (CLK1, nCLK1) selected 110 = Reserved 111 = Reserved EXTLOS1 R/O - External Loopback signal lost for PLL1: 0 = PLL1 has a valid feedback reference signal 1 = PLL1 has lost the external feedback reference signal and is no longer locked Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined. Table 6X. General Purpose Input Status Register Bit Field Locations and Descriptions Global Interrupt Status Register Block Field Locations Address (Hex) D7 D6 0219 D5 D4 Rsvd D3 D2 D1 D0 GPI[3] GPI[2] GPI[1] GPI[0] General Purpose Input Status Register Block Field Descriptions Bit Field Name Field Type Default Value GPI[3:0] R/O - REVISION 5 07/09/15 Description Shows current values on GPIO[3:0] pins that are configured as General-Purpose Inputs. 41 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Table 6Y. Global Interrupt Status Register Bit Field Locations and Descriptions Global Interrupt Status Register Block Field Locations Address (Hex) D7 D6 021A D5 D4 D3 D2 Rsvd D1 D0 Rsvd 021B INT Rsvd 021C Rsvd CALI_DBIT0[5:0] 021D Rsvd CALI_DBIT1[5:0] 021E Rsvd Rsvd Rsvd Rsvd nEEP_CRC Rsvd Rsvd BOOTFAIL Rsvd Rsvd EEPDONE 021F Rsvd Bit Field Name Field Type INT R/O - Device Interrupt Status: 0 = No Interrupt Status bits that are enabled are asserted (nINT pin released) 1 = At least one Interrupt Status bit that is enabled is asserted (nINT pin asserted low) BOOTFAIL R/O - Reading of Serial EEPROM failed. Once set this bit is only cleared by reset. Global Interrupt Status Register Block Field Descriptions Default Value Description nEEP_CRC R/O - EEPROM CRC Error (Active Low): 0 = EEPROM was detected and read, but CRC check failed - please reset the device via the nRST pin to retry (serial port is locked) 1 = No EEPROM CRC Error EEPDONE R/O - Serial EEPROM Read cycle has completed. Once set this bit is only cleared by reset. CALI_DBITn[5:0] R/O - Indicates current digital bit setting for PLLn Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 42 REVISION 5 07/09/15 8T49N287 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 3.63V Inputs, VI OSCI Other Input 0V to 2V -0.5V to VCC + 0.5V Outputs, VO (Q[0:7], nQ[0:7]) -0.5V to VCCOX + 0.5V Outputs, VO (GPIO[0:3], SDATA, SCLK, nINT) -0.5V to VCC + 0.5V Outputs, IO (Q[0:7], nQ[0:7]) Continuous Current Surge Current 40mA 65mA Outputs, IO (GPIO[0:3], SDATA, SCLK, nINT) Continuous Current Surge Current 8mA 13mA Junction Temperature, TJ 125C Storage Temperature, TSTG -65C to 150C NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. Supply Voltage Characteristics Table 7A. Power Supply Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter VCC Core Supply Voltage VCCA Analog Supply Voltage ICC Core Supply Current; NOTE 1 ICCA Analog Supply Current; NOTE 1 IEE Power Supply Current; NOTE 2 Minimum Typical Maximum Units 3.135 3.3 3.465 V VCC - 0.13 3.3 VCC V 74 100 mA PLL0 and PLL1 Enabled 206 265 mA Analog PLL1, Digital PLL1, and Calibration Logic for analog PLL1 Disabled 122 187 mA Q[0:7] Configured for LVPECL Logic Levels, Outputs Unloaded 562 735 mA Test Conditions NOTE 1: ICC and ICCA are included in IEE when Q[0:7] configured for LVPECL logic levels. NOTE 2: Internal dynamic switching current at maximum fOUT is included. REVISION 5 07/09/15 43 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Table 7B. Power Supply Characteristics, VCC = 2.5V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter Test Conditions VCC Core Supply Voltage VCCA Analog Supply Voltage ICC Core Supply Current; NOTE 1 ICCA Analog Supply Current; NOTE 1 IEE Power Supply Current; NOTE 2 Minimum Typical Maximum Units 2.375 2.5 2.625 V VCC - 0.13 2.5 VCC V 72 95 mA PLL0 and PLL1 Enabled 201 260 mA Analog PLL1, Digital PLL1, and Calibration Logic for analog PLL1 Disabled 119 182 mA Q[0:7] Configured for LVPECL Logic Levels, Outputs Unloaded 533 695 mA NOTE 1: ICC and ICCA are included in IEE when Q[0:7] configured for LVPECL logic levels. NOTE 2: Internal dynamic switching current at maximum fOUT is included. Table 7C. Maximum Output Supply Current, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40C to 85C Test Conditions VCCOx = 3.3V 5% VCCOx = 2.5V 5% VCCOx = 1.8V 5% LVPECL LVDS HCSL LVCMOS LVPECL LVDS HCSL LVCMOS LVCMOS Units Outputs Unloaded 50 60 50 55 40 50 40 45 35 mA Q1, nQ1 Output Supply Current Outputs Unloaded 50 60 50 55 40 50 40 45 35 mA ICCO2 Q2, nQ2 Output Supply Current Outputs Unloaded 80 90 80 80 70 80 70 70 60 mA ICCO3 Q3, nQ3 Output Supply Current Outputs Unloaded 80 90 80 80 70 80 70 70 60 mA ICCO4 Q4, nQ4 Output Supply Current Outputs Unloaded 55 65 55 55 45 55 45 45 40 mA ICCO5 Q5, nQ5 Output Supply Current Outputs Unloaded 55 65 55 55 45 55 45 45 40 mA ICCO6 Q6, nQ6 Output Supply Current Outputs Unloaded 55 65 55 55 45 55 45 45 40 mA ICCO7 Q7, nQ7 Output Supply Current Outputs Unloaded 55 65 55 55 45 55 45 45 40 mA Symbol Parameter ICCO0 Q0, nQ0 Output Supply Current ICCO1 NOTE: Internal dynamic switching current at maximum fOUT is included. NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 44 REVISION 5 07/09/15 8T49N287 DATA SHEET DC Electrical Characteristics Table 8A. LVCMOS/LVTTL DC Characteristics, VEE = 0V, TA = -40C to 85C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage PLL_BYP, S_A0 IIH IIL nRST, SDATA, SCLK Output High Voltage GPIO[3:0] Output Low Voltage Maximum Units 2 VCC +0.3 V VCC = 2.5V 1.7 VCC +0.3 V VCC = 3.3V -0.3 0.8 V VCC = 2.5V -0.3 0.7 V VCC = VIN = 3.465V or 2.625V 150 A VCC = VIN = 3.465V or 2.625V 5 A VCC = VIN = 3.465V or 2.625V 1 mA -5 A nRST, SDATA, SCLK VCC = 3.465V or 2.625V, VIN = 0V -150 A GPIO[3:0] VCC = 3.465V or 2.625V, VIN = 0V -1 mA VCC = 3.3V 5%, IOH = -5A 2.6 V VCC = 3.3V 5%, IOH = -50A 2.6 V VCC = 2.5V 5%, IOH = -5A 1.8 V VCC = 2.5V 5%, IOH = -50A 1.8 V GPIO[3:0] Output High Voltage nINT, SDATA,SCLK; NOTE 1 Output Low Voltage VCC = 3.3V Typical VCC = 3.465V or 2.625V, VIN = 0V GPIO[3:0] VOL Minimum PLL_BYP, S_A0 nINT, SDATA,SCLK; NOTE 1 VOH Test Conditions nINT, SDATA, SCLK; NOTE 1 VCC = 3.3V 5% or 2.5V5%, IOL = 5mA 0.5 V GPIO[3:0] VCC = 3.3V 5% or 2.5V5%, IOL = 5mA 0.5 V NOTE 1: Use of external pull-up resistors is recommended. Table 8B. Differential Input DC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current 150 A IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 VEE VCC -1.2 V CLKx, nCLKx VCC = VIN = 3.465V or 2.625V CLKx VCC = 3.465V or 2.625V, VIN = 0V -5 A nCLKx VCC = 3.465V or 2.625V, VIN = 0V -150 A NOTE: CLKx denotes CLK0, CLK1. nCLKx denotes nCLK0, nCLK1. NOTE 1: VIL should not be less than -0.3V. VIH should not be higher than VCC. NOTE 2: Common mode voltage is defined as the cross-point. REVISION 5 07/09/15 45 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Table 8C. LVPECL DC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40C to 85C VCCOx = 3.3V5% Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 Qx, nQx VOL Output Low Voltage; NOTE 1 Qx, nQx Minimum Typical VCCOx = 2.5V5% Maximum Minimum VCCOx - 1.3 VCCOx - 0.8 VCCOx - 1.95 VCCOx - 1.75 Typical Maximum Units VCCOx - 1.4 VCCOx - 0.9 V VCCOx - 1.95 VCCOx - 1.75 V NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE: Qx denotes Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7. nQx denotes nQ0, nQ1, nQ2, nQ3, nQ4, nQ5, nQ6, nQ7. NOTE 1: Outputs terminated with 50 to VCCOx - 2V. Table 8D. LVDS DC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VCCOx = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter Test Conditions VOD Differential Output Voltage Qx, nQx VOD VOD Magnitude Change Qx, nQx VOS Offset Voltage Qx, nQx VOS VOS Magnitude Change Qx, nQx Minimum Typical 195 1.1 Maximum Units 454 mV 50 mV 1.375 V 50 mV NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE: Qx denotes Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7. nQx denotes nQ0, nQ1, nQ2, nQ3, nQ4, nQ5, nQ6, nQ7. NOTE: Terminated 100 across Qx and nQx. Table 8E. LVCMOS DC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter VCCOx = 3.3V5% Test Conditions Minimum 2.6 VOH Output High Voltage Qx, nQx IOH = -8mA VOL Output Low Voltage Qx, nQx IOL = 8mA Typical Maximum VCCOx = 2.5V5% Minimum Typical Maximum 1.8 0.5 VCCOx = 1.8V 5% Minimum Typical Maximum 1.1 0.5 Units V 0.5 V NOTE: Qx denotes Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7. nQx denotes nQ0, nQ1, nQ2, nQ3, nQ4, nQ5, nQ6, nQ7. NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 46 REVISION 5 07/09/15 8T49N287 DATA SHEET Table 9. Input Frequency Characteristics, VCC = 3.3V5% or 2.5V5%, TA = -40C to 85C Symbol fIN Parameter Input Frequency; NOTE 1 OSCI, OSCO Test Conditions Minimum Using a crystal (See Table 10, Crystal Characteristics) Maximum Units 10 40 MHz Overdriving Crystal Input, Doubler Logic Enabled; NOTE 2 10 62.5 MHz Overdriving Crystal Input, Doubler Logic Disabled; NOTE 2 16 125 MHz 0.008 875 MHz 100 400 kHz CLKx, nCLKx fSCLK Serial Port Clock SCLK Slave Mode Typical NOTE: CLKx denotes CLK0, CLK1. nCLKx denotes nCLK0, nCLK1. NOTE 1: For the input reference frequency, the divider values must be set for the VCO to operate within its supported range. NOTE 2. For optimal noise performance, the use of a quartz crystal is recommended. Refer to Applications Information, Overdriving the XTAL Interface. Table 10. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units 40 MHz Fundamental Frequency 10 Equivalent Series Resistance (ESR) 15 Load Capacitance (CL) 12 pF Frequency Stability (total) REVISION 5 07/09/15 -100 47 100 ppm FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET AC Electrical Characteristics Table 11A. AC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VCCOx = 3.3V 5%, 2.5V 5% or 1.8V 5% (1.8V only supported for LVCMOS outputs), TA = -40C to 85C Symbol Parameter fVCO VCO Operating Frequency fOUT Test Conditions LVPECL, LVDS, HCSL Output Frequency Maximum Units 3000 4000 MHz Q0, Q1, Q4, Q5, Q6, Q7 Outputs 0.008 1000 MHz Q2, Q3 Outputs Integer Divide Ratio & No Added Phase Delay 0.008 666.67 MHz Q2, Q3 Outputs Non-integer Divide and/or Added Phase Delay 0.008 400 MHz 0.008 250 MHz LVCMOS tR / tF SR Typical LVPECL 20% to 80% 145 360 600 ps LVDS Output HCSL Rise and Fall Times LVCMOS; NOTE 1, 2 20% to 80% 100 230 400 ps 20% to 80% 150 300 600 ps 20% to 80%, VCCOx = 3.3V 180 350 600 ps 20% to 80%, VCCOx = 2.5V 200 350 550 ps 20% to 80%, VCCOx = 1.8V 200 410 650 ps LVPECL Measured on Differential Waveform, 150mV from Center 1 5 V/ns LVDS Measured on Differential Waveform, 150mV from Center 0.5 4 V/ns VCCOx = 2.5V, fOUT 125MHz; Measured on Differential Waveform, 150mV from Center 1.5 4 V/ns VCCOx = 3.3V, fOUT 125MHz; Measured on Differential Waveform, 150mV from Center 2.5 5.5 V/ns Output Slew Rate; NOTE 3 HCSL Q0, nQ0, Q1, nQ1 NOTE 4, 5, 6, 7 75 ps Q4, nQ4, Q5, nQ5 NOTE 4, 5, 6, 7 75 ps Q6, nQ6, Q7, nQ7 NOTE 4, 5, 6, 7 75 ps Q0, nQ0, Q1, nQ1 NOTE 4, 5, 6, 7 75 ps Q4, nQ4, Q5, nQ5 NOTE 4, 5, 6, 7 75 ps Q6, nQ6, Q7,nQ7 NOTE 4, 5, 6, 7 75 ps Q0, nQ0, Q1, nQ1 NOTE 4, 5, 6, 7 75 ps Q4, nQ4, Q5, nQ5 NOTE 4, 5, 6, 7 75 ps Q6, nQ6, Q7, nQ7 NOTE 4, 5, 6, 7 75 ps Q0, nQ0, Q1, nQ1 NOTE 1, 4, 5, 7, 8 80 ps LVCMOS Q4, nQ4, Q5, nQ5 NOTE 1, 4, 5, 7, 8 115 ps Q6, nQ6, Q7, nQ7 NOTE 1, 4, 5, 7, 8 115 ps LVPECL LVDS tsk(b) Minimum Bank Skew HCSL FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 48 REVISION 5 07/09/15 8T49N287 DATA SHEET Symbol Parameter odc Output Duty Cycle; NOTE 9 LVPECL, LVDS, HCSL Test Conditions Minimum Typical Maximum Units fOUT 666.667MHz 45 50 55 % fOUT > 666.667MHz 40 50 60 % 40 50 60 % 50 ppb LVCMOS Initial Frequency Offset; NOTE 10, 11, 12 Switchover or Entering / Leaving Holdover State Output Phase Change in Fully Hitless Switching; NOTE 11, 12, 13 Switchover or Entering / Leaving Holdover State 5 ns 1kHz 122.88MHz Output -123 dBc/Hz 10kHz 122.88MHz Output -131 dBc/Hz 100kHz 122.88MHz Output -134 dBc/Hz 1MHz 122.88MHz Output -147 dBc/Hz SSB(10M) 10MHz 122.88MHz Output -153 dBc/Hz SSB(30M) 30MHz 122.88MHz Output -154 dBc/Hz 800kHz 122.88MHz Output -83 dBc from VCC >80% to First Output Clock Edge 110 150 ms from VCC >80% to First Output Clock Edge (0 retries); I2C Frequency = 100kHz 150 200 ms from VCC >80% to First Output Clock Edge (0 retries); I2C Frequency = 400kHz 130 150 ms from VCC >80% to First Output Clock Edge (31 retries); I2C Frequency = 100kHz 925 1200 ms from VCC >80% to First Output Clock Edge (31 retries); I2C Frequency = 400kHz 360 500 ms 175 ps SSB(1k) SSB(10k) SSB(100k) SSB(1M) Single Sideband Phase Noise; NOTE 14 Spurious Limit at Offset; NOTE 15 Internal OTP Startup; NOTE 11 tstartup SPO Startup Time External EEPROM Startup; NOTE 11, 16 Static Phase Offset Variation; NOTE 17 fIN = fOUT = 156.25MHz -50 -175 NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Appropriate SE_MODE bit must be configured to select phase-aligned or phase-inverted operation. NOTE 2: All Q and nQ outputs in phase-inverted operation NOTE 3: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. NOTE 4: This parameter is guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Measured at the output differential cross point. NOTE 7: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions running off the same PLL. NOTE 8: Measured at VCCOx/2 of the rising edge. All Qx and nQx outputs phase-aligned. NOTE 9: Characterized in synthesizer mode. Duty cycle of bypassed signals (input reference clocks or crystal input) is not adjusted by the device. NOTE 10: Tested in fast-lock operation after >20 minutes of locked operation to ensure holdover averaging logic is stable. NOTE 11: This parameter is guaranteed by design. NOTE 12: Using internal feedback mode configuration. NOTE 13: Device programmed with SWMODEn = 0 (absorbs phase differences). NOTE 14: Characterized with 8T49N287B-901 units (synthesizer mode). REVISION 5 07/09/15 49 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET NOTE 15: Tested with all outputs operating at 122.88MHz. NOTE 16: Assuming a clear I2C bus. NOTE 17: This parameter was measured using CLK0 as the reference input and CLK1 as the external feedback input. Characterized with 8T49N287-908. Table 11B. HCSL AC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VCCOx = 3.3V 5% or 2.5V 5%, TA = -40C to 85C Symbol Parameter Test Conditions Minimum VRB Ring-back Voltage Margin; NOTE 1, 2 -100 tSTABLE Time before VRB is allowed; NOTE 1, 2 500 VMAX Absolute Max. Output Voltage; NOTE 3, 4 VMIN Absolute Min. Output Voltage; NOTE 3, 5 -300 VCROSS Absolute Crossing Voltage; NOTE 6, 7 230 VCROSS Total Variation of VCROSS Over all Edges; NOTE 6, 8 Typical Maximum Units 100 mV ps 1150 mV mV 550 mV 140 mV NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measurement taken from differential waveform. NOTE 2: TSTABLE is the time the differential clock must maintain a minimum 150mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB 100mV differential range. NOTE 3: Measurement taken from single ended waveform. NOTE 4: Defined as the maximum instantaneous voltage including overshoot. NOTE 5: Defined as the minimum instantaneous voltage including undershoot. NOTE 6: Measured at crossing point where the instantaneous voltage value of the rising edge of Qn equals the falling edge of nQn. NOTE 7: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. NOTE 8: Defined as the total variation of all crossing voltages of rising Qn and falling nQn. This is the maximum allowed variance in VCROSS for any particular system. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 50 REVISION 5 07/09/15 8T49N287 DATA SHEET Table 12A. Typical RMS Phase Jitter (Synthesizer Mode), VCC = 3.3V 5% or 2.5V 5%, VCCOx = 3.3V 5%, 2.5V 5% or 1.8V 5% (1.8V only supported for LVCMOS outputs), TA = -40C to 85C Symbol Units 280 287 fs 264 263 270 fs 289 266 265 N/A (NOTE 5) fs fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz 312 326 304 318 fs Q2, Q3 Fractional; NOTE 4 fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz 269 280 261 263 fs Q4, Q5, Q6, Q7; NOTE 1 fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz 302 321 295 301 fs Test Conditions LVPECL LVDS HCSL fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz; NOTE 1 282 299 fOUT = 156.25MHz, Integration Range: 12kHz - 20MHz; NOTE 2 265 fOUT = 622.08MHz, Integration Range: 12kHz - 20MHz; NOTE 3 Q2, Q3 Integer; NOTE 1 Q0, Q1 tjit() RMS Phase Jitter (Random) LVCMOS NOTE 6 Parameter NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE: Fox part numbers: 277LF-40-18 and 277LF-38.88-2 used for 40MHz and 38.88MHz crystals, respectively. NOTE: All outputs configured for the specific output type, as shown in the table. NOTE 1: Characterized with 8T49N287-901. NOTE 2: Characterized with 8T49N287-902. NOTE 3: Characterized with 8T49N287-903. NOTE 4: Characterized with 8T49N287-900. NOTE 5: This frequency is not supported for LVCMOS operation. NOTE 6: Qx and nQx are 180 out of phase. Table 12B. Typical RMS Phase Jitter (Jitter Attenuator Mode), VCC = 3.3V 5% or 2.5V 5%, VCCOx = 3.3V 5%, 2.5V 5% or 1.8V 5% (1.8V only supported for LVCMOS outputs), TA = -40C to 85C Symbol Parameter Test Conditions LVPECL LVDS HCSL fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz; NOTE 1 285 299 fOUT = 156.25MHz, Integration Range: 12kHz - 20MHz; NOTE 2 261 fOUT = 622.08MHz, Integration Range: 12kHz - 20MHz; NOTE 3 Q2, Q3 Integer; NOTE 1 NOTE 6 Units 280 275 fs 252 264 274 fs 221 203 202 N/A (NOTE 5) fs fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz 312 327 306 306 fs Q2, Q3 Fractional; NOTE 4 fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz 271 282 263 267 fs Q4, Q5, Q6, Q7; NOTE 1 fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz 308 320 295 288 fs Q0, Q1 tjit() RMS Phase Jitter (Random) LVCMOS NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE: Measured using a Rohde & Schwarz SMA100A as the input source. NOTE: Fox part numbers: 277LF-40-18 and 277LF-38.88-2 used for 40MHz and 38.88MHz crystals, respectively. NOTE: All outputs configured for the specific output type, as shown in the table. NOTE 1: Characterized with 8T49N287-905. NOTE 2: Characterized with 8T49N287-906. NOTE 3: Characterized with 8T49N287-907. NOTE 4: Characterized with 8T49N287-904. NOTE 5: This frequency is not supported for LVCMOS operation. NOTE 6: Qx and nQx are 180 out of phase. REVISION 5 07/09/15 51 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Table 13. PCI Express Jitter Specifications, VCC = 3.3V 5% or 2.5V 5%, VCCOx = 3.3V 5% or 2.5V 5%, TA = -40C to 85C Symbol Parameter tj (PCIe Gen 1) Phase Jitter Peak-to-Peak; NOTE 1, 4, 5 tREFCLK_HF_RMS Phase Jitter RMS; (PCIe Gen 2) NOTE 2, 4, 5 Typical Maximum PCIe Industry Specification Units = 100MHz, 40MHz Crystal Input, Evaluation Band: 0Hz - Nyquist (Clock Frequency/2) 8 16 86 ps = 100MHz, 40MHz Crystal Input, High Band: 1.5MHz - Nyquist (Clock Frequency/2) 0.8 1.8 3.1 ps = 100MHz, 40MHz Crystal Input, Low Band: 10kHz - 1.5MHz 0.03 0.5 3.0 ps 0.2 0.5 0.8 ps Test Conditions Minimum tREFCLK_LF_RMS (PCIe Gen 2) Phase Jitter RMS; NOTE 2, 4, 5 tREFCLK_RMS (PCIe Gen 3) Phase Jitter RMS; = 100MHz, 40MHz Crystal Input, NOTE 3, 4, 5 Evaluation Band: 0Hz - Nyquist (Clock Frequency/2) NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification. NOTE 4: This parameter is guaranteed by characterization. Not tested in production. NOTE 5: Outputs configured for HCSL mode. Fox 277LF-40-18 crystal used with doubler logic enabled. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 52 REVISION 5 07/09/15 8T49N287 DATA SHEET Noise PowerdBc/Hz Typical Phase Noise at 156.25MHz Offset Frequency (Hz) REVISION 5 07/09/15 53 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Applications Information Overdriving the Crystal Interface The OSCI input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The OSCO pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 5A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 5B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the OSCI input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. OSCO VCC R1 100 Ro C1 Zo = 50 RS OSCI 0.1F Zo = Ro + Rs R2 100 LVCMOS_Driver Figure 5A. General Diagram for LVCMOS Driver to XTAL Input Interface OSCO C2 Zo = 50 OSCI 0.1F Zo = 50 LVPECL_Driver R1 50 R2 50 R3 50 Figure 5B. General Diagram for LVPECL Driver to XTAL Input Interface FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 54 REVISION 5 07/09/15 8T49N287 DATA SHEET Wiring the Differential Input to Accept Single-Ended Levels Figure 6 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VCC/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. Suggest edge rate faster than 1V/ns. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 6. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels REVISION 5 07/09/15 55 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET 3.3V Differential Clock Input Interface Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 7A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. CLKx/nCLKx accepts LVDS, LVPECL, LVHSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figure 7A to Figure 7E show interface examples for the CLKx/nCLKx input driven by the most common driver types. The input interfaces suggested here are examples only. 3.3V 1.8V Zo = 50 CLK Zo = 50 nCLK Differential Input LVHSTL IDT LVHSTL Driver R1 50 R2 50 Figure 7D. CLKx/nCLKx Input Driven by a 3.3V LVPECL Driver Figure 7A. CLKx/nCLKx Input Driven by an IDT Open Emitter LVHSTL Driver Figure 7B. CLKx/nCLKx Input Driven by a 3.3V LVPECL Driver 3.3V Figure 7E. CLKx/nCLKx Input Driven by a 3.3V LVDS Driver 3.3V *R3 CLK nCLK HCSL *R4 Differential Input Figure 7C. CLKx/nCLKx Input Driven by a 3.3V HCSL Driver FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 56 REVISION 5 07/09/15 8T49N287 DATA SHEET 2.5V Differential Clock Input Interface CLKx/nCLKx accepts LVDS, LVPECL, LVHSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figure 8A to Figure 8D show interface examples for the CLKx/nCLKx input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 8A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 2.5V 1.8V Zo = 50 CLK Zo = 50 nCLK LVHSTL IDT Open Emitter LVHSTL Driver R1 50 R2 50 Differential Input Figure 8A. CLKx/nCLKx Input Driven by an IDT Open Emitter LVHSTL Driver Figure 8C. CLKx/nCLKx Input Driven by a 2.5V LVPECL Driver Figure 8B. CLKx/nCLKx Input Driven by a 2.5V LVPECL Driver Figure 8D. CLKx/nCLKx Input Driven by a 2.5V LVDS Driver REVISION 5 07/09/15 57 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Recommendations for Unused Input and Output Pins Inputs: Outputs: CLKx/nCLKx Input LVPECL Outputs For applications not requiring the use one or more reference clock inputs, both CLKx and nCLKx can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLKx to ground. It is recommended that CLKx, nCLKx not be driven with active signals when not enabled for use. Any unused LVPECL output pairs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVDS Outputs Any unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating there should be no trace attached. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVCMOS Outputs Any LVCMOS output can be left floating if unused. There should be no trace attached. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figure 9A and Figure 9B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are R3 125 3.3V R4 125 3.3V 3.3V Zo = 50 + _ Input Zo = 50 R1 84 Figure 9A. 3.3V LVPECL Output Termination FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR R2 84 Figure 9B. 3.3V LVPECL Output Termination 58 REVISION 5 07/09/15 8T49N287 DATA SHEET Termination for 2.5V LVPECL Outputs level. The R3 in Figure 10C can be eliminated and the termination is shown in Figure 10B. Figure 10A and Figure 10C show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCCO - 2V. For VCCO = 2.5V, the VCCO - 2V is very close to ground 2.5V VCCO = 2.5V 2.5V 2.5V VCCO = 2.5V R1 250 R3 250 50 + 50 + 50 - 50 2.5V LVPECL Driver - R1 50 2.5V LVPECL Driver R2 62.5 R2 50 R4 62.5 R3 18 Figure 10C. 2.5V LVPECL Driver Termination Example Figure 10A. 2.5V LVPECL Driver Termination Example 2.5V VCCO = 2.5V 50 + 50 - 2.5V LVPECL Driver R1 50 R2 50 Figure 10B. 2.5V LVPECL Driver Termination Example REVISION 5 07/09/15 59 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET 2.5V and 3.3V HCSL Recommended Termination Figure 11A is the recommended source termination for applications where the driver and receiver will be on a separate PCBs. This termination is the standard for PCI ExpressTMand HCSL output types. 0.5" Max Rs All traces should be 50 impedance single-ended or 100 differential. 0.5 - 3.5" 1-14" 0-0.2" 22 to 33 +/-5% L1 L2 L4 L1 L2 L4 L5 L5 PCI Expres s PCI Expres s Connector Driver 0-0.2" L3 L3 PCI Expres s Add-in Card 49.9 +/- 5% Rt Figure 11A. Recommended Source Termination (where the driver and receiver will be on separate PCBs) Figure 11B is the recommended termination for applications where a point-to-point connection can be used. A point-to-point connection contains both the driver and the receiver on the same PCB. With a matched termination at the receiver, transmission-line reflections will 0.5" Max Rs 0 to 33 L1 be minimized. In addition, a series resistor (Rs) at the driver offers flexibility and can help dampen unwanted reflections. The optional resistor can range from 0 to 33. All traces should be 50 impedance single-ended or 100 differential. 0-18" 0-0.2" L2 L3 L2 L3 0 to 33 L1 PCI Expres s Driver 49.9 +/- 5% Rt Figure 11B. Recommended Termination (where a point-to-point connection can be used) FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 60 REVISION 5 07/09/15 8T49N287 DATA SHEET LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 12A can be used LVDS Driver with either type of output structure. Figure 12B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver's amplitude and common-mode input range should be verified for compatibility with the output. ZO ZT LVDS Receiver ZT Figure 12A. Standard LVDS Termination LVDS Driver ZT 2 ZO ZT C ZT 2 LVDS Receiver Figure 12B. Optional LVDS Termination REVISION 5 07/09/15 61 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 13. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/ Electrically Enhance Lead frame Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 13. P.C. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale) Schematic and Layout Information I2C Serial EEPROM Recommendation Schematics for 8T49N287 can be found on IDT.com. Please search for the 8T49N287 device and click on the link for evaluation board schematics. The 8T49N287 was designed to operate with most standard I2C serial EEPROMs of 256 bytes or larger. Atmel AT24C04C was used during device characterization and is recommended for use. Please contact IDT for review of any other I2C EEPROM's compatibility with the 8T49N287. Crystal Recommendation This device was validated using FOX 277LF series through-hole crystals including part #277LF-40-18 (40MHz) and #277LF-38.88-2 (38.88MHz). If a surface mount crystal is desired, we recommend IDT Part #603-40-48 (40MHz) or #603-38.88-7 (38.88MHz) and FOX Part #603-40-48 (40MHz) or #603-38.88-7 (38.88MHz). FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 62 REVISION 5 07/09/15 8T49N287 DATA SHEET PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The block diagram below shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: Ht s = H3 s H1 s - H2 s The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: Y s = X s H3 s H1 s - H2 s In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. PCIe Gen 2A Magnitude of Transfer Function PCI Express Common Clock Architecture For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz - 50MHz) and the jitter result is reported in peak-peak. PCIe Gen 2B Magnitude of Transfer Function For PCI Express Gen 3, one transfer function is defined and the evaluation is performed over the entire spectrum. The transfer function parameters are different from Gen 1 and the jitter result is reported in RMS. PCIe Gen 1 Magnitude of Transfer Function For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz - 1.5MHz (Low Band) and 1.5MHz - Nyquist (High Band). The plots show the individual transfer functions as well as the overall transfer function Ht. REVISION 5 07/09/15 PCIe Gen 3 Magnitude of Transfer Function For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements. 63 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Power Dissipation and Thermal Considerations The 8T49N287 is a multi-functional, high speed device that targets a wide variety of clock frequencies and applications. Since this device is highly programmable with a broad range of features and functionality, the power consumption will vary as each of these features and functions is enabled. The 8T49N287 device was designed and characterized to operate within the ambient industrial temperature range of -40C to +85C. The ambient temperature represents the temperature around the device, not the junction temperature. When using the device in extreme cases, such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe and reliable junction temperature. Extreme care must be taken to avoid exceeding 125C junction temperature. The power calculation examples below were generated using a maximum ambient temperature and supply voltage. For many applications, the power consumption will be much lower. Please contact IDT technical support for any concerns on calculating the power dissipation for your own specific configuration. Power Domains The 8T49N287 device has a number of separate power domains that can be independently enabled and disabled via register accesses (all power supply pins must still be connected to a valid supply voltage). Figure 14 below indicates the individual domains and the associated power pins. Output Divider / Buffer Q0 (V CCO0) Output Divider / Buffer Q1 (V CCO1) Analog & Digital PLL0 (VCCA & Core V CC) Output Divider / Buffer Q2 (V CCO2) CLK Input & Divider Block (Core VCC) Output Divider / Buffer Q3 (V CCO3) Output Divider / Buffer Q4 (V CCO4) Output Divider / Buffer Q5 (V CCO5) Analog & Digital PLL1 (VCCA & Core V CC) Output Divider / Buffer Q6 (V CCO6) Output Divider / Buffer Q7 (V CCO7) Figure 14. 8T49N287 Power Domains For the output paths shown above, there are three different structures that are used. Q0 and Q1 use one output path structure, Q2 and Q3 use a second structure and Q[4:7] use a 3rd structure. Power consumption data will vary slightly depending on the structure used as shown in the appropriate tables below. Power Consumption Calculation Determining total power consumption involves several steps: 1. 2. 3. Determine the power consumption using maximum current values for core and analog voltage supplies from Table 7A and Table 7B. Determine the nominal power consumption of each enabled output path. a. This consists of a base amount of power that is independent of operating frequency, as shown in Table 15A through Table 15I (depending on the chosen output protocol). b. Then there is a variable amount of power that is related to the output frequency. This can be determined by multiplying the output frequency by the FQ_Factor shown in Table 15A through Table 15I. All of the above totals are then summed. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 64 REVISION 5 07/09/15 8T49N287 DATA SHEET Thermal Considerations Once the total power consumption has been determined, it is necessary to calculate the maximum operating junction temperature for the device under the environmental conditions it will operate in. Thermal conduction paths, air flow rate and ambient air temperature are factors that can affect this. The thermal conduction path refers to whether heat is to be conducted away via a heatsink, via airflow or via conduction into the PCB through the device pads (including the ePAD). Thermal conduction data is provided for typical scenarios in Table 14 below. Please contact IDT for assistance in calculating results under other scenarios. Table 14. Thermal Resistance JA for 56-Lead VFQFN, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2 16.0C/W 12.14C/W 11.02C/W Current Consumption Data and Equations Table 15A. 3.3V LVPECL Output Calculation Table Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 FQ_Factor (mA/MHz) Base Current (mA) 0.00593 40.1 0.01363 63.8 0.00591 42.9 Table 15D. 2.5V LVPECL Output Calculation Table Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Table 15B. 3.3V HCSL Output Calculation Table Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 FQ_Factor (mA/MHz) Base Current (mA) 0.00582 40.1 0.01358 63.8 0.00553 43.1 FQ_Factor (mA/MHz) Base Current (mA) 0.00627 48.6 0.01404 72.5 0.00630 51.3 REVISION 5 07/09/15 Base Current (mA) 0.00373 32.8 0.01134 56.5 0.00369 35.7 Table 15E. 2.5V HCSL Output Calculation Table Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Table 15C. 3.3V LVDS Output Calculation Table Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 FQ_Factor (mA/MHz) FQ_Factor (mA/MHz) Base Current (mA) 0.00354 32.9 0.01125 56.5 0.00353 35.7 Table 15F. 2.5V LVDS Output Calculation Table Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 65 FQ_Factor (mA/MHz) Base Current (mA) 0.00366 40.8 0.01148 64.5 0.00367 43.7 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Table 15G. 3.3V LVCMOS Output Calculation Table Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Table 15I. 1.8V LVCMOS Output Calculation Table Base Current (mA) Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 37.4 61.6 40.6 Base Current (mA) 27.4 51.4 30.3 Table 15H. 2.5V LVCMOS Output Calculation Table Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Base Current (mA) 30.8 54.8 33.7 Applying the values to the following equation will yield output current by frequency: Qx Current (mA) = FQ_Factor * Frequency (MHz) + Base Current where: Qx Current is the specific output current according to output type and frequency FQ_Factor is used for calculating current increase due to output frequency Base Current is the base current for each output path independent of output frequency The second step is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient, using the following equation: TJ = TA + (JA * Pdtotal) where: TJ is the junction temperature (C) TA is the ambient temperature (C) JA is the thermal resistance value from Table 14, dependent on ambient airflow (C/W) Pdtotal is the total power dissipation of the 8T49N287 under usage conditions, including power dissipated due to loading (W) Note that the power dissipation per output pair due to loading is assumed to be 27.95mW for LVPECL outputs and 44.5mW for HCSL outputs. When selecting LVCMOS outputs, power dissipation through the load will vary based on a variety of factors including termination type and trace length. For these examples, power dissipation through loading will be calculated using CPD (found in Table 2) and output frequency: PdOUT = CPD * FOUT * VCCO2 where: Pdout is the power dissipation of the output (W) Cpd is the power dissipation capacitance (pF) Fout is the output frequency of the selected output (MHz) VCCO is the voltage supplied to the appropriate output (V) FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 66 REVISION 5 07/09/15 8T49N287 DATA SHEET Example Calculations Example 1. Common Customer Configuration (3.3V Core Voltage) Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 PLL0 PLL1 Output Type LVPECL LVPECL LVPECL LVPECL LVDS LVDS LVCMOS LVCMOS Frequency (MHz) 245.76 245.76 33.333 33.333 125 125 25 25 Enabled Enabled VCCO 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 * Core Supply Current, ICC = 100mA (max) * Analog Supply Current, ICCA = 265mA (max) Q0 Current = 0.00593x245.76 + 40.1 = 41.56mA Q1 Current = 0.00593x245.76 + 40.1 = 41.56mA Q2 Current = 0.01363x33.333 + 63.8 = 64.25mA Q3 Current = 0.01363x33.333 + 63.8 = 64.25mA Q4 Current = 0.00630x125 + 51.3 = 52.09mA Q5 Current = 0.00630x125 + 51.3 = 52.09mA Q6 Current = 40.6mA Q7 Current = 40.6mA * Total Output Current = 397mA (max) Total Device Current = 100mA + 265mA + 397mA = 762mA Total Device Power = 3.465V * 762mA = 2640.3mW * Power dissipated through output loading: LVPECL = 27.95mW * 4 = 111.8mW LVDS = already accounted for in device power HCSL = n/a LVCMOS = 14.5pF * 25MHz * 3.465V2 * 2 output pairs = 8.7mW * Total Power = 2640.3mW + 111.8mW + 8.7mW = 2760.8mW or 2.8W With an ambient temperature of 85C and no airflow, the junction temperature is: TJ = 85C + 16.1C/W * 2.8W = 130.1C This junction temperature is above the maximum allowable. In instances where maximum junction temperature is exceeded adjustments need to be made to either airflow or ambient temperature. In this case, adjusting airflow to 1m/s (JA = 12.4C/W) will reduce junction temperature to 119.7C. If no airflow adjustments can be made, the maximum ambient operating temperature must be reduced by a minimum of 5.1C. REVISION 5 07/09/15 67 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Example 2. High-Frequency Customer Configuration (3.3V Core Voltage) Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 PLL0 PLL1 Output Type LVDS LVDS LVPECL LVPECL HCSL HCSL HCSL HCSL Frequency (MHz) 625.00 625.00 161.133 161.133 25 25 125 156.25 Enabled Disabled VCCO 2.5 2.5 2.5 2.5 3.3 3.3 3.3 3.3 * Core Supply Current, ICC = 100mA (max) * Analog Supply Current, ICCA = 187mA (max, PLL0 path only) Q0 Current = 0.00366x625 + 40.8 = 43.09mA Q1 Current = 0.00366x625 + 40.8 = 43.09mA Q2 Current = 0.01134x161.133 + 56.5 = 58.3mA Q3 Current = 0.01134x161.133 + 56.5 = 58.3mA Q4 Current = 0.00553x25 + 43.1 = 43.24mA Q5 Current = 0.00553x25 + 43.1 = 43.24mA Q6 Current = 0.00553x125 + 43.1 = 43.79mA Q7 Current = 0.00553x156.25 + 43.1 = 43.96mA * Total Output Current = 202.8mA (VCCO = 2.5V), 174.23mA (VCCO = 3.3V) Total Device Power = 3.465V *(100mA + 187mA + 174.23mA) + 2.625V * 202.8mA = 2130.5mW * Power dissipated through output loading: LVPECL = 27.95mW * 2 = 55.9mW LVDS = already accounted for in device power HCSL = 44.5mW * 4 = 178mW LVCMOS = n/a Total Power = 2130.5mW + 55.9mW + 178mW = 2364.4mW or 2.36W With an ambient temperature of 85C, the junction temperature is: TJ = 85C + 16.1C/W *2.36W = 123C This junction temperature is below the maximum allowable. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 68 REVISION 5 07/09/15 8T49N287 DATA SHEET Example 3. Low Power Customer Configuration (2.5V Core Voltage) Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 PLL0 PLL1 Output Type LVDS LVDS LVDS LVCMOS LVCMOS LVCMOS LVCMOS LVDS VCCO Frequency (MHz) 156.25 156.25 161.133 33.333 25 25 25 156.25 Enabled Enabled 2.5 2.5 2.5 1.8 1.8 1.8 1.8 2.5 * Core Supply Current, ICC = 95mA (max) * Analog Supply Current, ICCA = 260mA (max) Q0 Current = 0.00366x156.25 + 40.8 = 41.37mA Q1 Current = 0.00366x156.25 + 40.8 = 41.37mA Q2 Current = 0.01148x161.133 + 64.5 = 66.35mA Q3 Current = 51.4mA Q4 Current = 30.3mA Q5 Current = 30.3mA Q6 Current = 30.3mA Q7 Current = 0.00367x156.25 + 43.7 = 44.27mA * Total Output Current = 193.36mA (VCCO = 2.5V), 142.3mA (VCCO = 1.8V) Total Device Power = 2.625V *(95mA + 260mA + 193.36mA) + 1.89V * 142.3mA = 1708.4mW * Power dissipated through output loading: LVPECL = n/a LVDS = already accounted for in device power HCSL = n/a LVCMOS_33.3MHz = 17pF * 33.3MHz * 1.89V2 * 1 output pair = 2.02mW LVCMOS_25MHz = 12.5pF * 25MHz * 1.89V2 * 3 output pairs = 3.35mW Total Power = 1708.4mW + 2.02mW + 3.35mW = 1714mW or 1.7W With an ambient temperature of 85C, the junction temperature is: TJ = 85C + 16.1C/W *1.7W = 112.4C This junction temperature is below the maximum allowable. REVISION 5 07/09/15 69 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Reliability Information Table 16. JA vs. Air Flow Table for a 56-Lead VFQFN JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2 16.0C/W 12.14C/W 11.02C/W NOTE: Theta JA (JA)values calculated using a 4-layer JEDEC PCB (114.3mm x 101.6mm), with 2oz. (70m) copper plating on all 4 layers. Transistor Count The transistor count for 8T49N287 is: 998,958 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 70 REVISION 5 07/09/15 8T49N287 DATA SHEET 56-Lead VFQFN NL Package Outline REVISION 5 07/09/15 71 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET 56-Lead VFQFN NL Package Outline, continued FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 72 REVISION 5 07/09/15 8T49N287 DATA SHEET Ordering Information Table 17. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 8T49N287-dddNLGI IDT8T49N287-dddNLGI 56-Lead VFQFN, Lead-Free Tray -40C to +85C 8T49N287-dddNLGI8 IDT8T49N287-dddNLGI 56-Lead VFQFN, Lead-Free Tape & Reel, Pin 1 Orientation: EIA-481-C -40C to +85C 8T49N287-dddNLGI# IDT8T49N287-dddNLGI 56-Lead VFQFN, Lead-Free Tape & Reel, Pin 1 Orientation: EIA-481-D -40C to +85C NOTE: For the specific, publicly available -ddd order codes, refer to FemtoClock NG Universal Frequency Translator Ordering Product Information document. For custom -ddd order codes, please contact IDT for more information. Table 18. Pin 1 Orientation in Tape and Reel Packaging Part Number Suffix Pin 1 Orientation Illustration Correct Pin 1 ORIENTATION NLGI8 CARRIER TAPE TOPSIDE (Round Sprocket Holes) Quadrant 1 (EIA-481-C) USER DIRECTION OF FEED Correct Pin 1 ORIENTATION NLGI# CARRIER TAPE TOPSIDE (Round Sprocket Holes) Quadrant 2 (EIA-481-D) USER DIRECTION OF FEED REVISION 5 07/09/15 73 FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8T49N287 DATA SHEET Revision History Sheet Rev Table Page 3 2 Table 11A 55 3 5 Date General Description - first paragraph/last sentence, added HCSL. Features - added HCSL in "Accepts up to two LVPECL...." bullet and "Generates 8 LVPECL..." bullet. 11/06/14 AC Characteristics Table - updated LVDS Rise/Fall Time maximum spec. from 500 to 400ps. Miscellaneous content enhancement in: Output Phase Control on Switchover section; Table 6A, Table 6C, Table 6E and Table 6G, and Pin Assignment format. Table 11A 4 Description of Change 58 AC Characteristics Table - added fOUT minimum parameters. 75 Termination for 3.3V LVPECL Outputs updated Figure 9A. 79 Updated Crystal Recommendation. 11 "Device Start-up & Reset Behavior" - added second paragraph. FEMTOCLOCK(R) NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 74 3/20/15 6/01/15 7/9/15 REVISION 5 07/09/15 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. 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