September 2006
Advance Information
Copyright © Alliance Memory. All rights reserved.
AS7C1028
12/5/06; V.1.0 Alliance Memory P. 1 of 8
5V 256K X 4 CMOS SRAM (Common I/O)
®
Features
• Industrial (-40o to 85oC) temperature
• Organization: 262,144 words × 4 bits
• High speed
- 12 ns address access time
- 6 ns output enable access time
• Low power consumption via chip deselect
• One chip select plus one Output Enable pin
• Bidirectional data inputs and outputs
• TTL-compatible
• 28-pin JEDEC standard packages
- 400 mil SOJ
• ESD protection ≥ 2000 volts
Logic block diagram
A
11
A
10
262,144 x 4
Array
(262,144)
Input buffer
A0
A1
A2
A3
A4
A5
A6
A7
A
12 A
13 A
14 A
15 A
16
I/O0
I/O3
VCC
GND
OE
CE
WE
Address decoder
Address decoder
Control
circuit
Sense amp
A8
A9
A
17
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A17
A16
A15
A14
A13
A12
A11
NC
I/O3
I/O2
I/O1
I/O0
WE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CE
OE
GND
AS7C1028
16
15
28 Pin SOJ (400 mil)
AS7C1028
12/5/06; V.1.0 Alliance Memory P. 2 of 8
®
Functional description
The AS7C1028 is a 5V high-performance CMOS 1,048,576-bit Static Random-Access Memory (SRAM) device organized
as 262,144 words × 4 bits. It is designed for memory applications requiring fast data access at low voltage, including
PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 5.0V
operation witho ut sacrificing performa nce or op erat in g margins.
The device enters standb y mode when
CE
is high. Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output
enable access times (tOE) of 6 ns are ideal for high-performance applications. The chip enable (
CE
) input permits easy memory
expansion with multiple-bank memory organizations.
A write cycle is accomplished by asserting chip enable (
CE
) and write enable (
WE
) LOW. Data on the input pins I/O0-I/O7 is
written on the rising edge of
WE
(write cycle 1) or
CE
(write cycle 2). To avoid bus contention, external devices should drive
I/O pins only after outputs have been disabled with output enable (
OE
) or write enable (
WE
).
A read cycle is accomplished by asserting chip enable (
CE
) and output enable (
OE
) LOW, with write enable (
WE
) high. The
chip drives I/O pins with the data word referenced by the input address. When chip enable or output enab le is high, or w rite
enable is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0±0.5V supply. The AS7C1028 is packaged in
high volume industry standard pack ages.
Absolute maximum ratings
Note:
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum ratin g conditions for extended periods may affect reliability.
Truth table
Notes:
H = VIH, L = VIL, x = Don’t care.
VLC = 0.2V, VHC = VCC - 0.2V.
Other inputs ≥ VHC or VLC.
Parameter Symbol Min Max Unit
Voltage on VCC relative to GND Vt1 –0.5 +7.0 V
Voltage on any pin relative to GND Vt2 –0.5 VCC + 0.5 V
Power dissipation PD–1.25W
Storage temperature (plastic) Tstg –55 +125 oC
Ambient temperature with VCC applied Tbias –55 +125 oC
DC current into outputs (low) IOUT –50mA
CE WE OE
Data Mode
H X X High Z Standby (ISB, ISB1)
L H H High Z Output disable (ICC)
LHL D
OUT Read (ICC)
LLX D
IN Write (ICC)
AS7C1028
12/5/06; V.1.0 Alliance Memory P. 3 of 8
®
Recommended operating conditions
Note:
1 VIL min = –1.5V for pulse width less than 10ns, once per cycle .
DC operating characteristics (over the operating range)1
Capacitance (f = 1MHz, Ta = room temperature, VCC = NOMINAL)2
Note:
This parameter is guaranteed by devic e ch aracterization, but is not production tested .
Parameter Symbol Min Typical Max Unit
Supply voltage VCC 4.5 5.0 5.5 V
Input voltage VIH 2.2 – VCC+0.5 V
VIL(1) -0.5(1) –0.8V
Ambient operating temperature (Industrial) TA–40 – 85 oC
Parameter Symbol Test conditions
AS7C1028-12
UnitMin Max
Input leakage current |ILI|VCC = Max,
Vin = GND to VCC – 5 µA
Output leakage current |ILO|VCC = Max,
CS
= VIH,
VOUT = GND to VCC – 5 µA
Operating power supply current ICC VCC = Max, CE ≤ VIL
f = fMax, IOUT = 0mA –170 mA
Standby power supply current
ISB VCC = Max, CE > VIH
f = fMax, IOUT = 0mA –40 mA
ISB1
VCC = Max, CE > VCC–0.2V
VIN < GND + 0.2V or
VIN > VCC–0.2V, f = 0 –10 mA
Output voltage VOL IOL = 8 mA, VCC = Min –0.4 V
VOH IOH = –4 mA, VCC = Min 2.4 – V
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A,
CE
,
WE
,
OE
Vin = 3dV 8 pF
I/O capacitance CI/O I/O Vout = 3dV 8 pF
AS7C1028
12/5/06; V.1.0 Alliance Memory P. 4 of 8
®
Read cycle (over the operating range)3,9
Key to switching waveforms
Read waveform 1 (address controlled)3,6,7,9
Read waveform 2 (CE controlled)3,6,8,9
Parameter Symbol
AS7C1028-12
Unit NotesMin Max
Read cycle time tRC 12 – ns
Address access time tAA –12ns3
Chip enable (CE) access time tACE –12ns3
Output enable (OE) access time tOE –6ns
Output hold from address change tOH 4–ns5
CE LOW to output in low Z tCLZ 3 – ns 4, 5
CE HIGH to output in high Z tCHZ 0 6 ns 4, 5
OE LOW to output in low Z tOLZ 0 – ns 4, 5
OE HIGH to output in hig h Z tOHZ 0 5 ns 4, 5
Power up time tPU 0 – ns 4, 5
Power down time tPD –12ns4, 5
Undefined output/d on’t careFalling inputRising input
Address
D
out
Data valid
t
OH
tAA
t
RC
Supply
current
CE
OE
D
out
t
RC1
t
OE
t
OLZ
t
ACE
t
CHZ
t
CLZ
t
PU
t
PD
I
CC
I
SB
50% 50%
t
OHZ
Data valid
AS7C1028
12/5/06; V.1.0 Alliance Memory P. 5 of 8
®
Write cycle (over the operating range)11
Shaded areas contain advance information.
Write waveform 1 (WE controlled)10,11
Write waveform 2 (CE controlled)10,11
Parameter Symbol
AS7C1028-12
Unit NotesMin Max
Write cycle time tWC 12 – ns
Chip enable to write end tCW 10 – ns
Address setup to write end tAW 10 – ns
Address setup ti me tAS 0–ns
Write pulse width tWP 10 – ns
Write recovery time tWR 0–ns
Address hold from end of write tAH 0–ns
Data valid to write end tDW 7–ns
Data hold time tDH 0 – ns 4, 5
Write enable to output in high Z tWZ 0 5 ns 4, 5
Output active from write end tOW 3 – ns 4, 5
t
AW
t
AH
t
WC
Address
WE
D
in
D
out
t
DH
t
OW
t
DW
t
WZ
t
WP
t
AS
t
WR
Data valid
t
AW
Address
CE
WE
D
in
D
out
Data valid
t
CW
t
WP
t
DW
t
DH
t
AH
t
WZ
t
WC
t
AS
t
WR
AS7C1028
12/5/06; V.1.0 Alliance Memory P. 6 of 8
®
AC test conditions
Notes:
1 During VCC power-up, a pul l - u p r esistor to VCC on
CE
is required to meet ISB specification.
2 This parameter is sampled, but no t 100% te sted.
3 For test conditions, see AC Test Conditions, Figures A, B, C.
4 These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured ±20 0mV from steady-state voltage.
5 This parameter is guaranteed, but not tested.
6
WE
is High for read cycl e.
7
CE
and
OE
are Low for read cycle.
8 Address valid prior to or coincid en t with
CE
transition Low.
9 All read cycle timings are referenc ed from the last valid address to the first transitioning addre ss.
10
CE
or
WE
must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenc ed from the last valid addre ss to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 C=30pF, except on H igh Z and Low Z parameters, where C=5pF.
350
Ω
C(13)
320
Ω
D
out
GND
V
CC
168
Ω
D
out
+1.72V (5V)
Figure C: Output load
255
Ω
C(13)
480
Ω
D
out
GND
+5V
Figure B: Output lo
ad
Thevenin equivalent
- Output
l
oa
d
: see F
i
gure B or F
i
gure C.
- Input pulse level: GND to
V
CC. See Figure A.
- Input rise and fall times: 3 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
10%
90%
10%
90%
GND
V
CC
Figure A: Input pulse
3 ns
AS7C1028
12/5/06; V.1.0 Alliance Memory P. 7 of 8
®
Package diagrams
28-pin SOJ
400 mil
Min Max
in mils
A0.132 .0146
A1 0.062 -
A2 0.105 0.115
B0.024 0.032
b0.013 0.021
c0.720 0.012
D0.354 0.378
E0.395 0.405
E1 0.430 0.405
E2 0.430 0.440
e0.050 BSC
eD
E1
Pin 1
b
B
A1
A2
c
E2
Seating
Plane
E2
A
Note: This part is compatible with both pin numbering
conventions used by various manufacturers.
28-pin SOJ
400 mil
AS7C1028
®
Alliance Memory, Inc.
1116 South Amphlett
San Mateo, CA 94402
Tel: 650-525-3737
Fax: 650-525-0449
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
Part Number: AS7C1028
Document Version: v.1.0
© Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of
Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this
document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time,
without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product
data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or
warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described
herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness
for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions
of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The
purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual
property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a
malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting
systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
®
Ordering information
Part numbering system
Package Volt/Temp 12 ns
Plastic SOJ, 400 mil 5V industrial AS7C1028-12JIN
AS7C 1028 –XX X I X
SRAM prefix Device number Access time Package:
J=SOJ 400 mil Temperature range:
I = -40C to 85C N=Lead Free Part
