Amp
Regulator
GND
VCC
VOUT
OffsetGain
Trim
Control
To all subcircuits
The Allegro™ A1210-A1214 Hall-effect latches are next
generation replacements for the popular Allegro 317x and
318x lines of latching switches. The A121x family, produced
with BiCMOS technology, consists of devices that feature fast
power-on time and low-noise operation. Device programming
is performed after packaging, to ensure increased switchpoint
accuracy by eliminating offsets that can be induced by package
stress. Unique Hall element geometries and low-offset amplifiers
help to minimize noise and to reduce the residual offset voltage
normally caused by device overmolding, temperature excursions,
and thermal stress.
The A1210-A1214 Hall-effect latches include the following on
a single silicon chip: voltage regulator, Hall-voltage generator,
small-signal amplifier, Schmitt trigger, and NMOS output
transistor. The integrated voltage regulator permits operation
from 3.8 to 24 V. The extensive on-board protection circuitry
makes possible a ±30 V absolute maximum voltage rating
for superior protection in automotive and industrial motor
commutation applications, without adding external components.
All devices in the family are identical except for magnetic
switchpoint levels.
The small geometries of the BiCMOS process allow these
devices to be provided in ultrasmall packages. The package
styles available provide magnetically optimized solutions for
most applications. Package LH is an SOT23W, a miniature low-
profile surface-mount package, while package UA is a three-lead
ultramini SIP for through-hole mounting. Each package is lead
(Pb) free, with 100% matte-tin-plated leadframes.
A1210-DS, Rev. 15
MCO-0000574
• AEC-Q100 automotive qualified
• Continuous-time operation
□Fast power-on time
□Low noise
• Stable operation over full operating temperature range
• Reverse-battery protection
• Solid-state reliability
• Factory-programmed at end-of-line for optimum
performance
• Robust EMC performance
• High ESD rating
• Regulator stability without a bypass capacitor
Continuous-Time Latch Family
Functional Block Diagram
A1210, A1211, A1212, A1213, and A1214
FEATURES AND BENEFITS DESCRIPTION
February 4, 2019
PACKAGES:
Not to scale
3-pin SOT23W
(suffix LH)
3-pin SIP,
matrix HD style
(suffix UA)
3-pin SIP,
chopper style
(suffix UA)
NOT FOR
NEW DESIGN
Continuous-Time Latch Family
A1210, A1211,
A1212, A1213,
and A1214
2
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
SELECTION GUIDE
Part Number Packing [1] Mounting Ambient, TABRP (Min) BOP (Max)
A1210ELHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount –40°C to 85°C
–150 G 150 G
A1210ELHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
A1210LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
–40°C to 150°CA1210LLHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
A1210LUA-T [2] Bulk, 500 pieces/bag 3-pin SIP through hole
A1211LUA-T [2] Bulk, 500 pieces/bag 3-pin SIP through hole –40°C to 150°C –180 G 180 G
A1212LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
–40°C to 150°C –175 G 175 GA1212LLHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
A1212LUA-T [2] Bulk, 500 pieces/bag 3-pin SIP through hole
A1213LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
–40°C to 150°C –200 G 200 GA1213LLHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
A1213LUA-T [2] Bulk, 500 pieces/bag 3-pin SIP through hole
A1214LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
–40°C to 150°C –300 G 300 GA1214LLHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
A1214LUA-T [2] Bulk, 500 pieces/bag 3-pin SIP through hole
1 Contact Allegro for additional packing options.
2 The chopper-style UA package is not for new design; the matrix HD style UA package is recommended for new designs.
ABSOLUTE MAXIMUM RATINGS
Characteristic Symbol Notes Rating Unit
Supply Voltage VCC 30 V
Reverse Supply Voltage VRCC –30 V
Output Off Voltage VOUT 30 V
Reverse Output Voltage VROUT –0.5 V
Output Current IOUTSINK 25 mA
Magnetic Flux Density B 1 G = 0.1 mT (millitesla) Unlimited G
Operating Ambient Temperature TA
Range E –40 to 85 °C
Range L –40 to 150 °C
Maximum Junction Temperature TJ(max) 165 °C
Storage Temperature Tstg –65 to 170 °C
SPECIFICATIONS
Continuous-Time Latch Family
A1210, A1211,
A1212, A1213,
and A1214
3
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Terminal List
Name Number Description
Package LH Package UA
VCC 1 1 Connects power supply to chip
VOUT 2 3 Output from circuit
GND 3 2 Ground
Package UA, 3-Pin SIP Pinout DiagramPackage LH, 3-Pin SOT23W Pinout Diagram
1
3
2
GND
VOUT
VCC
1
2
3
GND
VOUT
VCC
PINOUT DIAGRAMS AND TERMINAL LIST TABLE
Continuous-Time Latch Family
A1210, A1211,
A1212, A1213,
and A1214
4
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
DEVICE QUALIFICATION PROGRAM
Contact Allegro for information.
EMC (Electromagnetic Compatibility) REQUIREMENTS
Contact Allegro for information.
Characteristic Symbol Test Conditions Min. Typ. Max. Units
ELECTRICAL CHARACTERISTICS
Supply Voltage [1] VCC Operating, TJ < 165°C 3.8 – 24 V
Output Leakage Current IOUTOFF VOUT = 24 V, B < BRP – – 10 µA
Output On Voltage VOUT(SAT) IOUT = 20 mA, B > BOP – 215 400 mV
Power-On Time [2] tPO
Slew rate (dVCC/dt) < 2.5 V/μs, B > BOP + 5 G or B < BRP
– 5 G – – 4 µs
Output Rise Time [3] trVCC = 12 V, RLOAD = 820 Ω, CS = 12 pF – – 400 ns
Output Fall Time [3] tfVCC = 12 V, RLOAD = 820 Ω, CS = 12 pF – – 400 ns
Supply Current ICCON B > BOP – 4.1 7.5 mA
ICCOFF B < BRP – 3.8 7.5 mA
Reverse Battery Current IRCC VRCC = –30 V – – –10 mA
Supply Zener Clamp Voltage VZICC = 10.5 mA; TA = 25°C 32 – – V
Supply Zener Current [4] IZVZ = 32 V; TA = 25°C – – 10.5 mA
MAGNETIC CHARACTERISTICS [5]
Operate Point BOP
A1210
South pole adjacent to branded face of
device
25 78 150 G
A1211 15 87 180 G
A1212 50 107 175 G
A1213 80 – 200 G
A1214 140 – 300 G
Release Point BRP
A1210
North pole adjacent to branded face of
device
–150 –78 –25 G
A1211 –180 –95 –15 G
A1212 –175 –117 –50 G
A1213 –200 – –80 G
A1214 –300 – –140 G
Hysteresis BHYS
A1210
BOP – BRP
50 155 – G
A1211 80 180 – G
A1212 100 225 350 G
A1213 160 – 400 G
A1214 280 – 600 G
1 Maximum voltage must be adjusted for power dissipation and junction temperature, see Power Derating section.
2 For VCC slew rates greater than 250 V/μs, and TA = 150°C, the Power-On Time can reach its maximum value.
3 CS =oscilloscope probe capacitance.
4 Maximum current limit is equal to the maximum ICC(max) + 3 mA.
5 Magnetic ux density, B, is indicated as a negative value for north-polarity magnetic elds, and as a positive value for south-polarity magnetic
elds. This so-called algebraic convention supports arithmetic comparison of north and south polarity values, where the relative strength of the eld
is indicated by the absolute value of B, and the sign indicates the polarity of the eld (for example, a –100 G eld and a 100 G eld have equivalent
strength, but opposite polarity).
OPERATING CHARACTERISTICS: Over full operating voltage and ambient temperature ranges, unless otherwise noted
Continuous-Time Latch Family
A1210, A1211,
A1212, A1213,
and A1214
5
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic Symbol Test Conditions Value Units
Package Thermal Resistance RθJA
Package LH, on single layer, single-sided PCB with copper limited to
solder pads 228 °C/W
Package LH, on single layer, double-sided PCB with 0.926 in2 copper
area 110 °C/W
Package UA on single layer, single-sided PCB with copper limited to
solder pads 165 °C/W
6
7
8
9
2
3
4
5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
20 40 60 80 100 120 140 160 180
Temperature (ºC)
Maximum Allowable V
CC
(V)
TJ(max) = 165ºC; ICC = ICC(max)
Power Derating Curve
(R
θJA
= 228 ºC/W)
Minimum-K PCB, Package LH
(R
θJA
= 110 ºC/W)
Low-K PCB, Package LH
(R
θJA
= 165 ºC/W)
Minimum-K PCB, Package UA
VCC(min)
VCC(max)
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
20 40 60 80 100 120 140 160 180
Temperature (°C)
Power Dissipation, P
D
(mW)
Power Dissipation versus Ambient Temperature
(RθJA = 165 ºC/W)
Minimum-K PCB, Package UA
(RθJA = 228 ºC/W)
Minimum-K PCB, Package LH
(RθJA = 110 ºC/W)
Low-K PCB, Package LH
Continuous-Time Latch Family
A1210, A1211,
A1212, A1213,
and A1214
6
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
CHARATERISTIC DATA
(A1210/11/12/13/14)
T
A
(°C)
Supply Current (On) versus Ambient Temperature
V
CC
(V)
ICCON (mA)
24
3.8
(A1210/11/12/13/14)
T
A
(°C)
Supply Current (Off) versus Ambient Temperature
V
CC
(V)
ICCOFF (mA)
24
3.8
(A1210/11/12/13/14)
T
A
(°C)
Output Voltage (On) versus Ambient Temperature
V
CC
(V)
VOUT(SAT) (mV)
24
3.8
(A1210/11/12/13/14)
Supply Current (On) versus Supply Voltage
T
A
(°C)
ICCON (mA)
V
CC
(V)
–40
25
150
(A1210/11/12/13/14)
Supply Current (Off) versus Supply Voltage
T
A
(°C)
ICCOFF (mA)
V
CC
(V)
–40
25
150
(A1210/11/12/13/14)
Output Voltage (On) versus Supply Voltage
T
A
(°C)
VOUT(SAT) (mV)
V
CC
(V)
–40
25
150
0
1.0
2.0
3.0
4.0
5.0
7.0
6.0
8.0
0
1.0
2.0
3.0
4.0
5.0
7.0
6.0
8.0
0
1.0
2.0
3.0
4.0
5.0
7.0
6.0
8.0
0
1.0
2.0
3.0
4.0
5.0
7.0
6.0
8.0
–500 50 100150 0510 15 20 25
–500 50 100150 0510 15 20 25
–500 50 100150 0510 15 20 25
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
350
400
Continuous-Time Latch Family
A1210, A1211,
A1212, A1213,
and A1214
7
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
V
CC
(V)
24
3.8
TA (°C)
V
CC
(V)
24
3.8
V
CC
(V)
24
3.8
T
A
(°C)
–40
25
150
T
A
(°C)
–40
25
150
T
A
(°C)
–40
25
150
(A1210)
Operate Point versus Ambient Temperature
BOP (G)
(A1210)
T
A (°C)
Release Point versus Ambient Temperature
BRP (G)
(A1210)
(A1210)
(A1210)
(A1210)
T
A (°C)
Hysteresis versus Ambient Temperature
BHYS (G)
BOP (G)BRP (G)BHYS (G)
Operate Point versus Supply Voltage
Release Point versus Supply Voltage
VCC (V)
VCC (V)
TA (°C) VCC (V)
Hysteresis versus Supply Voltage
25
50
75
125
100
150
-150
-125
-100
-50
-75
-25
–500 50 100150 0510 15 20 25
–500 50 100150 0510 15 20 25
–500 50 100150 0510 15 20 25
50
75
100
125
150
175
200
225
25
50
75
125
100
150
-150
-125
-100
-50
-75
-25
50
75
100
125
150
175
200
225
Continuous-Time Latch Family
A1210, A1211,
A1212, A1213,
and A1214
8
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
V
CC
(V)
24
3.8
T
A
(°C)
V
CC
(V)
24
3.8
V
CC
(V)
24
3.8
(A1211)
Operate Point versus Ambient Temperature
BOP (G)
(A1211)
T
A
(°C)
Release Point versus Ambient Temperature
BRP (G)
(A1211)
T
A
(°C)
Hysteresis versus Ambient Temperature
BHYS (G)
T
A
(°C)
V
CC
(V)
24
3.8
T
A
(°C)
V
CC
(V)
24
3.8
V
CC
(V)
24
3.8
(A1212)
Operate Point versus Ambient Temperature
BOP (G)
(A1212)
T
A
(°C)
Release Point versus Ambient Temperature
BRP (G)
(A1212)
T
A
(°C)
Hysteresis versus Ambient Temperature
BHYS (G)
T
A
(°C)
–500 50 100150
–500 50 100150
–500 50 100150
15
40
65
90
140
115
165
-180
-130
-155
-105
-55
-80
-30
80
100
120
140
160
180
200
220
240
–500 50 100150
–500 50 100150
–500 50 100150
-50
0
-25
75
25
50
125
150
100
175
-150
-125
-100
-50
-75
-175
100
150
200
250
300
350
Continuous-Time Latch Family
A1210, A1211,
A1212, A1213,
and A1214
9
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
FUNCTIONAL DESCRIPTION
Operation
The output of these devices switches low (turns on) when a
magnetic field perpendicular to the Hall element exceeds the
operate point threshold, BOP. After turn-on, the output is capable
of sinking 25 mA and the output voltage is VOUT(SAT). Notice
that the device latches; that is, a south pole of sufficient strength
towards the branded surface of the device turns the device on,
and the device remains on with removal of the south pole. When
the magnetic field is reduced below the release point, BRP
,
the device output goes high (turns off). The difference in the
magnetic operate and release points is the hysteresis, Bhys, of
the device. This built-in hysteresis allows clean switching of the
output, even in the presence of external mechanical vibration and
electrical noise.
Powering-on the device in the hysteresis range, less than BOP
and higher than BRP, allows an indeterminate output state. The
correct state is attained after the first excursion beyond BOP or
BRP.
Continuous-Time Benefits
Continuous-time devices, such as the A121x family, offer the
fastest available power-on settling time and frequency response.
Due to offsets generated during the IC packaging process,
continuous-time devices typically require programming after
packaging to tighten magnetic parameter distributions. In con-
trast, chopper-stabilized switches employ an offset cancellation
technique on the chip that eliminates these offsets without the
need for after-packaging programming. The tradeoff is a longer
settling time and reduced frequency response as a result of the
chopper-stabilization offset cancellation algorithm.
The choice between continuous-time and chopper-stabilized
designs is solely determined by the application. Battery manage-
ment is an example where continuous-time is often required. In
these applications, VCC is chopped with a very small duty cycle
in order to conserve power (refer to figure 2). The duty cycle
is controlled by the power-on time, tPO, of the device. Because
continuous-time devices have the shorter power-on time, they
are the clear choice for such applications.
For more information on the chopper stabilization technique,
refer to Technical Paper STP 97-10, Monolithic Magnetic Hall
Sensing Using Dynamic Quadrature Offset Cancellation and
Technical Paper STP 99-1, Chopper-Stabilized Amplifiers with a
Track-and-Hold Signal Demodulator.
Figure 1: Switching Behavior of Latches
On the horizontal axis, the B+ direction indicates increasing south polarity magnetic field strength, and the B– direction indicates decreasing
south polarity field strength (including the case of increasing north polarity). This behavior can be exhibited when using a circuit such as that
shown in Panel B.
BOP
BRP
BHYS
VCC
VOUT
VOUT(SAT)
Switch to Low
Switch to High
B+
B–
V+
0
0
(A) (B)
VCC
VS
Output
GND
VOUT
RL
A121x
Continuous-Time Latch Family
A1210, A1211,
A1212, A1213,
and A1214
10
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Figure 2: Continuous-Time Application, B < BRP
This figure illustrates the use of a quick cycle for chopping VCC in order to conserve battery power. Position 1, power is applied to the
device. Position 2, the output assumes the correct state at a time prior to the maximum Power-On Time, tPO(max). The case shown is where
the correct output state is HIGH
. Position 3, tPO(max) has elapsed. The device output is valid. Position 4, after the output is valid, a control unit
reads the output. Position 5, power is removed from the device.
VCC
VOUT
Output Sampled
1 5 4
2
t
t
t
PO(max)
3
Additional Application Information
Extensive applications information for Hall-effect devices is
available in:
• Hall-Effect IC Applications Guide, Application Note 27701
• Hall-Effect Devices: Gluing, Potting, Encapsulating, Lead
Welding and Lead Forming, Application Note 27703.1
• Soldering Methods for Allegro’s Products – SMT and
Through-Hole, Application Note 26009
All are provided on the Allegro website, www.allegromicro.com.
Continuous-Time Latch Family
A1210, A1211,
A1212, A1213,
and A1214
11
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
POWER DERATING
Power Derating
The device must be operated below the maximum junction
temperature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating sup-
plied power or improving the heat dissipation properties of the
application. This section presents a procedure for correlating
factors affecting operating TJ. (Thermal data is also available on
the Allegro MicroSystems Web site.)
The Package Thermal Resistance, RθJA, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity,
K, of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case, RθJC, is
relatively small component of RθJA. Ambient air temperature,
TA, and air motion are significant external factors, damped by
overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
PD = VIN × IIN (1)
 ΔT = PD × RθJA (2)
TJ = TA + ΔT (3)
For example, given common conditions such as: TA= 25°C,
VCC = 12 V, ICC = 4 mA, and RθJA = 140°C/W, then:
PD = VCC × ICC = 12 V × 4 mA = 48 mW
ΔT = PD × RθJA = 48 mW × 140°C/W = 7°C
TJ = TA + ΔT = 25°C + 7°C = 32°C
A worst-case estimate, PD(max), represents the maximum allow-
able power level (VCC(max), ICC(max)), without exceeding TJ(max),
at a selected RθJA and TA.
Example: Reliability for VCC at TA
=
150°C, package UA, using
minimum-K PCB.
Observe the worst-case ratings for the device, specifically:
RθJA
=
165°C/W, TJ(max) =
165°C, VCC(max)
= 24 V, and
ICC(max) = 7.5 mA.
Calculate the maximum allowable power level, PD(max). First,
invert equation 3:
ΔTmax = TJ(max) – TA = 165°C
–
150°C = 15
°C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
PD(max) = ΔTmax ÷ RθJA = 15°C ÷ 165°C/W = 91 mW
Finally, invert equation 1 with respect to voltage:
VCC(est) = PD(max) ÷ ICC(max) = 91 mW ÷ 7.5 mA = 12.1 V
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤VCC(est).
Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reli-
able operation between VCC(est) and VCC(max) requires enhanced
RθJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and
VCC(max) is reliable under these conditions.
Continuous-Time Latch Family
A1210, A1211,
A1212, A1213,
and A1214
12
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Figure 3: Package LH, 3-Pin SOT-23W
For Reference Only – Not for Tooling Use
(Reference DWG-2840)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A
B
C
D
C
Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Active Area Depth, 0.28 mm
Hall elements, not to scale
= Last three digits of device part numberN
Standard Branding Reference View
NNN
Branding scale and appearance at supplier discretion
Seating Plane
Gauge Plane PCB Layout Reference View
0.55 REF
0.25 BSC
0.95 BSC
0.95
1.00
0.70
2.40
2
1
B
A
Branded Face
2.90+0.10
–0.20
4°±4°
8X 10° REF
0.180+0.020
–0.053
0.05 +0.10
–0.05
0.25 MIN
1.91+0.19
–0.06
2.98+0.12
–0.08
1.00 ±0.13
0.40 ±0.10
D
D
D
1.49
0.96
3
= Last two digits of device part numberN
NNT
= Temperature codeT
PACKAGE OUTLINE DRAWINGS
Continuous-Time Latch Family
A1210, A1211,
A1212, A1213,
and A1214
13
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Figure 4: Package UA, 3-Pin SIP, Matrix Style
For Reference Only – Not for Tooling Use
(Reference DWG-0000404, Rev. 1)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
231
1.27 NOM
1.02 MAX 0.51 MAX
0.79 REF
B
A
B
C
A
D
E
D
E
E
2.04
1.44 E
Branding scale and appearance at supplier discretion
Hall element, not to scale
Mold Ejector
Pin Indent
Branded
Face
4.09+0.08
–0.05
0.41 +0.03
–0.06
3.02+0.08
–0.05
0.43+0.05
–0.07
14.99 ±0.25
Dambar removal protrusion (6×)
Gate and tie bar burr area
Active Area Depth, 0.50 ±0.08 mm
NNN
Standard Branding Reference View
= Supplier emblem
= Last three digits of device part numberN
2 × 45°
C
45°
3 × 10°
1.52 ±0.05
1
NNT
= Supplier emblem
= Last two digits of device part numberN
1
= Temperature codeT
Continuous-Time Latch Family
A1210, A1211,
A1212, A1213,
and A1214
14
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Figure 5: Package UA, 3-Pin SIP, Chopper Style
2 31
0.79 REF
1.27 NOM
2.16
MAX
0.51
REF
45°
C
45°
B
E
E
E
2.04
1.44
Gate burr area
A
B
C
Dambar removal protrusion (6X)
A
D
E
Branding scale and appearance at supplier discretion
Hall element, not to scale
Active Area Depth, 0.50 mm REF
For Reference Only; not for tooling use (reference DWG-9049)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Mold Ejector
Pin Indent
Branded
Face
DStandard Branding Reference View
NNN
1
= Supplier emblem
N = Last two digits of device part number
T = Temperature code
4.09 +0.08
–0.05
0.41 +0.03
–0.06
3.02 +0.08
–0.05
0.43 +0.05
–0.07
15.75 ±0.51
1.52 ±0.05
Continuous-Time Latch Family
A1210, A1211,
A1212, A1213,
and A1214
15
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
For the latest version of this document, visit our website:
www.allegromicro.com
Revision History
Number Date Description
10 May 29, 2012 Update UA package drawing
11 August 20, 2014 Revised Selection Guide, reformatted datasheet
12 January 1, 2015 Added LX option to Selection Guide
13 September 22, 2015 Corrected LH package Active Area Depth value; added AEC-Q100 qualification under
Features and Benefits
14 November 4, 2016 Chopper-style UA package designated as not for new design
15 February 4, 2019 Updated Active Area Depth for UA matrix-style package, and minor editorial updates
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