ML702201MB - OKI Electronic Components

D

ATA

S

HEET

ML7022-01

Single Rail Dual Channel PCM CODEC

August 2000

OKI TELECOMMUNICATIONS PRODUCTS

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Oki Semiconductor

CONTENTS

Description ...............................................................................................................................................................1

Features .....................................................................................................................................................................1

Block Diagram ........................................................................................................................................................2

Pin Conﬁguration (Top View) ............................................................................................................................... 3

Pin List ...................................................................................................................................................................... 4

Pin Functional Description ..................................................................................................................................... 5

Absolute Maximum Ratings ................................................................................................................................. 9

Recommended Operating Conditions .................................................................................................................9

Electrical Characteristics ...................................................................................................................................... 10

Timing Diagrams.................................................................................................................................................... 14

Application Circuits............................................................................................................................................... 17

Recommendations for Design .............................................................................................................................. 18

Package Dimensions.............................................................................................................................................. 19

1Oki Semiconductor

ML7022-01

Dual Channel PCM Line Card CODEC

DESCRIPTION

The ML7022 is a single-rail two-channel DSP CODEC IC for voice telecom line card applications. This

device incorporates dual 3-bit latches to directly control the modes of operation (Borscht functions) of a

complimentary SLIC. This functionality simplifies the design process, and provides a seamless interface

with popular SLICs such as Ericsson’s PBL38630/40 and Intersil’s UniSLIC14.

A parametric performance enhancement is obtained by providing on-chip delta-sigma ADC and DAC

converters to enhance frequency response, signal-to-noise, and idle channel noise. In order to meet

industry system specifications, like Bellcore’s TR-57 for digital-loop carriers (DLC), a proprietary DSP

was developed by Oki engineers for telecom voice applications.

Oki Semiconductor utilizes its advanced 0.45-µm double-poly CMOS process, coupled with a reduced-

footprint 30-pin SSOP package.

FEATURES

• Single 5-V Power Supply Operation

• Using

∆

-

Σ

ADC and DAC Technique

• Low Power Consumption

• ITU-T Companding Law - µ-law

• Built-in Dual 3-bit Latches with CMOS Drive Capability

• Serial PCM Interface

• Master Clock: 4.096 MHz

• Transmission Clocks: 256 to 4096 kbps

• Adjustable Transmit Gain

• Built-in Reference Voltage Supply

• Analog Output can directly drive a 600-

Ω

line transformer

• Echo-back Function enables readback of latch data

• Package Type: 30-pin plastic SSOP (SSOP30-P-56-0.65-K) (Product name: ML7022-01MB)

- 2-Channel Operating Mode Typical: 70 mW Maximum: 90 mW

- 1-Channel Operating Mode Typical: 40 mW Maximum: 55 mW

- Power Saving Mode (CPD1=CPD2=“0”) Typical: 9 mW Maximum: 12.5 mW

- Power Down Mode (PDN=“0”) Typical: 0.05 mW Maximum: 0.25 mW

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2 Oki Semiconductor

BLOCK DIAGRAM

RSYNC

DIN

RCONT

LATCH

BPF

TCONT

XSYNC

BCLK

DOUT

Power Cont.

&

Clock Gen.

Expander

Compressor

C1A

C2A

C3A

C1B

C2B

C3B

BPF

LPF

RC

LPF

Compressor

Expander

RC

LPF

RC

LPF

RC

LPF

AIN1

VDD

AG

DG

SG

GEN.

SGC

GSX1

AIN2

GSX2

AOUT1

AOUT2

MCK

PDN

∑-∆ AD

CONV.

∑-∆ AD

CONV.

∑-∆ AD

CONV.

∑-∆ AD

CONV.

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3Oki Semiconductor

PIN CONFIGURATION (TOP VIEW)

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

30-Pin Plastic SSOP

PDN

C1A

C2A

C3A

RSYNC

XSYNC

DG

DOUT

DIN

BCLK

MCK

C3B

C2B

C1B

TEST6

VDD

TEST1

TEST2

AIN1

GSX1

AOUT1

TEST3

AG

SGC

AOUT2

GSX2

AIN2

TEST4

TEST5

VDD

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4 Oki Semiconductor

PIN LIST

* VDD of pin 1 and VDD of pin 15 are connected internally, but these pins must be connected on the printed circuit board.

Pin Symbol Type Description

1 VDD - Power Supply

2 TEST1 I Device Test Pin 1

3 TEST2 I Device Test Pin 2

4 AIN1 I Channel-1 Transmit Op-amp Input

5 GSX1 O Channel-1 Transmit Op-amp Output

6 AOUT1 O Channel-1 Receive Output

7 TEST3 I Device Test Pin 3

8 AG - Analog Ground

9 SGC O Signal Ground

10 AOUT2 O Channel-2 Receive Output

11 GSX2 O Channel-2 Transmit Op-amp Output

12 AIN2 I Channel-2 Transmit Op-amp Input

13 TEST4 I Device Test Pin 4

14 TEST5 I Device Test Pin 5

15 VDD - Power Supply *

16 TEST6 I Device Test Pin 6

17 C1B O C1B Bit Latched Output

18 C2B O C2B Bit Latched Output

19 C3B O C3B Bit Latched Output

20 MCK I Master Clock (4.096 MHz)

21 BCLK I Shift Clock for the DIN and DOUT

22 DIN I Data Input

23 DOUT O Data Output

24 DG - Digital Ground

25 XSYNC I Transmit Synchronizing Signal

26 RSYNC I Receive Synchronizing Signal

27 C3A O C3A Bit Latched Output

28 C2A O C2A Bit Latched Output

29 C1A O C1A Bit Latched Output

30 PDN I Power Down Control

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5Oki Semiconductor

PIN FUNCTIONAL DESCRIPTION

In the example below, an analog input of 2.26 Vpp is present on the GSX pin, with a digital output of

+3.17 dBm0 (

µ

-law).

Figure 1. Circuit Diagram for Transmit Op-amp Input and Output

AIN1, AIN2, GSX1, GSX2

AIN1 and AIN2 are the transmit analog inputs for Channels 1 and 2.

GSX1 and GSX2 are the transmit level adjustments for Channels 1 and 2.

AIN1 and AIN2 are inverting inputs for the op-amp; GSX1 and GSX2 are connected to the output of the

op-amp and are used to adjust the level, as shown below.

If AIN1 and AIN2 are not used, connect AIN1 to GSX1 and AIN2 to GSX2. During power saving and

power down mode, the GSX1 and GSX2 outputs are at AG voltage.

AOUT1, AOUT2

AOUT1 is the receive analog output for Channel 1 and AOUT2 is used for Channel 2.

The output signal has an amplitude of 3.4 Vpp above and below the signal ground voltage (SG). When

the digital signal of +3.17 dBm0 is input to DIN, it can drive a load of 600

Ω

or more.

During power saving or power down mode, these outputs are at a high impedance.

VDD

Power supply for +5 V.

Connect a bypass capacitor of 0.1

µ

F with excellent high frequency characteristics between this pin and

the AG pin.

Although VDD pin 1 and VDD pin 15 are connected internally, these pins must be connected on the

printed circuit board.

R1

C1

C2

R2

R3

R4

CH1 Gain

Gain = R2 / R1 ≤ 10

R1: Variable

R2 > 20 kΩ

C1 > 1 / (2 x 3.14 x 30 x R1)

CH2

Analog

Input

GSX1

GSX2

AIN2

SG

-

+

CH1

Analog

Input

CH2 Gain

Gain = R4 / R3 ≤ 10

R3: Variable

R4 > 20 kΩ

C1 > 1 / (2 x 3.14 x 30 x R3)

AIN1

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6 Oki Semiconductor

AG

Ground for the analog signal circuits.

DG

Ground for the digital signal circuits.

This ground is separate from the analog signal ground. The DG pin must be connected to the AG pin on

the printed circuit board to make a common analog ground.

SGC

Used to generate the signal ground voltage level, by connecting a bypass capacitor. Connect a 0.1

µ

F

capacitor with excellent high frequency characteristics between the AG pin and the SGC pin.

During power down mode, these outputs are at the voltage level of AG with about 50 k

Ω

impedance.

MCK

Master clock input.

The frequency must be 4.096 MHz.

BCLK

Shift clock signal input for the DIN and DOUT signals.

The frequency, equal to the data rate, is 256 kHz to 4096 kHz. This signal must be synchronized in phase

with the MCK (generated from the same clock source as MCK).

Figure 1

and Figure 2 on page 14 shows

the phase difference of MCK and BCLK.

RSYNC

Receive synchronizing signal input.

Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchro-

nized in phase with the MCK (generated from the same clock source as MCK).

XSYNC

Transmit synchronizing signal input.

The PCM output signal from the DOUT pin is output in synchronization with this transmit synchroniz-

ing signal. This synchronizing signal synchronizes all timing signals of all section. This signal must be

synchronized in phase with the MCK (generated from the same clock source as MCK).

DIN

DIN is a data input pin.

The voice band signal is converted to an analog signal in synchronization with the RSYNC signal and

BCLK. The analog signal of channel 1 is output from AOUT1 pin and the analog signal of channel 2 is

output from AOUT2 pin.

The 28-bit signal structure is shown in

Figure 3

and Figure 4 on page 14. It consists of voice band PCM

signals (8 bits each), the general-purpose latch signal (6 bits total), the power down control signal (1 bit

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7Oki Semiconductor

per channel) and empty bits (4 bits). The signal is shifted at a falling edge of the BCLK signal and latched

into the internal register when shifted by 28 bits.

The start of the PCM data (Channel 1’s MSD) is identified at the rising edge of RSYNC.

The general purpose latch signals (C3A,C2A,C1A,C3B,C2B,C1B) are output from six latch output pins.

When the CPD1 (bit of DIN) =“0”, Channel 1 block is in a power down state. When the CPD2 (bit of DIN)

=“0”, Channel 2 block is in a power down state.

DOUT

DOUT is a data output pin.

The signal consists of a total of 28 bits containing the voice band PCM signals (each channel 8 bits), the

echo bit (6 bits for latch signal and 2 bits for power down state indication), and empty bits (4 bits). The

output coding format follows ITU-T recommendation on coding law.

The output signal is output from Channel 1's MSD bit in a sequential order, synchronizing with the rising

edge of the BCLK signal. The first bit of DOUT may be output at the rising edge of the XSYNC signal,

based on the timing between BCLK and XSYNC.

This pin is in a high impedance state during power down state.

A pull-up resistor must be connected to this pin because it is an open drain output.

C1A, C2A, C3A, C1B, C2B, C3B

General-purpose latched output signal.

C1A, C2A, C3A, C1B, C2B, C3B bits of DIN are latched using internal timing.

These outputs can drive a LSTTL/CMOS device without an external resistor.

PDN

Power down control signal.

When PDN is at logic “0” level, both Channel 1 and Channel 2 circuits are in the power down state.

Also, all internal latches are in initial state (logic “0” level).

TEST1, TEST2, TEST3, TEST4, TEST5, TEST6

These pins are used for device test.

These device test pin must be connected to the AG pin.

Output Coding Format

Input/Output Level

PCMIN / PCMOUT

µ

-law

MSD D2 D3 D4 D5 D6 D7 D8

+ Full scale 1 0000000

+0 1 1111111

-0 0 1111111

- Full scale 0 0000000

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8 Oki Semiconductor

Effect of Power Control on DOUT

PDN CPD1 CPD2 CH1 PCM Data CH2 PCM Data CH1 Echo Bit CH2 Echo Bit

0 0/1 0/1 H H H H

1 0 0 11111111 11111111

Latched data Latched data

1 1 0 Operate 11111111

1 0 1 11111111 Operate

1 1 1 Operate Operate

Effect of Power Control on Latched Output

PDN CPD1 CPD2 Lin C1A, C2A, C3A C1B, C2B, C3B

0 0/1 0/1 0 L L

1 0/1 0/1 0 Latched data Latched data

0/1 0/1 0/1 1 L L

Effect of Power Control on Analog Output

PDN CPD1 CPD2 GSX1 GSX2 AOUT1 AOUT2 SGC

0 0/1 0/1 High impedance High impedance High impedance High impedance

[1]

1. The voltage level of AG with about 50 k

Ω

1 0 0 High impedance High impedance High impedance High impedance Operate

1 1 0 Operate High impedance Operate High impedance Operate

1 0 1 High impedance Operate High impedance Operate Operate

1 1 1 Operate Operate Operate Operate Operate

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9Oki Semiconductor

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Condition Rating Unit

Power Supply Voltage V

DD

- -0.3 to +7.0 V

Analog Input Voltage V

AIN

- -0.3 to VDD+0.3 V

Digital Input Voltage V

DIN

- -0.3 to VDD+0.3 V

Storage Temperature T

STG

- -55 to +150

°

C

Parameter Symbol Condition Min Typ Max Unit

Power Supply Voltage V

DD

Voltage must be fixed 4.75 5.0 5.25 V

Operating Temperature T

OP

- -40 - +85

°

C

Analog Input Voltage V

AIN

Gain=1 - - 3.4 V

PP

High Level Input Voltage V

IH

All Digital Input Pins 2.2 - VDD V

Low Level Input Voltage V

IL

0 - 0.8 V

MCK Frequency F

MCK

MCK -0.01% 4096 +0.01% kHz

BCLK Frequency F

BCLK

BCLK 256 - 4096 kHz

Sync Pulse Frequency F

SYNC

XSYNC, RSYNC - 8 - kHz

Clock Duty Ratio D

CLK

MCK, BCLK 40 50 60 %

Digital Input Rise Time T

IR

All Digital Input Pins

-

- 50 ns

Digital Input Fall Time T

IF

-

- 50 ns

MCK to BCLK Phase Difference T

MB

MCK, BCLK - - 50 ns

Transmit Sync Pulse Setting Time T

XS

BCLK to XSYNC 50 - - ns

T

SX

XSYNC to BCLK 50 - - ns

Receive Sync Pulse Setting Time T

RS

BCLK to RSYNC 50 - - ns

T

SR

RSYNC to BCLK 50 - - ns

Sync Pulse Width T

WS

XSYNC, RSYNC 1 BCLK

-

100

µ

s

DIN Set-up Time T

DS

DIN 50 - - ns

DIN Hold Time T

DH

DIN 50 - - ns

Digital Output Load R

DL

Pull-up Resistor, DOUT 0.5 - - k

Ω

C

DL

DOUT - - 50 pF

Digital Output Load C1A, C2A, C3A,C1B, C2B, C3B

-

- 50 pF

Bypass Capacitor for SGC C

SG

SG to AG 0.1 - -

µ

F

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10 Oki Semiconductor

ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics

VDD = 4.75 to 5.25 V, Ta = -40 to +85

°

C

Parameter Symbol Condition Min Typ Max Unit

Power Supply Current

IDD1 2CH Operating Mode, No Signal

PDN=“1”, CPD1=CPD2=“1”

- 14.0 18.0 mA

IDD2 1CH Operating Mode, No Signal

PDN=“1”, CPD1=“1”, CPD2=“0”

or

PDN=“1”, CPD1=“0”, CPD2=“1”

- 8.0 11.0 mA

IDD3 Power Saving Mode

PDN=“1”, CPD1=CPD2=“0”

- 1.8 2.5 mA

IDD4 Power Down Mode

PDN=“0”

- 0.01 0.05 mA

High Level Input Leakage Current IIH All Digital Input Pins VI=VDD - - 2.0 µA

Low Level Input Leakage Current IIL All Digital Input Pins VI=0V - - 0.5 µA

Digital Output Low Voltage

VOL DOUT, Pull-up=0.5 kΩ0 0.2 0.4 V

C1A, C2A, C3A, C1B, C2B, C3B

IOL=0.4 mA

0 0.2 0.4 V

Digital Output High Voltage

VOH C1A, C2A, C3A, C1B, C2B, C3B

IOH=0.4 mA

2.5 - - V

C1A, C2A, C3A, C1B, C2B, C3B

IOH=50 µA

VDD-0.5 - - V

Digital Output Leakage Current IODOUT High Impedance State - - - 10 µA

Input Capacitance CIN --5-pF

Analog Interface Characteristics

VDD = 4.75 to 5.25 V, Ta = -40 to +85°C

Parameter Symbol Condition Min Typ Max Unit

SGC Rise Time TSGC SG to AG 0.1 µF

Rise time to 90% of max. level

-- 10 ms

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11Oki Semiconductor

Transmit Analog Interface Characteristics

VDD = 4.75 to 5.25 V, Ta = -40 to +85°C

Parameter Symbol Condition Min Typ Max Unit

Input Resistance RINX AIN1, AIN2 10 - - MΩ

Output Load Resistance RLGX 1. GSX1, GSX2 with respect to SG.

2. 0.27 dBm (600 Ω) = 3.17 dBm0

(µ-law) = 2.26 VPP

20 - - kΩ

Output Load Capacitance CLGX - - 30 pF

Output Amplitude VOGX -1.13 - 1.13 V

Offset Voltage VOSGX

1. GSX1, GSX2 with respect to SG.

2. 0.27 dBm (600 Ω) = 3.17 dBm0

(µ-law) = 2.26 VPP

3. Gain = 1

-20 - 20 mV

Receive Analog Interface Characteristics

VDD = 4.75 to 5.25 V, Ta = -40 to +85°C

Parameter Symbol Condition Min Typ Max Unit

Output Load Resistance RLAO AOUT1, AOUT2 (each)

with respect to SG

0.6 - kΩ

Output Load Capacitance CLAO AOUT1, AOUT2 - 50 pF

Output Amplitude VOAO AOUT1, AOUT2, RLAO=0.6 kΩ

with respect to SGO

-1.7 - 1.7 V

Offset Voltage VOSAO AOUT1, AOUT2

with respect to SG

-100 - 100 mV

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12 Oki Semiconductor

AC Characteristics

(VDD = 4.75 to 5.25 V, Ta = -40 to +85°C)

Parameter Symbol

Freq

(Hz)

Level

(dBm0) Condition Min Typ Max Unit

Transmit

Frequency Response

Loss T1 60

0

GSXn to DOUT (Attenuation)

25 45 -

dB

Loss T2 300 -0.15 0.15 0.20

Loss T3 1020 Reference

Loss T4 3000 -0.15 0.02 0.20

Loss T5 3300 -0.15 0.1 0.80

Loss T6 3400 0 0.6 0.80

Receive

Frequency Response

Loss R1 100

0 DIN to AOUTn (Attenuation)

-0.15 0.04 0.2

dB

Loss R2 1020 Reference

Loss R3 3000 -0.15 0.07 0.2

Loss R4 3300 -0.15 0.2 0.8

Loss R5 3400 0 0.6 0.8

Transmit Signal to Distortion Ratio

SDT1

1020

3

GSXn to DOUT (Attenuation)

(C-message Filter is used)

36 43 -

dB

SDT2 03640-

SDT3 -30 36 38 -

SDT4 -40 30 32 -

SDT5 -45 25 29 -

Receive Signal to Distortion Ratio

SDR1

1020

3

DIN to AOUTn (Attenuation)

(C-message Filter is used)

36 42 -

dB

SDR2 03639-

SDR3 -30 36 39 -

SDR4 -40 30 33 -

SDR5 -45 25 30 -

Transmit Gain Tracking

GTT1

1020

3

GSXn to DOUT

-0.2 0.02 0.2

dB

GTT2 -10 Reference

GTT3 -40 -0.2 0.06 0.2

GTT4 -50 -0.6 0.4 0.6

GTT5 -55 -1.2 0.4 1.2

Receive Gain Tracking

GTR1

1020

3

DIN to AOUTn

-0.2 0 0.2

dB

GTR2 -10 Reference

GTR3 -40 -0.2 -0.02 0.2

GTR4 -50 -0.6 -0.1 0.6

GTR5 -55 -1.2 -0.2 1.2

Idle Channel Noise

NIDLET- - AINn = SG (C-message Filter is used)

AINn to DOUT

-1416

dBmc0

NIDLER- - DIN = 0 code (C-message Filter is used)

DIN to AOUTn

-610

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13Oki Semiconductor

Absolute Level (Initial Difference)

AVT1020

0

GSXn to DOUT

Vdd=5 V, Ta = 25°C

0.535 0.555 0.574

Vrms

AVR1020 DIN to AOUTn

Vdd=5 V, Ta = 25°C

0.806 0.835 0.864

Absolute Level

(Deviation of temperature and power)

AVTT 1020

0

Vdd=4.75 to 5.25 V

Ta = -40 to 85°C

-0.3 - 0.3

Vrms

AVRT 1020 -0.3 - 0.3

Absolute Delay TD1020 0 A to A Mode

BCLK = 2048 kHz

- 0.58 0.6 ms

Transmit Group Delay

TGD T1 500

0 Minimum value of the group delay

distortion

- 0.26 0.75

ms

TGD T2 600 - 0.16 0.35

TGD T3 1000 - 0.02 0.125

TGD T4 2600 - 0.05 0.125

TGD T5 2800 - 0.07 0.75

Receive Group Delay

TGD R1 500

0 Minimum value of the group delay

distortion

- 0.00 0.75

ms

TGD R2 600 - 0.00 0.35

TGD R3 1000 - 0.00 0.125

TGD R4 2600 - 0.09 0.125

TGD R5 2800 - 0.12 0.75

Cross Talk Attenuation

CRT 1020

0

Trans to Receive 75 83 -

dB

CRR Receive to Trans 75 80 -

CRCH Channel to Channel 75 78 -

Discrimination DIS

4.6 k to 72 k

0 0 to 4 kHz 30 32 - dB

Out of Band Spurious OBS

300 to 3.4 k

0 4.6 kHz to 1000 kHz - -37.5 -35 dB

Signal Frequency

Distortion

SFDT1020

0 0 to 4 kHz

- -50 -40 dBm0

SFDR - -48 -40

Intermodulation

Distortion

IMDTfa=470

fb=320 -4 2 fa - fb

- -50 -40

dBm0

IMDR- -54 -40

Power Supply Noise

Rejection Ratio

PSRT1 0 to 4 k

100

mVrms

The measurement under idle channel

noise

40 44 -

dB

PSRT2 4 k to 50 k 50 55 -

PSRR1 0 to 4 k 40 45 -

PSRR2 4 k to 50 k 50 56 -

Digital Output Delay Time

TSD DOUT

Pull-up resistor = 0.5 kΩ

CL = 50 pF and 1 LSTTL

20 - 100

ns

TXD1 20 - 100

TXD2 20 - 100

TPDC C1A, C2A, C3A, C1B, C2B, C3B; CL = 50 pF and 1 LSTTL 20 - 1000

DOUT Operation Delay Time TDDO Time of operation start after power on - 4 - ms

AOUT Signal Output Delay Time TDAO Time of base band signal output start after power on - 4 - ms

AC Characteristics (Continued)

(VDD = 4.75 to 5.25 V, Ta = -40 to +85°C)

Parameter Symbol

Freq

(Hz)

Level

(dBm0) Condition Min Typ Max Unit

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14 Oki Semiconductor

TIMING DIAGRAMS

Figure 2. Transmit Side Timing Diagram

Figure 3. Receive Side Timing Diagram

Figure 4. Transmit Side Bit Conﬁguration

Figure 5. Receive Side Bit Conﬁguration

MCK

BCLK

XSYNC

DOUT

TXS

D2

123 45678

TSX

TXD1 TSD

D3 D4D5 D6 D7 D8MSD

TWS

TXD2

TMB

MCK

BCLK

RSYNC

DIN

TRS

D2

12345678

TSR

TDS

TWS

TDH

D3 D4 D5MSD D6 D7 D8

TMB

191725 1

BCLK

XSYNC

DOUT

MSD

D2

D3

D4

D5

D6

D7

D8

EPD1

EC3A

EC2A

EC1A

MSD

D2

D3

D4

D5

D6

D7

D8

EPD2

EC3B

EC2B

EC1B

MSD

D2

D3

ECHO bits

CH2 PCM Data

ECHO bitsCH1 PCM Data

1 9 17 25 1

MSD

D2

D3

D4

D5

D6

D7

D8

CPD1

C3A

C2A

C1A

MSD

D2

D3

D4

D5

D6

D7

D8

CPD2

C3B

C2B

C1B

BCLK

XSYNC

DOUT

MSD

D2

D3

CH2 PCM Data

CH1 PCM Data Latch Data Latch Data

CH2 power down control bit

CH1 power down control bit

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15Oki Semiconductor

Figure 6. Control Bit Timing and Echo Back Timing

MSD

D2

D3

D4

D5

D6

D7

D8

CP D1

C3A

C2A

C1A

MSD

D2

D3

D4

D5

D6

D7

D8

CP D2

C3B

C2B

C1B

MSD

D2

D3

D4

D5

D6

D7

D8

CP D1

C3A

C2A

C1A

MSD

D2

D3

D4

D5

D6

D7

D8

CP D2

C3B

C2B

C1B

MSD

D2

D3

D4

D5

D6

D7

D8

MSD

D2

D3

D4

D5

D6

D7

D8

MSD

D2

D3

D4

D5

D6

D7

D8

MSD

D2

D3

D4

D5

D6

D7

D8

EPD2

EC 3B

EC 2B

EC 1B

XSYNC

RSYNC

DIN

DOUT

C3A, C2A

C1A, C3B

C2B, C1B

BCLK

91725 1 917251

CH1 PCM

Output Data

Echo

Bit

CH2 PCM

Output Data

Echo

Bit

CH2 PCM

Output Data

Echo

Bit

CH1 PCM

Output Data

Echo

Bit

TPDC

CH2 PCM

Input Data

CH1 PCM

Input Data

CH2 PCM

Input Data

CH1 PCM

Input Data

Control

Data

Control

Data

Control

Data

Control

Data

TPDC

EPD1

EC 3A

EC 2A

EC 1A

EPD2

EC 3B

EC 2B

EC 1B

EPD1

EC 3A

EC 2A

EC 1A

■ ML7022-01 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

16 Oki Semiconductor

Figure 7. SGC, DOUT, and AOUT Output Timing

TDAO

SGC

DOUT

AOUTn

PDN

TDDO

TSGC

SG Level

High Impedance

CPD1

(CPD2)

––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ ML7022-01 ■

17Oki Semiconductor

APPLICATION CIRCUIT

AIN1

GSX1

AOUT1

AIN2

GSX2

AOUT2

SGC

AG

DG

VDD

DOUT

DIN

MCK

BCLK

XSYNC

RSYNC

PDN

TEST1

TEST2

TEST3

TEST4

TEST5

TEST6

C1A

C2A

C3A

C1B

C2B

C3B

0.1 µF

Channel 1

Analog Input

Channel 2

Analog Input

Channel 2

Analog Output

Channel 1

Analog Output

0.1 µF

2 CH Multiplex PCM Signal Output

1 µF

0 V

+ 5 V +

2 CH Multiplex PCM Signal Input

Master Clock and Bit Clock Input

Power Down Control

0 : Power Down / 1 : Operation

+ 5 V

1 kΩ

ML7022

Latch Output

■ ML7022-01 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

18 Oki Semiconductor

RECOMMENDATIONS FOR DESIGN

• To assure specified electrical characteristics, use bypass capacitors with excellent high frequency

characteristics for the power supply and keep them as close as possible to the device pins. Connect

the AG pin and DG pin to each other as closely as possible. Connect to the system ground with low

impedance.

• A short lead type socket must be used.

• When mounted on a frame, use electromagnetic shielding, if any electromagnetic emission sources

such as power supply transformers surround the device.

• Keep the voltage on the VDD pin not lower than -0.3 V even instantaneously to avoid latch-up

phenomenon when turning the power on.

• Use a low noise power supply (having low level high frequency spike noise or pulse noise) to avoid

erroneous operation and the degradation of the characteristics of these device.

––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ ML7022-01 ■

19Oki Semiconductor

PACKAGE DIMENSIONS

(Units: mm)

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very

susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform

reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin num-

ber, package code and desired mounting conditions (reflow method, temperature and times).

SSOP30-P-56-0.65-K

Package material

Lead frame material

Pin treatment

Solder plate thickness

Package weight (g)

Epoxy resin

42 alloy

Solder plating

5 µm or more

0.19 TYP.

Mirror finish

■ ML7022-01 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

20 Oki Semiconductor

Notes

Oki Semiconductor

The information contained herein can change without notice owing to product and/or technical improvements.

Please make sure before using the product that the information you are referring to is up-to-date.

The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action

and performance of the product. When you actually plan to use the product, please ensure that the outside conditions are reflected in

the actual circuit and assembly designs.

Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect,

improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited

to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range.

Neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in connection with

the use of product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a

third party's right which may result from the use thereof.

When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges,

including but not limited to operating voltage, power dissipation, and operating temperature.

The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,office

automation, communication equipment, measurement equipment, consumer electronics, etc.).These products are not authorized for

use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application

where the failure of such system or application may result in the loss or damage of property or death or injury to humans. Such

applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, including

life support and maintenance.

Certain parts in this document may need governmental approval before they can be exported to certain countries. The purchaser

assumes the responsibility of determining the legality of export of these parts and will take appropriate and necessary steps, at their

own expense, for export to another country.

Oki Semiconductor reserves the right to make changes in specifications at anytime and without notice. This information furnished by

Oki Semiconductor in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Oki

Semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. No license is

granted under any patents or patent rights of Oki.

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