DATA SHEET O K I T E L E C O M M U N I C A T I O N S P R O D U C T S ML7022-01 Single Rail Dual Channel PCM CODEC August 2000 ------------------------------------------------------------------------------------------- CONTENTS Description ...............................................................................................................................................................1 Features .....................................................................................................................................................................1 Block Diagram ........................................................................................................................................................2 Pin Configuration (Top View) ............................................................................................................................... 3 Pin List ...................................................................................................................................................................... 4 Pin Functional Description ..................................................................................................................................... 5 Absolute Maximum Ratings ................................................................................................................................. 9 Recommended Operating Conditions .................................................................................................................9 Electrical Characteristics ...................................................................................................................................... 10 Timing Diagrams.................................................................................................................................................... 14 Application Circuits............................................................................................................................................... 17 Recommendations for Design .............................................................................................................................. 18 Package Dimensions.............................................................................................................................................. 19 Oki Semiconductor ML7022-01 Dual Channel PCM Line Card CODEC DESCRIPTION The ML7022 is a single-rail two-channel DSP CODEC IC for voice telecom line card applications. This device incorporates dual 3-bit latches to directly control the modes of operation (Borscht functions) of a complimentary SLIC. This functionality simplifies the design process, and provides a seamless interface with popular SLICs such as Ericsson's PBL38630/40 and Intersil's UniSLIC14. A parametric performance enhancement is obtained by providing on-chip delta-sigma ADC and DAC converters to enhance frequency response, signal-to-noise, and idle channel noise. In order to meet industry system specifications, like Bellcore's TR-57 for digital-loop carriers (DLC), a proprietary DSP was developed by Oki engineers for telecom voice applications. Oki Semiconductor utilizes its advanced 0.45-m double-poly CMOS process, coupled with a reducedfootprint 30-pin SSOP package. FEATURES * Single 5-V Power Supply Operation * Using - ADC and DAC Technique * Low Power Consumption - 2-Channel Operating Mode - 1-Channel Operating Mode - Power Saving Mode (CPD1=CPD2="0") - Power Down Mode (PDN="0") * * * * * * * * * * Typical: Typical: Typical: Typical: 70 mW 40 mW 9 mW 0.05 mW Maximum: Maximum: Maximum: Maximum: 90 mW 55 mW 12.5 mW 0.25 mW ITU-T Companding Law - -law Built-in Dual 3-bit Latches with CMOS Drive Capability Serial PCM Interface Master Clock: 4.096 MHz Transmission Clocks: 256 to 4096 kbps Adjustable Transmit Gain Built-in Reference Voltage Supply Analog Output can directly drive a 600- line transformer Echo-back Function enables readback of latch data Package Type: 30-pin plastic SSOP (SSOP30-P-56-0.65-K) (Product name: ML7022-01MB) Oki Semiconductor 1 2 Oki Semiconductor VDD AG DG SGC AOUT2 AOUT1 GSX2 AIN2 GSX1 AIN1 SG GEN. LPF LPF - AD CONV. RC LPF BPF BPF - AD CONV. - AD CONV. - AD CONV. RC LPF RC LPF RC LPF Power Cont. & Clock Gen. Expander Expander Compressor Compressor LATCH RCONT TCONT DIN RSYNC BCLK XSYNC DOUT ML7022-01 ---------------------------------------------------------------------------------- BLOCK DIAGRAM C1A C2A C3A C1B C2B C3B PDN MCK --------------------------------------------------------------------------------- ML7022-01 PIN CONFIGURATION (TOP VIEW) VDD 1 30 PDN TEST1 2 29 C1A TEST2 3 28 C2A AIN1 4 27 C3A GSX1 5 26 RSYNC AOUT1 6 25 XSYNC TEST3 7 24 DG AG 8 23 DOUT SGC 9 22 DIN AOUT2 10 21 BCLK GSX2 11 20 MCK AIN2 12 19 C3B TEST4 13 18 C2B TEST5 14 17 C1B VDD 15 16 TEST6 30-Pin Plastic SSOP Oki Semiconductor 3 ML7022-01 ---------------------------------------------------------------------------------- PIN LIST Pin Symbol Type 1 VDD - Power Supply 2 TEST1 I Device Test Pin 1 3 TEST2 I Device Test Pin 2 4 AIN1 I Channel-1 Transmit Op-amp Input 5 GSX1 O Channel-1 Transmit Op-amp Output 6 AOUT1 O Channel-1 Receive Output 7 TEST3 I Device Test Pin 3 8 AG - Analog Ground 9 SGC O Signal Ground 10 AOUT2 O Channel-2 Receive Output 11 GSX2 O Channel-2 Transmit Op-amp Output 12 AIN2 I Channel-2 Transmit Op-amp Input 13 TEST4 I Device Test Pin 4 14 TEST5 I Device Test Pin 5 15 VDD - Power Supply * 16 TEST6 I Device Test Pin 6 17 C1B O C1B Bit Latched Output 18 C2B O C2B Bit Latched Output 19 C3B O C3B Bit Latched Output 20 MCK I Master Clock (4.096 MHz) 21 BCLK I Shift Clock for the DIN and DOUT 22 DIN I Data Input 23 DOUT O Data Output 24 DG - Digital Ground 25 XSYNC I Transmit Synchronizing Signal 26 RSYNC I Receive Synchronizing Signal 27 C3A O C3A Bit Latched Output 28 C2A O C2A Bit Latched Output 29 C1A O C1A Bit Latched Output 30 PDN I Power Down Control Description * VDD of pin 1 and VDD of pin 15 are connected internally, but these pins must be connected on the printed circuit board. 4 Oki Semiconductor --------------------------------------------------------------------------------- ML7022-01 PIN FUNCTIONAL DESCRIPTION In the example below, an analog input of 2.26 Vpp is present on the GSX pin, with a digital output of +3.17 dBm0 (-law). GSX1 R2 CH1 Analog Input AIN1 - C1 + R1 CH1 Gain Gain = R2 / R1 10 R1: Variable R2 > 20 k C1 > 1 / (2 x 3.14 x 30 x R1) SG GSX2 R4 CH2 Analog Input AIN2 - C2 + R3 CH2 Gain Gain = R4 / R3 10 R3: Variable R4 > 20 k C1 > 1 / (2 x 3.14 x 30 x R3) SG Figure 1. Circuit Diagram for Transmit Op-amp Input and Output AIN1, AIN2, GSX1, GSX2 AIN1 and AIN2 are the transmit analog inputs for Channels 1 and 2. GSX1 and GSX2 are the transmit level adjustments for Channels 1 and 2. AIN1 and AIN2 are inverting inputs for the op-amp; GSX1 and GSX2 are connected to the output of the op-amp and are used to adjust the level, as shown below. If AIN1 and AIN2 are not used, connect AIN1 to GSX1 and AIN2 to GSX2. During power saving and power down mode, the GSX1 and GSX2 outputs are at AG voltage. AOUT1, AOUT2 AOUT1 is the receive analog output for Channel 1 and AOUT2 is used for Channel 2. The output signal has an amplitude of 3.4 Vpp above and below the signal ground voltage (SG). When the digital signal of +3.17 dBm0 is input to DIN, it can drive a load of 600 or more. During power saving or power down mode, these outputs are at a high impedance. VDD Power supply for +5 V. Connect a bypass capacitor of 0.1 F with excellent high frequency characteristics between this pin and the AG pin. Although VDD pin 1 and VDD pin 15 are connected internally, these pins must be connected on the printed circuit board. Oki Semiconductor 5 ML7022-01 ---------------------------------------------------------------------------------- AG Ground for the analog signal circuits. DG Ground for the digital signal circuits. This ground is separate from the analog signal ground. The DG pin must be connected to the AG pin on the printed circuit board to make a common analog ground. SGC Used to generate the signal ground voltage level, by connecting a bypass capacitor. Connect a 0.1 F capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. During power down mode, these outputs are at the voltage level of AG with about 50 k impedance. MCK Master clock input. The frequency must be 4.096 MHz. BCLK Shift clock signal input for the DIN and DOUT signals. The frequency, equal to the data rate, is 256 kHz to 4096 kHz. This signal must be synchronized in phase with the MCK (generated from the same clock source as MCK). Figure 1 and Figure 2 on page 14 shows the phase difference of MCK and BCLK. RSYNC Receive synchronizing signal input. Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the MCK (generated from the same clock source as MCK). XSYNC Transmit synchronizing signal input. The PCM output signal from the DOUT pin is output in synchronization with this transmit synchronizing signal. This synchronizing signal synchronizes all timing signals of all section. This signal must be synchronized in phase with the MCK (generated from the same clock source as MCK). DIN DIN is a data input pin. The voice band signal is converted to an analog signal in synchronization with the RSYNC signal and BCLK. The analog signal of channel 1 is output from AOUT1 pin and the analog signal of channel 2 is output from AOUT2 pin. The 28-bit signal structure is shown in Figure 3 and Figure 4 on page 14. It consists of voice band PCM signals (8 bits each), the general-purpose latch signal (6 bits total), the power down control signal (1 bit 6 Oki Semiconductor --------------------------------------------------------------------------------- ML7022-01 per channel) and empty bits (4 bits). The signal is shifted at a falling edge of the BCLK signal and latched into the internal register when shifted by 28 bits. The start of the PCM data (Channel 1's MSD) is identified at the rising edge of RSYNC. The general purpose latch signals (C3A,C2A,C1A,C3B,C2B,C1B) are output from six latch output pins. When the CPD1 (bit of DIN) ="0", Channel 1 block is in a power down state. When the CPD2 (bit of DIN) ="0", Channel 2 block is in a power down state. DOUT DOUT is a data output pin. The signal consists of a total of 28 bits containing the voice band PCM signals (each channel 8 bits), the echo bit (6 bits for latch signal and 2 bits for power down state indication), and empty bits (4 bits). The output coding format follows ITU-T recommendation on coding law. The output signal is output from Channel 1's MSD bit in a sequential order, synchronizing with the rising edge of the BCLK signal. The first bit of DOUT may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state during power down state. A pull-up resistor must be connected to this pin because it is an open drain output. Output Coding Format PCMIN / PCMOUT -law Input/Output Level MSD D2 D3 D4 D5 D6 D7 + Full scale 1 0 0 0 0 0 0 0 +0 1 1 1 1 1 1 1 1 -0 0 1 1 1 1 1 1 1 - Full scale 0 0 0 0 0 0 0 0 D8 C1A, C2A, C3A, C1B, C2B, C3B General-purpose latched output signal. C1A, C2A, C3A, C1B, C2B, C3B bits of DIN are latched using internal timing. These outputs can drive a LSTTL/CMOS device without an external resistor. PDN Power down control signal. When PDN is at logic "0" level, both Channel 1 and Channel 2 circuits are in the power down state. Also, all internal latches are in initial state (logic "0" level). TEST1, TEST2, TEST3, TEST4, TEST5, TEST6 These pins are used for device test. These device test pin must be connected to the AG pin. Oki Semiconductor 7 ML7022-01 ---------------------------------------------------------------------------------- Effect of Power Control on DOUT PDN CPD1 CPD2 CH1 PCM Data CH2 PCM Data CH1 Echo Bit CH2 Echo Bit 0 0/1 0/1 H H H H 1 0 0 11111111 11111111 1 1 0 Operate 11111111 1 0 1 11111111 Operate Latched data Latched data 1 1 1 Operate Operate Effect of Power Control on Latched Output PDN CPD1 CPD2 Lin C1A, C2A, C3A 0 0/1 0/1 0 L L 1 0/1 0/1 0 Latched data Latched data 0/1 0/1 0/1 1 L L C1B, C2B, C3B Effect of Power Control on Analog Output PDN CPD1 CPD2 GSX1 GSX2 AOUT1 0 0/1 0/1 High impedance High impedance High impedance 1 0 0 High impedance High impedance High impedance High impedance Operate 1 1 0 Operate High impedance Operate High impedance Operate 1 0 1 High impedance Operate High impedance Operate Operate 1 1 1 Operate Operate Operate Operate Operate 1. The voltage level of AG with about 50 k 8 Oki Semiconductor AOUT2 High impedance SGC [1] --------------------------------------------------------------------------------- ML7022-01 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Power Supply Voltage VDD - -0.3 to +7.0 Analog Input Voltage VAIN - -0.3 to VDD+0.3 V V Digital Input Voltage VDIN - -0.3 to VDD+0.3 V Storage Temperature TSTG - -55 to +150 C RECOMMENDED OPERATING CONDITIONS Parameter Condition Min Typ Max Power Supply Voltage Symbol VDD Voltage must be fixed 4.75 5.0 5.25 V Operating Temperature TOP - -40 - +85 C Analog Input Voltage VAIN Gain=1 - - 3.4 VPP High Level Input Voltage VIH All Digital Input Pins V Low Level Input Voltage VIL 2.2 - VDD 0 - 0.8 V Unit MCK Frequency FMCK MCK -0.01% 4096 +0.01% kHz BCLK Frequency FBCLK BCLK 256 - 4096 kHz Sync Pulse Frequency FSYNC XSYNC, RSYNC kHz Clock Duty Ratio DCLK MCK, BCLK All Digital Input Pins - 8 - 40 50 60 % - - 50 ns - 50 ns ns Digital Input Rise Time TIR Digital Input Fall Time TIF MCK to BCLK Phase Difference TMB MCK, BCLK - - 50 Transmit Sync Pulse Setting Time TXS BCLK to XSYNC 50 - - ns TSX XSYNC to BCLK 50 - - ns Receive Sync Pulse Setting Time TRS BCLK to RSYNC 50 - - ns TSR RSYNC to BCLK 50 - - ns Sync Pulse Width TWS XSYNC, RSYNC 1 BCLK - 100 s DIN Set-up Time TDS DIN 50 - - ns DIN Hold Time TDH DIN 50 - - ns Digital Output Load RDL Pull-up Resistor, DOUT 0.5 - - k CDL DOUT - - 50 pF C1A, C2A, C3A,C1B, C2B, C3B - - 50 pF 0.1 - - F Digital Output Load Bypass Capacitor for SGC CSG SG to AG Oki Semiconductor 9 ML7022-01 ---------------------------------------------------------------------------------- ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics VDD = 4.75 to 5.25 V, Ta = -40 to +85C Symbol Parameter Min Typ Max Unit IDD1 2CH Operating Mode, No Signal PDN="1", CPD1=CPD2="1" - 14.0 18.0 mA IDD2 1CH Operating Mode, No Signal PDN="1", CPD1="1", CPD2="0" or PDN="1", CPD1="0", CPD2="1" - 8.0 11.0 mA IDD3 Power Saving Mode PDN="1", CPD1=CPD2="0" - 1.8 2.5 mA IDD4 Power Down Mode PDN="0" - 0.01 0.05 mA Power Supply Current Condition High Level Input Leakage Current IIH All Digital Input Pins VI=VDD - - 2.0 A Low Level Input Leakage Current IIL All Digital Input Pins VI=0V - - 0.5 A VOL DOUT, Pull-up=0.5 k 0 0.2 0.4 V C1A, C2A, C3A, C1B, C2B, C3B 0 0.2 0.4 V 2.5 - - V VDD-0.5 - - V Digital Output Low Voltage IOL=0.4 mA VOH C1A, C2A, C3A, C1B, C2B, C3B IOH=0.4 mA Digital Output High Voltage C1A, C2A, C3A, C1B, C2B, C3B IOH=50 A Digital Output Leakage Current IO DOUT High Impedance State - - - 10 A Input Capacitance CIN - - 5 - pF Min Typ Max Unit 10 ms Analog Interface Characteristics VDD = 4.75 to 5.25 V, Ta = -40 to +85C Parameter Symbol SGC Rise Time 10 Oki Semiconductor TSGC Condition SG to AG 0.1 F Rise time to 90% of max. level -- --------------------------------------------------------------------------------- ML7022-01 Transmit Analog Interface Characteristics VDD = 4.75 to 5.25 V, Ta = -40 to +85C Parameter Symbol Condition Min Typ Max Unit Input Resistance RINX AIN1, AIN2 10 - - M Output Load Resistance RLGX 20 - - k Output Load Capacitance CLGX - - 30 pF Output Amplitude VOGX 1. GSX1, GSX2 with respect to SG. 2. 0.27 dBm (600 ) = 3.17 dBm0 (-law) = 2.26 VPP -1.13 - 1.13 V Offset Voltage VOSGX -20 - 20 mV Max Unit 1. GSX1, GSX2 with respect to SG. 2. 0.27 dBm (600 ) = 3.17 dBm0 (-law) = 2.26 VPP 3. Gain = 1 Receive Analog Interface Characteristics VDD = 4.75 to 5.25 V, Ta = -40 to +85C Parameter Output Load Resistance Symbol Condition Min Typ RLAO AOUT1, AOUT2 (each) with respect to SG 0.6 - k Output Load Capacitance CLAO AOUT1, AOUT2 - 50 pF Output Amplitude VOAO AOUT1, AOUT2, RLAO=0.6 k with respect to SGO -1.7 - 1.7 V Offset Voltage VOSAO AOUT1, AOUT2 with respect to SG -100 - 100 mV Oki Semiconductor 11 ML7022-01 ---------------------------------------------------------------------------------- AC Characteristics (VDD = 4.75 to 5.25 V, Ta = -40 to +85C) Parameter Transmit Frequency Response Receive Frequency Response Transmit Signal to Distortion Ratio Receive Signal to Distortion Ratio Transmit Gain Tracking Symbol Freq (Hz) Min Typ Max Loss T1 60 25 45 - Loss T2 300 -0.15 0.15 0.20 Loss T3 1020 Loss T4 3000 Loss T5 3300 -0.15 0.1 0.80 Loss T6 3400 0 0.6 0.80 Loss R1 100 -0.15 0.04 0.2 Loss R2 1020 Loss R3 3000 Idle Channel Noise 12 Oki Semiconductor Condition 0 GSXn to DOUT (Attenuation) -0.15 0.02 0.20 0.07 0.2 Loss R4 -0.15 0.2 0.8 Loss R5 3400 0 0.6 0.8 0 DIN to AOUTn (Attenuation) SDT1 3 36 43 - SDT2 0 36 40 - 36 38 - 30 32 - SDT3 GSXn to DOUT (Attenuation) -30 (C-message Filter is used) SDT4 -40 SDT5 -45 25 29 - SDR1 3 36 42 - 36 39 - 36 39 - 30 33 - SDR2 0 SDR3 -30 1020 DIN to AOUTn (Attenuation) (C-message Filter is used) SDR4 -40 SDR5 -45 25 30 - GTT1 3 -0.2 0.02 0.2 GTT2 -10 GTT3 1020 -40 0.06 0.2 -0.6 0.4 0.6 -55 -1.2 0.4 1.2 3 -0.2 0 0.2 -50 GTT5 GTR1 GSXn to DOUT -10 -40 dB dB dB Reference -0.2 -0.02 0.2 GTR4 -50 -0.6 -0.1 0.6 GTR5 -55 -1.2 -0.2 1.2 1020 dB Reference -0.2 GTT4 GTR3 dB Reference 3300 1020 Unit Reference -0.15 GTR2 Receive Gain Tracking Level (dBm0) DIN to AOUTn NIDLET - - AINn = SG (C-message Filter is used) AINn to DOUT - 14 16 NIDLER - - DIN = 0 code (C-message Filter is used) DIN to AOUTn - 6 10 dB dBmc0 --------------------------------------------------------------------------------- ML7022-01 AC Characteristics (Continued) (VDD = 4.75 to 5.25 V, Ta = -40 to +85C) Parameter Absolute Level (Initial Difference) Absolute Level (Deviation of temperature and power) Absolute Delay Transmit Group Delay Receive Group Delay Cross Talk Attenuation Symbol Freq (Hz) AVT 1020 AVR 1020 AVTT 1020 AVRT 1020 TD 1020 Level (dBm0) 0 0 0 Min Typ Max GSXn to DOUT Vdd=5 V, Ta = 25C Condition 0.535 0.555 0.574 DIN to AOUTn Vdd=5 V, Ta = 25C 0.806 0.835 0.864 Vdd=4.75 to 5.25 V Ta = -40 to 85C -0.3 - 0.3 -0.3 - 0.3 Vrms - 0.58 0.6 ms A to A Mode BCLK = 2048 kHz TGD T1 500 - 0.26 0.75 TGD T2 600 - 0.16 0.35 TGD T3 1000 - 0.02 0.125 TGD T4 2600 - 0.05 0.125 0 Minimum value of the group delay distortion TGD T5 2800 - 0.07 0.75 TGD R1 500 - 0.00 0.75 TGD R2 600 - 0.00 0.35 - 0.00 0.125 - 0.09 0.125 TGD R3 1000 TGD R4 2600 TGD R5 2800 CRT 1020 0 0 CRR CRCH Minimum value of the group delay distortion - 0.12 0.75 Trans to Receive 75 83 - Receive to Trans 75 80 - Unit Vrms ms ms dB Channel to Channel 75 78 Discrimination DIS 4.6 k to 72 k 0 0 to 4 kHz 30 32 - dB Out of Band Spurious OBS 300 to 3.4 k 0 4.6 kHz to 1000 kHz - -37.5 -35 dB SFDT 1020 - -50 -40 dBm0 0 0 to 4 kHz - -48 -40 -4 2 fa - fb Signal Frequency Distortion Intermodulation Distortion Power Supply Noise Rejection Ratio SFDR IMDT IMDR - -50 -40 - -54 -40 40 44 - 50 55 - PSRT1 0 to 4 k PSRT2 4 k to 50 k PSRR1 0 to 4 k 40 45 - PSRR2 4 k to 50 k 50 56 - DOUT Pull-up resistor = 0.5 k CL = 50 pF and 1 LSTTL 20 - 100 20 - 100 20 - 100 20 - 1000 TSD Digital Output Delay Time fa=470 fb=320 TXD1 100 mVrms The measurement under idle channel noise TXD2 TPDC C1A, C2A, C3A, C1B, C2B, C3B; CL = 50 pF and 1 LSTTL dBm0 dB ns DOUT Operation Delay Time TDDO Time of operation start after power on - 4 - ms AOUT Signal Output Delay Time TDAO Time of base band signal output start after power on - 4 - ms Oki Semiconductor 13 ML7022-01 ---------------------------------------------------------------------------------- TIMING DIAGRAMS MCK T MB BCLK 1 2 T XS 3 4 5 6 7 8 TS X XSYNC T WS TS D T X D1 DOUT T X D2 M SD D2 D3 D4 D5 D6 D7 D8 Figure 2. Transmit Side Timing Diagram MCK T MB BCLK 1 2 T RS 3 4 5 6 7 8 TSR RSYNC T WS TD S DIN M SD T DH D2 D3 D4 D5 D6 D7 D8 Figure 3. Receive Side Timing Diagram 1 9 17 25 1 BCLK XSYNC ECHO bits Figure 4. Transmit Side Bit Configuration 1 9 17 25 1 BCLK CH1 PCM Data Latch Data CH1 power down control bit CH2 PCM Data Latch Data CH2 power down control bit Figure 5. Receive Side Bit Configuration 14 Oki Semiconductor D2 D3 MSD C3B C2B C1B CPD2 D6 D7 D8 D4 D5 D2 D3 MSD C3A C2A C1A D8 CPD1 D6 D7 D5 D4 DOUT MSD D2 D3 XSYNC D3 D2 MSD EC1B EC2B EC3B D8 CH2 PCM Data ECHO bits EPD2 D6 D7 D5 D4 D3 D2 MSD EC1A EC3A EC2A D8 CH1 PCM Data EPD1 D6 D7 D5 D4 D3 D2 MSD DOUT TPDC Echo Bit CH1 PCM Output Data TPDC C3A, C2A C1A, C3B C2B, C1B EC 1A EC 2A EC 3A EP D1 D8 D7 D6 D5 D4 D3 D2 MSD Echo Bit C1A C2A C3A CP D1 D8 D7 D6 D5 D4 D3 D2 MSD CH2 PCM Output Data EC 1B EC 2B EC 3B EP D2 D8 D7 D6 D5 D4 D3 D2 MSD Echo Bit C1B C2B C3B CP D2 D8 D7 D6 D5 D4 D3 D2 MSD CH2 PCM Output Data EC 1A EC 2A EC 3A EP D1 D8 D7 D6 D5 D4 D3 D2 MSD Echo Bit C1A C2A C3A CP D1 D8 D7 D6 D5 D4 D3 D2 MSD CH1 PCM Output Data EC 1B EC 2B EC 3B EP D2 D8 D7 D6 D5 D4 D3 D2 MSD DOUT C1B C2B C3B CP D2 D8 D7 D6 D5 D4 D3 D2 MSD DIN XSYNC RSYNC BCLK 1 CH1 PCM Input Data 9 Control Data 17 CH2 PCM Input Data 25 Control Data 1 CH1 PCM Input Data 9 Control Data 17 CH2 PCM Input Data 25 Control Data --------------------------------------------------------------------------------- ML7022-01 Figure 6. Control Bit Timing and Echo Back Timing Oki Semiconductor 15 AOUTn DOUT CPD1 (CPD2) SGC PDN TSGC High Impedance TDDO TDAO SG Level ML7022-01 ---------------------------------------------------------------------------------- Figure 7. SGC, DOUT, and AOUT Output Timing 16 Oki Semiconductor +5V 0V Channel 2 Analog Output Channel 2 Analog Input Channel 1 Analog Output Channel 1 Analog Input 1 F + 0.1 F 0.1 F VDD DG AG SGC AOUT2 GSX2 AIN2 AOUT1 GSX1 AIN1 ML7022 C2B C3B C1B C3A C2A C1A TEST6 TEST5 TEST4 TEST3 TEST2 TEST1 PDN RSYNC XSYNC BCLK MCK DIN DOUT 1 k Latch Output 0 : Power Down / 1 : Operation Power Down Control Master Clock and Bit Clock Input Master Clock and Bit Clock Input 2 CH Multiplex PCM Signal Input 2 CH Multiplex PCM Signal Output +5V --------------------------------------------------------------------------------- ML7022-01 APPLICATION CIRCUIT Oki Semiconductor 17 ML7022-01 ---------------------------------------------------------------------------------- RECOMMENDATIONS FOR DESIGN * To assure specified electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. Connect the AG pin and DG pin to each other as closely as possible. Connect to the system ground with low impedance. * A short lead type socket must be used. * When mounted on a frame, use electromagnetic shielding, if any electromagnetic emission sources such as power supply transformers surround the device. * Keep the voltage on the VDD pin not lower than -0.3 V even instantaneously to avoid latch-up phenomenon when turning the power on. * Use a low noise power supply (having low level high frequency spike noise or pulse noise) to avoid erroneous operation and the degradation of the characteristics of these device. 18 Oki Semiconductor --------------------------------------------------------------------------------- ML7022-01 PACKAGE DIMENSIONS (Units: mm) SSOP30-P-56-0.65-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 m or more 0.19 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). Oki Semiconductor 19 ML7022-01 ---------------------------------------------------------------------------------- Notes 20 Oki Semiconductor The information contained herein can change without notice owing to product and/or technical improvements. Please make sure before using the product that the information you are referring to is up-to-date. The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product. When you actually plan to use the product, please ensure that the outside conditions are reflected in the actual circuit and assembly designs. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in connection with the use of product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges, including but not limited to operating voltage, power dissipation, and operating temperature. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,office automation, communication equipment, measurement equipment, consumer electronics, etc.).These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans. Such applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, including life support and maintenance. Certain parts in this document may need governmental approval before they can be exported to certain countries. The purchaser assumes the responsibility of determining the legality of export of these parts and will take appropriate and necessary steps, at their own expense, for export to another country. Copyright 2000 Oki Semiconductor Oki Semiconductor reserves the right to make changes in specifications at anytime and without notice. This information furnished by Oki Semiconductor in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Oki Semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Oki. Oki Semiconductor Oki REGIONAL SALES OFFICES Northwest Area Southwest Area 785 N. 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