CY7C4255, CY7C4265, CY7C4265A
8K/16K x 18 Deep Sync FIFOs
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-06004 Rev. *E Revised June 03, 2009
Features
■High Speed, Low Power, First-In First-Out (FIFO) Memories
❐8K x 18 (CY7C4255)
❐16K x 18 (CY7C4265/4265A)[1]
■0.5 Micron CMOS for Optimum Speed and Power
■High Speed 100 MHz Operation (10 ns read/write cycle times)
■Low Power — ICC = 45 mA
■Fully Asynchronous and Simultaneous Read and Write
Operation
■Empty, Full, Half Full, and Programmable Almost Empty and
Almost Full Status Flags
■TTL compatible
■Retransmit Function
■Output Enable (OE) Pins
■Independent Read and Write Enable Pins
■Center Power and Ground Pins for Reduced Noise
■Supports Free-running 50 percent Duty Cycle Clock Inputs
■Width and Depth Expansion Capability
■64-pin TQFP and 64-pin STQFP
■Pin-compatible Density Upgrade to CY7C42X5 Family
■Pin-compatible Density Upgrade to IDT72205/15/25/35/45
■Pb-free Packages Available
Functional Description
The CY7C4255/65/65A are high speed, low power, first-in
first-out (FIFO) memories with clocked read and write interfaces.
All are 18 bits wide and are pin/functionally compatible to the
CY7C42X5 Synchronous FIFO family. The CY7C4255/65/65A
can be cascaded to increase FIFO depth. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs, including
high speed data acquisition, multiprocessor interfaces, and communi-
cations buffering.
These FIFOs have 18-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free running Clock (WCLK) and a Write Enable
pin (WEN). When WEN is asserted, data is written into the FIFO on the
rising edge of the WCLK signal. While WEN is held active, data is contin-
ually written into the FIFO on each cycle. The output port is controlled in
a similar manner by a free-running Read Clock (RCLK) and a Read
Enable pin (REN). In addition, the CY7C4255/65/65A have an Output
Enable pin (OE). The read and write clocks may be tied together for
single-clock operation or the two clocks may be run independently for
asynchronous read/write applications. Clock frequencies up to
100 MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices. Depth expansion is
possible using the Cascade Input (WXI, RXI), Cascade Output
(WXO, RXO), and First Load (FL) pins. The WXO and RXO pins are
connected to the WXI and RXI pins of the next device, and the WXO
and RXO pins of the last device should be connected to the WXI and
RXI pins of the first device. The FL pin of the first device is tied to VSS
and the FL pin of all the remaining devices should be tied to VCC.
Note
1. CY7C4265 and CY7C4265A are functionally identical
Logic Block Diagram
Q
0–17
THREE–STATE
OUTPUT REGISTER READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
EXPANSION
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D
0–17
REN
RCLK
FF
EF
PAE
WENWCLK
RS
FL/RT
WXI
OE
RAM
ARRAY
8K x 18
16K x 18
PAF
WXO/HF
RXI
RXO
SMODE
[+] Feedback [+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Document #: 38-06004 Rev. *E Page 2 of 23
Pin Description
The CY7C4255/65/65A provides five status pins. These pins are
decoded to determine one of five states: Empty, Almost Empty,
Half Full, Almost Full, and Full. The Half Full flag shares the WXO
pin. This flag is valid in the standalone and width-expansion
configurations. In the depth expansion, this pin provides the
expansion out (WXO) information that is used to signal the next
FIFO when it is activated.
The Empty and Full flags are synchronous, that is, they change
state relative to either the Read Clock (RCLK) or the Write Clock
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag archi-
tecture guarantees that the flags remain valid from one clock
cycle to the next. The Almost Empty/Almost Full flags become
synchronous if the VCC/SMODE is tied to VSS. All configura-
tions are fabricated using an advanced 0.5μ CMOS
technology. Input ESD protection is greater than 2001V, and
latch up is prevented by the use of guard rings.
Pin Configurations
Figure 1. 64-Pin TQFP/STQFP (Top View)
EF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 50
32 49
16
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
Q15
GND
Q16
Q17
GND
VCC
RS
OE
LD
REN
RCLK
GND
D17
D16
PAE
WCLK
WEN
WXI
VCC
PAF
RXI
FF
WXO/HF
RXO
Q0
Q1
GND
Q2
Q3
Q14
Q13
GND
Q12
Q11
VCC
Q10
Q9
GND
Q8
Q7
Q6
Q5
GND
Q4
VCC
VCC/SMODE
FL/RT
CY7C4255
CY7C4265/65A
Table 1. Selection Guide
Description 7C4255/65-10 7C4255/65/65A-15 7C4255/65-25 7C4255/65-35
Maximum Frequency (MHz) 100 66.7 40 28.6
Maximum Access Time (ns) 8 10 15 20
Minimum Cycle Time (ns) 10 15 25 35
Minimum Data or Enable Set-Up (ns) 3 4 6 7
Minimum Data or Enable Hold (ns) 0.5 1 1 2
Maximum Flag Delay (ns) 8 10 15 20
Active Power Supply
Current (ICC1) (mA) Commercial 45 45 45 45
Industrial 50 50 50 50
Table 2. Density and Package
Description CY7C4255 CY7C4265/65A
Density 8K x 18 16K x18
Package 64-pin TQFP, STQFP 64-pin TQFP, STQFP
[+] Feedback [+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Document #: 38-06004 Rev. *E Page 3 of 23
Table 3. Pin Definitions
Signal Name Description I/O Function
D0 –17 Data Inputs I Data inputs for an 18-bit bus.
Q0–17 Data Outputs O Data outputs for an 18-bit bus.
WEN Write Enable I Enables the WCLK input.
REN Read Enable I Enables the RCLK input.
WCLK Write Clock I The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable flag-offset register.
RCLK Read Clock I The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset
register.
WXO/HF Write Expansion
Out/Half Full Flag O Dual-Mode Pin:
Single device or width expansion – Half Full status flag.
Cascaded – Write Expansion Out signal, connected to WXI of next device.
EF Empty Flag O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF Full Flag O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE Programmable
Almost Empty
O When PAE is LOW, the FIFO is almost empty based on the almost-empty offset value
programmed into the FIFO. PAE is asynchronous when VCC/SMODE is tied to VCC; it
is synchronized to RCLK when VCC/SMODE is tied to VSS.
PAF Programmable
Almost Full
O When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when VCC/SMODE is tied to VCC; it
is synchronized to WCLK when VCC/SMODE is tied to VSS.
LD Load I When LD is LOW, D0–17 (Q0–17) are written (read) into (from) the program-
mable-flag-offset register.
FL/RT First Load/
Retransmit
I Dual-Mode Pin:
Cascaded – The first device in the daisy chain has FL tied to VSS; all other devices
has FL tied to VCC. In standard mode or width expansion, FL is tied to VSS on all
devices.
Not Cascaded – Tied to VSS. Retransmit function is also available in stand-alone mode
by strobing RT.
WXI Write Expansion
Input I Cascaded – Connected to WXO of previous device.
Not Cascaded – Tied to VSS.
RXI Read Expansion
Input
I Cascaded – Connected to RXO of previous device.
Not Cascaded – Tied to VSS.
RXO Read Expansion
Output
O Cascaded – Connected to RXI of next device.
RS Reset I Resets device to empty condition. A reset is required before an initial read or write
operation after power up.
OE Output Enable I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected.
If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
VCC/SMODE Synchronous
Almost Empty/
Almost Full Flags
I Dual-Mode Pin:
Asynchronous Almost Empty/Almost Full flags – tied to VCC.
Synchronous Almost Empty/Almost Full flags – tied to VSS.
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
[+] Feedback [+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Document #: 38-06004 Rev. *E Page 4 of 23
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.[2]
Storage Temperature ................................ –65°C to +150°C
Ambient Temperature with Power Applied. –55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ................................................–0.5V to +7.0V
DC Input Voltage ......................................... −0.5V to VCC+0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
(per MIL–STD–883, Method 3015)
Latch Up Current .....................................................>200 mA
Operating Range
Range
Ambient
Temperature[3] VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial[4] –40°C to +85°C 5V ± 10%
Electrical Characteristics Over the Operating Range[4]
Parameter Description Test Conditions 7C42X5-10 7C42X5,
7C4265A-15 7C42X5-25 7C42X5-35 Unit
Min Max Min Max Min Max Min Max
VOH Output HIGH Voltage VCC = Min.,
IOH = –2.0 mA
2.4 2.4 2.4 2.4 V
VOL Output LOW Voltage VCC = Min.,
IOL = 8.0 mA
0.4 0.4 0.4 0.4 V
VIH[5] Input HIGH Voltage 2.0 VCC 2.0 VCC 2.0 VCC 2.0 VCC V
VIL[5] Input LOW Voltage –0.5 0.8 –0.5 0.8 –0.5 0.8 –0.5 0.8 V
IIX Input Leakage
Current
VCC = Max. –10 +10 –10 +10 –10 +10 –10 +10 μA
IOZL
IOZH
Output OFF,
High Z Current
OE > VIH,
VSS < VO < VCC
–10 +10 –10 +10 –10 +10 –10 +10 μA
ICC1[6] Active Power Supply
Current
Commercial 45 45 45 45 mA
Industrial 50 50 50 50 mA
ICC2[7] Average Standby
Current Commercial 10 10 10 10 mA
Industrial 15 15 15 15 mA
Notes
2. The Voltage on any input or I/O pin cannot exceed the power pin during power up.
3. TA is the “Instant On” case temperature.
4. See the last page of this specification for Group A subgroup testing information.
5. The VIH and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the previous device
or VSS.
6. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs are
unloaded. ICC1(typical) = (25 mA + (freq – 20 MHz) * (1.0 mA/MHz)).
7. All inputs = VCC – 0.2V, except RCLK and WCLK (which are switching at frequency = 20 MHz), and FL/RT which is at VSS. All outputs are unloaded.
8. Tested initially and after any design changes that may affect these parameters.
9. Tested initially and after any process changes that may affect these parameters.
Capacitance[8, 9]
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 5.0V
5pF
COUT Output Capacitance 7 pF
[+] Feedback [+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Document #: 38-06004 Rev. *E Page 5 of 23
Figure 2. AC Test Loads and Waveforms[10, 11]
Switching Characteristics Over the Operating Range
Parameter Description 7C42X5-10 7C42X5,
7C4265A-15 7C42X5-25 7C42X5-35 Unit
Min Max Min Max Min Max Min Max
tSClock Cycle Frequency 100 66.7 40 28.6 MHz
tAData Access Time 2 8 2 10 2 15 2 20 ns
tCLK Clock Cycle Time 10 15 25 35 ns
tCLKH Clock HIGH Time 4.5 6 10 14 ns
tCLKL Clock LOW Time 4.5 6 10 14 ns
tDS Data Set Up Time 3 4 6 7 ns
tDH Data Hold Time 0.5 1 1 2 ns
tENS Enable Set Up Time 3 4 6 7 ns
tENH Enable Hold Time 0.5 1 1 2 ns
tRS Reset Pulse Width[12] 10 15 25 35 ns
tRSR Reset Recovery Time 8 10 15 20 ns
tRSF Reset to Flag and Output Time 10 15 25 35 ns
tPRT Retransmit Pulse Width 30 35 45 55 ns
tRTR Retransmit Recovery Time 60 65 75 85 ns
tOLZ Output Enable to Output in Low Z[12] 0000ns
tOE Output Enable to Output Valid 3 738312315ns
tOHZ Output Enable to Output in High Z[13] 3738312315ns
tWFF Write Clock to Full Flag 8 10 15 20 ns
tREF Read Clock to Empty Flag 8 10 15 20 ns
tPAFasynch Clock to Programmable Almost-Full Flag[13]
(Asynchronous mode, VCC/SMODE tied to VCC)12 16 20 25 ns
tPAFsynch Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS)
8101520ns
tPAEasynch Clock to Programmable Almost-Empty Flag[14]
(Asynchronous mode, VCC/SMODE tied to VCC)
12 16 20 25 ns
tPAEsynch Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS)8101520ns
tHF Clock to Half-Full Flag 12 16 20 25 ns
tXO Clock to Expansion Out 6 10 15 20 ns
3.0V
5V
OUTPUT
R1 1.1 K
Ω
R2
680Ω
CL
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤3ns ≤3ns
OUTPUT 1.91V
Equivalent to: THÉ VENIN EQUIVALENT
410Ω
ALL INPUT PULSES
[+] Feedback [+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Document #: 38-06004 Rev. *E Page 6 of 23
tXI Expansion in Pulse Width 4.5 6.5 10 14 ns
tXIS Expansion in Set-Up Time 4 5 10 15 ns
tSKEW1 Skew Time between Read Clock and Write Clock
for Full Flag 5 6 10 12 ns
tSKEW2 Skew Time between Read Clock and Write Clock
for Empty Flag
5 6 10 12 ns
tSKEW3 Skew Time between Read Clock and Write Clock
for Programmable Almost Empty and Program-
mable Almost Full Flags (Synchronous Mode
only)
10 15 18 20 ns
Switching Characteristics Over the Operating Range (continued)
Parameter Description 7C42X5-10 7C42X5,
7C4265A-15 7C42X5-25 7C42X5-35 Unit
Min Max Min Max Min Max Min Max
Notes
10. CL = 30 pF for all AC parameters except for tOHZ.
11. CL = 5 pF for tOHZ.
12. Pulse widths less than minimum values are not enabled.
13. Values guaranteed by design, not currently tested.
14. tPAFasynch, tPAEasynch, after program register write is not be valid until 5 ns + tPAF(E).
[+] Feedback [+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Document #: 38-06004 Rev. *E Page 7 of 23
Switching Waveforms
Figure 3. Write Cycle Timing
Figure 4. Read Cycle Timing
Notes
15. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time
between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
16. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF goes HIGH during the current clock cycle. It the time
between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.
tCLKH tCLKL
NO OPERATION
tDS
tSKEW1
tENS
WEN
tCLK
tDH
tWFF tWFF
tENH
WCLK
D0–D17
FF
REN
RCLK
[15]
tCLKH tCLKL
NO OPERATION
tSKEW2
WEN
tCLK
tOHZ
tREF tREF
RCLK
Q0–Q17
EF
REN
WCLK
OE
tOE
tENS
tOLZ
tA
tENH
VALID DATA
[16]
[+] Feedback [+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Document #: 38-06004 Rev. *E Page 8 of 23
Figure 5. Reset Timing[17]
Figure 6. First Data Word Latency after Reset with Simultaneous Read and Write
Notes
17. The clocks (RCLK, WCLK) can be free-running during reset.
18. After reset, the outputs are LOW if OE = 0 and three-state if OE = 1.
19. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or
tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW).
20. The first word is available the cycle after EF goes HIGH, always.
Switching Waveforms (continued)
tRS
tRSR
Q0–Q17
RS
tRSF
tRSF
tRSF OE = 1
OE = 0
REN,WEN,
LD
EF,PAE
FF,PAF,
HF
[18]
D0(FIRSTVALID WRITE)
tSKEW2
WEN
WCLK
Q0–Q17
EF
REN
OE
tOE
tENS
tOLZ
tDS
RCLK
tREF
tA
tFRL
D1D2D3D4
D0D1
D0–D17
tA
[19]
[20]
[+] Feedback [+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Document #: 38-06004 Rev. *E Page 9 of 23
Figure 7. Empty Flag Timing
Figure 8. Full Flag Timing
Switching Waveforms (continued)
D1D0
tENS
tSKEW2
WEN
WCLK
Q0–Q17
EF
REN
OE
tDS
tENH
RCLK
tREF
tA
tFRL
D0–D17
D0
tSKEW2
tFRL
tREF
tDS
tENS tENH
tREF
[19]
[19]
NEXT DATA READ
DATA WRITE
NO WRITE
DATA IN OUTPUT REGISTER
FF
WCLK
Q0–Q17
REN
OE
RCLK
tA
D0–D17
DATA READ
tSKEW1 tDS
tENS
tENH
WEN
tWFF
tA
tSKEW1
tENS
tENH
tWFF
DATA WRITE
NO WRITE
tWFF
LOW
[15] [15]
[+] Feedback [+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Document #: 38-06004 Rev. *E Page 10 of 23
Figure 9. Half-Full Flag Timing
Figure 10. Programmable Almost Empty Flag Timing
Switching Waveforms (continued)
tENH
WEN
WCLK
HF
REN
RCLK
tCLKH
tHF
tENS
HALF FULL + 1
OR MORE
tCLKL
tENS
HALF FULL OR LESS HALF FULLOR LESS
tHF
tENH
WEN
WCLK
PAE
REN
RCLK
tCLKH
tPAE
tENS
N + 1 WORDS
IN FIFO
tCLKL
tENS
tPAE
n WORDS IN FIFO
[21]
Note
21. PAE is offset = n. Number of data words into FIFO already = n.
[+] Feedback [+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Document #: 38-06004 Rev. *E Page 11 of 23
Figure 11. Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW))
Figure 12. Programmable Almost Full Flag Timing
Notes
22. PAE offset − n.
23. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of
WCLK and the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK.
24. If a read is preformed on this rising edge of the read clock, there are Empty + (n−1) words in the FIFO when PAE goes LOW.
25. PAF offset = m. Number of data words written into FIFO already = 8192 − (m + 1) for the CY7C4255 and 16384 − (m + 1) for the CY7C4265/65A.
26. PAF is offset = m.
27. 8192 − m words in CY7C4255 and 16384 – m words in CY7C4265/65A.
28. 8192 − (m + 1) words in CY7C4255 and 16384 – (m + 1) CY7C4265/65A.
Switching Waveforms (continued)
Note
tENH
WCLK
PAE
RCLK
tCLKH
tENS
tCLKL
tENS
tPAE synch
N + 1 WORDS
INFIFO
tENH
tENS
tENH
tENS
tPAE synch
REN
WEN
WEN2
tSKEW3
Note
[23]
22
24
Note
tENH
WEN
WCLK
PAF
REN
RCLK
tCLKH
tPAF
tENS
tCLKL
tENS
tPAF
FULL– M WORDS
INFIFO FULL– (M+1) WORDS
IN FIFO[28]
[27]
25
[26]
[+] Feedback [+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Document #: 38-06004 Rev. *E Page 12 of 23
Figure 13. Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW))
Figure 14. Write Programmable Registers
Notes
29. If a write is performed on this rising edge of the write clock, there are Full − (m − 1) words of the FIFO when PAF goes LOW.
30. PAF offset = m.
31. tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of
RCLK and the rising edge of WCLK is less than tSKEW3, then PAF may not change state until the next WCLK rising edge.
Switching Waveforms (continued)
Note
Note
tENH
WCLK
PAF
RCLK
tCLKH
tENS
FULL– M WORDS
IN FIFO
tCLKL
tENS
FULL– M + 1 WORDS
IN FIFO
tENH
tENS
tENH
tENS
tPAF
REN
WEN
WEN2
tSKEW3 tPAF synch
29
30
[27]
[31]
tENH
LD
WCLK
tCLKH
tENS
tCLKL
PAE OFFSET
D0–D17
WEN
tENS
PAF OFFSET
PAE OFFSET
tCLK
D0–D11
tDS tDH
[+] Feedback [+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Document #: 38-06004 Rev. *E Page 13 of 23
Figure 15. Read Programmable Registers
Figure 16. Write Expansion Out Timing
Figure 17. Read Expansion Out Timing
Figure 18. Write Expansion In Timing
Notes
32. Write to Last Physical Location.
33. Read from Last Physical Location.
Switching Waveforms (continued)
tENH
LD
RCLK
tCLKH
tENS
tCLKL
PAE OFFSET
Q0–Q17
WEN
tENS
PAF OFFSET PAE OFFSET
tCLK
UNKNOWN
tA
WEN
WCLK
WXO
tCLKH
tENS
tXO
tXO
Note 32
Note 32
REN
WCLK
RXO
tCLKH
tENS
tXO
tXO
Note 33
WCLK
WXI
tXI
tXIS
[+] Feedback [+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Document #: 38-06004 Rev. *E Page 14 of 23
Figure 19. Read Expansion In Timing
Figure 20. Retransmit Timing[34, 35, 36]
Notes
34. Clocks are free-running in this case.
35. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags are valid at tRTR.
36. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags.
Switching Waveforms (continued)
RCLK
RXI
tXI
tXIS
REN/WEN
FL/RT
tPRT
tRTR
EF/FF
and all
async flags
HF/PAE/PAF
[+] Feedback [+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Document #: 38-06004 Rev. *E Page 15 of 23
Architecture
The CY7C4256/65 consists of an array of 8K/16K words of 18
bits each (implemented by a dual-port array of SRAM cells), a
read pointer, a write pointer, control signals (RCLK, WCLK, REN,
WEN, RS), and flags (EF, PAE, HF, PAF, FF). The
CY7C4255/65/65A also includes the control signals WXI, RXI,
WXO, RXO for depth expansion.
Resetting the FIFO
Upon power up, the FIFO must be reset with a Reset (RS) cycle.
This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs go LOW after the falling edge of
RS only if OE is asserted. For the FIFO to reset to its default
state, a falling edge must occur on RS and the user must not read
or write while RS is LOW.
FIFO Operation
When the WEN signal is active (LOW), data present on the D0–17
pins is written into the FIFO on each rising edge of the WCLK
signal. Similarly, when the REN signal is active LOW, data in the
FIFO memory are presented on the Q0–17 outputs. New data is
presented on each rising edge of RCLK while REN is active LOW
and OE is LOW. REN must set up tENS before RCLK for it to be
a valid read function. WEN must occur tENS before WCLK for it
to be a valid write function.
An output enable (OE) pin is provided to three-state the Q0–17
outputs when OE is deasserted. When OE is enabled (LOW),
data in the output register is available to the Q0–17 outputs after
tOE. If devices are cascaded, the OE function only outputs data
on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and under flow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0–17 outputs even
after additional reads occur.
Programming
The CY7C4255/65/65A devices contain two 14-bit offset
registers. Data present on D0–13 during a program write deter-
mines the distance from Empty (Full) that the Almost Empty
(Almost Full) flags become active. If the user elects not to
program the FIFO’s flags, the default offset values are used (see
Table 4 ). When the Load LD pin is set LOW and WEN is set
LOW, data on the inputs D0–13 is written into the Empty offset
register on the first LOW-to-HIGH transition of the Write Clock
(WCLK). When the LD pin and WEN are held LOW then data is
written into the Full offset register on the second LOW-to-HIGH
transition of the Write Clock (WCLK). The third transition of the
Write Clock (WCLK) again writes to the Empty offset register
(see Table 4). Writing all offset registers does not have to occur
at one time. One or two offset registers can be written and then,
by bringing the LD pin HIGH, the FIFO is returned to normal
read/write operation. When the LD pin is set LOW, and WEN is
LOW, the next offset register in sequence is written.
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW; then,
data can be read on the LOW-to-HIGH transition of the Read
Clock (RCLK).
Flag Operation
The CY7C4255/65/65A devices provide five flag pins to indicate
the condition of the FIFO contents. Empty and Full are
synchronous. PAE and PAF are synchronous if VCC/SMODE is
tied to VSS.
Full Flag
The Full Flag (FF) goes LOW when device is Full. Write opera-
tions are inhibited whenever FF is LOW regardless of the state
of WEN. FF is synchronized to WCLK: it is exclusively updated
by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) goes LOW when the device is empty. Read
operations are inhibited whenever EF is LOW, regardless of the
state of REN. EF is synchronized to RCLK, i.e., it is exclusively
updated by each rising edge of RCLK.
Programmable Almost Empty/Almost Full Flag
The CY7C4255/65/65A features programmable Almost Empty
and Almost Full Flags. Each flag can be programmed (described
in the Programming section) a specific distance from the corre-
sponding boundary flags (Empty or Full). When the FIFO
contains the number of words or fewer for which the flags have
been programmed, the PAF or PAE are asserted, signifying that
the FIFO is either Almost Full or Almost Empty. See Table 5 on
page 16 for a description of programmable flags.
When the SMODE pin is tied LOW, the PAF flag signal transition
is caused by the rising edge of the write clock and the PAE flag
transition is caused by the rising edge of the read clock.
Table 4. Write Offset Register
LD WEN WCLK[37] Selection
0 0 Writing to offset registers:
Empty Offset
Full Offset
0 1 No Operation
1 0 Write Into FIFO
1 1 No Operation
Note
37. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
[+] Feedback [+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Document #: 38-06004 Rev. *E Page 16 of 23
Retransmit
The retransmit feature is beneficial when transferring packets of
data. It enables the receipt of data to be acknowledged by the
receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the stand-alone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred and at least one word has been read since
the last RS cycle. A HIGH pulse on RT resets the internal read
pointer to the first physical location of the FIFO. WCLK and
RCLK may be free running but must be disabled during and tRTR
after the retransmit pulse. With every valid read cycle after
retransmit, previously accessed data is read and the read pointer
is incremented until it is equal to the write pointer. Flags are
governed by the relative locations of the read and write pointers
and are updated during a retransmit cycle. Data written to the
FIFO after activation of RT are transmitted also.
The full depth of the FIFO can be repeatedly retransmitted.
Notes
38. n = Empty Offset (Default Values: CY7C4255/CY7C4265/65A n = 127).
39. m = Full Offset (Default Values: CY7C4255/CY7C4265/65A n = 127).
Table 5. Flag Truth Table
Number of Words in FIFO FF PAF HF PAE EF
CY7C4255 – 8K x 18 CY7C4265/65A – 16K x 18
00 HHHLL
1 to n[38] 1 to n[38] HH H L H
(n + 1) to 4096 (n + 1) to 8192 H H H H H
4097 to (8192 – (m + 1)) 8193 to (16384 – (m + 1)) H H L H H
(8192 – m)[39] to 8191 (16384 – m)[39] to 16383 H L L H H
8192 16384 L L L H H
[+] Feedback [+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Document #: 38-06004 Rev. *E Page 17 of 23
Width Expansion Configuration
The CY7C4255/65/65A can be expanded in width to provide word widths greater than 18 in increments of 18. During width expansion
mode all control line inputs are common and all flags are available. Empty (Full) flags should be created by ANDing the Empty (Full)
flags of every FIFO; the PAE and PAF flags can be detected from any one device. This technique avoids reading data from, or writing
data to the FIFO that is “staggered” by one clock cycle due to the variations in skew between RCLK and WCLK. Figure 21 demon-
strates a 36-word width by using two CY7C4255/65/65As.
Figure 21. Block Diagram of 8K x18/16K x 18 Synchronous FIFO Memory Used in a Width Expansion Configuration
Depth Expansion Configuration
(with Programmable Flags)
The CY7C4255/65/65A can easily be adapted to applications requiring more than 8192/16384 words of buffering. Figure 22 shows
Depth Expansion using three CY7C42X5s. Maximum depth is limited only by signal loading. Follow these steps:
1. The first device must be designated by grounding the First Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device.
4. The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next device.
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in the Depth Expansion Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by ORing together these respective flags for monitoring. The composite
PAE and PAF flags are not precise.
FF
FF EF EF
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
PROGRAMMABLE(PAE)
HALF FULL FLAG (HF)
FULL FLAG (FF)
7C4255
7C4265
1836
DATA IN (D)
RESET(RS)
18
RESET(RS)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAF)
EMPTY FLAG (EF)
18
DATA OUT (Q)
18 36
FIRST LOAD (FL)
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
7C4255
7C4265
[+] Feedback [+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Document #: 38-06004 Rev. *E Page 18 of 23
Figure 22. Block Diagram of 8Kx18/16Kx18 Synchronous FIFO Memory with Programmable Flags used in Depth Expansion
Configuration
WRITE CLOCK(WCLK)
WRITE ENABLE(WEN)
RESET(RS)
LOAD (LD)
FF
PAF PAF
FF EF
PAE PAE
EF
WXI RXI
FIRST LOAD (FL)
READ CLOCK(RCLK)
READ ENABLE(REN)
OUTPUT ENABLE(OE)
WXO RXO
PAF
FF EF
PAE
WXI RXI
WXO RXO
VCC
FL
PAF
FF EF
PAE
WXI RXI
WXO RXO
7C4255
7C4265
VCC
FL
DATA IN(D) DATA OUT (Q)
7C4255
7C4265
7C4255
7C4265
[+] Feedback [+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Document #: 38-06004 Rev. *E Page 19 of 23
Figure 23. Typical AC and DC Characteristics
0.60
0.80
1.00
1.20
1.40
1.60
−55.00 5.00 65.00 125.00
0.80
0.90
1.00
1.10
1.20
4.00 4.50 5.00 5.50 6.00
SUPPLY VOLTAGE (V)
NORMALIZED tA vs. SUPPLY
VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED tA vs. AMBIENT
TEMPERATURE
AMBIENT TEMPERATURE (°C)
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
TA= 25°C
FREQUENCY (MHz)
NORMALIZED SUPPLY CURRENT
vs. FREQUENCY
SUPPLY VOLTAGE (V)
VCC = 5.0V
NORMALIZED ICC
0.60
0.80
1.00
1.20
1.40
4.00 4.50 5.00 5.50 6.00 0.80
0.90
1.00
1.10
1.20
−55.00 5.00 65.00 125.00
0.50
0.75
1.00
1.25
1.50
1.75
20.00 30.00 40.00 50.00 60.00
NORMALIZED tA
NORMALIZED tA
NORMALIZED ICC
NORMALIZED ICC
AMBIENT TEMPERATURE (°C)
VIN = 3.0V
TA = 25°C
f = 28 MHz
VIN = 3.0V
VCC = 5.0V
f = 28 MHz
VCC = 5.0V
TA = 25°C
VIN = 3.0V
[+] Feedback [+] Feedback
CY7C4255, CY7C4265, CY7C4265A
Document #: 38-06004 Rev. *E Page 20 of 23
Ordering Information
8Kx18 Deep Sync FIFO
Speed
(ns) Ordering Code
Package
Name
Package
Type
Operating
Range
10 CY7C4255–10AC 51-85046 64-Pin Thin Quad Flatpack Commercial
CY7C4255–10AXC 51-85046 64-Pin Thin Quad Flatpack (Pb-free)
CY7C4255–10ASC 51-85051 64-Pin Small Thin Quad Flatpack
15 CY7C4255–15AC 51-85046 64-Pin Thin Quad Flatpack Commercial
CY7C4255–15AXC 51-85046 64-Pin Thin Quad Flatpack (Pb-free)
16Kx18 Deep Sync FIFO
Speed
(ns) Ordering Code
Package
Diagram
Package
Type
Operating
Range
10 CY7C4265–10AC 51-85046 64-Pin Thin Quad Flatpack Commercial
CY7C4265–10ASC 51-85051 64-Pin Small Thin Quad Flatpack
CY7C4265–10ASXC 51-85051 64-Pin Small Thin Quad Flatpack (Pb-free)
CY7C4265–10AI 51-85046 64-Pin Thin Quad Flatpack Industrial
CY7C4265–10AXI 51-85046 64-Pin Thin Quad Flatpack (Pb-free)
15 CY7C4265–15AC 51-85046 64-Pin Thin Quad Flatpack Commercial
CY7C4265–15AXC 51-85046 64-Pin Thin Quad Flatpack (Pb-free)
CY7C4265-15ASC 51-85051 64-Pin Small Thin Quad Flatpack
CY7C4265A–15ASI 51-85051 64-Pin Small Thin Quad Flatpack Industrial
[+] Feedback [+] Feedback
Document #: 38-06004 Rev. *E Revised June 03, 2009 Page 23 of 23
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C4255, CY7C4265, CY7C4265A
© Cypress Semiconductor Corporation, 2005-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
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Document Title: CY7C4255, CY7C4265, CY7C4265A 8K/16K X 18 Deep Sync FIFOs
Document Number: 38-06004
REV. ECN NO. Orig. of
Change
Submission
Date Description of Change
** 106465 SZV 07/11/01 Change from Spec Number: 38-00468 to 38-06004
*A 122257 RBI 12/26/02 Power up requirements added to Maximum Ratings Information
*B 252889 YDT See ECN Removed PLCC package and pruned parts from Order Information
*C 385985 ESH See ECN Added Pb-Free logo to top of first page
Added CY7C4265-10ASXC, CY7C4265-10AXI, CY7C4265-15AXC,
CY7C4255-10AXC, CY7C4255-15AXC to ordering information
*D 2623658 VKN/PYRS 12/17/08 Added CY7C4265A part
Updated Ordering information table
*E 2714768 VKN/AESA 06/04/2009 Corrected defective Logic Block diagram, Pinouts, and Package diagrams
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