M28W800BB100N1T - STMicroelectronics

1/42May 2002

M28W800BT

M28W800BB

8 Mbit (512Kb x16, Boot Block)

3V Supply Flash Memory

FEATURES SUMMARY

■SUPPLY VOLTAGE

–V

DD = 2.7V to 3.6V Core Power Supply

–V

DDQ= 1.65V to 3.6V for Input/Output

–V

PP = 12V for fast Program (optional)

■ACCESS TIME: 70, 85, 90,100ns

■PROGRAMMING TIME

– 10µs typical

– Double Word Programming Option

■COMMON FLASH INTERFACE

– 64 bit Security Code

■MEMORY BLOCKS

– Parameter Blocks (Top or Bottom location)

– Main Blocks

■BLOCK PROTECTION on TWO PARAMETER

BLOCKS

–WP

for Block Protection

■AUTOMATIC STAND-BY MODE

■PROGRAM and ERASE SUSPEND

■100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Top Device Code, M28W800BT: 8892h

– Bottom Device Code, M28W800BB: 8893h

Figure 1. Packages

FBGA

TSOP48 (N)

12 x 20mm

TFBGA46 (ZB)

6.39 x 6.37mm

M28W800BT, M28W800BB

2/42

TABLE OF CONTENTS

SUMMARYDESCRIPTION...........................................................5

Figure2.LogicDiagram..........................................................5

Table 1. Signal Names . . . ........................................................5

Figure 3. TSOP Connections.......................................................6

Figure 4. TFBGA Connections (Top view through package). ..............................7

Figure5.BlockAddresses.........................................................8

SIGNALDESCRIPTIONS............................................................9

AddressInputs(A0-A18)..........................................................9

Data Input/Output (DQ0-DQ15). . . ..................................................9

ChipEnable(E). ................................................................9

Output Enable (G). ..............................................................9

Write Enable (W). . ..............................................................9

WriteProtect(WP)...............................................................9

Reset(RP).....................................................................9

DD Supply Voltage..............................................................9

DDQ Supply Voltage.............................................................9

PP ProgramSupplyVoltage ......................................................9

SS Ground. ...................................................................9

BUSOPERATIONS................................................................10

Read.........................................................................10

Write.........................................................................10

OutputDisable.................................................................10

Standby. . ....................................................................10

Automatic Standby. .............................................................10

Reset. .......................................................................10

Table2.BusOperations.........................................................10

COMMANDINTERFACE ...........................................................11

ReadMemoryArraycommand....................................................11

ReadStatusRegisterCommand...................................................11

Read Electronic Signature Command...............................................11

ReadCFIQueryCommand.......................................................11

BlockEraseCommand..........................................................11

ProgramCommand.............................................................11

Double Word Program Command . .................................................12

ClearStatusRegisterCommand...................................................12

Program/Erase Suspend Command ................................................12

Program/EraseResumeCommand ................................................12

BlockProtection................................................................12

Table3.Commands ............................................................13

Table4.ReadElectronicSignature.................................................13

Table5.MemoryBlocksProtectionTruthTable.......................................13

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M28W800BT, M28W800BB

Table6.Program,EraseTimesandProgram/EraseEnduranceCycles ....................14

STATUSREGISTER...............................................................15

Program/EraseControllerStatus(Bit7).............................................15

Erase Suspend Status (Bit 6) .....................................................15

EraseStatus(Bit5).............................................................15

ProgramStatus(Bit4)...........................................................15

PP Status(Bit3)...............................................................15

ProgramSuspendStatus(Bit2)...................................................15

BlockProtectionStatus(Bit1).....................................................16

Reserved(Bit0)................................................................16

Table7.StatusRegisterBits......................................................16

MAXIMUMRATING................................................................17

Table8.AbsoluteMaximumRatings................................................17

DCandACPARAMETERS.........................................................18

Table 9. Operating and AC Measurement Conditions...................................18

Figure6.ACMeasurementI/OWaveform...........................................18

Figure 7. AC Measurement Load Circuit. . . ..........................................18

Table 10. Device Capacitance.....................................................18

Table11.DCCharacteristics......................................................19

Figure8.ReadACWaveforms....................................................20

Table12.ReadACCharacteristics.................................................20

Figure 9. Write AC Waveforms, Write Enable Controlled . . . .............................21

Table 13. Write AC Characteristics, Write Enable Controlled .............................22

Figure10.WriteACWaveforms,ChipEnableControlled................................23

Table14.WriteACCharacteristics,ChipEnableControlled .............................24

Figure11.Power-UpandResetACWaveforms.......................................25

Table15.Power-UpandResetACCharacteristics ....................................25

PACKAGE MECHANICAL . . . .......................................................26

Figure12.TSOP48-48leadPlasticThinSmallOutline,12x20mm,PackageOutline ........26

Table 16. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 26

Figure 13. TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline27

Table17.TFBGA466.39x6.37mm-8x6ballarray,0.75mmpitch,PackageMechanicalData...27

Figure 14. TFBGA46 Daisy Chain - Package Connections (Top view through package)........28

Figure 15. TFBGA46 Daisy Chain - PCB Connections proposal (Top view through package)....28

PARTNUMBERING...............................................................29

Table18.OrderingInformationScheme.............................................29

Table19.DaisyChainOrderingScheme............................................29

REVISIONHISTORY...............................................................30

Table20.DocumentRevisionHistory...............................................30

M28W800BT, M28W800BB

4/42

APPENDIX A. BLOCK ADDRESS TABLES . . ..........................................31

Table 21. Top Boot Block Addresses, M28W800BT ....................................31

Table22.BottomBootBlockAddresses,M28W800BB.................................31

APPENDIXB.COMMONFLASHINTERFACE(CFI) .....................................32

Table23.QueryStructureOverview................................................32

Table 24. CFI Query Identification String . . ..........................................32

Table25.CFIQuerySystemInterfaceInformation.....................................33

Table26.DeviceGeometryDefinition...............................................34

Table 27. Primary Algorithm-Specific Extended Query Table .............................35

Table28.SecurityCodeArea.....................................................35

APPENDIX C. FLOWCHARTS AND PSEUDO CODES....................................36

Figure 16. Program Flowchart and Pseudo Code . . ....................................36

Figure 17. Double Word Program Flowchart and Pseudo Code ...........................37

Figure 18. Program Suspend & Resume Flowchart and Pseudo Code .....................38

Figure 19. Erase Flowchart and Pseudo Code ........................................39

Figure 20. Erase Suspend & Resume Flowchart and Pseudo Code. .......................40

APPENDIXD.COMMANDINTERFACEANDPROGRAM/ERASECONTROLLERSTATE.......41

Table29.WriteStateMachineCurrent/Next..........................................41

5/42

M28W800BT, M28W800BB

SUMMARY DESCRIPTION

The M28W800B is a 8 Mbit (512Kbit x 16) non-vol-

atileFlashmemorythatcanbeerasedelectrically

at the block level and programmed in-system on a

Word-by-Word basis. These operations can be

performed using a single low voltage (2.7 to 3.6V)

supply. VDDQ allows to drive the I/O pin down to

1.65V. An optional 12V VPP power supply is pro-

vided to speed up customer programming.

The device features an asymmetrical blocked ar-

chitecture. The M28W800B has an array of 23

blocks: 8 Parameter Blocks of 4 KWord and 15

Main Blocks of 32 KWord. M28W800BT has the

Parameter Blocks at the top of the memory ad-

dress space while the M28W800BB locates the

Parameter Blocks starting from the bottom. The

memory maps are shown in Figure 5, Block Ad-

dresses.

Parameter blocks 0 and 1 can be protected from

accidental programming or erasure. Each block

can be erased separately. Erase can be suspend-

ed in order to perform either read or program in

any other block and then resumed. Program can

be suspended to read data in any other block and

then resumed. Each block can be programmed

and erased over 100,000 cycles.

Program and Erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller takes care of the tim-

ings necessary for program and erase operations.

The end of a program or erase operation can be

detected and any error conditions identified. The

command set required to control the memory is

consistent with JEDEC standards.

The memory is offered in TSOP48 (10 X 20mm),

and TFBGA46 (6.39 x 6.37mm, 0.75mm pitch)

packages and is supplied with all the bits erased

(set to ’1’).

Figure 2. Logic Diagram

Table 1. Signal Names

A0-A18 Address Inputs

DQ0-DQ15 Data Input/Output

EChip Enable

GOutput Enable

WWrite Enable

RP Reset

WP Write Protect

VDD Core Power Supply

VDDQ Power Supply for

Input/Output

VPP Optional Supply Voltage for

Fast Program & Erase

VSS Ground

NC Not Connected Internally

AI03581

A0-A18

DQ0-DQ15

VDD

M28W800BT

M28W800BB

VSS

VDDQ VPP

M28W800BT, M28W800BB

6/42

Figure 3. TSOP Connections

DQ3

DQ9

DQ2

A6 DQ0

DQ6

A9 DQ13

A17

A10 DQ14

DQ12

DQ10

DQ15

VDD

DQ4

DQ5

DQ7

VPP

AI03582

M28W800BT

M28W800BB

24 25

DQ8

A18

DQ1

DQ11

A12

A13

A16

A11

VDDQ

A15

A14 VSS

VSS

7/42

M28W800BT, M28W800BB

Figure 4. TFBGA Connections (Top view through package)

AI03805

87654321

A7VPP

A8A11

A13

A0EDQ8DQ5DQ14A16

VSS

DQ0DQ9DQ3DQ6DQ15VDDQ

DQ1DQ10VDD

DQ7VSS

DQ2

A2A5A17WA10A14

A1A3A6A9A12A15

RP A18

DQ4

DQ13 G

DQ12

DQ11

WP NC

M28W800BT, M28W800BB

8/42

Figure 5. Block Addresses

Note: Also see Appendix A, Tables 21 and 22 for a full listing of the Block Addresses.

AI04384

4 KWords

7FFFF

7F000

32 KWords

0FFFF

08000

32 KWords

07FFF

00000

M28W800BT

Top Boot Block Addresses

4 KWords

78FFF

78000

32 KWords

70000

77FFF

Total of 8

4 KWord Blocks

Total of 15

32 KWord Blocks

4 KWords

7FFFF

78000 32 KWords

32 KWords

00FFF

00000

M28W800BB

Bottom Boot Block Addresses

4 KWords

77FFF

0FFFF 32 KWords

70000

08000

Total of 15

32 KWord Blocks

Total of 8

4 KWord Blocks

07FFF

07000

9/42

M28W800BT, M28W800BB

SIGNAL DESCRIPTIONS

See Figure 2 Logic Diagram and Table 1,Signal

Names, for a briefoverview of the signals connect-

ed to this device.

Address Inputs (A0-A18). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

Data Input/Output (DQ0-DQ15). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation or inputs a command

or data to be programmed during a Write Bus op-

eration.

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. When Chip Enable is

at VILand Reset is at VIH the device is in active

mode. When Chip Enable is at VIH the memory is

deselected, the outputs are high impedance and

the power consumption is reduced to the stand-by

level.

Output Enable (G). The Output Enable controls

data outputs during the Bus Read operation of the

memory.

WriteEnable(W

). The Write Enable controls the

Bus Write operation of the memory’s Command

Interface. The data and address inputs are latched

ontherisingedgeofChipEnable,E,orWriteEn-

able, W, whichever occurs first.

Write Protect (WP). Write Protect is an input to

protect or unprotect the two lockable parameter

blocks. When Write Protect is at VIL, the lockable

blocks are protected and Program or Erase oper-

ations are not possible. When Write Protect is at

VIH, the lockable blocks are unprotected and can

be programmed or erased (refer to Table 4, Mem-

ory Blocks Protection Truth).

Reset (RP). The Reset input provides a hard-

wareresetofthememory.WhenResetisatV

IL,

the memory is in reset mode: the outputs are high

impedance and the current consumption is mini-

mized. When Reset is at VIH, the device is in nor-

mal operation. Exiting reset mode the device

enters read array mode, but a negative transition

of Chip Enable or a change of the address is re-

quired to ensure valid data outputs.

VDD Supply Voltage. VDD provides the power

supply to the internal core of the memory device.

It is the main power supply for all operations

(Read, Program and Erase).

VDDQ Supply Voltage. VDDQ provides the

power supply to the I/O pins and enables all Out-

puts to be powered independently from VDD.VDDQ

canbetiedtoV

DD or can use a separate supply.

VPP Program Supply Voltage. VPP is both a

control input and a power supply pin. The two

functions are selected by the voltage range ap-

plied to the pin. The Supply Voltage VDD and the

Program Supply Voltage VPP canbeappliedin

any order.

If VPP is kept in a low voltage range (0V to 3.6V)

VPP is seen as a control input. In this case a volt-

age lower than VPPLK gives an absolute protection

against program or erase, while VPP >V

PP1 en-

ables these functions (see Table 11, DC Charac-

teristics for the relevant values). VPP is only

sampled at the beginning of a program or erase; a

change in its value after the operation has started

does not have any effect and program or erase op-

erations continue.

If VPP is in the range 11.4V to 12.6V it acts as a

power supply pin. In this condition VPP must be

stable until the Program/Erase algorithm is com-

pleted (see Table 13 and 14).

VSS Ground. VSS is the reference for all voltage

measurements.

Note: Each device in a system should have

VDD,VDDQ and VPP decoupled with a 0.1µF ca-

pacitor close to the pin. See Figure 7, AC Mea-

surement Load Circuit. The PCB trace widths

should be sufficient to carry the required VPP

Program and Erase currents.

M28W800BT, M28W800BB

10/42

BUS OPERATIONS

There are six standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby, Automatic Standby and Re-

set. See Table 2, Bus Operations, for a summary.

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect bus operations.

Read. Read Bus operations are used to output

the contents of the Memory Array, the Electronic

Signature, the Status Register and the Common

Flash Interface. Both Chip Enable and Output En-

ablemustbeatV

IL in order to perform a read op-

eration. The Chip Enable input should be used to

enable the device. Output Enable should be used

to gate data onto the output. The data read de-

pends on the previous command written to the

memory (see Command Interface section). See

Figure 8, Read Mode AC Waveforms, and Table

12, Read AC Characteristics, for details of when

the output becomes valid.

Read mode is the default state of the device when

exiting Reset or after power-up.

Write. Bus Write operations write Commands to

the memory or latch Input Data to be programmed.

A write operation is initiated when Chip Enable

and Write Enable are at VIL with Output Enable at

VIH. Commands, Input Data and Addresses are

latched on the rising edge of Write Enable or Chip

Enable, whichever occurs first.

See Figures 9 and 10, Write AC Waveforms, and

Tables 13 and 14, Write AC Characteristics, for

details of the timing requirements.

Output Disable. The data outputs are high im-

pedance when the Output Enable is at VIH.

Standby. Standby disables most of the internal

circuitry allowing a substantial reduction of the cur-

rent consumption. The memory is in stand-by

when Chip Enable is at VIH andthedeviceisin

read mode. The power consumption is reduced to

the stand-by level and the outputs are set to high

impedance, independently from the Output Enable

or Write Enable inputs. If Chip Enable switches to

VIH during a program or erase operation, the de-

vice enters Standby mode when finished.

Automatic Standby. Automatic Standby pro-

vides a low power consumption state during Read

mode. Following a read operation, the device en-

ters Automatic Standby after 150ns of bus inactiv-

ity, even if Chip Enable is low, VIL, and the supply

current is reduced to IDD1. The data Inputs/Out-

puts will still output data.

Reset. During Reset mode, when Output Enable

is low, VIL, the memory is deselected and the out-

puts are high impedance. The memory is in Reset

mode when Reset is at VIL. The power consump-

tion is reduced to the Standby level, independently

from the Chip Enable, Output Enable or Write En-

able inputs. If Reset is pulled to VSS during a Pro-

gram or Erase, this operation is aborted and the

memory content is no longer valid.

Table 2. Bus Operations

Note: X = VIL or VIH,V

PPH =12V±5%.

Operation E G W RP WP VPP DQ0-DQ15

Read VIL VIL VIH VIH X Don't Care Data Output

Write VIL VIH VIL VIH XVDD or VPPH Data Input

Output Disable VIL VIH VIH VIH X Don't Care Hi-Z

Standby VIH XX

IH X Don't Care Hi-Z

Reset X X X VIL X Don't Care Hi-Z

11/42

M28W800BT, M28W800BB

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. An internal Program/Erase Controller han-

dles all timings and verifies the correct execution

of the Program and Erase commands. The Pro-

gram/Erase Controller provides a Status Register

whose output may be read at any time, to monitor

the progress of an operation, or the Program/

Erase states. See Appendix D, Table 29, Write

State Machine Current/Next, for a summary of the

Command Interface.

The Command Interface is reset to Read mode

when power is first applied, when exiting from Re-

set or whenever VDD is lower than VLKO.Com-

mand sequences must be followed exactly. Any

invalid combination of commands will reset the de-

vice to Read mode. Refer to Table 3, Commands,

in conjunction with the text descriptions below.

Read Memory Array command

TheReadcommandreturnsthememorytoits

Read mode. One Bus Write cycle is required to is-

sue the Read Memory Array command and return

the memory to Read mode. Subsequent read op-

erations will read the addressed location and out-

put the data. When a device Reset occurs, the

memory defaults to Read mode.

Read Status Register Command

The Status Register indicates when a program or

erase operation is complete and the success or

failure of the operation itself. Issue a Read Status

contents. Subsequent Bus Read operations read

the Status Register, at any address, until another

command is issued. See Table 7, Status Register

Bits, for details on the definitions of the bits.

The Read Status Register command may be is-

sued at any time, even during a Program/Erase

operation. Any Read attempt during a Program/

Erase operation will automatically output the con-

tent of the Status Register.

Read Electronic Signature Command

The Read Electronic Signature command reads

the Manufacturer and Device Codes.

The Read Electronic Signature command consists

of one write cycle, a subsequent read will output

the Manufacturer or the Device Code depending

on the levels of A0. The Manufacturer Code is out-

put when the address line A0 is at VIL, the Device

Code is output when A0 is at VIH. Addresses A1-

A7 must be kept to VIL, other addresses are ig-

nored. The codes are output on DQ0-DQ7 with

DQ8-DQ15 at 00h. (see Table 4)

Read CFI Query Command

The Read Query Command is used to read data

fromtheCommonFlashInterface(CFI)Memory

Area, allowing programming equipment or appli-

cations to automatically match their interface to

the characteristics of the device.

One Bus Write cycle is required to issue the Read

Query Command. Once the command is issued

subsequent Bus Read operations read from the

Common Flash Interface Memory Area. See Ap-

pendix B, Common FlashInterface, Tables 23, 24,

25, 26, 27 and 28 for details on the information

contained in the Common Flash Interface memory

area.

Block Erase Command

TheBlockErasecommandcanbeusedtoerase

a block. It sets all the bits within the selected block

to ’1’. All previous data in the block is lost. If the

block is protected then the Erase operation will

abort, the data in the block will notbe changed and

the Status Register will output the error.

Two Bus Write cycles are required to issue the

command.

■The first bus cycle sets up the Erase command.

■The second latches the block address in the

internal state machine and starts the Program/

Erase Controller.

If the second bus cycle is not Write Erase Confirm

(D0h), Status Register bits b4 and b5 are set and

the command aborts.

Erase aborts if Reset turns to VIL. As data integrity

cannot be guaranteed when the Erase operation is

aborted, the block must be erased again.

During Erase operations the memory will only ac-

cept the Read Status Register command and the

Program/Erase Suspend command, all other com-

mands will be ignored. Typical Erase times are

given in Table 6, Program, Erase Times and Pro-

gram/Erase Endurance Cycles.

See Appendix C, Figure 19, Erase Flowchart and

Pseudo Code, for the flowchart for using the Erase

command.

Program Command

The memory array can be programmed word-by-

word. Two bus write cycles are required to issue

the Program command.

■The first bus cycle sets up the Program

command.

■The secondlatchestheAddress and theDatato

be written and starts the Program/Erase

Controller.

During Program operations the memory will only

accept the Read Status Register command and

the Program/Erase Suspend command. All other

M28W800BT, M28W800BB

12/42

commands will be ignored. Typical Program times

are given in Table 6, Program, Erase Times and

Program/Erase Endurance Cycles.

Programming aborts if Reset goes to VIL. As data

integrity cannot be guaranteed when the program

operation is aborted, the block containing the

memory location must be erased and repro-

grammed.

See Appendix C, Figure 16, Program Flowchart

and Pseudo Code, for the flowchart for using the

Program command.

Double Word Program Command

This feature is offered to improve the programming

throughput, writing a page of two adjacent words

in parallel.The two words must differ only for the

address A0. Programming should not be attempt-

ed when VPP is not at VPPH. The command can be

executed if VPP is below VPPH but the result is not

guaranteed.

Three bus write cycles are necessary to issue the

Double Word Program command.

■The first bus cycle sets up the Double Word

Program command.

■The second bus cycle latches the Address and

theDataofthefirstwordtobewritten.

■The third bus cycle latches the Address and the

Data of the second word to be written and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started. Program-

ming aborts if Reset goes to VIL. As data integrity

cannot be guaranteed when the program opera-

tion is aborted, the block containing the memory

location must be erased and reprogrammed.

See Appendix C, Figure 17, Double Word Pro-

gram Flowchart and Pseudo Code, for the flow-

chart for using the Double Word Program

command.

Clear Status Register Command

The Clear Status Register command can be used

to reset bits 1, 3, 4 and 5 in the Status Register to

‘0’. One bus write cycle is required to issue the

Clear Status Register command.

The bits in the Status Register do not automatical-

ly return to ‘0’ when a new Program or Erase com-

mand is issued. The error bits in the Status

new Program or Erase command.

Program/Erase Suspend Command

The Program/Erase Suspend command is used to

pause a Program or Erase operation. One bus

write cycle is required to issue the Program/Erase

command and pause the Program/Erase control-

ler.

During Program/Erase Suspend the Command In-

terface will accept the Program/Erase Resume,

Read Array, Read Status Register, Read Electron-

ic Signature and Read CFI Query commands. Ad-

ditionally, if the suspend operation was Erase then

the Program command will also be accepted. Only

the blocks not being erased may be read or pro-

grammed correctly.

During a Program/Erase Suspend, the device can

be placed in a pseudo-standby mode by taking

Chip Enable to VIH. Program/Erase is aborted if

Reset turns to VIL.

See Appendix C, Figure 18, Program Suspend &

Resume Flowchart and Pseudo Code, and Figure

20, Erase Suspend & Resume Flowchart and

Pseudo Code for flowcharts for using the Program/

Erase Suspend command.

Program/Erase Resume Command

The Program/Erase Resume command can be

used to restart the Program/Erase Controller after

a Program/Erase Suspend operation has paused

it. One Bus Write cycle is required to issue the

command. Once the command is issued subse-

quent Bus Read operations read the Status Reg-

ister.

See Appendix C, Figure 18, Program or Double

Word Program Suspend & Resume Flowchart and

Pseudo Code, and Figure 20, Erase Suspend &

Resume Flowchart and Pseudo Code for flow-

charts for using the Program/Erase Resume com-

mand.

Block Protection

Two parameter/lockableblocks (blocks #0 and #1)

can be protected against Program or Erase oper-

ations. Unprotected blocks can be programmed or

erased.

To protect the two lockable blocks set Write Pro-

tect to VIL. When VPP is below VPPLK all blocks are

protected. Any attempt to Program or Erase pro-

tected blocks will abort, the data in the block will

not be changed and the Status Register outputs

the error.

Table 5, Memory Blocks Protection Truth Table,

defines the protection methods.

13/42

M28W800BT, M28W800BB

Table 3. Commands

Note: 1. X = Don't Care.

2. A0=VIL outputs Manufacturer code, A0=VIH outputs Device code. Address A7-A1 must be VIL.

3. Addr 1 and Addr 2 must be consecutive Addresses differing only for A0.

Table 4. Read Electronic Signature

Note: RP =V

IH.

Table 5. Memory Blocks Protection Truth Table

Note: 1. X = Don't Care

2. VPP must also be greater than the Program Voltage Lock Out VPPLK.

Commands No. of

Cycles

Bus Write Operations

1st Cycle 2nd Cycle 3nd Cycle

Bus

Op. Addr Data Bus

Op. Addr Data

Read Memory Array 1+ Write X FFh Read Read

Addr Data

Read Status Register 1+ Write X 70h Read X Status

Read Electronic Signature 1+ Write X 90h Read Signature

Addr (2) Signature

Read CFI Query 1+ Write X 98h Read CFI Addr Query

Erase 2 Write X 20h Write Block

Addr D0h

Program 2 Write X 40h or

10h Write Addr Data

Input

Double Word Program(3) 3 Write X 30h Write Addr 1 Data

Input Write Addr 2 Data

Input

Clear Status Register 1 Write X 50h

Program/Erase Suspend 1 Write X B0h

Program/Erase Resume 1 Write X D0h

Code Device E G W A0 A1-A7 A8-A18 DQ0-DQ7 DQ8-DQ15

Manufact. Code VIL VIL VIH VIL VIL Don't Care 20h 00h

Device Code M28W800BT VIL VIL VIH VIH VIL Don't Care 92h 88h

M28W800BB VIL VIL VIH VIH VIL Don't Care 93h 88h

VPP (1) RP WP (1) Lockable Blocks

(blocks #0 and #1) Other Blocks

XVIL X Protected Protected

VIL VIH X Protected Protected

VDD or VPPH (2) VIH VIL Protected Unprotected

VDD or VPPH (2) VIH VIH Unprotected Unprotected

M28W800BT, M28W800BB

14/42

Table 6. Program, Erase Times and Program/Erase Endurance Cycles

Parameter Test Conditions M28W800B Unit

Min Typ Max

Word Program VPP =V

DD 10 200 µs

Double Word Program VPP =12V±5% 10 200 µs

Main Block Program VPP =12V±5% 0.16 5 s

VPP =V

DD 0.32 5 s

Parameter Block Program VPP =12V±5% 0.02 4 s

VPP =V

DD 0.04 4 s

Main Block Erase VPP =12V±5% 110 s

PP =V

DD 110 s

Parameter Block Erase VPP =12V±5% 0.8 10 s

VPP =V

DD 0.8 10 s

Program/Erase Cycles (per Block) 100,000 cycles

15/42

M28W800BT, M28W800BB

STATUS REGISTER

The Status Register provides information on the

current or previous Program or Erase operation.

The various bits convey information and errors on

the operation. To read the Status register the

Read StatusRegister command can be issued, re-

fer to the Read Status Register Command section.

To output the contents, the Status Register is

latched on the falling edge of the Chip Enable or

Output Enable signals, and can be read until Chip

Enable or Output Enable returns to VIH. Either

Chip Enable or Output Enable must be toggled to

update the latched data.

Bus Read operations from any address always

read the Status Register during Program and

Erase operations.

The bits in the Status Register are summarized in

Table 7, Status Register Bits. Refer to Table 7 in

conjunction with the following text descriptions.

Program/Erase Controller Status (Bit 7). The Pro-

gram/Erase Controller Status bit indicates whether

the Program/Erase Controller is active or inactive.

When the Program/Erase Controller Status bit is

Low (set to ‘0’), the Program/Erase Controller is

active; when the bit is High (set to ‘1’), the Pro-

gram/Erase Controller is inactive, and the device

is ready to process a new command.

The Program/Erase Controller Status is Low im-

mediately after a Program/Erase Suspend com-

mand is issued until the Program/Erase Controller

pauses. After the Program/Erase Controller paus-

es the bit is High .

During Program, Erase, operations the Program/

EraseControllerStatusbitcanbepolledtofindthe

end of the operation. Other bits in the Status Reg-

ister should not be tested until the Program/Erase

Controller completes the operation and the bit is

High.

After the Program/Erase Controller completes its

operation the Erase Status, Program Status, VPP

Status and Block Protection Status bits should be

tested for errors.

Erase Suspend Status (Bit 6). The Erase Sus-

pend Status bit (set to ‘1’) indicates that an Erase

operation has been suspended or is going to be

suspended.

The Erase Suspend Status should only be consid-

ered valid when the Program/Erase Controller Sta-

tus bit is High (Program/Erase Controller inactive).

Bit 7 is set within 30µs of the Program/Erase Sus-

pend command being issued therefore the memo-

ry may still complete the operation rather than

entering the Suspend mode.

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns Low.

Erase Status (Bit 5). The Erase Status bit can be

used to identify if the memory has failed to verify

that the block has erased correctly. When the

Erase Status bit is High (set to ‘1’), the Program/

Erase Controller has applied the maximum num-

ber of pulses to the block and still failed to verify

that the block has erased correctly. The Erase Sta-

tus bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

Once set High, the Erase Status bit can only be re-

set Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

Program Status (Bit 4). The Program Status bit

is used to identify a Program failure. When the

Program Status bit is High (set to ‘1’), the Pro-

gram/Erase Controller has applied the maximum

number of pulses to the byte and still failed to ver-

ify that it has programmed correctly. The Program

Status bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

Once set High, the Program Status bit can only be

reset Low by a Clear Status Register command or

a hardware reset. If set High it should be reset be-

fore a new command is issued, otherwise the new

command will appear to fail.

VPP Status (Bit 3). The VPP Status bit can be

used to identify an invalid voltage on the VPP pin

during Program and Erase operations. The VPP

pin is only sampled at the beginning of a Program

or Erase operation. Indeterminate results can oc-

cur if VPP becomes invalid during an operation.

When the VPP Status bit is Low (set to ‘0’), the volt-

age on the VPP pin was sampled at a valid voltage;

when the VPP Status bit is High (set to ‘1’), the VPP

pin has a voltage that is below the VPP Lockout

Voltage, VPPLK, the memory is protected and Pro-

gram and Erase operations cannot be performed.

Once setHigh, the VPP Status bit can onlybe reset

Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

Program Suspend Status (Bit 2). The Program

Suspend Status bit (set to ‘1’) indicates that a Pro-

gram operation has been suspended or is going to

be suspended.

The Program Suspend Status should only be con-

sidered valid when the Program/Erase Controller

Status bit is High (Program/Erase Controller inac-

tive). Bit 2 is set within 5µs of the Program/Erase

Suspend command being issued therefore the

M28W800BT, M28W800BB

16/42

memory may still complete the operation rather

than entering the Suspend mode.

When a Program/Erase Resume command is is-

sued the Program Suspend Status bit returns Low.

Block Protection Status (Bit 1). The Block Pro-

tectionStatusbitcanbeusedtoidentifyifaPro-

gram or Erase operation has tried to modify the

contents of a protected block.

When the Block Protection Status bit is High (set

to ‘1’), a Program or Erase operation has been at-

tempted on a protected block.

Once set High, the Block Protection Status bit can

only be reset Low by a Clear Status Register com-

mand or a hardware reset. If set High it should be

reset before a new command is issued, otherwise

the new command will appear to fail.

Reserved (Bit 0). Bit 0 of the Status Register is

reserved. Its value must be masked.

Note: Refer to Appendix C, Flowcharts and

Pseudo Codes, for using the Status Register.

Table 7. Status Register Bits

Note: Logic level '1' is High, '0' is Low.

Bit Name Logic Level Definition

7 P/E.C. Status '1' Ready

'0' Busy

6 Erase Suspend Status '1' Suspended

'0' In progress or Completed

5 Erase Status '1' Erase Error

'0' Erase Success

4 Program Status '1' Program Error

'0' Program Success

3VPP Status '1' VPP Invalid, Abort

'0' VPP OK

2 Program Suspend Status '1' Suspended

'0' In Progress or Completed

1 Block Protection Status '1' Program/Erase on protected Block, Abort

'0' No operation to protected blocks

0 Reserved

17/42

M28W800BT, M28W800BB

MAXIMUM RATING

Stressingthedeviceabovetheratinglistedinthe

Absolute Maximum Ratings table may cause per-

manent damage to the device. Exposure to Abso-

lute Maximum Rating conditions for extended

periods may affect device reliability. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 8. Absolute Maximum Ratings

Note: 1. Depends on range.

Symbol Parameter Value Unit

Min Max

TAAmbient Operating Temperature (1) –40 85 °C

TBIAS Temperature Under Bias –40 125 °C

TSTG Storage Temperature –55 155 °C

VIO Input or Output Voltage –0.6 VDDQ+0.6 V

VDD,V

DDQ Supply Voltage –0.6 4.1 V

VPP Program Voltage –0.6 13 V

M28W800BT, M28W800BB

18/42

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, and the DC and AC charac-

teristics of the device. The parameters in the DC

and AC characteristics Tables that follow, are de-

rived from tests performed under the Measure-

ment Conditions summarized in Table 9,

Operating and AC Measurement Conditions. De-

signers should check that the operating conditions

in their circuit match the measurement conditions

when relying on the quoted parameters.

Table 9. Operating and AC Measurement Conditions

Figure 6. AC Measurement I/O Waveform Figure 7. AC Measurement Load Circuit

Table 10. Device Capacitance

Note: Sampled only, not 100% tested.

M28W800BT, M28W800BB

Parameter 70 85 90 100 Units

Min Max Min Max Min Max Min Max

VDD Supply Voltage 2.7 3.6 2.7 3.6 2.7 3.6 2.7 3.6 V

VDDQ Supply Voltage (VDDQ ≤ VDD)2.7 3.6 2.7 3.6 2.7 3.6 1.65 3.6 V

Ambient Operating Temperature –40 85 –40 85 –40 85 – 40 85 °C

Load Capacitance (CL)50 50 50 50 pF

Input Rise and Fall Times 5 5 5 5 ns

Input Pulse Voltages 0toV

DDQ 0toV

DDQ V

Input and Output Timing Ref.

Voltages VDDQ/2 VDDQ/2 VDDQ/2 VDDQ/2 V

AI00610

VDDQ

VDDQ/2

AI00609C

VDDQ

CL includes JIG capacitance

25kΩ

DEVICE

UNDER

TEST

0.1µF

VDD

0.1µF

VDDQ

25kΩ

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN =0V 6pF

OUT Output Capacitance VOUT =0V 12 pF

19/42

M28W800BT, M28W800BB

Table 11. DC Characteristics

Symbol Parameter Test Condition Min Typ Max Unit

ILI Input Leakage Current 0V≤VIN ≤VDDQ ±1 µA

ILO Output Leakage Current 0V≤ VOUT ≤VDDQ ±10 µA

IDD Supply Current (Read) E=V

SS,G=V

IH,f=5MHz 10 20 mA

IDD1 Supply Current (Stand-by or

Automatic Stand-by) E=V

DDQ ±0.2V,

RP =V

DDQ ± 0.2V 15 50 µA

IDD2 Supply Current

(Reset) RP =V

SS ± 0.2V 15 50 µA

IDD3 Supply Current (Program)

Program in progress

VPP =12V±5% 10 20 mA

Program in progress

VPP =V

DD 10 20 mA

IDD4 Supply Current (Erase)

Erase in progress

VPP =12V±5% 520mA

Erase in progress

VPP =V

DD 520mA

DD5 Supply Current

(Program/Erase Suspend) E=V

DDQ ±0.2V,

Erase suspended 50 µA

IPP Program Current

(Read or Stand-by) VPP >V

DD 400 µA

IPP1 Program Current

(Read or Stand-by) VPP ≤VDD 5µA

PP2 Program Current (Reset) RP =V

SS ± 0.2V 5µA

PP3 Program Current (Program)

Program in progress

VPP =12V±5% 10 mA

Program in progress

VPP =V

DD 5µA

PP4 Program Current (Erase)

Erase in progress

VPP =12V±5% 10 mA

Erase in progress

VPP =V

DD 5µA

IL Input Low Voltage –0.5 0.4 V

VDDQ ≥2.7V –0.5 0.8 V

VIH Input High Voltage VDDQ –0.4 VDDQ +0.4 V

VDDQ ≥2.7V 0.7 VDDQ VDDQ +0.4 V

VOL Output Low Voltage IOL = 100µA, VDD =V

DDmin,

VDDQ =V

DDQ min 0.1 V

VOH Output High Voltage IOH = –100µA, VDD =V

DD min,

VDDQ =V

DDQ min VDDQ –0.1 V

VPP1 Program Voltage (Program or

Erase operations) 1.65 3.6 V

VPPH Program Voltage

(Program or Erase

operations) 11.4 12.6 V

VPPLK Program Voltage

(Program and Erase lock-out) 1V

LKO VDD Supply Voltage (Program

and Erase lock-out) 2V

M28W800BT, M28W800BB

20/42

Figure 8. Read AC Waveforms

Table 12. Read AC Characteristics

Note: 1. Sampled only, not 100% tested.

2. G may be delayed by up to tELQV -t

GLQV after the falling edge of E without increasing tELQV.

Symbol Alt Parameter M28W800B Unit

70 85 90 100

tAVAV tRC Address Valid to Next Address Valid Min 70 85 90 100 ns

tAVQV tACC Address Valid to Output Valid Max 70 85 90 100 ns

tAXQX (1) tOH Address Transition to Output Transition Min 0 0 0 0 ns

tEHQX (1) tOH Chip Enable High to Output Transition Min 0 0 0 0 ns

tEHQZ (1) tHZ Chip Enable High to Output Hi-Z Max 20 20 25 30 ns

tELQV (2) tCE Chip Enable Low to Output Valid Max 70 85 90 100 ns

tELQX (1) tLZ Chip Enable Low to Output Transition Min 0 0 0 0 ns

tGHQX (1) tOH Output Enable High to Output Transition Min 0 0 0 0 ns

tGHQZ (1) tDF Output Enable High to Output Hi-Z Max 20 20 25 30 ns

tGLQV (2) tOE Output Enable Low to Output Valid Max 20 20 30 35 ns

tGLQX (1) tOLZ Output Enable Low to Output Transition Min 0 0 0 0 ns

DQ0-DQ15

AI03578b

VALID

A0-A18

tAXQX

tAVAV

VALID

tAVQV

tELQV

tELQX

tGLQV

tGLQX

ADDR. VALID

CHIP ENABLE OUTPUTS

ENABLED DATA VALID STANDBY

tGHQX

tGHQZ

tEHQX

tEHQZ

21/42

M28W800BT, M28W800BB

Figure 9. Write AC Waveforms, Write Enable Controlled

DQ0-DQ15 COMMAND CMD or DATA STATUS REGISTER

VPP

VALIDA0-A18

tAVAV

tQVVPL

tAVWH tWHAX

PROGRAM OR ERASE

tELWL tWHEH

tWHDX

tDVWH

tWLWH

tWHWL

tVPHWH

SET-UP COMMAND CONFIRM COMMAND

OR DATA INPUT STATUS REGISTER

READ

1st POLLING

tELQV

AI03579b

tWPHWH

tWHGL

tQVWPL

tWHEL

M28W800BT, M28W800BB

22/42

Table 13. Write AC Characteristics, Write Enable Controlled

Note: 1. Sampled only, not 100% tested.

2. Applicable if VPP is seen as a logic input (VPP <3.6V).

Symbol Alt Parameter M28W800B Unit

70 85 90 100

tAVAV tWC Write Cycle Time Min 70 85 90 100 ns

tAVWH tAS Address Valid to Write Enable High Min 45 45 50 50 ns

tDVWH tDS Data Valid to Write Enable High Min 45 45 50 50 ns

tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 0 0 ns

tELQV Chip Enable Low to Output Valid Min 70 85 90 100 ns

tQVVPL (1,2) Output Valid to VPP Low Min 0 0 0 0 ns

tQVWPL Output Valid to Write Protect Low Min 0 0 0 0 ns

tVPHWH (1) tVPS VPP High to Write Enable High Min 200 200 200 200 ns

tWHAX tAH Write Enable High to Address Transition Min 0 0 0 0 ns

tWHDX tDH Write Enable High to Data Transition Min 0 0 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 0 0 0 ns

tWHEL Write Enable High to Chip Enable Low Min 25 25 30 30 ns

tWHGL Write Enable High to Output Enable Low Min 20 20 30 30 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 25 25 30 30 ns

tWLWH tWP Write Enable Low to Write Enable High Min 45 45 50 50 ns

tWPHWH Write Protect High to Write Enable High Min 45 45 50 50 ns

23/42

M28W800BT, M28W800BB

Figure 10. Write AC Waveforms, Chip Enable Controlled

DQ0-DQ15 COMMAND CMD or DATA STATUS REGISTER

VPP

VALIDA0-A18

tAVAV

tQVVPL

tAVEH tEHAX

PROGRAM OR ERASE

tWLEL tEHWH

tEHDX

tDVEH

tELEH

tEHEL

tVPHEH

POWER-UP AND

SET-UP COMMAND CONFIRM COMMAND

OR DATA INPUT STATUS REGISTER

READ

1st POLLING

tELQV

AI03580b

tWPHEH

tEHGL

tQVWPL

M28W800BT, M28W800BB

24/42

Table 14. Write AC Characteristics, Chip Enable Controlled

Note: 1. Sampled only, not 100% tested.

2. Applicable if VPP is seen as a logic input (VPP <3.6V).

Symbol Alt Parameter M28W800B Unit

70 85 90 100

tAVAV tWC Write Cycle Time Min 70 85 90 100 ns

tAVEH tAS Address Valid to Chip Enable High Min 45 45 50 50 ns

tDVEH tDS Data Valid to Chip Enable High Min 45 45 50 50 ns

tEHAX tAH Chip Enable High to Address Transition Min 0 0 0 0 ns

tEHDX tDH Chip Enable High to Data Transition Min 0 0 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low Min 25 25 30 30 ns

tEHGL Chip Enable High to Output Enable Low Min 25 25 30 30 ns

tEHWH tWH Chip Enable High to Write Enable High Min 0 0 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High Min 45 45 50 50 ns

tELQV Chip Enable Low to Output Valid Min 70 85 90 100 ns

tQVVPL (1,2) Output Valid to VPP Low Min 0 0 0 0 ns

tQVWPL Data Valid to Write Protect Low Min 0 0 0 0 ns

tVPHEH (1) tVPS VPP High to Chip Enable High Min 200 200 200 200 ns

tWLEL tCS Write Enable Low to Chip Enable Low Min 0 0 0 0 ns

tWPHEH Write Protect High to Chip Enable High Min 45 45 50 50 ns

25/42

M28W800BT, M28W800BB

Figure 11. Power-Up and Reset AC Waveforms

Table 15. Power-Up and Reset AC Characteristics

Note: 1. The device Reset is possible but not guaranteed if tPLPH < 100ns.

2. Sampled only, not 100% tested.

3. It is important to assert RP in order to allow proper CPU initialization during power up or reset.

Symbol Parameter Test Condition M28W800B Unit

70 85 90 100

tPHWL

tPHEL

tPHGL

Reset High to Write Enable Low, Chip

Enable Low, Output Enable Low

During

Program

and Erase Min 50 50 50 50 µs

others Min 30 30 30 30 ns

tPLPH(1,2) Reset Low to Reset High Min 100 100 100 100 ns

tVDHPH(3) Supply Voltages High to Reset High Min 50 50 50 50 µs

AI03453b

tPHWL

tPHEL

tPHGL

E, G

VDD, VDDQ

tVDHPH

tPHWL

tPHEL

tPHGL

tPLPH

Power-Up Reset

M28W800BT, M28W800BB

26/42

PACKAGE MECHANICAL

Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

Note: Drawing is not to scale.

Table 16. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data

Symbol mm inches

Typ Min Max Typ Min Max

A 1.20 0.0472

A1 0.05 0.15 0.0020 0.0059

A2 0.95 1.05 0.0374 0.0413

B 0.17 0.27 0.0067 0.0106

C 0.10 0.21 0.0039 0.0083

D 19.80 20.20 0.7795 0.7953

D1 18.30 18.50 0.7205 0.7283

E 11.90 12.10 0.4685 0.4764

e 0.50 – – 0.0197 – –

L 0.50 0.70 0.0197 0.0279

α0° 5° 0° 5°

N48 48

CP 0.10 0.0039

TSOP-a

1 N

N/2

DIE

LA1 α

27/42

M28W800BT, M28W800BB

Figure 13. TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline

Drawing is not to scale.

Table 17. TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data

E1E

bA2

BGA-Z13

ddd

BALL "A1"

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.200 0.0079

A2 1.000 0.0394

b 0.400 0.350 0.450 0.0157 0.0138 0.0177

D 6.390 6.290 6.490 0.2516 0.2476 0.2555

D1 5.250 – – 0.2067 – –

ddd 0.100 0.0039

E 6.370 6.270 6.470 0.2508 0.2469 0.2547

e 0.750 – – 0.0295 – –

E1 3.750 – – 0.1476 – –

FD 0.570 – – 0.0224 – –

FE 1.310 – – 0.0516 – –

SD 0.375 – – 0.0148 – –

SE 0.375 – – 0.0148 – –

M28W800BT, M28W800BB

28/42

Figure 14. TFBGA46 Daisy Chain - Package Connections (Top view through package)

Figure 15. TFBGA46 Daisy Chain - PCB Connections proposal (Top view through package)

AI03860

87654321

AI03861

87654321

START

POINT

END

POINT

29/42

M28W800BT, M28W800BB

PART NUMBERING

Table 18. Ordering Information Scheme

Table 19. Daisy Chain Ordering Scheme

Note:Devices are shipped from thefactory with the memory content bits erased to ’1’. For a list of available

options (Speed, Package,etc...) or for further information on anyaspectof this device, please contact

the ST Sales Office nearest to you.

Example: M28W800BT 90 N 6 T

Device Type

M28

Operating Voltage

W=V

DD = 2.7V to 3.6V; VDDQ = 1.65V to 3.6V

Device Function

800B = 8 Mbit (512Kb x16), Boot Block

Array Matrix

T=TopBoot

B = Bottom Boot

Speed

70 = 70 ns

85 = 85 ns

90 = 90 ns

100 = 100 ns

Package

N = TSOP48: 12 x 20 mm

ZB = TFBGA46: 6.39 x 6.37mm, 0.75 mm pitch

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

T = Tape & Reel Packing

Example: M28W800B -GB T

Device Type

M28W800B

Daisy Chain

-ZB = TFBGA46: 6.39 x 6.37mm, 0.75 mm pitch

Option

T = Tape & Reel Packing

M28W800BT, M28W800BB

30/42

REVISION HISTORY

Table 20. Document Revision History

Date Version Revision Details

July 1999 -01 First Issue

10-May-2001 -02 Completely rewritten and restructured, 70ns and 85ns speed class added.

29-May-2001 -03 Corrections to CFI data and Block Address Table.

31-May-2001 -04 Package changes - TFBGA45 replaced by TFBGA46.

31-Oct-2001 -05

Document status changed from Preliminary Data to Datasheet

VDDQ Maximum changed to 3.3V

Commands Table, Read CFI Query Address on 1st cycle changed to ‘X’ (Table 3)

tWHEL description clarified (Table 13)

16-May-2002 -06 VDDQ Maximum changed to 3.6V, TFBGA package dimensions added to description.

31/42

M28W800BT, M28W800BB

APPENDIX A. BLOCK ADDRESS TABLES

Table 21. Top Boot Block Addresses,

M28W800BT Table 22. Bottom Boot Block Addresses,

M28W800BB

#Size

(KWord) Address Range

0 4 7F000-7FFFF

1 4 7E000-7EFFF

2 4 7D000-7DFFF

3 4 7C000-7CFFF

4 4 7B000-7BFFF

5 4 7A000-7AFFF

6 4 79000-79FFF

7 4 78000-78FFF

8 32 70000-77FFF

9 32 68000-6FFFF

10 32 60000-67FFF

11 32 58000-5FFFF

12 32 50000-57FFF

13 32 48000-4FFFF

14 32 40000-47FFF

15 32 38000-3FFFF

16 32 30000-37FFF

17 32 28000-2FFFF

18 32 20000-27FFF

19 32 18000-1FFFF

20 32 10000-17FFF

21 32 08000-0FFFF

22 32 00000-07FFF

#Size

(KWord) Address Range

22 32 78000-7FFFF

21 32 70000-77FFF

20 32 68000-6FFFF

19 32 60000-67FFF

18 32 58000-5FFFF

17 32 50000-57FFF

16 32 48000-4FFFF

15 32 40000-47FFF

14 32 38000-3FFFF

13 32 30000-37FFF

12 32 28000-2FFFF

11 32 20000-27FFF

10 32 18000-1FFFF

9 32 10000-17FFF

8 32 08000-0FFFF

7 4 07000-07FFF

6 4 06000-06FFF

5 4 05000-05FFF

4 4 04000-04FFF

3 4 03000-03FFF

2 4 02000-02FFF

1 4 01000-01FFF

0 4 00000-00FFF

M28W800BT, M28W800BB

32/42

APPENDIX B. COMMON FLASH INTERFACE (CFI)

TheCommonFlashInterfaceisaJEDECap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system software to query the device to determine

various electrical and timing parameters, density

information and functions supported by the mem-

ory. The system can interface easily with the de-

vice, enabling the software to upgrade itself when

necessary.

When the CFI Query Command (RCFI) is issued

the device enters CFI Query mode and the data

structure is read from the memory. Tables 23, 24,

25, 26, 27 and 28 show the addresses used to re-

trieve the data.

The CFI data structure also contains a security

area where a 64 bit unique security number is writ-

ten (see Table 28, Security Code area). This area

can be accessed only in Read mode by the final

user. It is impossible to change the security num-

ber after it has been written by ST. Issue a Read

command to return to Read mode.

Table 23. Query Structure Overview

Note: Query data are always presented on the lowest order data outputs.

Table 24. CFI Query Identification String

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

Offset Sub-section Name Description

00h Reserved Reserved for algorithm-specific information

10h CFI Query Identification String Command set ID and algorithm data offset

1Bh System Interface Information Device timing & voltage information

27h Device Geometry Definition Flash device layout

P Primary Algorithm-specific Extended Query table Additional information specific to the Primary

Algorithm (optional)

A Alternate Algorithm-specific Extended Query table Additional information specific to the Alternate

Algorithm (optional)

Offset Data Description Value

00h 0020h Manufacturer Code ST

01h 8892h

8893h Device Code Top

Bottom

02h-0Fh reserved Reserved

10h 0051h Query Unique ASCII String "QRY" “Q”

11h 0052h Query Unique ASCII String "QRY" “R”

12h 0059h Query Unique ASCII String "QRY" “Y”

13h 0003h Primary Algorithm Command Set and Control Interface ID code 16 bit ID

code defining a specific algorithm Intel

Compatible

14h 0000h

15h offset = P =

0035h Address for Primary Algorithm extended Query table P=35h

16h 0000h

17h 0000h Alternate Vendor Command Set and Control Interface ID Code second

vendor - specified algorithm supported (note: 0000h means none exists) NA

18h 0000h

19h value = A =

0000h Address for Alternate Algorithm extended Query table

note: 0000h means none exists NA

1Ah 0000h

33/42

M28W800BT, M28W800BB

Table 25. CFI Query System Interface Information

Offset Data Description Value

1Bh 0027h VDD Logic Supply Minimum Program/Erase or Write voltage

bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100 mV 2.7V

1Ch 0036h VDD Logic Supply Maximum Program/Erase or Write voltage

bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100 mV 3.6V

1Dh 00B4h VPP [Programming] Supply Minimum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV 11.4V

1Eh 00C6h VPP [Programming] Supply Maximum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV 12.6V

1Fh 0004h Typical timeout per single word program = 2nµs 16µs

20h 0004h Typical timeout for Double Word Program = 2nµs 16µs

21h 000Ah Typical timeout per individual block erase = 2nms 1s

22h 0000h Typical timeout for full chip erase = 2nms NA

23h 0005h Maximum timeout for word program = 2ntimes typical 512µs

24h 0005h Maximum timeout for Double Word Program = 2ntimes typical 512µs

25h 0003h Maximum timeout per individual block erase = 2ntimes typical 8s

26h 0000h Maximum timeout for chip erase = 2ntimes typical NA

M28W800BT, M28W800BB

34/42

Table 26. Device Geometry Definition

Offset Word

Mode Data Description Value

27h 0014h Device Size = 2nin number of bytes 1MByte

28h

29h 0001h

0000h Flash Device Interface Code description x16

Async

2Ah

2Bh 0002h

0000h Maximum number of bytes in multi-byte program or page = 2n4

2Ch 0002h Number of Erase Block Regions within the device.

It specifies the number of regions within the device containing contiguous

Erase Blocks of the same size.

M28W800BT

2Dh

2Eh 000Eh

0000h Region 1 Information

Number of identical-size erase block = 000Eh+1 15

2Fh

30h 0000h

0001h Region 1 Information

Block size in Region 1 = 0100h * 256 byte 64KByte

31h

32h 0007h

0000h Region 2 Information

Number of identical-size erase block = 0007h+1 8

33h

34h 0020h

0000h Region 2 Information

Block size in Region 2 = 0020h * 256 byte 8KByte

M28W800BB

2Dh

2Eh 0007h

0000h Region 1 Information

Number of identical-size erase block = 0007h+1 8

2Fh

30h 0020h

0000h Region 1 Information

Block size in Region 1 = 0020h * 256 byte 8KByte

31h

32h 000Eh

0000h Region 2 Information

Number of identical-size erase block = 000Eh+1 15

33h

34h 0000h

0001h Region 2 Information

Block size in Region 2 = 0100h * 256 byte 64KByte

35/42

M28W800BT, M28W800BB

Table 27. Primary Algorithm-Specific Extended Query Table

Note: 1. See Table 24, offset 15h for P pointer definition.

Table 28. Security Code Area

Offset

P = 35h (1) Data Description Value

(P+0)h = 35h 0050h

Primary Algorithm extended Query table unique ASCII string “PRI”

"P"

(P+1)h = 36h 0052h "R"

(P+2)h = 37h 0049h "I"

(P+3)h = 38h 0031h Major version number, ASCII "1"

(P+4)h = 39h 0030h Minor version number, ASCII "0"

(P+5)h = 3Ah 0006h Extended Query table contents for Primary Algorithm. Address (P+5)h

contains less significant byte.

bit 0 Chip Erase supported (1 = Yes, 0 = No)

bit 1 Erase Suspend supported (1 = Yes, 0 = No)

bit 2 Program Suspend (1 = Yes, 0 = No)

bit 3 Lock/Unlock supported (1 = Yes, 0 = No)

bit 4 Queued Erase supported (1 = Yes, 0 = No)

bit 31 to 5 Reserved; undefined bits are ‘0’

Yes

(P+6)h = 3Bh 0000h

(P+7)h = 3Ch 0000h

(P+8)h = 3Dh 0000h

(P+9)h = 3Eh 0001h Supported Functions after Suspend

Read Array, Read Status Register and CFI Query are always supported

during Erase or Program operation

bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No)

bit 7 to 1 Reserved; undefined bits are ‘0’ Yes

(P+A)h = 3Fh 0000h Block Lock Status

Defines which bits in the Block Status Register section of the Query are

implemented.

bit 0 Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No)

bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)

bit 15 to 2 Reserved for future use; undefined bits are ‘0’

(P+B)h = 40h 0000h

(P+C)h = 41h 0030h VDD Logic Supply Optimum Program/Erase voltage (highest performance)

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

(P+D)h = 42h 00C0h VPP Supply Optimum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

12V

(P+E)h 0000h Reserved

Offset Data Description

81h XXXX

64 bits unique device number.

82h XXXX

83h XXXX

84h XXXX

M28W800BT, M28W800BB

36/42

APPENDIX C. FLOWCHARTS AND PSEUDO CODES

Figure 16. Program Flowchart and Pseudo Code

Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

Write 40h or 10h

AI03538b

Start

Write Address

& Data

Read Status

YES

b7 = 1

YES

b3 = 0

b4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

program_command (addressToProgram, dataToProgram) {:

writeToFlash (any_address, 0x40) ;

/*or writeToFlash (any_address, 0x10) ; */

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

YES

End

YES

b1 = 0 Program to Protected

Block Error (1, 2)

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

if (status_register.b4==1) /*program error */

error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

}

37/42

M28W800BT, M28W800BB

Figure 17. Double Word Program Flowchart and Pseudo Code

Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.

Write 30h

AI03539b

Start

Write Address 1

& Data 1 (3)

Read Status

YES

b7 = 1

YES

b3 = 0

b4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

YES

End

YES

b1 = 0 Program to Protected

Block Error (1, 2)

Write Address 2

& Data 2 (3)

double_word_program_command (addressToProgram1, dataToProgram1,

addressToProgram2, dataToProgram2)

{

writeToFlash (any_address, 0x30) ;

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

/*Memory enters read status state after

the Program command*/

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

if (status_register.b4==1) /*program error */

error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

}

M28W800BT, M28W800BB

38/42

Figure 18. Program Suspend & Resume Flowchart and Pseudo Code

Write 70h

AI03540b

Read Status

YES

b7 = 1

YES

b2 = 1

Program Continues

Write D0h

Read data from

another address

Start

Write B0h

Program Complete

Write FFh

Read Data

program_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

writeToFlash (any_address, 0x70) ;

/* read status register to check if

program has already completed */

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b2==0) /*program completed */

{ writeToFlash (any_address, 0xFF) ;

read_data ( ) ; /*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

}

else

{ writeToFlash (any_address, 0xFF) ;

read_data ( ); /*read data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume program*/

}

Write FFh

39/42

M28W800BT, M28W800BB

Figure 19. Erase Flowchart and Pseudo Code

Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.

Write 20h

AI03541b

Start

Write Block

Address & D0h

Read Status

YES

b7 = 1

YES

b3 = 0

YES

b4, b5 = 1

VPP Invalid

Error (1)

Command

Sequence Error (1)

b5 = 0 Erase Error (1)

End

YES

b1 = 0 Erase to Protected

Block Error (1)

YES

erase_command ( blockToErase ) {

writeToFlash (any_address, 0x20) ;

writeToFlash (blockToErase, 0xD0) ;

/* only A12-A20 are significannt */

/* Memory enters read status state after

the Erase Command */

} while (status_register.b7== 0) ;

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

if ( (status_register.b4==1) && (status_register.b5==1) )

/* command sequence error */

error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

if ( (status_register.b5==1) )

/* erase error */

error_handler ( ) ;

}

M28W800BT, M28W800BB

40/42

Figure 20. Erase Suspend & Resume Flowchart and Pseudo Code

Write 70h

AI03549b

Read Status

YES

b7 = 1

YES

b6 = 1

Erase Continues

Write D0h

Read data from

another block

Program

Start

Write B0h

Erase Complete

Write FFh

Read Data

erase_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

writeToFlash (any_address, 0x70) ;

/* read status register to check if

erase has already completed */

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b6==0) /*erase completed */

{ writeToFlash (any_address, 0xFF) ;

read_data ( ) ;

/*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

}

else

{ writeToFlash (any_address, 0xFF) ;

read_program_data ( );

/*read or program data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume erase*/

}

Write FFh

41/42

M28W800BT, M28W800BB

APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE

Table 29. Write State Machine Current/Next

Note: Elect.Sg. = Electronic Signature.

Current

State SR

bit 7

Data

When

Read

Command Input (and Next State)

Read

Array

(FFh)

Program

Setup

(10/40h)

Erase

Setup

(20h)

Erase

Confirm

(D0h)

Program/

Erase

Suspend

(B0h)

Program/

Erase

Resume

(D0h)

Read

Status

(70h)

Clear

Status

(50h)

Read

Elect.Sg.

(90h)

Read

Array “1” Array Read

Array Program

Setup Erase

Setup Read Array Read

Status Read

Array Read

Elect.Sg.

Read

Status “1” Status Read

Array Program

Setup Erase

Setup Read Array Read

Status Read

Array Read

Elect.Sg.

Read

Elect.Sg. “1” Electronic

Signature Read

Array Program

Setup Erase

Setup Read Array Read

Status Read

Array Read

Elect.Sg.

Program

Setup “1” Status Program (Command input = Data to be Programmed)

Program

(continue) “0” Status Program (continue)

Program

Suspend

to Read

Status

Program (continue)

Program

Suspend

to Read

Status

“1” Status

Program

Suspend

to Read

Array

Program Suspend to

Read Array Program

(continue)

Program

Suspend

to Read

Array

Program

(continue)

Program

Suspend

to Read

Status

Program

Suspend

to Read

Array

Program

Suspend

to Read

Elect.Sg.

Program

Suspend

to Read

Array

“1” Array

Program

Suspend

to Read

Array

Program Suspend to

Read Array Program

(continue)

Program

Suspend

to Read

Array

Program

(continue)

Program

Suspend

to Read

Status

Program

Suspend

to Read

Array

Program

Suspend

to Read

Elect.Sg.

Program

Suspend

to Read

Elect.Sg.

“1” Electronic

Signature

Program

Suspend

to Read

Array

Program Suspend to

Read Array Program

(continue)

Program

Suspend

to Read

Array

Program

(continue)

Program

Suspend

to Read

Status

Program

Suspend

to Read

Array

Program

Suspend

to Read

Elect.Sg.

Program

(complete) “1” Status Read

Array Program

Setup Erase

Setup Read Array Read

Status Read

Array Read

Elect.Sg.

Erase

Setup “1” Status Erase Command Error Erase

(continue)

Erase

Command

Error

Erase

(continue) Erase Command Error

Erase

Cmd.

Error “0” Status Read

Array Program

Setup Erase

Setup Read Array Read

Status Read

Array Read

Elect.Sg.

Erase

(continue) “1” Status Erase (continue)

Erase

Suspend

to Read

Status

Erase (continue)

Erase

Suspend

to Read

Status

“1” Status

Erase

Suspend

to Read

Array

Program

Setup

Erase

Suspend

to Read

Array

Erase

(continue)

Erase

Suspend

to Read

Array

Erase

(continue)

Erase

Suspend

to Read

Status

Erase

Suspend

to Read

Array

Erase

Suspend

to Read

Elect.Sg.

Erase

Suspend

to Read

Array

“1” Array

Erase

Suspend

to Read

Array

Program

Setup

Erase

Suspend

to Read

Array

Erase

(continue)

Erase

Suspend

to Read

Array

Erase

(continue)

Erase

Suspend

to Read

Status

Erase

Suspend

to Read

Array

Erase

Suspend

to Read

Elect.Sg.

Erase

Suspend

to Read

Elect.Sg.

“1” Electronic

Signature

Erase

Suspend

to Read

Array

Program

Setup

Erase

Suspend

to Read

Array

Erase

(continue)

Erase

Suspend

to Read

Array

Erase

(continue)

Erase

Suspend

to Read

Status

Erase

Suspend

to Read

Array

Erase

Suspend

to Read

Elect.Sg.

Erase

(complete) “1” Status Read

Array Program

Setup Erase

Setup Read Array Read

Status Read

Array Read

Elect.Sg.

M28W800BT, M28W800BB

42/42

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