Order Number: 251902, Re vision: 010
Augus t 20 05
Int el StrataFlash® Wireless Memory
(L18)
28F640L18, 28F128L18, 28F256L18
Datas h eet
Product Features
The Intel StrataFlash® wire les s memory (L18) device is the latest generation of Int e l
StrataFlash® memory devic e s f e a turing flexible, multiple- pa rtition, dual opera tion. It provides
high perf ormance synchronous-burst read mode and a synchronous read mode using 1.8 V low-
voltage, multi-level cell (MLC) technology.
The multiple-partition architectu re en ables background prog ramming or erasing to occu r in one
parti tion while code execution or data rea ds take place in another par tition. This dual- operatio n
archit ecture also allows a syste m to inter leave code operations while program and erase
opera tions take place in the background. The 8-Mbit or 16-Mbit partitions allow syst em
designers to choose the size of the code and data segm ents. The L18 wir eles s memory device is
manufact ured using Intel 0.13 µm ETOX™ VIII process tec hnology. It is available in industry-
standar d chip scale packaging.
■High perf o rmance R ea d-While-Write/Erase
— 85 ns initial access
— 54 MHz with zero wait state, 14 ns clock-to-
data output synchronous-burst mode
— 25 ns asynchronous-page mode
— 4-, 8-, 16-, and c ontinuous-word burst mode
— Bu rst su spe n d
— Programmable WAIT configuration
— Buffered Enhanced Factory Programming
(BEFP) at 5 µs/byte (Typ)
— 1.8 V low-power buffe red programming at
7 µs/byte (Typ)
■Architecture
— Asymmetrica lly-block ed architecture
— Multiple 8-Mbit partitions: 64-Mbit and 128-
Mbit devices
— Multiple 16-Mbit partitions: 256-Mbit devices
— Four 16-Kw ord parameter blocks: top or
bottom configurations
— 64-Kword main blocks
— Dual-operation: Read-While-Wr ite (RWW) or
Read-Whil e-Erase (RWE)
— Status Register for partition and device status
■Power
—V
CC (core) = 1.7 V - 2.0 V
—V
CCQ (I/O ) = 1.35 V - 2.0 V, 1.7 V - 2.0 V
— Standby current: 30 µA (Typ) for 256-Mbit
— 4-Word synchronous read current: 15 m A (Typ)
at 54 MHz
— Automatic Power Savings mode
■Security
— OTP space:
• 64 unique factory device identifier bits
• 64 user-programmable OTP bits
• Additional 2048 user-programmable OT P bit s
— Absolute write protection: VPP = GND
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual bloc k lock-down
■Software
— 20 µ s (Typ) program suspend
— 20 µ s (Typ) erase sus pend
— Intel® Flash Data Integrator optimized
— Basic Command Set (BCS) and Extended
Command Set (ECS) c o mpa tible
— Common Flash Interface (CFI) capable
■Quality and Reliability
— Expanded temperature: –25° C to +85° C
— Minimum 100,000 erase cycles per block
— ETOX™ VIII proces s technology (0.13 µm)
■Dens ity and Packa gi ng
— 64-, 128-, and 256-Mbit density in VF BGA
packages
— 128/0 and 256/0 density in SCSP
— 16-bit wide data bus
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
2 Order Numb er: 25190 2, Revision: 010
Lega l Lines and Disc laimers
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INTELLEC TUAL PROPERTY RIGHT. Intel products are not i ntended for use i n medical, life saving, life sustai ning, critical control or safety systems, or
in nuclear facility app licat ions.
The Intel S t rataFlash® Wireless Memory (L18) may contain design defects or errors known as errata which may cause the product to deviate from
published spec ifications. Current characterized err ata are available on requ est .
Intel may make cha nges to speci ficatio ns and prod uct descript io ns at any time, witho ut noti ce.
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Contact your local Intel sale s office or your distribu tor to obtain the latest specifi cation s and befo re placi ng your product order.
Copies of documents wh ich have an order numb er and are referenc ed in this docum ent, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyrigh t © 2005, Intel Corpor ation. All Rights Reserved.
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 3
Contents
1.0 Introduction ...............................................................................................................................9
1.1 Nomenclature .......................................................................................................................9
1.2 Acronyms..............................................................................................................................9
1.3 Conventions........................................................................................................................10
2.0 Functional Overview ............................................................................................................11
3.0 Package Information............................................................................................................12
3.1 VF BGA Packages..............................................................................................................12
3.2 SCSP Packages.................................................................................................................14
4.0 Ballout and Signal Descriptions ......................................................................................16
4.1 Signal Ballout......................................................................................................................16
4.1.1 VF BGA Package Ballout.......................................................................................16
4.1.2 SCSP Package Ballout..........................................................................................18
4.2 Signal Descriptions.............................................................................................................19
4.2.1 VF BGA Package Signal Descriptions...................................................................19
4.2.2 128/0 and 256/0 SCSP Package Signal Descriptions ...........................................21
4.3 Memory Map.......................................................................................................................23
5.0 Maximum Ratings and Operating Conditions ...........................................................25
5.1 Absolute Maximum Ratings................................................................................................25
5.2 Operati n g Cond iti o n s. .................... ........................................... ..........................................25
6.0 Electrical Specifications.....................................................................................................26
6.1 DC Current Characteristics.................................................................................................26
6.2 DC Voltage Characteristics.................................................................................................27
7.0 AC Charact eris tics................................................................................................................28
7.1 AC Test Conditions................. ............. ............................................ ...................................28
7.2 Capacitance........................................................................................................................29
7.3 AC Read Specifications (VCCQ = 1.35 V – 2.0 V) ............................................................30
7.4 AC Read Specifications 64- and 128-Mbit (VCCQ = 1.7–2.0 V) ........................................31
7.5 AC Read Specifications 256-Mbit (VCCQ = 1.7–2.0 V) .....................................................32
7.6 AC Write Specifi ca tio n s... .... ............. ........................................... .......................................37
7.7 Program and Erase Characteristics....................................................................................41
8.0 Power and R eset Speci fi cations .....................................................................................42
8.1 Power Up and Down...........................................................................................................42
8.2 Reset ..................................................................................................................................42
8.3 Power Supply Decoupling ...................................................................................................43
8.4 Automatic Power Saving .....................................................................................................44
9.0 Device Operati ons.................................................................................................................45
9.1 Bus Operations...................................................................................................................45
9.1.1 Reads ....................................................................................................................46
9.1.2 Writes.....................................................................................................................46
9.1. 3 Outpu t Disa b l e.... .................................. ........................................... ......................46
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
4 Order Numb er: 25190 2, Revision: 010
9.1.4 Standby..................................................................................................................46
9.1.5 Reset .....................................................................................................................46
9.2 Device Commands .............................................................................................................47
9.3 Command Definitions .........................................................................................................48
10.0 Read Operations....................................................................................................................50
10.1 Asynchronous Page-Mode Read........................................................................................50
10.2 Synchronous Burst-Mode Read..........................................................................................5 0
10.2.1 Burst Suspend.......................................................................................................5 1
10.3 Read Configuration Register (RCR)...................................................................................51
10.3.1 Read Mode............................................................................................................5 2
10.3.2 Latency Count........................................................................................................52
10.3.3 WAIT Polarity.........................................................................................................54
10.3.3.1 WAIT Signal Function............................................................................54
10.3.4 Data Hold...............................................................................................................55
10.3.5 WAIT Delay............................................................................................................56
10.3.6 Burst Sequence.....................................................................................................56
10.3.7 Clock Edge............................................................................................................57
10.3.8 Burst Wrap.............................................................................................................57
10.3.9 Burst Length ..........................................................................................................5 7
11.0 Programming Operations ..................................................................................................58
11.1 Word Programming.............................................................................................................58
11. 1. 1 Fac tory Wo rd Pro gr amming. ............. ............. .............. ............. ............. ....... ... ......59
11.2 Buffered Programming........................................................................................................59
11. 3 Buff er ed Enh ance d Fact ory Pro g rammi ng .... .................... ............. .............. ............. .........60
11. 3. 1 Buf fe red EFP Requir e m ents an d Consi der at i ons.............. .... ............. ... .............. ..60
11. 3. 2 Buf fe red EFP Setup Phase ......................... ............. .............. ............. ...................61
11.3.3 Buffered EFP Program/Verify Phase.....................................................................6 1
11.3.4 Buffered EFP Exit Phase.......................................................................................62
11. 4 Pro gram Suspe nd............... .............. ............. ............. .............. ............. ....... ... ...................62
11. 5 Pro gram Re su me...... .... ............. ............. .............. ............. ............. .............. ............. .........63
11. 6 Pro gram Prote ction....... ... .................... ....... ... ........................... ............. ............. ............ ....63
12.0 Erase Operati ons...................................................................................................................64
12.1 Block Erase.........................................................................................................................6 4
12.2 Erase Suspend...................................................................................................................64
12.3 Erase Resume....................................................................................................................6 5
12.4 Erase Protection.................................................................................................................65
13.0 Security Modes.......................................................................................................................66
13.1 Block Locking......................................................................................................................6 6
13.1.1 Lock Block .............................................................................................................66
13.1.2 Unlock Block..........................................................................................................66
13. 1. 3 Lock -D ow n Bloc k....... .......................... .............. ............. ............. .............. ............66
13. 1. 4 Blo ck Lo ck Sta tu s...... .................... ............. ........................................... ................67
13.1.5 Block Locking During Suspend..............................................................................6 7
13. 2 Pro tec tio n Re gis te rs ......................... ... .................... ............. .............. ............................ ....68
13. 2. 1 Re adi n g the Prote cti o n Regis t e rs....................................................... ... ................69
13.2.2 Programming the Protection Registers..................................................................7 0
13.2.3 Locking the Protection Registe rs...........................................................................70
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 5
14.0 Dual-Operation Considerations.......................................................................................71
14.1 Memory Partitioning............................................................................................................71
14.2 Read-While-Write Command Sequences...........................................................................71
14.2.1 Simultaneous Operation Details ............................................................................72
14.2.2 Synchronous and Asynchronous RWW Characteristics and Waveforms..............72
14.2.2.1 Write operation to asynchronous read transition ...................................72
14.2.2.2 Write to synchronous read operation transition .....................................73
14. 2. 2. 3 Writ e Ope ra tio n with Cloc k Acti v e...... ............. .......................................73
14.2.3 Rea d Opera tio n Du rin g Buffere d Programmi n g.... .... ............. ............. .............. .....73
14.3 Simu ltan e ous Oper a tio n Restr i ctio n s ...... .......................... .............. ............. ............. .........74
15.0 Special Read States ..............................................................................................................75
15.1 Read Status Register..........................................................................................................75
15.1.1 Clear Status Register.............................................................................................76
15.2 Read Device Identifier ........................................................................................................76
15.3 CFI Que ry.... .... ............. ... .............. ... .................... ............. .............. ...................................77
Appendix A Write State Machine (WS M)...........................................................................78
Appendix B Flowcharts............................................................................................................85
Appendix C Common Flash Interface................................................................................93
Appendix D Additional In formation...................................................................................103
Appendix E Ordering Information......................................................................................104
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
6 Order Numb er: 25190 2, Revision: 010
Revision History
Revisio n Da te Revi sion Desc r i p t i o n
10/15/02 -001 Initial Release
01/20/03 -002 Revised 256-Mbit Partition Size
Revised 256-Mbit Memory Map
Change W AIT function to de-ass ert during Asynchronou s Operations (Asy nchronous Reads and all
Writes)
Change WAIT function to active during Synchronous Non-Array Read
Updated all Waveforms to reflect new WAIT function
Revised Section 8.2.2
Added Synchronous Read to Write transition Section
Improved 1.8 Volt I/O Bin 2 speed to 95ns from 105ns
Added new AC specs: R15, R16, R17, R111, R311, R312, W21, and W22
Various text edit s
04/11/03 -003 Added SCSP for 128/0 and 256/0 Ball-out and Mechanical Drawing
08/04/03 -004 Changed ICCS and ICCR values
Added 256- Mbit AC Speed
Changed Program and Erase Spec
Combined the Buffered Programming Flow Chart and Read While Buffered programming Flow
Chart
Revised Read While Buffered Programming Flow Chart
Revised Appendix A Write State Machine
Revised CFI Table 21 CFI Identification
Various text edit s.
01/20/04 -005 Various text clarifications, various text edits, block locking state diagram clarification, synchronous
read to write timing clarification, write to synchronous read timing clarification
05/22/04 -006 Minor text edits
Changed Capacitance values
Changed Standby Curr ent (typ), Power Down Current (typ), Erase Suspend Current (typ), and
Automatic Power Sav ings Curr ent (typ)
Updated Transient Equialent Testing Load Circuit
09/02/04 -007 Added Table 7 “Bus Operations Summar y” on page 45
Modified Table 32 “L18 S CSP Packag e Order i ng Info rmation” on p age 105 and added th e following
order items:
* RD48F2000L0Y TQ0, RD48F2000L0YBQ0
* RD48F4000L0Y TQ0, RD48F4000L0YBQ0
* PF48F3000L0YTQ0, PF48F3000L0YBQ0
* PF48F4000L0YTQ0, PF48F4000L0YBQ0
* NZ48F4000L0YTQ0, NZ48F4000L0YBQ0
* JZ48F4000LOYTQ0, JZ48F4000LOYBQ0
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 7
09/29/04 -008 Removed two mechanical drawings for 9x7.7x1.0 mm and 9x11x1.0 mm
Added mechanical drawing Figure 4 “256-Mbit, 88-ball (80-active ball) SCSP Drawing and Dimen-
sions (8x11x1.0 mm)” on page 15
In Table 32 “L18 SCSP Package Ordering Information” on page 105, corrected 256L18 package
size from 8x10x1.2 mm to 8x11x1.2 mm
04/22/05 -009 Removed Bin 2 LC and Frequency Support Tables
Added back VF BGA mechanical drawings
Renamed 256-Mbit UT-SCSP to be 256-Mbit SCSP
Updated Ordering Info
Minor text edits
Converted datasheet to new template
In Table 4 “Bottom Parameter Memory Map” on page 24, corrected 256-Mbit Blk 131 address
range from 100000 - 10FFFF to 800000 - 80FFFF
In Section 5.1, “Absolute Maximum Ratings” on page 25, corrected Voltage on any signal (except
VCC, VPP) from -0.5 V to +3.8 V to -0.5 V to +2.5 V
In Section E.2, “Ordering Information for SCSP” on page 105, corrected package designators for
leaded and lead-free packages from RD/PF to NZ/JZ
8/4/05 -010 Recreated the PDF to r esolve some display problems.
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
8 Order Numb er: 25190 2, Revision: 010
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 9
1.0 Introduction
Th is document pr ovides inf ormatio n about the Intel StrataFlash® wireless memory device (L18).
This docu men t describes the device features, operation, and specifications.
1.1 Nomenclature
1. 8 V: ran ge of 1.7 V – 2. 0 V (exc e pt whe re no t ed )
1.8 V Exten d e d Ra n g e : range of 1.35 V – 2.0 V
VPP = 9.0 V: VPP volt a ge range of 8.5 V – 9.5 V
Block: A group of bits, bytes or words within the flash memor y arr ay that erase simul taneously
when the Erase command is issued to the device. The Intel StrataFlash® Wireless Memory (L18)
has two block sizes: 16-Kword, and 64-Kword.
Main block: An a rray bloc k that is usually used to store code a nd/or data. Main bloc ks are la rge r
tha n parameter blocks.
Parameter block : An array block tha t is usually used to store fr e que ntly c ha nging da ta or smal l
system paramete rs that traditionally would be stored in EEPROM.
Top parameter device: Previous ly referred to as a to p-b oot device, a device w ith its paramet er
pa rtiti on located at the highest physical address of its memory map . Para meter blocks within a
parameter partition are located at the highest physi cal address of the param eter partiti on.
Bottom p arameter device: Previou sl y referred to as a bottom-bo ot device, a device with its
parameter partition located at th e lowest physical add ress of its memory map. Par ameter blocks
within a parameter partition are located at the low est physical address of the parameter partition.
Partition: A group of block s that share com mon pr ogram/er ase circuitry. Blocks with in a partition
al so share a common status register. If any block within a pa rtition is being programmed or erased,
only status register da ta (rather tha n array data) is available when a ny a ddress wi thin that part ition
is read.
Main partition: A partition cont a ining only main blocks.
Parameter pa rti tio n: A pa rtition containing parameter blocks and main bloc ks.
1.2 Acronyms
CUI: Command User Interface
MLC: Multi- Level Cell
OTP: One-Time Programmable
PLR: Protecti on Lock Register
PR: Protection Register
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
10 Order Number: 251902, Re vision: 010
RCR: Read Configuration Register
RFU: Rese rv e d for Fu t ur e Us e
SR: Status Register
WSM: Write State Machine
1.3 Conventions
VCC: si gn a l or volta ge co n ne c t ion
VCC: signal or voltage level
0x: hexa d e cimal num b e r prefix
0b: binary number prefix
SR[4]: Denote s an individu a l re giste r bit.
A[15:0]: Denotes a group of simila rly named signals, such as addres s or data bus.
A5: Denotes on e elem ent of a si gnal group members hip, such as an address.
bit: bin ar y un it
byte: eight bits
word: two by t es, or s i xt e e n bi ts
Kbit: 1024 bits
KByte: 1024 bytes
KWord: 1024 words
Mbit: 1,04 8,576 bits
MByte: 1,048,5 76 bytes
MWord: 1,048,576 words
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 11
2.0 Functional Overview
The Intel StrataFlash® Wireless Memory (L18) provides read-while-write and read-while-erase
ca pa bility with density upgrade s throu gh 256-Mbit. Th is family of devices provide s high
perfor mance at low voltage o n a 16-bit dat a bus. Indiv idually erasable m emory blo cks are sized f or
optimum cod e a nd data storage.
Each devic e de nsity contain s one parameter pa rtiti on a nd several main pa rtitions. The flash
mem ory ar ray is group ed in to mult ipl e 8- Mbi t or 16-Mbi t par ti tio ns. By div idi ng the fla sh m emory
into partitions, program or erase operations can take place at the same time as read operations.
Although each partitio n has write , er ase, and burs t read capabilities, simultaneous operation is
lim ited to write or eras e in one parti tion while other part itions are in read m ode. The Int el
StrataFlash® Wireless Memory (L18) allows bur st reads that cross part ition boundari es . User
application code is responsible for ensuring that bur s t reads do not cross int o a par tition that is
programming or eras ing.
Upon init ia l power up or return fr om reset, the de vice d e faults to asynchronous page-mode rea d.
Configuring the Re a d Configurati on Re gister enabl e s s ynchronous burst-mode r e a ds. In
synchronous bu rst mode, output data is synchronize d with a user-supplied cl ock signal. A WAIT
signal provides easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and in terface, the Int el Strata Flash® Wireless Memory
(L18) i ncorpo rates tech nolog y that enables fast f acto ry program and er ase oper ations . Desig ned for
low-voltag e systems, the Intel StrataFlash® Wireless Memory (L18) supports read operations with
VCC at 1.8 volt, and erase and program operat ions with VPP at 1.8 V or 9.0 V. Buffered Enh anced
Fac tory Progr amming (Buffer e d EFP) provide s the fastes t flash array programming performance
with VPP at 9.0 volt, which in c reases factory throughput. W ith VPP at 1.8 V, VCC an d VPP can be
tied to gether for a simpl e, u ltra-low power des ign. In additi on to voltage flexibility, a dedicat ed
VPP conne c t ion provides complete da ta protection when VPP is less th an VPPLK.
A Command User I nterface (CUI ) is the interface between the system proc essor and all internal
oper ations of the Intel S trataFlash® Wireless Memor y (L18 ). An inter nal Write State Machine
(WSM) automatically executes the algorithms and timings necessary for block erase and program.
A Status Register indicates erase or program completion an d any erro rs that may have occurred .
An industry-standard c omman d se quence invokes program and erase automation. Each erase
operation erases one block. The Erase Sus pend f eature allows syst em software to pause an erase
cycle to r ead or program data in another block. Progr a m Suspend allows system so ftware to pause
programming to read othe r locations. Da ta i s pr ogrammed in word increments.
The Intel StrataFlash® Wireless Memory (L18) offers power savings through Automatic Power
Savi ngs (A PS) mode and stan dby mode. Th e devic e automat icall y enters APS foll owing r ead-cyc le
completion. Standby is initiated wh en the system des e lects the devic e by dea sser ting CE# or by
asser ting RST#. Combined, these features can significantly reduce po wer consumptio n.
Th e Intel St rataFlash ® Wireless Me mory (L18)’s protectio n re gister allows unique flash devi c e
ident ification that can be used to increase system security. Al so, the individual Block Lock feature
provide s z e ro - l a te n c y bloc k lo c king a nd un l o c ki ng.
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
12 Order Number: 251902, Re vision: 010
3.0 P ackage Information
3.1 VF BGA Packages
Figure 1. 64- and 128-Mbit, 56-B all VF BGA Packag e Drawing and Dime nsions
E
Seating
Plane
Top View - Ball Si de Down Bottom View - Ball Side Up
Y
A
A1
D
A2
A1 Ind e x
Mark
S1
S2
e
b
A1 In dex
Mark
A
B
C
D
E
F
G
87654321 876 54321
A
B
C
D
E
F
G
Note: Drawing not to sc ale
Side View
Millimeters Inches
Dimensions Symbol Min Nom Max Notes Min Nom Max
Package Height A 1.000 0.0394
Ball Height A1 0.150 0.0059
Package Body Thickness A2 0.665 0.0262
Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167
Package Body Length (64Mb, 128Mb) D 7.600 7.700 7.800 0.2992 0.3031 0.3071
Package Body Width (64Mb, 128Mb) E 8.900 9.000 9.100 0.3504 0.3543 0.3583
Pitch e 0.75 0 0.02 95
Ball (Lead) Count N 56 56
Seati ng P lane C oplanar ity Y 0.1 00 0.0039
Corner to Ball A1 Distance Along D S1 1.125 1.225 1.325 0.0443 0.0482 0.0522
Corner to Ball A1 Distance Along E S2 2.150 2.250 2.350 0.0846 0.0886 0.0925
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 13
Fig u re 2. 256-M b it, 79 -Ball VF BGA Pac kage Drawing and Dimension s
Dimensions Table
Side View
Top View - Ball Side Down Bottom View - Ball Side Up
A2 A
Seating
Plane
Y
A1
S2
A1 Index
Mark
E
b
A1 I ndex
Mark
S1
e
D
A
B
C
D
E
F
G
4567321
8
910111213
A
B
C
D
E
F
G
456732189
10 11 1213
Drawing not to scale
Millimeters Inches
Dimensions Symbol Min Nom Max Notes Min Nom Max
Package Height A 1.000 0.0394
Ball Height A1 0.150 0.0059
Pack age Body T hi ckness A2 0.66 5 0 . 0262
Ball (Lead) Width b 0.325 0. 3 75 0 .425 0.0128 0. 0148 0. 0 167
Package Body Length (256Mb) D 10.900 11.000 11.100 0.4291 0.4331 0.4370
Package Body Width (256Mb) E 8.900 9.000 9.100 0.3504 0.3543 0.3583
Pitch e 0.7 50 0.02 95
Ball (Lead) Count N 79 79
Seating Plane Coplanarity Y 0.100 0.0039
Corner to Ball A1 Distance Along D S1 0.900 1.000 1.100 0.0354 0.0394 0.0433
Corner to Ball A1 Di stance Along E S2 2 .15 0 2 .2 50 2.350 0 .08 46 0.08 86 0.0 92 5
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
14 Order Number: 251902, Re vision: 010
3.2 SCSP Packages
Figure 3. 128-Mbit, 88-ball (80-active ball) SCSP Drawing and Dimensions (8x10x1.2 mm)
Millimeters Inches
Dimensions S ymbol Min Nom Max Notes Min N om Max
Pa ckage H eight A 1.200 0.0472
Ball H eigh t A 1 0.200 0.0079
Pa ckage Body T hickness A 2 0.860 0.0339
Ball (Lead) W id th b 0.325 0.375 0.425 0.0128 0.01 48 0.0167
Pa ckag e B od y Leng th D 9.900 10.000 10.1 00 0.3898 0.39 37 0.3976
Pa ckag e B od y W idth E 7.900 8.000 8.100 0.3110 0.31 50 0.3189
Pitch e 0.800 0.03 15
Ball (Lead ) Co un t N 88 88
Se ating Plan e Coplan arity Y 0.100 0.0039
Corne r to B all A 1 Distan ce A lo ng E S1 1.100 1.200 1.300 0.0433 0.04 72 0.0512
Corne r to B all A 1 Distan ce A lo ng D S2 0.500 0.600 0.700 0.0197 0.02 36 0.0276
Top View - Ball Down Bottom View - Ball
Up
A
A2
D
E
Y
A1
Draw ing not to scale.
S2
S1
A
C
B
E
D
G
F
J
H
K
L
M
e
1
2345678
b
A
C
B
E
D
G
F
J
H
K
L
M
A 1 Index
Mark
12345678
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 15
Figure 4. 256-Mbit, 88 -ba ll (80-act ive ball) SCSP Dr awing and Dimensions (8x11x1.0 mm)
Millimeters Inches
Dimensions Symbol Min Nom Max Notes Min Nom Max
Package Height A 1.00 0.0394
B all He ight A 1 0.117 0.0046
Packag e Body T h icknes s A 2 0.740 0.0291
B all (Lea d ) W id th b 0.300 0.350 0.400 0.0118 0.0138 0.0157
Packag e Body Len gth D 10.900 11.00 11.100 0.4291 0.4331 0.4370
Packag e Body W id th E 7.900 8.00 8.100 0.3110 0.3150 0.3189
P itch e 0.8 0 0 .03 1 5
Ball (Lead) Count N 88 88
Seating Plane Coplanarity Y 0.100 0.0039
Corner to Ball A 1 D istance A lon g E S1 1.100 1.200 1.300 0.0433 0.0472 0.0512
Corner to Ball A 1 D istance A lon g D S2 1.000 1.100 1.200 0.0394 0.0433 0.0472
Top View - Ball Down Bottom View - Ball U p
A
A2
D
E
Y
A1
D rawing not to scale.
S2
S1
A
C
B
E
D
G
F
J
H
K
L
M
e
1
2345678
b
A
C
B
E
D
G
F
J
H
K
L
M
A1 Index
Mark
123 456 78
Note: Dimensions A1, A2, and b are preliminary
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
16 Order Number: 251902, Re vision: 010
4.0 B allout and Signal Descriptions
4.1 Sig nal Ba llout
This sectio n includes signal ballouts for the f ollowing packages:
•VF BGA Package Ballout
•SCSP Package Bal lout
4.1.1 VF BGA Package B allout
The Intel StrataFlash® Wireles s Memory (L18) is available in a VF BGA p ackage with 0.75 m m
ball-pitch. Figure 5 s hows th e bal lou t for th e 64 -Mbit and 128 -M bit dev ices in th e 56 -b all VF BGA
package with a 7x8 ac tiv e-ball matrix. Figure 6 shows the dev ice ball out f or th e 25 6- Mbit devic e in
the 63-b all VF BGA package with a 7x9 activ e-ball matrix. Both package densitie s are ideal for
space-constrained board applications
Note: On lower-density devices, upper-address balls can be treated as NC. (e.g., for 64-Mbit density, A22 will be NC)
Fig ur e 5. 7x8 Act ive-Ball Matrix for 64-, and 128-Mbit Dens i ties in VF BGA Pack ag es
V FBG A 7x 8
Bot tom Vie w - Ba ll Side Up
V FBGA 7x8
Top Vi e w - Bal l Side Dow n
23456781
A8 VSS VCC VPP A18 A6 A4
A9 A20 CLK RST# A17 A5 A3
A10 A21 WE# A19 A7 A2
A14 WAIT A16 D12 WP# A22
D15 D6 D4 D2 D1 CE# A0
D14 D13 D11 D10 D9 D0 OE#
ADV#
A1
VSSQ VCC D3 VCCQ D8 VSSQ
A11
A12
A13
A15
VCCQ
VSS
D7 D5
A
B
C
D
E
F
G
23456781
A8VSSVCCVPPA18A6A4
A9A20CLKRST#A17A5A3
A10A21WE#A19A7A2
A14WAITA16
D12WP#
A22
D15D6
D4
D2D1CE#A0
D14D13D11D10D9D0
OE#
ADV#
A1
VSSQVCCD3VCCQD8VSSQ
A11
A12
A13
A15
VCCQ
VSS
D7D5
A
B
C
D
E
F
G
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 17
Note: On lower density devices upper address balls can be treated as RFUs. (A24 is for 512-Mbit and A25 is for 1-Gbit
densities). All ball locations are populated.
Fig u r e 6. 7x9 Active -Ball Matrix for 256-M b it Density in V F BGA Package
RFU VCCA4 A6 A18 VPP VSS A8 A11
RFU CLK
A3 A5 A17 RST# A20 A9 A12
A25 ADV#A2 A7 A19 WE# A21 A10 A13
A24 A16A1 A22 WP# D12 WAIT A14 A15
A23 D4A0 CE# D1 D2 D6 D15 VCCQ
RFU D11OE# D0 D9 D10 D13 D14 VSS
RFU VCCVSSQ D8 VCCQ D3 D5 VSSQ D7
Bottom View - Ball Side Up
A
B
C
D
E
F
G
DU
DU DU
DU
DU
DU DU
DU DU
DU DU
DU
DU
DU DU
DU
11 101213 7 5 4 3 2 1
896
RFUVCC A4A6A18VPPVSSA8A11
RFUCLK A3A5A17RST#A20A9A12
A25
ADV# A2A7A19WE#
A21A10
A13
A24A16 A1A22WP#D12WAITA14A15
A23
D4 A0CE#D1D2
D6D15
VCCQ
RFUD11 OE#D0D9D10D13D14VSS
RFUVCC VSSQD8VCCQD3D5VSSQD7
Top Vie w- B a ll Sid e D own
A
B
C
D
E
F
G
DU
DUDU
DU
DU
DUDU
DU
DU
DUDU
DU
DU
DUDU
DU
1110 12 1375432
1896
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
18 Order Number: 251902, Re vision: 010
4.1.2 SCSP Package Ballout
The L18 wireless memory in QUAD+ ballout device is available in an 88-ball (80-a ctive ball)
St acked Chip Scale Package (S CSP) for the 128- and 256-Mbit devices. For Mec hani cal
Information, refer t o Section 3.0, “Pack age Information” on page 12.
Figure 7. 88-Ball (80-Active Ball) SCSP Package Ba llout
F lash s
p
ecific
SR AM /PSR AM specific
G lobal
Legend:
Top View - Ball Side Dow n
87654321
A
B
C
D
E
F
G
H
J
K
L
M
DU
A4
DU DU DU
DUDUDU DU
A5
A3
A2 A7
A1 A6
A0
A18 A19 VSS
VSSA23
A24
A25
A17
F2-V C C
CLK
A21
A22 A12
A11
A13A9P1-CS#
F-VPP,
F-VPEN
A20 A10 A15
F-W E # A 8
D8 D2 D10 D5 D13 W AIT
A14 A16
F1 -C E # P -M ode
VSS VSS VSS
P2-CS#
F1-V C C
F2-VCC VCCQF3 -C E #
D0 D1
D9
D3
D4 D6
D7
D15D11
D12 D14
F1-O E #
F2-O E #
P-VCC
S-CS2
R-W E#
R-UB#
R-LB#
R-O E#
S-VCC
S-CS1#
F1-V C C
F-W P # A D V #
F-R ST#
F2-C E #
VCCQ
VSS VSSVCCQ VSS
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 19
4.2 Signal Descriptions
This section includes signal descriptions for the following packages:
•VF BGA Package Signal Descriptions
•SCSP P a c ka ge Signal De scriptions
4.2.1 VF BGA Package Signal Descriptions
Table 1 describes the active signals used on the Intel S trataFlash® Wireless Memory (L18), VF
BGA package.
Table 1. S i g n al Descriptions (Sheet 1 of 2)
Symbol Type Name and Function
A[MAX:0] Input ADDRESS: Device address inputs. 64-Mbit: A[21:0]; 128-Mbit: A [22:0]; 256-Mbit: A[23:0].
DQ[15:0] Input/
Output
DA TA INPUT/OUTPUTS: Inputs data and commands during wr ite c ycle s; output s dat a dur i ng memory,
Status Register, Protection Register, and Read Configuration Register reads. Data balls float when the
CE# or OE# are deasserted. Data is internally latched during writes.
ADV# Input
ADDRESS VALI D: Active-low input. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
In asynchronous mode, the address is latched when ADV# going high or continuously flows through if
ADV# is held low.
CE# Input CHIP ENABLE: Active-low input. CE#-lo w selects the device. CE#-high desel ects t he dev ice, placing it
in standby, w ith DQ[15:0] and WAIT in High-Z.
CLK Input CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode and
increment s the internal address generat or . During synchrono us read operations , addresses are latche d
on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, w hichever occurs first.
OE# Input OUTPUT ENABLE: Active- low input. OE#-low enables the device’s output data buffers during read
cycles. OE#-high places the data outputs in High-Z and WAIT in High-Z.
RST# Input RESET: Active-low input. RST# resets internal automation and inhibits write operations. This provides
data protection during power transitions. RST#-high enables normal operation. Exit from reset places
the device in asynchronous read array mode.
WAIT Output
WAIT: Indicates dat a valid in synchronous ar ray o r n on-ar ray burst r eads . Conf iguration Regis ter bit 10
(RCR[10], WT) determines its polarity when asserted. With CE# and OE# at VIL, WAIT’s active output
is VOL or VOH when CE# and OE# are asserted. WAIT is high-Z if CE# or OE# is VIH.
• In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when deasserted.
• In asynchronous page mode, and all write modes, WAIT is deasserted.
WE# Input WRITE ENABLE: Active-low input. WE# controls writes to the device. Addres s and dat a are latched on
the rising edge of WE#.
WP# Input WRITE PROTECT: Active- low input. WP#-low enabl es the lock -down m echanis m. Block s i n lock -down
cannot be unlocked with the Unlock command. WP#-high overrides the lock-down function enabling
blocks to be erased or programmed using software commands.
VPP Power
/lnput
Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory
contents cannot be altered when VPP ≤ VPPLK. Block eras e and pr og ram at in valid VPP volt ages s hould
not be attempted.
Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, the VIH level of VPP can be as low as VPPLmin. VPP must remain above
VPPLmin to perform in-system program or erase. VPP may be 0 V during read operations.
VPPH can be applied to m ain bl ocks for 1 000 cy cles max imum and to param eter bloc ks for 2500 cycles.
VPP can be connected to 9 V for a cumulati ve tota l not to exceed 80 hours . Extended use of this pin at
9 V may derate flash performance/behavior.
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
20 Order Number: 251902, Re vision: 010
VCC Power Device Core Power Supply: C ore (logic) source voltage. Writes to the flash array are inhibited when
VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted.
VCCQ Power Output Power Supply: Output-driver source voltage. This ball can be tied directly to VCC if operating
within VCC range.
VSS Power Ground: Ground reference for device logic voltag es. Connect to system ground.
VSSQ Power Ground: Ground reference for device output voltages. Connect to system ground.
DU — Do Not Use: Do not use this ball. This ball should not be connected to any power supplies, signals or
other balls, and must be left floating.
RFU — Reserved for Future Use: Reserved by Intel for future device functionality and enhancement.
Table 1. Signal Descri ptions (S hee t 2 of 2)
Symbol Type Name and Function
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 21
4.2.2 12 8/0 and 256/0 SCSP Package Signal Descriptions
Table 2 describes the active signals use d on the 12 8/0 and 256/0 SCSP.
Table 2. Dev i ce Signal Descr iptions fo r S CSP (Sheet 1 of 2)
Symbol Type Description
A[Max:0] Input ADDRESS INPUTS: Inputs for all die addresses during read and write operations.
• 128-Mbit Die: A[Max] = A22
• 256-Mbit Die: A[Max] = A23
DQ[15:0] Input/
Output
DATA INPUTS/OUTPU TS: Inputs data and commands during write cycles, outputs data during read
cycles. Data signals float when the device or its outputs are deselected. Data is internally latched
during writes.
F1-CE#
F2-CE#
F3-CE# Input
FLASH CHIP ENABLE: Low-true: selects the associated flash memory die. When asserted, flash
internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the
associated flash die is deselected, power is reduced to standby levels, data and WAIT outputs are
placed in high-Z state.
F1-CE# selects the flash die.
F2-CE# and F3-CE# are available on stacked combinations with two or three flash dies else they are
RFU. They each can be tied high to VCCQ through a 10K-ohm resistor for future design flexibility.
S-CS1#
S-CS2 Input
SRAM CHIP SELECTS: When both SRAM chip selects are asserted, SRAM internal control logic,
input buffers, decoders, and sense amplifiers are active. When either/both SRAM chip selects are
deasserte d (S-CS1# = VIH or S-CS2 = VIL), the SRAM is deselected and its power is reduced to
standby levels.
Treat this signal as NC (No Connect) for this device.
P-CS# Input
PSRAM CHIP SELECT: Low-true; when asserted, PSRAM internal control logic, input buffers,
decoders, and sense ampli fiers are act ive. When deasserted, the PSRAM is deselected and its pow er
is reduced to standby levels.
Treat this signal as NC (No Connect) for this device.
F1-OE#
F2-OE# Input
FLASH OUTPUT ENABLE: Low-true; enables the flash output buffers. OE#-high disables the flash
output buffers, and places the flash outputs in High-Z.
F1-OE# controls the outputs of the flash die.
F2-OE# is available on stacked combinations with two or three flash dies else it is RFU. It can be
pulled high to VCCQ through a 10K-ohm r esistor for futur e design flexibility.
R-OE# Input RAM OUTPUT ENABLE: Low-true; R-OE#-low enables the s electe d R AM output bu ffers . R-O E#-high
disables the RAM output buffers, and places the selected RAM outputs in High-Z.
Treat this signal as NC (No Connect) for this device.
WE# Input FLASH WRITE ENABLE: Low-true; WE# controls writes to the selected flash die. Address and data
are latched on the rising edge of WE#.
R-WE# Input RAM WRITE ENABLE: Low-true; R-WE# controls writes to the selected RAM die.
Treat this signal as NC (No Connect) for this device.
CLK Input
FLASH CLOCK: Synchronizes the devi ce w ith th e sys tem’ s b us fr equenc y in sync hronous- read m ode
and increments the internal address generator. During synchronous read operations, addresses are
latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs
first.
WAIT Output
FLASH WAIT: Indicates data valid in synchronous array or non-array burst reads. Configuration
Register bit 10 (RCR[10], WT) determines its polarity when asserted. With CE# and OE# at VIL,
W AIT’ s active output is VOL or VOH when CE# and OE# are asserted. WAIT is high-Z if CE# or OE# is
VIH.
• In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when deasserted.
• In asynchronous page mode, and all write modes, WAIT is deasserted.
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
22 Order Number: 251902, Re vision: 010
WP# Input
FLASH WRITE PROTECT: Low-true; WP# enables/disables the lock-down protection mechanism of
the selected flash die. WP#-low enables the lock-down mechanism - locked down blocks cannot be
unlocked with software commands. WP#-high disables the lock-down mechanism, allowing locked
down blocks to be unlocked with software commands.
ADV# Input
FLASH ADDRESS VALID: Active-low input. During synchronous read operations, addresses are
latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs
first.
In asynchronous mode, the address is latched when ADV# going high or continuously flows through if
ADV# is held low.
R-UB#
R-LB# Input RAM UPPER / LOWER BYTE ENABLES: Low-true; During RAM reads , R-UB#-l ow enables the RAM
high order bytes on DQ[15:8], and R-LB#-low enables the RAM low-order bytes on DQ[7:0].
Treat this signal as NC (No Connect) for this device.
RST# Input FLASH RESET: Low-true; RST#-low initializes flash internal circuitry and disables flash operations.
RST#-high enables flas h operation. E xit from reset pl aces the fla sh in asy nchronous r ead arr ay mo de.
P-Mode Input PSRAM MODE: Low-true; P-MODE is used to program the configuration register, and enter/exit low
power mode.
Treat this signal as NC (No Connect) for this device.
VPP,
VPEN Power/
Input
Flash Program/Erase Power: A valid voltage on this pin allows erasing or programming. Memory
contents cannot be alter ed when VPP ≤ VPPLK. Block er as e an d progr am at invalid VPP volt ages should
not be attempted.
Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, the VIH level of VPP can be as low as VPPLmin. VPP must remain above
VPPLmin to perform in-system flash modification. VPP may be 0 V during read operations.
VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
cycles. VPP c an be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9 V may reduce block cycling capability.
VPEN (Erase/Program/Block Lock Enables) is not available for L18 products.
F1-VCC
F2-VCC Power Flash Logic Power: F1 -VCC suppli es power to the core logic of flash die #1; F2-VC C supplies power
to the core logic of flash die #2. Write operations are inhibited when VCC ≤ VLKO. Device operations at
invalid VCC voltages should not be attem p ted.
S-VCC Power SRAM Power Supply: Supplies power for SRAM operations.
Treat this signal as NC (No Connect) for this device.
P-VCC Power PSRAM Power Supply: Supplies power for PSRAM operations.
Treat this signal as NC (No Connect) for this device.
VCCQ Power Flash I/O Power: Supply power for the input and output buffer s.
VSS Power Ground: Connect to system ground. Do not float any VSS connection.
RFU — Reserved for Future Use: Reserve for future device functionality/ enhancements. Contact Intel
regarding their future use.
DU — Do Not Use: Do not connect to any other signal, or power supply; must be left floating.
NC — No Connect: No internal connection; can be driven or floated.
Table 2. D evice Signa l Des criptions for SCSP (Shee t 2 of 2)
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 23
4.3 Memor y Map
See Table 3 and Table 4. The memory arr a y is divided into multip le partitions; one pa ram e ter
partition and several main partitions:
•64-Mbit devi c e . This contains ei ght partitions: on e 8-Mbit para meter partition, seven 8-Mbit
main par titions.
•128-Mbit dev ic e . This contains six t e e n part itions: one 8-Mbit parameter pa rtition, fif t e en 8-
Mbit main partitions.
•256-Mbit dev ic e . This c ontains sixte e n part itions: one 16-Mbit paramete r part ition, fifteen 16 -
Mbit main partitions.
Table 3. Top Parameter Memory Map
Size (KW ) Blk 64-Mbit Size (KW) Blk 128-Mb it
43
8-Mbit Parame ter
Partition
One Partitio n
16 66 3FC000-3FFFFF
8-Mbit Parame ter
Partition
One Partitio n
16 130 7FC000-7FFFFF
16 65 3F8000-3FBFFF 16 129 7F8000-7FBFFF
16 64 3F4000-3F7FFF 16 128 7F4000-7F7FFF
16 63 3F0000-3F3FFF 16 127 7F0000-7F3FFF
64 62 3E0000-3EFFFF 64 126 7E0000-7EFFFF
…
…
…
…
…
…
64 56 380000-38FFFF 64 120 780000-78FFFF
8-Mbit Main
Partition
Seven
Partitions
64 55 370000-37FFFF
8-Mbit Main
Partitions
Fifteen
Partitions
64 119 770000-77FFFF
…
…
…
…
64 0 000000-00FFFF 64 0 000000-00FFFF
Si ze (KW) Blk 256-Mbit
16 -Mbit Pa ra mete r
Partition
One Partition
16 258 FFC000-FFFFFF
16 257 FF8000-FFBFFF
16 256 FF4000-FF7FFF
16 255 FF0000-FF3FFF
64 254 FE0000-FEFFFF
…
…
…
64 240 F00000-FFFFFF
16-Mbi t Main P a rtition s
Seven
Partitions
64 239 EF0000-EFFFFF
…
64 128 800000-80FFFF
Eight
Partitions
64 127 7F0000-7FFFFF
…
64 0 000000-00FFFF
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
24 Order Number: 251902, Re vision: 010
Table 4. Bottom Pa ram et er M emo ry M ap
Size (KW ) B l k 64-Mbit Size (KW ) Blk 128- Mbit
8-Mbit Main
Partitions
Seven
Partitions
64 66 3F0000-3FFFFF
8-Mbit Main
Partitions
Fifteen
Partitions
64 130 7F0000-7FFFFF
…
…
…
…
…
…
64 11 080000-08FFFF 64 11 080000-08FFFF
8- Mb i t P a rame te r
Partition
One Partition
64 10 070000-07FFFF
8- Mb i t P a rame te r
Partition
One Partition
64 10 070000-07FFFF
…
…
…
…
…
…
64 4 010000-01FFFF 64 4 010000-01FFFF
16 3 00C000-00FFFF 16 3 00C000-00FFFF
16 2 008000-00BFFF 16 2 008000-00BFFF
16 1 004000-007FFF 16 1 004000-007FFF
16 0 000000-003FFF 16 0 000000-003FFF
Size (KW ) B lk 256-Mbit
16-Mbit Main Partitions
Eight
Partitions
64 258 FF0000-FFFFFF
…
…
…
64 131 800000-80FFFF
Seven
Partitions
64 130 7F0000-7FFFFF
…
…
…
64 19 100000-10FFFF
16-Mbit Parameter
Partition
One Partition
64 18 0F0000-0FFFFF
…
…
…
64 4 010000-01FFFF
16 3 00C000-00FFFF
16 2 008000-00BFFF
16 1 004000-007FFF
16 0 000000-003FFF
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 25
5.0 Maximum Ratings and Operating Conditions
5.1 Absolute Maximum Ratings
Warning: Stressi ng the device beyo nd the “ Absolute Maximum Ratings” may ca use permanen t damage.
These are stre ss r atings only.
5.2 O perating Conditions
Warning: Opera tion be yond the “Op e ra ting Conditions” is not recommende d and e xtended exposure beyond
the “Operating Conditions” may affect device reliability.
Parameter Maximum Rating Notes
Temperature under bias –25 °C to +85 °C
Storage temperature –65 °C to +125 °C
Voltage on any signal (except VCC, VPP) –0.5 V to +2.5 V 1
VPP voltage –0.2 V to +10 V 1,2,3
VCC voltage –0.2 V to +2.5 V 1
VCCQ voltage –0.2 V to +2.5 V 1
Output short circuit current 100 mA 4
Notes:
1. Voltages shown are specified with respect to VSS. Minimum DC voltage is –0.5 V on input/output
signals and –0.2 V on VCC, VCCQ, and VPP. During transitions, this lev el may undersh oot to –2.0 V for
periods < 20 ns. Ma ximum DC v oltage on VCC is VCC +0.5 V, which, during transit ions, may o vershoot
to VCC +2.0 V for periods < 20 ns. Maximum DC voltage on input/output signals and VCCQ is VCCQ
+0.5 V, which, during transitions, may overshoot to VCCQ +2.0 V for periods < 20 ns.
2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods < 20 ns.
3. P rogram/erase voltage is typically 1.7 V – 2.0 V. 9.0 V can be applied for 80 hours maximum total, to
any blocks for 1000 cycles maximum. 9.0 V program/erase voltage may reduce block cycling
capability.
4. Output shorted for no more than one second. No more than one output shorted at a time.
Symbol Parameter Min Max Units Notes
TCOperating Temperature –25 +85 °C 1
VCC VCC Supply Voltage 1.7 2.0
V
VCCQ I/O Supply Voltage 1.8 V Range 1.7 2.0
1.8 V Extended Range 1.35 2.0
VPPL VPP Voltage Supply (Logic Level) 0.9 2.0
2
VPPH Factory word programming VPP 8.5 9.5
tPPH Maximum VPP Hours VPP = VPPH -80Hours
Block
Erase
Cycles
Main and Par ameter Blocks VPP = VCC 100,000 - CyclesMain Blocks VPP = VPPH -1000
Parame ter Blocks VPP = VPPH -2500
Notes:
1. TC = Case temperature
2. In typic al operation, the VPP pr ogram vol tage i s VPPL. VPP ca n be connec ted to 8.5 V – 9.5 V for 1000
cycles on main blocks and 2500 cycles on parameter blocks.
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
26 Order Number: 251902, Re vision: 010
6.0 Electrical Specifications
6.1 DC Current Characteristics
Sym Parameter VCCQ 1.7 V – 2.0 V
1.35 V - 2.0 V Unit Test Con ditions Notes
Typ Max
ILI Input Load Cur rent - ±1 µA VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or VSS 1
ILO Output
Leakage
Current DQ[15:0], WAIT - ±1 µA VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or VSS
ICCS
ICCD
VCC Standby,
Power Down
64-Mbit 15 30
µA
VCC = VCCMax
VCCQ = VCCQMax
CE# = VCCQ
RST# = VCCQ (for ICCS)
RST# = GND (for ICCD)
WP# = VIH 1,2
128-Mbit 20 70
256-Mbit 25 110
ICCAPS APS
64-Mbit 15 30
µA
VCC = VCCMax
VCCQ = VCCQMax
CE# = VSSQ
RST# = VCCQ
All inputs are at rail to rail (VCCQ
or VSSQ).
128-Mbit 20 70
256-Mbit 25 110
ICCR Average
VCC Read
Current
Asynchr onous Single- Word
f = 5MHz (1 CLK) 13 15 mA
VCC = VCCMax
CE# = VIL
OE # = VIH
Inputs: VIL or
VIH
1
Page-Mode Read
f = 13 MHz (5 CLK) 8 9 mA 4-Word Read
Synchronous Burst Read
f = 40MHz, LC = 3
12 16 mA Burst length = 4
14 18 mA Burst length = 8
16 20 mA Burst length = 16
20 25 mA Burst length =
Continuous
Synchronous Burst Read
f = 54MHz, LC = 4
15 18 mA Burst length = 4
18 22 mA Burst length = 8
21 25 mA Burst length = 16
22 27 mA Bur st Length =
Continuous
ICCW,
ICCE
VCC Prog ram Current,
VCC Erase Current
35 50 mA VPP = VPPL, program/erase in
progress 1,3,4,
7
25 32 mA VPP = VPPH, pro gram/er ase in
progress 1,3,5,
7
ICCWS,
ICCES
VCC Program Suspen d Curr ent,
VCC Erase Suspend Current
64-Mbit 15 30 µA CE# = VCCQ; suspend in progr ess 1 ,6,3128-Mbit 20 70
256-Mbit 25 110
IPPS,
IPPWS,
IPPES
VPP Standby Current,
VPP Program Suspend Current,
VPP Erase Suspend Current 0.2 5 µA VPP = VPPL, suspend in progress 1,3
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 27
6.2 DC Voltage Charac t erist i cs
IPPR VPP Read 2 15 µA VPP ≤ VCC
1,3
IPPW VPP Program Curren t 0.05 0.10 mA VPP = VPPL, program in progress
822 V
PP = VPPH, progr am in progress
IPPE VPP Erase Current 0.05 0.10 mA VPP = VPPL, erase in progress
822 V
PP = VPPH, erase in progress
Notes:
1. All currents are RMS unless noted. Ty pic al values at typical VCC, TC = +25°C.
2. ICCS is the average current measured over any 5 ms time interval 5 µs after CE# is deasserted.
3. Sampled, not 100% tested.
4. VCC read + program current is the sum of VCC read and VCC program currents.
5. VCC read + erase current is the sum of V CC read and VCC erase currents.
6. ICCES is specified with the device deselected. If device is read while in erase suspend, current is ICCES
plus ICCR
7. ICCW, ICCE measured over typical or max times specified in Section 7.7, “Program and Erase
Characteristics” on page 41
Sym Parameter VCCQ 1.35 V – 2.0 V 1.7 V – 2.0 V Unit Test Condition Notes
Min Max Min Max
VIL Input Low Voltage 0 0.2 0 0.4 V 1
VIH Input High Voltage VCCQ – 0.2 VCCQ VCCQ – 0.4 VCCQ V1
VOL Output Low Voltage - 0.1 - 0.1 V VCC = VCCMin
VCCQ = VCCQMin
IOL = 100 µA
VOH Output High Voltage VCCQ – 0.1 - VCCQ – 0.1 - V VCC = VCCMin
VCCQ = VCCQMin
IOH = –100 µA
VPPLK VPP Lock-Out Voltage - 0.4 - 0.4 V 2
VLKO VCC Lock Voltage 1.0 - 1.0 - V
VLKOQ VCCQ Lock Voltage 0.9 - 0.9 - V
NOTES:
1. VIL can undershoot to –0.4 V and VIH can overshoot to VCCQ + 0.4 V for durations of 20 ns or less.
2. VPP ≤ VPPLK inhibits erase and program operations. Do not use VPPL and VPPH outside their valid ranges.
Sym Parameter VCCQ 1.7 V – 2.0 V
1.35 V - 2.0 V Unit Test Conditions Notes
Typ Max
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
28 Order Number: 251902, Re vision: 010
7.0 AC Characteristics
7.1 AC Test Conditions
Note: AC test inputs are driven at VCCQ for Logic "1" and 0.0 V for Logic "0." Input/output timing begins/ends
at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed occurs at VCC = VCCMin.
Notes:
1. See the following table for component values.
2. Test configuration component value for worst case speed conditions.
3. CL includes jig capacitance.
Figure 8. AC Input /Output Refere nce Wa veform
Input V
CCQ
/2 V
CCQ
/2 Output
V
CCQ
0V
Test Points
Figure 9. Transient Equivalent Testing Lo ad Circuit
Device
Unde r Test Out
CL
Table 5. Test configuration component value for wors t ca se speed condi tions
Test Configuration CL (pF)
1.35 V Standard Test 30
1.7 V Standard Test 30
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 29
7.2 Capacitance
Figure 10. Clock Input AC Waveform
CLK [C]
V
IH
V
IL
R203R202
R201
CLKINPUT.WM
F
Table 6. Ca paci tanc e
Symbol Parameter Signals Min Typ Max Unit Condition Note
CIN Input Capacitance
Address, CE#,
WE#, OE#,
RST#, CLK,
ADV#, WP# 267 pF
Typ temp= 25 °C,
Max temp = 85 °C,
VCC=VCCQ=(0-1.95) V,
Silicon die 1,2
COUT Output Capacitance Data, WAIT 2 4 5 pF
NOTES:
1. Sampled, not 100% tested.
2. Silicon die capacitance only, add 1 pF for discrete packages.
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
30 Order Number: 251902, Re vision: 010
7.3 AC Read Specifications (VCCQ = 1.35 V – 2.0 V)
Num Symbol Parameter All DensitiesSpeed –90 Units Notes
Min Max
Asynchronous Specifications
R1 tAVAV Read cycl e time 90 - ns 6
R2 tAVQV Address to output valid - 90 ns
R3 tELQV CE# low to outpu t valid - 90 ns
R4 tGLQV O E# lo w to outpu t valid - 25 ns 1,2
R5 tPHQV R ST# hi gh to output valid - 150 ns 1
R6 tELQX CE# low to output in low - Z 0 - ns 1,3
R7 tGLQX OE# low to output in low-Z 0 - ns 1,2,3
R8 tEHQZ CE# hi gh to output in high-Z - 20 ns 1,3R9 tGHQZ OE# high to output in high-Z - 20 ns
R10 tOH Output hold from first occurring addr ess, CE# , or OE# change 0 - ns
R11 tEHEL C E# pul se width high 17 - ns 1
R12 tELTV CE# low to WAIT valid - 17 ns 1
R13 tEHTZ CE# high to WAIT high Z - 17 ns 1,3
R15 tGLTV OE# low to WAIT valid - 17 ns 1
R16 tGLTX OE # lo w t o WAIT in low -Z 0 - ns 1,3
R17 tGHTZ O E # high to WAIT in high-Z - 20 ns 1,3
Latching Specifications
R101 tAVVH Address setup to ADV# high 7 - ns
1
R102 tELVH CE# low to ADV# high 10 - ns
R103 tVLQV ADV# low to output valid - 90 ns
R104 tVLVH ADV# pulse w idth low 7 - ns
R105 tVHVL ADV# pul se width high 7 - ns
R106 tVHAX Address hold from ADV# high 7 - ns 1, 4
R108 tAPA Page address access - 30 ns 1
R111 tphvh RS T# hi gh to ADV# high 30 - ns 1
Clock Specifications
R200 fCLK CLK frequency - 47 M Hz
1,3
R201 tCLK CLK per iod 21.3 - ns
R202 tCH/CL CLK hi gh/low tim e 4. 5 - ns
R203 tFCLK/RCLK CL K fall /ris e time - 3 n s
Synchronous Specifications
R301 tAVCH/L Address setup to CLK 7 - ns
1
R302 tVLCH/L ADV# low setup to CLK 7 - ns
R303 tELCH/L CE# lo w setup t o CLK 7 - ns
R304 tCHQV / tCLQV CLK to output valid - 17 ns
R305 tCHQX Output hol d from CLK 3 - ns 1,5
R306 tCHAX Address hold from CLK 7 - ns 1,4,5
R307 tCHTV CLK to WAIT valid - 17 ns 1,5
R311 tCHVL CLK Valid to ADV# Setup 0 - ns 1
R312 tCHTX WAIT Hold from CLK 3 - ns 1,5
NOTES:
1. See Figure 8, “AC Input/O utput R eference W av eform” on p age 28 for timing measurements and max allow able input slew
rate.
2. OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.
3. Sampled, not 100% tested.
4. Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first.
5. Applies only to subsequent synchronous reads.
6. The specifications in this table will only be used by customers (1) who desire a 1.35 to 2.0 VCCQ operating range OR (2)
who desire to transition their host controller from a 1.7 V to 2.0 V VCCQ voltage now to a lower range in the future.
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 31
7.4 AC Read Specifications 64- and 128-Mbit (VCCQ = 1.7–2.0 V)
Num Symbol Parameter Speed –85 Units Notes
Min Max
Asynchronous Specifications
R1 tAVAV Read cycle time 85 - ns 6
R2 tAVQV Address to output valid - 85 ns
R3 tELQV CE# low to output valid - 85 ns
R4 tGLQV O E# lo w to outpu t valid - 20 ns 1,2
R5 tPHQV RST# hi gh to output valid - 150 n s 1
R6 tELQX CE# low to o u tp ut in low - Z 0 - ns 1 ,3
R7 tGLQX OE# low to output in low-Z 0 - ns 1,2,3
R8 tEHQZ CE# high to output in high-Z - 17 ns 1,3R9 tGHQZ OE# high to output in high-Z - 17 ns
R10 tOH Output hold from first occurring addr ess, CE# , or OE# change 0 - ns
R11 tEHEL CE# pulse width high 14 - ns 1
R12 tELTV CE# low to WAIT valid - 14 ns 1
R13 tEHTZ CE# high to WAIT high Z - 14 n s 1,3
R15 tGLTV OE# low to WAIT valid - 14 ns 1
R16 tGLTX OE# low to WAIT in low-Z 0 - ns 1,3
R17 tGHTZ OE# high to WAIT in high-Z - 17 n s 1,3
Latching Specifications
R101 tAVVH Address setup to ADV# high 7 - ns 1
R102 tELVH CE # low to ADV# high 10 - ns
R103 tVLQV ADV# low to output valid - 85 ns 1,6
R104 tVLVH AD V# pul se w idth low 7 - ns 1
R105 tVHVL ADV# pulse width high 7 - n s
R106 tVHAX Address hold f rom ADV# high 7 - ns 1,4
R108 tAPA Page address access - 25 ns 1
R111 tphvh RS T# high to ADV # high 30 - ns 1
Clock Specifications
R200 fCLK CLK frequen cy - 54 MHz
1,3
R201 tCLK CLK period 18.5 - ns
R202 tCH/CL CLK high/low time 3.5 - n s
R203 tFCLK/RCLK CLK fall /rise time - 3 ns
Synchronous Specifications
R301 tAVCH/L Address setup to CLK 7 - ns
1
R302 tVLCH/L ADV# low setup to CLK 7 - n s
R303 tELCH/L C E# lo w setup to CLK 7 - ns
R304 tCHQV / tCLQV CLK to output valid - 14 ns
R305 tCHQX Output hold from CLK 3 - ns 1,5
R306 tCHAX Address hold from CLK 7 - ns 1, 4,5
R307 tCHTV CLK to WAIT valid - 14 ns 1,5
R311 tCHVL CLK Valid to ADV# Setup 0 - n s 1
R312 tCHTX WAIT Hold from CLK 3 - ns 1,5
NOTES:
1. See Figure 8, “AC Input/Output Reference Waveform” on page 28 for timing measurements and maximum allowable
input slew rate.
2. OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.
3. Sampled, not 100% tested.
4. Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first.
5. Applies only to subsequent synchronous reads.
6. The specifications in Section 7.3 will only be used by customers (1) who desire a 1.35 to 2.0 VCCQ operating range OR
(2) who desire to transition their host controller from a 1.7 V to 2.0 V VCCQ voltage now to a lower range in the future.
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
32 Order Number: 251902, Re vision: 010
7.5 AC Read Specifications 256-Mbit (VCCQ = 1.7–2.0 V)
Num Symbol Parameter Speed –85 Units Notes
Min Max
Asynchronous Specifications
R1 tAVAV Read cycle time VCC = VCCQ = 1.8 V – 2.0 V 85 - ns
6
VCC = VCCQ = 1.7 V – 2.0 V 88 -
R2 tAVQV Address to output vali d VCC = VCCQ = 1.8 V – 2.0 V -85
ns
VCC = VCCQ = 1.7 V – 2.0 V -88
R3 tELQV CE# low to output valid VCC = VCCQ = 1.8 V – 2.0 V -85
ns
VCC = VCCQ = 1.7 V – 2.0 V -88
R4 tGLQV OE# low to output valid - 20 ns 1,2
R5 tPHQV RST# high to output valid - 150 ns 1
R6 tELQX CE# low to output in low-Z 0 - ns 1,3
R7 tGLQX OE# low to output in low- Z 0 - ns 1, 2 ,3
R8 tEHQZ CE# high to output in high-Z - 17 ns 1,3R9 tGHQZ OE# hi gh to output in high-Z - 17 ns
R10 tOH Out put hold from first occurring addr ess, CE#, or OE# change 0 - ns
R11 tEHEL CE# pulse width high 14 - ns 1
R12 tELTV CE# low to WAIT valid - 14 ns 1
R13 tEHTZ CE# hi gh to WAIT high Z - 14 ns 1,3
R15 tGLTV OE# low to WAIT valid - 14 ns 1
R16 tGLTX OE# low to WAI T in low- Z 0 - ns 1,3
R17 tGHTZ OE # high to WAIT in high-Z - 17 ns 1,3
Latching Specifications
R101 tAVVH Address setup to ADV# high 7 - ns 1
R102 tELVH CE# l ow to ADV# high 10 - ns
R103 tVLQV ADV# low to output valid VCC = VCCQ = 1.8 V – 2.0 -85
ns 1,6
VCC = VCCQ = 1.7 V – 2.0 -88
R104 tVLVH ADV# pulse w idth low 7 - ns 1
R105 tVHVL ADV# pulse width high 7 - ns
R106 tVHAX Address hold from ADV# high 7 - ns 1,4
R108 tAPA Page address access - 25 ns 1
R111 tphvh RS T# high to ADV # high 30 - ns 1
Clock Specifications
R200 fCLK CLK frequ ency - 54 MHz
1,3
R201 tCLK CLK per iod 18.5 - ns
R202 tCH/CL C LK hi gh/ low time 3.5 - ns
R203 tFCLK/RCLK CLK fall/rise time - 3 ns
Synchronous Specifications
R301 tAVCH/L Address setup to CLK 7 - ns
1
R302 tVLCH/L ADV# low set u p to CLK 7 - ns
R303 tELCH/L CE# low set u p to CLK 7 - ns
R304 tCHQV / tCLQV CLK to output valid - 14 ns
R305 tCHQX Output hold from CLK 3 - ns 1,5
R306 tCHAX Ad dres s hold from CL K 7 - ns 1 ,4,5
R307 tCHTV CLK to WAIT valid - 14 ns 1,5
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 33
Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0 Wait asserted low).
R311 tCHVL CLK Valid to ADV# Setu p 0 - ns 1
R312 tCHTX WAIT Hold from CLK 3 - ns 1,5
NOTES:
1. See Fi gure 8, “AC In put/Output Re ference W aveform” on page 28 for timing meas urement s an d max all owable input slew
rate.
2. OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.
3. Sampled, not 100% tested.
4. Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first.
5. Applies only to subsequent synchronous reads.
6. The specifications in Section 7.3 will only be used by customers (1) who desire a 1.35 to 2.0 VCCQ operating range OR
(2) who desire to transition their host controller from a 1.7 V to 2.0 V VCCQ voltage now to a lower range in the future.
Num Symbol Parameter Speed –85 Units Notes
Min Max
Figure 11. Async hronous Singl e- Word Read with A DV# Low
R5
R7
R6
R17R15
R9R4
R8R3
R1
R2 R1
A
ddress [A]
ADV#
CE # [E}
OE# [G]
WAIT [T]
Data [ D/Q]
RST# [P]
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
34 Order Number: 251902, Re vision: 010
Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0 Wait asserted low).
Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0 Wait asserted low).
Figure 12. Asy nchronous Single-Word Read with ADV# Latch
R10
R7
R6
R17R15
R9R4
R8R3
R106
R101
R105R105
R2 R1
A
ddr ess [A]
A[1:0][A]
ADV#
CE# [E}
OE# [G]
WAIT [T]
Data [D/Q]
Figure 13. Asynchronous Page-Mode Read Timing
R108 R9R7
R17R15
R10R4
R8R3
R106
R101
R105R105
R1R1
R2
A
[Max:2] [A]
A[1:0]
ADV#
CE# [E]
OE# [G]
WAIT [ T]
DA TA [D/Q ]
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 35
Notes:
1. W AIT is driven pe r OE# as sert ion during s ynchronous array or non-arr ay read, and can be confi gured to
assert either during or one data cycle before valid data.
2. This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is
terminated by CE# deassertion after the first word in the burst.
Notes:
1. WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during
initial latency and deasserted during valid data (RCR[10] = 0 Wait asserted low).
2. At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the
starting address is not 4-word boundary aligned.
Figure 14. Synchronous Single-W ord Array or Non-array Read Ti ming
R312
R305R304
R4
R17R307R15
R9R7
R8
R303
R102 R3
R104
R106R101
R104
R105R105
R2
R306R301
CLK [C ]
A
ddress [A]
ADV# [V]
CE# [E]
OE# [G]
WAIT [T]
Data [D/Q]
Figure 15. Continuous Burst Read, showing an Output Dela y Timing
R305R305R305R305
R304
R4
R7
R312R307R15
R303
R102 R3
R106
R105R105
R101 R2
R304R304R304R306
R302
R301
CL K [C ]
A
ddress [A]
ADV# [V]
CE # [E]
OE # [G]
WAIT [T]
Dat a [D/Q]
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
36 Order Number: 251902, Re vision: 010
Note: WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during
initial latency and deasserted during valid data (RCR[10] = 0 Wait asserted low).
Notes:
1. CLK can be stopped in either high or low state.
2. WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during
initial latency and deasserted during valid data (RCR[10] = 0 Wait asserted low).
Figure 16. Synchronous Burst-Mode Four-Word Read Timing
Latency Count
A
Q0 Q1 Q2 Q3
R307
R10
R304
R305R304
R4
R7
R17R15
R9
R8
R303
R3
R106
R102
R105R105
R101 R2
R306
R302
R301
CLK [C]
ddress [A]
ADV# [V]
CE# [E]
OE# [G]
WAIT [T]
Data [D /Q]
Figure 17. Burs t Suspe nd Timing
Q0 Q1 Q1 Q2
R15R17
R304R304
R7
R6
R312R15
R4R9R4
R3
R106
R101
R105R105
R1R1
R2
R305R305R304
CLK
Address [A]
ADV#
CE# [E]
OE# [G]
WAIT [T]
WE# [W]
DATA [ D/Q ]
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 37
7.6 AC Write Specifications
Nbr. Symbol Parameter (1, 2) Min Max Units Notes
W1 tPHWL RST# high recovery to WE# low 150 - n s 1,2,3
W2 tELWL CE# setup to WE# low 0 - ns 1,2,3
W3 tWLWH WE# write pulse width low 50 - ns 1,2,4
W4 tDVWH Data setup to WE# high 50 - ns
1,2
W5 tAVWH Address setup to WE# high 50 - ns
W6 tWHEH CE# hold from WE# high 0 - ns
W7 tWHDX Data hold from WE# high 0 - ns
W8 tWHAX Address hold from WE# high 0 - ns
W9 tWHWL WE# pulse width high 20 - ns 1,2,5
W10 tVPWH V
PP setup to WE# high 200 - ns 1,2,3,7
W11 tQVVL VPP hold from Status read 0 - ns
W12 tQVBL WP# hold from Status read 0 - ns 1,2,3,7
W13 tBHWH WP# setup to WE# high 200 - ns
W14 tWHGL WE# high to OE# low 0 - ns 1,2,9
W16 tWHQV WE# high to read valid tAVQV + 35 - ns 1,2,3,6,10
Writ e to Asynchronous Read Specifications
W18 tWHAV WE# high to Address valid 0 - ns 1,2,3,6
Writ e to Synchronous Read Specifications
W19 tWHCH/L WE# high to Clock valid 19 - ns 1,2,3,6,10
W20 tWHVH WE# high to ADV# high 19 - ns
Writ e Specifications with Clock Active
W21 tVHWL ADV# high to WE# low - 20 ns 1,2,3,11
W22 tCHWL Clock high to WE# low - 20 ns
Notes:
1. Write timing characteristics during erase suspend are the same as write-only operations.
2. A write operation can be terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Write pulse wi dth low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs las t) to CE#
or WE# high (whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH.
5. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to
CE# or WE# low (whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = t EHWL).
6. tWHVH or tWHCH/L must be met when transitioning from a write cycle to a synchronous burst read.
7. VPP and WP# should be at a valid level until erase or program success is determined.
8. This specification is only applicable when transitioning from a write cycle to an asynchronous read.
See spec W19 and W20 for synchronous read.
9. When doing a Read Status operation following any comm a nd that alters the Status Register, W14 is
20 ns.
10. Add 10ns if the wri te oper atio ns resul t s in a RCR or block lock status change, for the s ubseque nt read
operation to reflect this change.
11. These specs are required only when the device is in a synchronous mode and clock is active during
address setup phase.
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
38 Order Number: 251902, Re vision: 010
Note: Wait de asserted during asynchronous read and during write. WAIT High-Z during write per OE#
deasserted.
Figure 18. Write to Write Timing
W1
W7W4W7W4
W3W9 W3W9W3W3
W6W2W6W2
W8W8 W5W5
A
ddress [ A]
CE# [ E }
WE# [W ]
OE# [G]
WA IT [T]
Da ta [D/Q]
RST# [P]
Figure 19. Asy nchronous Read to Write Timing
Q D
R5
W7
W4R10
R7
R6
R17R15
W6W3W3W2
R9R4
R8R3
W8W5
R1
R2 R1
A
ddress [A]
CE# [E}
OE# [G]
WE# [W ]
WAIT [T]
Data [D/Q]
RST # [P]
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 39
Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0 Wait
asserted low). Clock is ignored during write operation.
Figure 20. Write to Asynchronous Read Timing
D Q
W1
R9 R8
R4
R3
R2
W7W4
R17R15
W14
W18W3W3
R10W6W2
R1R1W8W5
A
ddress [A]
ADV# [V]
CE # [ E}
WE # [ W]
OE# [G]
WAIT [T]
Data [D/Q]
RST # [P]
Figure 21. Synchronous Read to Write Timing
Latenc y Co unt
Q D D
W7R305
R304
R7
R312R307R16
W15
W22
W21
W9
W8 W9W3
W22 W21
W3W2
R8
R4
W6
R11R13
R11
R303
R3
R104R104
R106
R102
R105R105
W18
W5
R101 R2
R306
R302
R301
CLK [C]
A
ddress [A]
ADV# [V]
CE# [E]
OE# [ G ]
WE#
W AIT [T]
Data [D/Q]
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
40 Order Number: 251902, Re vision: 010
Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0 Wait
asserted low).
Figure 22. Write to Synchronous Read Timing
Lat ency C ount
D Q Q
W1
R304
R305R304
R3
W7
W4
R307R15
R4
W20
W19
W18
W3W3
R11 R303
R11
W6
W2
R104 R106
R104
R306W8W5
R302 R301 R2
CLK
A
dd res s [A ]
ADV#
CE# [E}
WE# [W]
OE# [G]
WAIT [T]
Dat a [D /Q]
RST# [P]
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 41
7.7 Program and Era se Ch aract e rist ic s
Nbr. Symbol Parameter VPPL VPPH Units Notes
Min Typ Max Min Typ Max
Conventional Word Programming
W200 tPROG/W Program
Time Single word - 90 180 - 85 170 µs 1
Single cell - 30 60 - 30 60
Buffered Programming
W200 tPROG/W Program
Time Single word - 90 180 - 85 170 µs 1
W201 tPROG/PB One Buffer (32 words) - 440 880 - 340 680
Buffered Enhanced Factory Progr am ming
W451 tBEFP/W Program Single word n/a n/a n/a - 10 - µs 1,2
W452 tBEFP/
Setup Buffered EFP Setup n/a n/a n/a 5 - - 1
Erasing and Suspending
W500 tERS/PB Erase T ime 16-Kword Parameter - 0.4 2.5 - 0.4 2.5 s1
W501 tERS/MB 64-Kword Main - 1.2 4 - 1.0 4
W600 tSUSP/P Suspend
Latency Program suspend - 20 25 - 20 25 µs
W601 tSUSP/E Erase suspend - 20 25 - 20 25
Notes:
1. Typi cal values m easured at TC = +25 °C and nominal voltages. Performance numbers are valid for all
speed versions. Excludes system overhead. Sampled, but not 100% tested.
2. Averaged over entire device.
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
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8.0 P ower and Reset Specifications
8.1 Pow er Up and Down
Power s uppl y sequencing is not requ ired if VCC, VCCQ, and VPP a re connected to ge ther; If
VCCQ and/or VPP are no t connected to the VCC supp ly, then VCC should attain VCCMIN before
app lying VCCQ and VPP. Device inpu ts shou ld not be driven be fore s upply voltage equals VCCMIN.
Power suppl y transitions should only occur whe n RST# is low. This protec ts the dev ic e from
accidental programming or erasure during power transitions.
8.2 Reset
Asserting RST# during a system reset is important with automated pr ogram/erase devi ces because
systems typically expec t to r ead from flash memory when coming out of r es et. If a CPU reset
occurs without a flash memory re se t, proper CPU initialization may not occur. This is because the
fla sh memory may be providing status information, inste a d of array data as e xpe cted. Connec t
RST# to the same active-l ow reset signal used for C PU initialization.
Also, because the de vic e is disabled when RST # is asse rted, it ignores its control inputs during
power-up/down. Invalid bus cond itions are masked, providing a level of memory protection.
System des igners should guard against spuriou s w rites when VCC voltag es ar e above VLKO.
Because both W E # and CE# must be asserted for a write operation, deasser ting either sig nal
inhibits writes to the device.
The Command User Interface (CUI) architecture provides addit ional protection because alteration
of memory content s can only occur after successful completion of a two-step command s equence
(see Section 9.2, “ Device Com mands” on page 4 7 ).
Nbr. Symbol Parameter Min Max Unit Notes
P1 tPLPH RST# pulse width low 100 - ns 1,2,3,4
P2 tPLRH R ST# low to device reset during erase - 25 µs 1,3,4,7
RST# low to device reset during program - 25 1,3,4,7
P3 tVCCPH VCC Power valid to RST# deassertion (high) 60 - 1,4,5,6
Notes:
1. These specifications are valid for all device versions (packages and speeds).
2. The device may reset if tPLPH is < tPLPHmin, but this is not guaranteed.
3. Not applicable if RST# is tied to Vcc.
4. Sampled, but not 100% tested.
5. If RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC ≥ VCC min.
6. If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage m ust not exceed
VCC until VCC ≥ VCC(min).
7. Re set completes within tPLPH if RST# is asserted while no eras e or program operation is executing.
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 43
8.3 Power Supply Decoupling
Flash mem or y devices require careful power supply decoupling. Three basi c power supply curr ent
considerations ar e: 1) standby curr ent levels; 2) active current lev els; and 3) transi ent peaks
produced when CE# and OE# are asserted and deassert ed.
When the device is accessed, man y internal condit ions change. Circuits within the device enable
char ge-pumps, and internal logic states change at high speed. All of these internal activities
produce transient s i gnals. Transient current magnitudes de pe nd on the de vice outputs ’ ca pacitive
and ind uctive loading. Two-line contr ol and correct decoupling capacit or se lection suppress
trans ient voltage peaks.
Because Intel® Multi-Level Cell (MLC) flash m emory devi ces draw their po wer from VCC, VPP,
and VCCQ, eac h power co nnection shou ld hav e a 0.1 µF ceramic capacitor connected to a
co rrespo nding gr ound conn ection. H igh-fr equenc y , inh erentl y l ow-in ductance capacito rs shou ld be
placed as clo s e as pos si ble to package leads.
Additiona lly, for every eight devices used i n the system, a 4.7 µF e le c trolytic capaci tor should be
placed between power and ground clo s e to the devices. The bulk capacitor is meant to overcom e
voltage droop caused by PCB trace inductance.
Fig u re 23. Reset Op eration Wavefo rms
(
A) Reset during
read mode
(B) Reset during
program or block er ase
P1
≤
P2
(C) Reset during
program or block er ase
P1
≥
P2
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
RST# [ P]
RST# [ P]
RST# [ P]
Abort
Complete
Abort
Complete
V
CC
0V
V
CC
(D) VCC Power -up to
RST# high
P1 R5
P2
P3
P2 R5
R5
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
44 Order Number: 251902, Re vision: 010
8.4 Automatic Power Saving
Automatic Power Saving (APS) provides low powe r opera t ion during a read’s active state. I CCAPS
is the averag e current measured over any 5 ms time inter val, 5 µs after CE# is deas s erted. During
APS, average curr ent is measured over the same tim e interval 5 µs af ter the followi ng events
happen: (1) ther e is no inter nal read , program or erase op eration s cease; (2 ) CE# is assert ed; (3) the
address lines are quiescent and at V SSQ or VCCQ. OE # ma y also be dri v e n du ri ng APS .
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 45
9.0 Device Operations
This section provides an overview of device operations. The system CPU pro vides control of all in-
syst em read, wr ite, and erase operations of the device via the syste m bus. The on-chip Writ e State
Machine (WSM) manages all block -er ase and word-program algorithms .
Device commands are writ ten to the Command User Interface (CUI) to control all flash memor y
device operations. The CUI does not occupy an addressable memory location; it is the mechanism
through which the flash device is controlled.
9.1 Bus Operations
CE# -low and RST#-high e nable de vic e read opera tions. The device internally decodes upper
addr es s in puts to determine the accessed pa rtition. ADV#- low opens the internal address latches.
OE#-low activates the ou tputs and gates selected data onto the I/O bus.
In as ync hrono us m od e, th e addr es s i s la tc hed when A DV# goe s hig h or co nti nuo usly f lows t hroug h
if ADV# is held low. In s ynchronous mode, the a ddress is latched by the fi rst of either the rising
ADV# edge or the next va lid CLK edge with ADV# low (WE# and RST # must be VIH; CE# must
be VI L ).
Bus cycles to/from the L18 device conform to standard microprocessor bus operations. Table 7
summarizes the bus operations and the log ic levels that must be ap plied to the device’s contro l
signal inputs.
Table 7. Bus Operations Sum mary
Bus Operation RST # CLK ADV# CE# OE# WE# WAIT D Q[15:0] No tes
Read
Asynchronous VIH X L L L H Deasserted Output
Synchronous VIH Running L L L H Driven Output
Burst Suspend VIH Halted X L H H High-Z Output
Write VIH X L L H L High-Z Input 1
Output Disable VIH X X L H H High-Z High-Z 2
Standby VIH X X H X X High-Z High-Z 2
Reset VIL X X X X X High-Z High-Z 2,3
Notes:
1. Refer to the Table 8, “Command Bus Cycles” on page 47 for valid DQ[15:0] during a write operation.
2. X = Don’t Care (H or L).
3. RST# must be at VSS ± 0.2 V to meet the maximum specified power-down current.
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Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
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9.1.1 Reads
To perform a read o per ation, RST# and WE# must be deasserted while CE# and OE# are asser ted.
CE# is the device-select control. When asserted, it enables the flash me m ory device. OE# is the
dat a -output c ontrol. Whe n a sserted, the a ddress e d flash memory data is driven onto the I /O bus.
See Section 10.0, “Rea d Operations” on page 50 for det ails on the available read modes, and see
Sectio n 15.0, “Sp ecial Read St ates ” on page 75 for details regarding the available read states.
The Au toma t ic P ower S avin gs (APS ) feat ur e provi de s lo w po wer ope rat ion fol lowin g re a ds dur in g
active mode. Af ter data is read from the memory arr ay and the address lines ar e quiescent, APS
automatically places the device into standby. In APS, device curr ent is reduced to ICCAPS (see
Sectio n 6. 1, “DC Cur ren t Characterist ics ” on page 26).
9.1.2 Writes
To perfo rm a write op eration , both CE# an d WE# are as serted w hile RS T# and OE# are deasser ted.
During a write opera tion, address and data are la tched on the ri sing edge of WE# or CE #,
whi chev er oc cu rs fir s t. Ta ble 8, “Command Bus Cyc l e s” on page 47 shows the bus cycle sequence
for e ach of the supported de vice commands, while Table 9 , “Command Codes and Definitions” on
page 48 describes each command. See Section 7. 0, “AC Characteristics” on page 28 fo r sig n al-
timin g details.
Note: W rite operat ions wit h i nvalid V CC and/ or VPP voltag es ca n pr odu ce spu ri ous r esul ts a nd sho uld no t
be attempted .
9.1.3 Output Disable
When OE# is deasser ted, device outputs DQ[15:0] are disabled and placed in a high-impedance
(High-Z) st ate, WAIT is also placed in High-Z.
9.1.4 Standby
When CE# is deasser ted the device is deselected and placed in stand by, substantially reducing
power consumption. In stand by, the data outputs a re pl aced in High-Z, independent of the level
placed on OE# . S tan dby curr ent, ICCS, is the av erage curr ent measu red over an y 5 ms t ime interv al,
5 µs after CE# is deasserte d. Dur ing standby, average current is measured over the same tim e
interval 5 µs after CE# is deasserted.
When the device is desel ected (while CE# is deas serted) during a program or erase operation, it
continues to consume active power until the program or erase operation is completed.
9.1.5 Reset
As with any automated device, it is imp or tant to assert RST# when th e syst em is reset. When the
system comes out of reset, the system processor attempt s to read from the flash memory if it is the
system boo t device. If a CPU reset oc curs with no flash memor y reset, impr oper CPU ini tializati on
may occur becaus e the f las h me mo ry may be providing stat us informatio n rather than array data.
Flash memory devices from Intel allow pro per CPU initialization foll owing a system reset through
the use o f the RST# input. RST# should be controlled by the same low-true re set signal that resets
the syst em CPU.
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 47
After initial pow e r-up or rese t, the dev ic e de faul ts to asyn c hronous Read Array, and th e Sta tus
Register is set to 0x80. Ass e rting RST# de-energizes all internal circuits, and places the ou tput
dri ver s in High-Z. When RST# is asserted, the device shuts down the operation in progress, a
proces s which takes a minimum amount of t im e to complete. When RST# has been deasser ted, the
device is reset to asynchr onous Read Array stat e.
Note: If RST# is asserted during a program or era se o per ation, the operation is terminated and the
memory con tents at the abo rted loc ation (for a pro gram) or blo ck (for an erase ) are no longer val id,
becaus e the data may have been only partiall y written or erased.
When returning from a res et (RST# deasserted), a minimum wa it is required bef ore the initial read
acces s outputs valid dat a. Al so, a minimum delay is re quired after a reset be fo re a write cycle can
be initiated. After thi s wake-up interval passes , normal operation is r estored. See Section 7.0, “AC
Characteristics” on page 28 for det a ils about signal-timing.
9.2 Device Commands
Device operations are initiated by writing specifi c device commands to the Com mand User
Interf ace (CUI). See Table 8, “Command Bus Cy c le s” on page 47.
Several commands are used to modif y ar ray data including Word Program and Block Erase
commands. Writing either command to the CUI initiates a sequence of internally-timed f unc tions
that culminate in the completion of the requ ested task. However, the operation can be aborted by
either as s erting RST# or by issuing an appr opr iate suspend command.
Table 8. Com mand Bu s Cycle s (Sheet 1 o f 2)
Mode Command Bus
Cycles
First Bus Cycle Second Bus C ycle
Oper Addr1Data2Oper Addr1Data2
Read
Read Array 1 Write PnA 0xFF
Read Device Identifier ≥ 2 Write PnA 0x90 Read PBA+IA ID
CFI Query ≥ 2 Write PnA 0x98 Read PnA+QA QD
Read Status Register 2 Write PnA 0x70 Read PnA SR D
Clear Status Register 1 Write X 0x50
Program
Word Program 2 Wri te WA 0x40/
0x10 Write WA WD
Buffered Program3 > 2 Write WA 0x E8 Wri te WA N - 1
Buffered Enhanced F actory Program
(Buffered EF P)4> 2 Write WA 0x80 Write WA 0xD0
Erase Block Erase 2 Write BA 0x20 Write BA 0xD 0
Suspend Program/Erase Suspend 1 Write X 0xB0
Program/Erase Resume 1 Write X 0xD0
Block
Locking/
Unlocking
Lock Block 2 Write BA 0x60 Write BA 0x01
Unlock Block 2 Write BA 0x60 Write BA 0xD0
Lock-down Block 2 Write BA 0x60 Write BA 0x2F
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
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9.3 Command Definitions
Valid device command codes and descriptions are shown in Table 9.
Protection Program Protection Register 2 Write PRA 0xC0 Write PRA PD
Program Lock Register 2 Write LRA 0xC0 Write LRA LRD
Configuration Program Read Configuration Register 2 Write RCD 0x60 Write RCD 0x03
Notes:
1. First command cycle address should be the same as the operation’s target address.
PnA = Address within the partition.
PBA = Partition base address.
IA = Identification code address offset.
QA = CFI Query address offset.
BA = Address within the block.
WA = Word address of memory location to be written.
PRA = Protection Register addr ess.
LRA = Lock Register address.
X = Any valid address within the device.
2. ID = Identifier data.
QD = Query data on DQ[15:0].
SRD = Status Register data.
WD = Word data.
N = Word count of data to be loaded into the write buffer.
PD = Protection Register data.
PD = Protection Register data.
LRD = Lock Register data.
RCD = Read Configuration Register data on A[15:0]. A[MAX:16] can select any partition.
3. Th e second c ycl e of the Buffer ed Pr ogram Command i s the word count of the data to be loaded into the write buf fer. This
is followed by up to 32 words of data.Then the confir m command (0xD0) is issued, triggering the array programming
operation.
4. The confirm command (0xD0) is followed by the buffer data.
Table 8. Command Bus Cycl es (Sheet 2 of 2)
Mode Command Bus
Cycles
First Bus Cycle Second Bus Cycle
Oper Addr1Data2Oper Addr1Data2
Table 9. C om m and Codes and Definitions (She et 1 of 2)
Mode Code Device Mode Description
Read
0xFF Read Array Places the addressed partition in Read Array mode. Array data is output on DQ[15:0].
0x70 Read Status
Register
Places the addressed partition in Read Status Register mode. The partition enters this
mode after a program or erase command is issued. Status Register data is output on
DQ[7:0].
0x90
Read Device
ID or
Configuration
Register
Places the addressed partition in Read Device Identifier mode. Subsequent reads from
addresses within the partition outputs manufacturer/dev ice cod es, Confi guration R egister
data, Block Lock status, or Protection Register data on DQ[15:0].
0x98 Read Query Places the addres sed p ar tition in Read Query mode. Subsequent reads fr om the parti tion
addresses output Common Flash Interface information on DQ[7:0].
0x50 Clear Status
Register The WSM can only set Status Register error bits. The Clear Status Register command is
used to clear the SR error bits.
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 49
Write
0x40 Word Program
Setup
First cycle of a 2-cycle programming command; prepares the CUI for a write operation.
On the next write cycle, the address and data are latched and the WSM executes the
programming algorithm at the addr essed location. During program operations, the
partition responds only to Read Status Register and Program Suspend commands. CE#
or OE# must be toggled to update the Status Register in asynchronous read. CE# or
ADV# must be toggled to update the Status Register Data for synchronous Non-array
read. The Read Array com mand must be issued to read array data af ter progr amming has
finished.
0x10 Alternate Word
Program
Setup Equivalent to the Word Program Setup command, 0x40.
0xE8 Buffered
Program This comm and loa ds a variable number of bytes up to the buf fer s ize of 32 w ords onto the
program buffer.
0xD0 Buffered
Program
Confirm
The confirm command is Iss ued a fter the data streaming for writing into the buffer is done.
This instructs the WSM to perform the Buffered Program algorithm, writing the data from
the buffer to the flash memory array.
0x80
Buffered
Enhanced
Factory
Programming
Setup
First cycle of a 2-cycle command; initiates Buffered Enhanced Factory Program mode
(Buffered EFP). The CUI then waits for the Buffered EFP Confirm command, 0xD0, that
initiates the Buffered E FP algori thm. All other comm ands are ignor ed when B uffered EFP
mode begins.
0xD0 Buffered EFP
Confirm If the previous command was Buffered EFP Setup (0x80), the CUI latches the address
and data, and prepares the device for Buffered EFP mode.
Erase
0x20 Block Erase
Setup
First cycle of a 2-cycle command; prepares the CUI for a block-erase operation. The
WSM performs the erase algorithm on the block addressed by the Erase Confirm
command. If the next command is not the Erase Confirm (0xD0) command, the CUI sets
Status Register bits SR[4] and SR[5], and places the addressed partition in read status
register mode.
0xD0 Block Erase
Confirm
If the first command was Block Eras e Setup ( 0x20), the CUI latches the address and dat a,
and the WSM erases the addressed block. During block-erase operations, the partition
respo nds only to Read S tatus Register an d Erase Suspend commands. CE# or OE# must
be toggled to update the Status Register in asynchronous read. CE# or ADV# must be
toggled to update the Status Register Data for synchronous Non-array read.
Suspend 0xB0 Program or
Erase
Suspend
This command issued to any device address initiates a suspend of the currently-
executing program or block erase operation. The Status Register indicates successful
suspend operation by setting either SR[2] (program suspended) or SR[6] (erase
suspended), along with SR[7] (ready). The Write State Machine remains in the suspend
mode regardless of control signal states (except for RST# asserted).
0xD0 Suspend
Resume This command issued to any device address resumes the suspended program or block-
erase operation.
Block Locking/
Unlocking
0x60 Lock Block
Setup
First cycle of a 2-cycle command; prepares the CUI for block lock configuration changes.
If the next command is not Block Lock (0x01), Block Unlock (0xD0), or Block Lock-Down
(0x2F), the CUI sets Status Register bits SR[4] and SR[5], indicating a command
sequence error.
0x01 Lock Block If the previous command was Block Lock Setup (0x60), the addressed block is locked.
0xD0 Unl ock Bloc k If the previous command was Block Lock Setup (0x60), the addressed block is unlocked.
If the addressed block is in a lock-down state, the operation has no effect.
0x2F Lock-Down
Block If the previous command was Block Lock Setup (0x60), the addressed block is locked
down.
Protection 0xC0 Program
Protection
Register
Setup
First cycle of a 2-cycle command; prepares the device for a Protection Register or Lock
Register p rog ram operation. The second cyc le latc hes the regi ster addres s and dat a, and
starts the programming algorithm.
Configuration
0x60
Read
Configuration
Register
Setup
First cycle of a 2-cycle command; prepares the CUI for device read configuration. If the
Set Read Configura tion Register command ( 0x03) is not the nex t command, the CUI sets
Status Register bits SR[4] and SR[5], indicating a command sequence error.
0x03 Read
Configuration
Register
If the previous command was Read Confi guration Reg ister Setup (0x60), the CUI latches
the address and writes A[15: 0] to the Read Configuration Register. Following a Configur e
Read Configuration Register command, subsequent read operations access array data.
Table 9. Command Code s and Definitions (Shee t 2 of 2)
Mode Code Device Mode Description
Intel StrataFlash® Wireless Memory (L18)
Augu st 2005 Int el S trataFlash® Wireless Memor y (L18) Datasheet
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10.0 Read Operations
The device s upports two read modes: asynchronous page mode a nd synchronous burst mode .
Asynchronous page mode is t he de faul t re a d mode a fter device powe r-up or a reset. The Re a d
Configuration Register must be configured to enable synchronous burst reads of the flash memory
array (see Section 10.3, “Rea d Configurati on Re gister (RCR)” on page 51).
Each partition of the device can be in any of four read states: Read Array, Read Identifier, Read
Status or Read Query. Upon power -up, or after a reset , all partitions of the device default to Read
Array. To change a partition ’s read sta te, the appropriate read command must be written to the
device (s ee S ectio n 9 .2, “D evi ce Com mand s” on p age 47). See S ection 1 5.0, “Specia l Read Sta tes”
on pa ge 75 for details regarding Read Status, Read ID, and CFI Query modes.
The following sections describe re a d-mode operations in detail.
10.1 Asynchronous Page-Mode Read
Following a device power-up or reset, as ynchronou s pa ge mo de is the default read mode and all
partitions are se t to Re a d Array. However, to perform array reads after any other devi c e ope rati on
(e.g. write operation), the Read Array comma nd must be is sued in order to read fr om the f las h
memory array.
Note: As ynchronous page-m ode reads can only be performed when Read Configuration Re gister bit
RCR[15] is set (see Sectio n 10.3, “Re a d Configuration Register (RCR)” on page 51).
To pe rform an asynchronous page-mode re a d, an ad dress is driven onto A[MAX:0], and CE# and
ADV# are a sserted. WE# an d RST# must already have been deasserted . WAIT i s deasser ted durin g
asynchronous page mode. ADV# can be dr ive n high to latch the address, or it mu st be held low
througho ut the read cycle. CLK is not used for asynchronous pag e-mode r eads, and is ignored. If
only a synchronous rea ds are to be pe rformed, CLK sh ould be tied to a vali d VIH lev e l, WAI T
signal can be float e d a nd ADV# mu st be tied t o ground. Array da ta is driven onto DQ[15:0] after
an initial access tim e t AVQV delay. (see Section 7.0, “AC Cha racteristic s” on page 28).
In asynchronous page mode, four data words are “sen s ed” s im ultaneously f ro m th e flash memory
array and load ed into an internal page bu ffer. The buf fer word correspondin g to th e initial addres s
on A[M AX: 0] is driv en on to DQ[ 15:0] after the i nit ial ac cess delay. Add ress bi ts A[ MA X:2] s ele ct
the 4-word page. Address bits A[1:0] determine which word of the 4-word page is output from the
data buffer at any given time.
10.2 Synchronous Burst-Mode Read
To pe rform a synchronous burst- read, an initia l address i s driven onto A[MAX:0], a nd CE# and
ADV# are asserted. WE # and RST# must alr eady have been deasserted. ADV# is as se rted, and
then deasserted to latch the address. Alternately, ADV# can rem a in asserted throughout the burst
access, in whi ch case the address is latched on the next valid CLK edge while ADV# is ass erted.
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Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
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During synchronous ar ra y and non-a rray rea d modes, the first word is output from the data buffer
on the next valid CLK edge after the ini tial access latency delay (see Section 10.3. 2, “Latency
Count” on page 52). Subseque nt data is output on va lid CLK edges following a minim um dela y.
Howe ve r, for a synchronous non -a rra y re ad, the sa me word of data will be output on successive
clock edges unt il the burst length requirements a re sa tisfied.
10.2.1 Burst Suspend
The Burst Suspend fe ature of the device can reduce or el iminate the in itial access latency incurred
when sy stem soft war e ne ed s to sus p end a bur st s equ ence t hat i s i n prog res s in or der to retr iev e da ta
from anoth er device on the same sy stem b us. The system processor can r esume the bu rst sequence
later. Burst suspend provides maximum benef it in non-cache sys tem s.
Burst accesses can be suspended during the initial access latency (before data is received) or after
the dev ice has output data. When a burs t acces s is suspended, internal array sensin g con tinues and
any previously latche d internal data is retained. A burst sequence can be suspended and resum ed
without limit as long as device operatio n conditions are met.
Burst S uspend occurs when CE# is asserted, the current address has been latched (either ADV#
risin g edg e or valid CLK edge) , CLK is halted, and OE# is deasserted. CLK can be halted when it
is at VIH or VIL. WAIT is in High-Z during OE# deassertion.
To resume the burst access , OE# is reass erted, and CLK is restarted. Su bs equent CLK edges
resume the burst sequence .
Within the device, CE# and OE# gate WAIT. Therefore, dur ing Burst Suspend WAIT is placed in
high-impedance state wh en OE# is deass erted and resumed active when OE# is re-asserted. See
Figure 17 , “ Bu rst Su spe nd Ti mi ng” on pa ge 36 .
10.3 Read Configuration Register (RCR)
Th e RC R is used to se le c t the read mode (synchronous or a synchronous ), and it de fines the
syn c hronous burst c haracteristics of the device. To modify RCR settings, use the Configure Rea d
Configuration Register command (see Section 9.2, “Device Commands” on page 47).
RCR cont ents can be examined using the Read Device Identifier command, and then reading f rom
<partition base address> + 0x05 (see Section 15.2, “Read D e vic e Identifier” on pa ge 76).
The RCR is shown in Table 10. The follow ing sections des c ribe each RCR bit.
Table 10. Read Configuration Register Descript io n (Sheet 1 of 2)
Read Configur ation Register (RCR)
Read
Mode RES Latency Count WAIT
Polarity Data
Hold WAIT
Delay Burst
Seq CLK
Edge RES RES Burst
Wrap Burst Length
RM RLC[2:0] WP DH WD BS CE R R BW BL[2:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name Description
15 Read Mode (RM) 0 = Synchronous burst-mode read
1 = Asynchronous page-mode read (default)
14 Reserved (R) Reserved bits should be cleared (0)
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10.3.1 Read Mode
The Read Mode (RM) bit s e le c t s syn c hronous burst-mode or a synchronous page-mode ope ration
for the device. When the RM bit is s et, asynchronous page mode is selected (default). Wh en RM is
cleared, synchronous burst mode is selected.
10.3.2 Latency Count
The Latency Count bi ts , LC[ 2:0], tell the device how many clock cycles must el aps e fr om the
rising edge of ADV# (or from the first valid clock edge afte r ADV# is asse rted) until the first data
word is to be driven onto DQ[15:0]. The in put clock frequency is used to determine this value.
Figure 24 shows the data output latency for the differ ent settings of LC[2:0].
Synch ron ous b urs t wi th a Latenc y Co unt se tti ng of C ode 4 wi ll r esul t in zero WAIT state ; ho wev er,
a Latency Count setting of Code 5 will cause 1 WAIT state (Code 6 will cause 2 WAIT states, and
Code 7 will caus e 3 WAIT states) after ev e ry four words, regardless of whether a 16-word
bound ary is c rossed . If RCR [9] ( Data H old ) bit is se t (dat a ho ld of tw o c locks ) this WAIT con dition
will not o ccur bec ause en ough clocks e lapse d uring each burs t cycle t o elim inate subseq uent WAIT
states.
Refer to Table 11 and Table 12 for Latency Code Settings.
13:11 Latency Count (LC[2:0]) 010 =Code 2
011 =Code 3
100 =Code 4
101 =Code 5
110 =Code 6
111 =Code 7 (default)
(O ther bit settings are reserved)
10 Wait Polarity (WP) 0 =WAIT signal is active low
1 =WAIT signal is ac tive high (d efault)
9 Data Hold (DH) 0 =Data held for a 1-clock data cycle
1 =Data held for a 2-clock data cycle (default)
8 Wait Delay (WD) 0 =WAIT deasserted with valid data
1 =WAIT deasserted one data cycle before valid data (default)
7 Burst Sequence (BS) 0 =Reserved
1 =Linear (default)
6 Clock Edge (CE) 0 = Falling edge
1 = Rising edge (default)
5:4 Reserved (R) Reserved bits should be cleared (0)
3 Burst Wrap (BW) 0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
2:0 Burst Length (BL[2:0]) 001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
(Other bit settings are reserved)
Note: Latency Code 2, Data Hold for a 2-clock data cycle (DH = 1) Wait must be deasserted with valid data (WD =
0). WD = 1 is not supported.
Table 10. R ea d Configu ration Register Description (Sheet 2 of 2)
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 53
See Figure 25, “E xa mple Latency C ount Setting” on p a ge 54.
Figure 24. First-Access Latency Count
Table 11. LC and Frequency Supp ort (tAVQV/tCHQV = 85 ns / 14 ns)
VCCQ = 1.7 V to 2.0 V
Latency Count Settings Frequency Support (MHz)
2≤ 28
3≤ 40
4, 5, 6 or 7 ≤ 54
Table 12. LC and Frequency Supp ort (tAVQV/tCHQV = 90 ns / 17 ns)
VCCQ = 1.35 V to 2.0 V
Latency Count Settings Frequency Support (MHz)
2≤ 27
3, 4, 5, 6 or 7 ≤ 40
Code 1
(Reserved
Code 6
Code 5
Code 4
Code 3
Code 2
Code 0 (Reserved)
Code 7
Valid
Address
Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output
Valid
Output
Address [A]
ADV# [V]
DQ15-0 [D/Q]
CLK [C]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
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10.3.3 WAIT Polarity
The WAIT Polarity bi t (WP), RCR[10] determines the asserted level (VOH or VOL) of WAIT.
When WP is set, WAIT is asser ted- high (default). Wh en WP is cleared, WAIT is assert ed-low.
WAIT changes state on valid clock edges during active bus cycles (CE# asserted, OE# asserted,
RST# deasserted).
10.3.3.1 WAIT Signal Function
The WAIT signa l indi c a te s data va lid when the device is operating i n synchronous mode
(RCR[15] =0). The WAIT signal is only “ deasserted” when data is valid on the bus.
When the devi ce is operating in s ynchronous non-array read mo de, such as read status, read ID, or
read query the WAIT signal is als o “deasserte d” wh en data is valid on the bus.
WAI T behav i or during synchronous non-a rray rea ds at the e nd of word line wo rks correctly only
on the first data access.
When the device is ope ratin g in asynchronous page mode, asynchronous single wo rd read mode,
and all write op erations, WAI T is set to a deasserted state as determin ed by RCR[10]. See Figure
12, “As ynchronous Single-Word Rea d with ADV # Latch” on page 34, and Figu re 13,
“Asynchronous Pa ge -Mode Re a d Timing” on page 34.
Figure 25. Exampl e Latenc y Coun t Setting
CLK
CE#
ADV#
A[MAX:0]
D[15:0]
tData
Code 3
Address
Data
012
34
R103
High-Z
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10.3.4 Data Hold
For bu rst rea d op er atio ns , the Dat a Hold (D H) bit det ermin es wh ethe r t he d ata out put re mai ns val id
on DQ[1 5:0 ] for one or two-clock cycles . This period of ti me is called the “data cycle”. When DH
is se t, output data is he ld for two clocks (default). When DH is cleared, output data is held for one
clock (see Figure 26) . The processo r’s data setup time and the flash memory ’s clock-to-data ou tput
de la y should be co nsidered whe n de te rmining whether to hold output data for one or two cl oc ks. A
method for de terminin g the Data Hold configuration is sho wn below:
To set the device at one c lock data hold for s ubsequent rea ds, the f ollowing condition must be
satisfied:tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)
tDATA = Data set up to Clock (defined by CPU)
For example, with a c lock freque nc y of 40 MHz, the c l ock period is 25 ns. Assuming
tCHQV = 20 ns and tDATA = 4ns. Apply ing these values to the formula above:
20 ns + 4 ns ≤ 25 ns
Th e eq uation is sati sf ie d and data will be ava ilable at every cloc k pe riod with data hold setting at
one clo ck.
If tCHQV (ns) + tDATA (ns) > One CLK Period (ns), da ta hold setting of 2 clock periods must be
used.
Table 13. WAIT Functionality Table
Condition WAIT Notes
CE# = ‘1’, OE# = ‘X’
CE# = ‘X’, OE# = ‘1 ’
High-Z 1
CE# =’0 ’, OE# = ‘0’ Active 1
Synchronous Array Reads Active 1
Synchronous Non- Array Re a ds Activ e 1
All Asynchronous Reads Deasserted 1
All Wr it es H igh- Z 1, 2
Notes:
1. Active: WAIT is asserted until data becomes valid, then
deasserts
2. When OE# = VIH during writes, WAIT = High-Z
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10.3.5 WAIT Delay
The WAIT Delay (WD) bi t c ontro ls the WAIT assertion-dela y be havior during synchronous burst
reads. WAI T can be asserted either during or one data cycle before inv a lid data is outpu t on
DQ[15:0]. When WD is set, WAIT is asserted one data cycle before invali d data (default). When
WD is cleared, WAIT is asserted during invalid data.
10.3.6 Burst Sequence
The Burst Sequence ( BS) bit select s li near-burst sequence (default). Only linear-bur s t sequence is
supported. Table 14 shows the synchronous burst sequen c e for all burst l e ngths, as well as the
eff ect of the Burst Wrap (BW) setting.
Figure 26. Data Hold Timing
Valid
Output
Valid
Output
Valid
Output Valid
Output Valid
Output
CLK [C]
D[15:0] [Q]
D[15:0] [Q]
2 CLK
Data Hold
1 CLK
Data Hold
Table 14. Burst Seque nce Word Ord ering (Shee t 1 of 2)
Start
Addr.
(DEC) Burst Wrap
(RCR[3])
Burst Addressing Sequence (DEC)
4-Word Burst
(BL[2:0] = 0b001) 8- Word Bu rst
(BL[2:0] = 0b010) 16 -Wo rd B u rst
(BL[2:0] = 0b011) Continuous Burst
(BL[2:0] = 0b111)
0 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4…14-15 0-1-2-3-4-5-6-…
1 0 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5…15-0 1-2-3-4-5-6-7-…
2 0 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6…15-0-1 2-3-4-5-6-7-8-…
3 0 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7…15-0-1-2 3-4-5-6-7-8-9-…
40 4-5-6-7-0-1-2-3 4-5-6-7-8…15-0-1-2-3 4-5-6-7-8-9-10…
50 5-6-7-0-1-2-3-4 5-6-7-8-9…15-0-1-2-3-4 5-6-7-8-9-10-11…
60 6-7-0-1-2-3-4-5 6-7-8-9-10…15-0-1-2-3-4-5 6-7-8-9-10-11-12-…
70 7-0-1-2-3-4-5-6 7-8-9-10…15-0-1-2-3-4-5-6 7-8-9-10-11-12-13…
…
…
…
…
…
…
14 0 14-15-0-1-2…12-13 14-15-16-17-18-19-20-…
15 0 15-0-1-2-3…13-14 15-16-17-18-19-20-21-…
…
…
…
…
…
…
0 1 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4…14-15 0-1-2-3-4-5-6-…
1 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5…15-16 1-2-3-4-5-6-7-…
2 1 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6…16-17 2-3-4-5-6-7-8-…
3 1 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7…17-18 3-4-5-6-7-8-9-…
41 4-5-6-7-8-9-10-11 4-5-6-7-8…18-19 4-5-6-7-8-9-10…
51 5-6-7-8-9-10-11-12 5-6-7-8-9…19-20 5-6-7-8-9-10-11…
61 6-7-8-9-10-11-12-13 6-7-8-9-10…20-21 6-7-8-9-10-11-12-…
71 7-8-9-10-11-12-13-14 7-8-9-10-11…21-22 7-8-9-10-11-12-13…
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel Strata F l as h® Wireless Memory (L18) Augu st 2005
Order Num ber: 2519 02, Revi si on: 010 57
10.3.7 Clock Edge
The Clock Edge (CE) bit selects either a rising (defaul t) or falling clock edge for CL K. This clock
edge is used at the start of a burst cycl e , to output synchronous da ta, and to ass e rt/dea ssert WAIT.
10.3.8 Burst Wrap
The Burst Wrap ( BW) bit determines whether 4-word , 8-wo rd, or 16-word burst leng th acces s e s
wrap within the selec t ed word-length boundarie s or cross word-length boundaries. When BW is
set , burst wr apping does not occur (default). When BW is cleared, burst wrapp ing occurs.
When performing synchronous burst reads with BW set (no wrap), an output dela y may occur
when the burst s e quence cros ses its firs t de vice-row (16-word) boundary. If the burst sequence’s
sta rt ad dress is 4-word aligned, then no delay occu rs. I f the start address is at the end of a 4-word
boundary, the worst case output delay is one clock cy cle les s than the first access Latency Count.
This delay can take place only once, and doesn’t occur if the burst sequence does not cross a
de vice-row boundary. WAI T informs the system of this delay wh e n it occurs.
10.3.9 Burst Length
Th e Burst Leng th bit (BL [2:0]) selects the line ar burst leng th for all synchronous b urst r e a ds of the
fla sh mem ory arra y. The burst lengths are 4-word, 8-wo rd, 16-word, and continuous word.
Conti nuous- burst access es are linear only, an d do not wrap withi n any word length bo undari es (see
Table 14, “Burst Sequence Word Ordering” on page 56). When a burst cycle begins, the device
outp uts synchronous bur s t data until it reaches the end of the “burstable” address space.
…
…
…
…
…
…
14 1 14-15-16-17-18…28-29 14-15-16-17-18-19-20-…
15 1 15-16-17-18-19…29-30 15-16-17-18-19-20-21-…
Table 14. Burst Sequence Word Ordering (Sheet 2 of 2)
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11.0 Program ming Operations
The device supports thre e programming me thods: Word Progr a mming ( 40h/10h), Buffered
Programm ing (E 8h, D0h), and Buffered Enhanced Facto ry Progr amming (Buffered EFP) (80h,
D0h). See Sec tion 9.0, “Device Operatio ns” on page 45 for details on the various programming
commands iss ued to the device.
Successful programming requires the addressed block to be unlocked. I f the bloc k is locked down,
WP # m ust be de a ss e rt e d a nd th e bl o c k m u s t be unloc k e d be f ore att e mp ting to pr ogram the bl ock.
Atte mpting to program a locke d block cause s a program error (SR[4] and SR[1] set) and
termination of the operati on. See Section 13.0, “Securit y Modes” on page 66 fo r de tai ls on loc ki ng
an d unloc k i ng bloc k s .
The following sections describe device progra mming in detail.
11.1 Word Programming
Word progra mming operations ar e initiated by writing the Word P rogram Setup command to the
device (s ee S ecti on 9. 0, “D evic e Op era tio ns ” on pa ge 45). Thi s is f oll owe d by a second wr it e to th e
device with the address and data to be programmed. The partiti on access ed during both write
cycles outp uts Status Register data when read. The partition accessed during the second cycle (the
data cycle) of t he program command sequence is the location where the da ta is written. See Figure
39, “Word Program Flowchart” on page 85.
Prog ramming can o ccur in o nly one par tit ion at a time; all o ther p art itions must be in a r ead st ate or
in erase suspend. VPP must be above VPPLK, and w ithin the specified VPPL min/ max values
(nominally 1.8 V).
During programming, the Write State Machine (WSM) executes a sequence of intern ally-timed
events that program the desired data bits at the addressed location, and verifies that the bits are
suff iciently program m e d. Progr amming the flash memory array changes “ones” to “zeros.”
Memory array bi ts that are zeros can be changed to on es only by erasing the block (see Section
12.0, “Erase Oper a tions” on page 64).
The Status Regi ster ca n be examined for programming progress an d e rrors by re ading any addres s
within the par tition that is be ing programmed. The partition remains in the Read Status Register
state until anoth er command i s written to that partit ion. Issuing the Rea d S tatus R e gister comman d
to anothe r partition addres s se ts that partition to the Read S tatus Regis ter state, allow ing
programmi ng progre ss to b e monitored at that partition’s address.
St atus Register bit SR[7 ] ind icates the programming status while the sequence executes.
Commands that can be issued to th e programmin g partition during programmin g are Program
Suspend, Read Status Register , Read Device Identifier, CFI Q uery, and Read Array (this returns
unknown data).
When programming has fini shed, Stat us Register bit SR[4] (when set) indic a tes a programming
fai lure. If SR[3] is set, th e WSM could not perform the word pr ogramming operation bec ause VPP
was outside of its acceptable limits. If S R[1] is set, the word programmi ng operation attempted to
program a locked bloc k, causing the op eration to abort.
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Before is suing a new command, the S tatus Register contents should be examined and then cleared
using th e Clear Status Register command. Any val id comm and can follow, when word
programmin g has comple ted.
11.1.1 Factory Word Programming
Fac tory wor d prog ram ming is simi lar to wo rd pro gr ammin g in that i t use s the s ame comma nds and
programm ing algo rithms. However, factory word programmin g e nhances the programming
pe rformance with VPP = VPPH. This can enable faster pro gramming times during OEM
manu fac tur in g proc e sses. F actor y wor d p ro gram ming i s not inte nde d for ext end ed u se. S ee Section
5.2, “Operating Conditions” on page 25 for lim itations whe n VPP = VPPH.
Note: When VPP = VPPL, the device draws programming current f rom the VCC s u pply. If V PP is dri ve n
by a l ogic signal, VPPL must remain above VPPL MIN to program the device. W hen VPP = VPPH,
the device dr aws programming current from th e VPP s upply. Figure 27, “Example VPP Supp ly
Connections” on page 63 shows exa mples of de vice power su pply configurations.
11.2 Buffered Programming
Th e devic e fe a tures a 32-word buffer to enable o ptimum pr ogramming performance . For Buffered
Program ming, data is firs t written t o a n on-ch ip writ e buffer. Then the buffer data is programme d
into the fl as h memory ar ray in buffe r-size in crements. This can improve system programming
performance significantly over non-buffered programming.
When the Buf fered Programming Setup command is issued (see Section 9. 2, “De vic e Commands”
on page 47), Status Register information is u pdated and reflects the ava ilability of the wr ite buffer.
SR[ 7] indicates buffer availability: if set, the buffer is available; if cleared, the write buffe r is not
av a ilable. To retry, issue the Buffered Programming Setup command again, a nd re-check SR[7].
When SR[7] is set, the buffer is ready for loading. (see Figu re 41 , “Buffer Pr o g ra m Fl owcha r t” on
page 87).
On the next write, a word count is written to the device at the buffer address. This tells the device
how m a ny data words will be written to the bu ffer, up to the m a ximum size of the buffer.
On the next write, a device start address is given along with the first data to be written to the flash
mem ory array. Subse quent write s provide additional device addre sses an d da ta. All dat a ad dress e s
must lie within the start address plus the word count. Optimum progr a mm ing performance and
lowe r power usage are obtai ne d by alig ning the starting address a t the beginning of a 32-wo rd
boun dar y ( A[4:0 ] = 0x 00). Cro ssi ng a 32-wo rd bou nda ry dur in g prog ram ming wi ll d oub le t he to tal
pro gramming tim e.
After the la st data is written to the bu ffer, the Buffered Program ming Confirm command must be
iss ued to th e original bl oc k a ddress. T he WSM begins to program buffer contents to the fla sh
memor y arra y. If a comman d other than the Buf fered Progra mming Co nfir m command i s wr itten to
the dev ice, a command sequence error occurs a nd Status Register bits S R[7,5,4] are set. If an error
occurs while writing to th e array, the device stops programming, and Status Register bits SR[7,4]
are set, indicating a programmi ng failure.
Reading from another partition is allowed while data is b e ing progr ammed into the array from the
write buf fer (see Secti on 14.0, “Dual-Operation Considerations” on page 71).
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When Buffered Progra mming has completed, additional buffer writes can be initi ated by issuing
another Buffered P rogramming Setup command and re peating the buf fered program sequence.
Buffered programming may be performed with VPP = VPPL or VPPH (see Se c tion 5.2, “Opera ting
Conditions” on page 25 for limitations when operating the device with VPP = VPPH).
If an a ttempt is made t o program past an erase-block boundary using the Buffered Program
command, the device aborts the operation. This generates a comma nd sequence error, and Status
Register b its SR[5,4] are set.
If Buffered programming is attem pted while VPP is below VPPLK, Sta tus Reg i st er bits SR [4 ,3 ] are
set. If any errors are detected that have set Status Register bits, the Status Register should be
cleared using the Clear Status Register command.
11.3 Buffered Enhanced Factory Programming
Buf fered Enhanced Factory Programing (Buffered EFP) speeds up Multi-Level Cell (MLC) flash
programming for today's beat-rate-sensitive manufacturing environments. The enhanced
programmi ng algorithm used in Buffer ed EFP eliminates traditional programming elem ents that
drive up over he ad in device programmer s yste ms .
Buf fer ed EFP consists of three phases: Setup , Program/Verif y, and Exit (see Figure 42 , “B u ffe re d
EFP Flowchart” on page 88). It uses a write buff er to sprea d MLC program per formance across 32
data words. Verification occurs in the same phase as programming to accurately program the flash
memory cell to the correct bit state.
A single two-cycle command sequen ce programs the entire block of data. This enhancement
eliminates three writ e cycles per buffer: two commands and the w ord count for each set of 32 data
words. Host prog rammer bus cycles fil l the device’s writ e buffer followed by a statu s check. SR[0]
indicat es when data from the buffer has been programmed into sequential fla sh memor y array
locations.
Following the buff er-to-flash array programming sequence, th e Write State Machine (WSM)
increments internal addressing to automatically select the nex t 32-word array boundary. This
aspec t of Buffered EFP saves host progra mming equipment the add ress-bus setu p ove rhe a d.
With adequate continuity testing, programming equipment can rely on the WSM’s internal
verification to ensure that the dev ice has programmed prope rly. This elimina tes the ext ernal post-
program ver ifi cation and its associated overhead.
11.3.1 Buffered EFP Require ments and Considerati o ns
Buffered EFP re quirements:
•Ambient temperature: TA = 25°C, ±5°C
•VCC within specified operating range.
•VPP dr ive n to VPPH.
•Target bl oc k unloc ked before iss uing the Buffered EFP Setup and Confirm commands.
•The first-word address (WA0) for the block to be programmed must be held constant from the
setu p phase t hrough all data s treaming into the target block, until transition to the exit phas e is
desired.
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•WA0 must alig n with the start of an array buffer boundary1.
Buffered EFP considera tions:
•For optimum performance, cycling must be limited below 100 erase cycles per block2.
•Buffered E FP progra ms one block at a time; al l buffer data must f a ll within a single block3.
•Buffered E FP c a nnot be sus pended.
•Progr a mming to the flash memory array can occur only whe n the buffer is full 4.
•Read operation while performing Buffered EF P is not supported.
NOTES:
1. Word buffer boundaries in the array are determined by A[4:0] (0x00 thr ough 0x1F). The alignment start
point is A[4:0] = 0x00.
2. Some degradation in performance may occur if this limit is exceeded, but the internal algorithm
continues to work properly.
3. If the internal address counter increments beyond the block's maximum address, addressing wraps
around to the beginning of the block.
4. If the number of words is less than 32, remaining locations must be filled with 0xFFF F.
11.3.2 Buffered EFP Setup Phase
After rece iving the Buffered EFP Setup and Confirm command sequen ce, Status Regist er bit SR[7]
(Rea dy) is cleared, indicating that the WS M is busy with Buffered E FP algorithm start up. A dela y
before checkin g SR[7] is req uired to allow the WSM enough time to perform all of its setups and
checks (Block-Lock status, VPP level, etc. ). If an error is detected, SR[4] is set and Buffered EFP
oper ation ter minates . If the block was found to be locked, SR[ 1] is also set. SR [3] is set if the erro r
occur red due to an incorrect VPP lev e l.
Note: Reading from the devic e after the Buffered EF P Setup and Confirm c ommand se quence outputs
Status Register data. Do not is sue the Read Status Register command; it w ill be interpreted as data
to be loaded into the buffer.
11.3.3 Buffered EFP Program/Verify Phase
After the B uffered EFP Setup Phase has complete d, the host progr a mming system m ust check
SR[ 7,0] to deter mine the availab ility of the write bu f fer fo r data stream ing. SR[7] cle ared indi cates
the dev ice is busy and the Buff e red EFP program/ver ify phase is activated. SR[0] indicates the
write buffer is available.
Two basic sequences repeat in this phase: loading of the writ e buffer, followed by buffer data
programming to the array. For Buffered EFP, the count value for buffer loading is always the
maximum b uffer siz e of 32 words. During the buffe r-loading seque nc e , data is stored to s e quen tia l
buffer locations starting at ad dress 0x00. Programm ing of the buf fer contents to the flash me mo ry
arr ay starts as soo n as the buf fer is full. If the numb er of words is less than 32, th e remain ing buf fer
locations must be filled with 0xF FFF.
Caution: The buff er m ust be comp letel y fil le d for programmi ng to occu r. S upp lyi ng an address ou tsid e of th e
current block's rang e during a buffer-fil l se quence causes the algo r ithm to exit immedia tely. Any
data previousl y loaded into the buffer during the fill cycle is not programmed into the array.
The starting address for data en try must be buffer size aligned, if not the Buffered EFP algorithm
will be aborted and the pro gram fail (SR[ 4]) flag will be set.
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Data words from the write buf fer are di rected to sequential m emory locations in the flash memory
ar ra y ; progra mming cont i nu e s f ro m where th e pr e vi o us bu ffe r se qu e nc e en d e d. The hos t
programmi ng system must poll SR[0] to dete rmine whe n the buffer progra m s e quence comple te s.
SR[0] cleared indicates that all buffer data has been transf erred to the flash array; SR[0] set
indicat es that the buffer is not availab le yet for the next fill cyc le. The host system may check full
status for errors a t any time, but it is o nly necessary on a bl ock basis after Buffered E FP exit. After
the buffer fill cycle, no write c ycles should be issued to th e device until SR[0] = 0 and the d e vice is
ready for the next buffer fill.
Note: Any spur ious writes are ignored after a buffer fill ope rati on a nd when inte rnal program is
proceeding.
The host programming system continues the Buffered EFP algor ithm by pro viding t he ne xt group
of data words to be wr itten to the buf fer. Alternatively, it can terminate this p hase by changing the
block a ddress to one outside of the c urrent block’s range .
The Program/Ver ify phase concludes when the programmer writes to a different block address;
dat a supplied must be 0x FFFF. Upon Program/Verif y pha se completion, the devic e ente rs the
Buf fered EF P Exit phase.
11.3.4 Buffered EFP Exit Phase
When SR[7] is set , the device has returned to normal operating condition s. A full status check
should be performed on the partition be ing programmed at this time to e nsu re the entire block
programme d succes sfully. When exiting the Buffered EFP algorithm wit h a blo c k add ress change,
the read mode of both the programmed and the addressed partition w ill not change. After Buffe red
EFP exit, any valid command can be issued to the devi ce.
11.4 Program Suspend
Issuing the Program Suspe nd command while pr ogramming s uspends the programming operation.
This allows data t o be accessed from memo ry locatio ns other than the one being programm ed. The
Program Suspend command ca n be issued to any de vice addre ss; the co rresponding partition is not
aff ected. A program operation can be suspended to perform reads only. Additionally, a program
operation that is running during an er ase suspend can be susp ended to per form a read operation
(see Figure 40, “Program Suspend/Resume Flowchart” on page 86).
When a programmi ng op eration is executing , iss uing the Program Susp end command requests the
WSM to suspe nd the programmin g algorithm at predetermined points. The partit ion that is
suspended continues to outp ut S tatus Regis ter data after the Program Suspend command is is sued.
Prog ra mming is suspended when Status Register bits SR[7,2] a re set. Suspend la te ncy is specified
in Section 7.7, “Program and Erase Characteristics ” on page 41.
To rea d data from blocks with in the sus pe nded par t ition, the Read Array com mand must be iss ued
to that partition. Read Array, Read Status Regi ster , Read Device Identifier, CFI Query, and
Program Resume are va lid commands during a program suspend.
A program operation does not need to be susp e nded in order to read data from a bl oc k in a nother
partition that is not progr amming. If the other partition is already in a Read Array, Read De vice
Identifier , or CFI Query state, is suing a valid add ress returns correspo nding read data. If the othe r
partition is not in a read mode, one of the read commands must be issued to the partition before
dat a can be read.
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During a program suspend, deasserting CE# places the device in standby, reducing active current.
VPP must rem ain at its pro gramming level, and WP# m ust remai n unchanged while in pro gram
suspend. If RST# is asserted, the device is reset.
11.5 Program Resum e
The Resume command ins tructs the device to continue program m ing, and automatically clears
Status Register bits SR[7,2]. This command can be written to any partit ion. When read at the
partition that’s progra mming , the device outputs data corresponding to the pa rtition’s last sta te. If
err or bits are set, the S tatus Register s hould be cleared before issuing the nex t instruction . RS T#
must remain dea sserted (see Figure 40, “Program Suspend/Resume Flowchar t” on page 86).
11.6 Program Pro tection
Whe n VPP = VIL, absolute hard wa re write protection is pr ovided for all device bl oc ks. If VPP is
below VPPLK, programmi ng opera tions halt and SR[3] is set indicati ng a VPP-level error. Block
lock registers are not affected by the voltage lev el on VPP; they may still be progra mmed and read,
even if VPP is less than VPPLK.
Figure 27. Example VPP Supply Connections
• Factory Programming with VPP = VPPH
• Complete write/Erase Protection when VPP ≤ VPPLK
VCC
VPP
VCC
VPP
• Low Voltage and Factory Programming
• Low-voltage Programming only
• Logic Control of Device Protection
VCC
VPP
• Low Voltage Programming Only
• Full Device Protection Unavailable
VCC
VPP
≤ 10K Ω
VPP
VCC VCC
PROT #
VCC
VPP=VPPH
VCC
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12.0 Erase Operations
Flash erasing is performed on a bl ock basis. A n entire block is er ased each time an erase command
sequence is is sued, and only one block is erased at a time. When a block is erased, all bi ts within
that block read as logical ones. The following sections describe block erase ope rations in detai l .
12.1 Bl ock Erase
Block erase operations are initiated by writing th e Block Erase Setu p command to the address of
the block to be eras ed (see Section 9.2, “Device Comma nds” on pa ge 47). Next, the Block Erase
Confirm command is writt en to the address of the block to be erased . Erasing can occur in onl y one
partition at a time; all other pa rtitions must be in a read state. I f the device is placed in standby
(CE# deasserted) during an erase operation, the device completes the erase operati on be fore
entering standby.VPP mu st be a bove VPPLK and the block must be unlocked (see Figu re 43, “B l ock
Erase Flowchart” on page 89).
During a block erase, the Write State Machine (WSM) ex ecutes a sequence of int ern ally-timed
events that conditi ons, er ases, and verifies all bits wi thin th e block. Erasing th e flash me mory array
changes “zer os” to “ones.” Memory array bits that are ones can be changed to zeros only by
programmi ng the blo c k (see Section 11.0 , “Programming Operat ions” on page 58).
The Status Register can be examined fo r bl ock eras e progress and errors by readin g any address
within the par tition that is be ing er ased. The partition remains in the Read Status Register state
until another com mand is written to that partition. Iss uing the Read Status Regis ter command to
another partition addr es s sets that partit ion to the Read Status Register state, allowing erase
progr ess to be monit ore d at tha t p art ition’s addr ess . SR[ 0] i ndi cat es w het her the add resse d pa rtit ion
or another partition is erasing. T he pa rtition’s Status Register bit SR[7] is s e t upon e rase
completion.
St atus Register bit SR[7 ] in dicates block erase status while the sequence executes. When the erase
operat ion has finished, Status Register bit SR[5 ] indicates an erase f ailure if set. SR[ 3] set would
indicat e that the WSM could not perform the erase operation because V PP was outside of its
acceptable limits. SR[1] set indicates that the erase operation attempted to era se a lo cked block,
causing the operation to abort.
Before issuing a new command, the Status Register contents sho uld be examined and then cleared
using the Clear Status Register command. A ny valid command can follow once the block erase
operation has completed.
12.2 Erase Suspend
Issuing the Erase Su spend command while era sing suspends the block erase operat ion. This allows
data to be accessed fro m memory locations other than the one being erased. The Erase Suspend
command can be is s ued to any device address; the correspo nding partition is not aff ected. A block
era se opera tion can be suspended to perform a wor d or buffe r program operation, or a read
operat ion w ithin any block except the block that is erase suspended (see Figure 40, “Program
Suspe nd/Resum e Flowchart” on pa ge 86).
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When a blo ck erase o peratio n is ex ecuting , issuing the Erase S uspend co mmand re quests t he WSM
to s usp end the erase algo rithm at pr edet ermin ed poi nts. The partiti on tha t is s usp ended co nti nue s to
outp ut S tatus Register data after the Erase Suspend command is issued . Bl ock er as e is susp ended
when Status Register bits SR[7,6] are set. Suspend lat ency is specified in Secti on 7.7, “Program
and Erase Characteristics” on page 41.
To read data from blocks within the sus pende d partition (other than an erase-suspended block), the
Re a d Array c ommand must be is sued to that partition first. During E rase Suspend, a Pr ogram
comman d can be iss ued to any block other th an the er ase-suspended block. Block erase cannot
resum e until program operations initiated du ring erase suspend compl e te. Read Array, Read Status
Register, Read Device Identifier, CFI Query, an d Erase Resum e are valid commands during Erase
Suspend. Additionally, Clear Status Register, Program, Program Suspend, Block Lock, Block
Unlock, and Blo ck Lock -D own are valid commands during Er as e Su spend.
To read data from a block in a parti tion that is not er asing, the erase op eration does not need to be
susp ended. If the other pa rti tion is already in Read Array, Read Device Identifier, or CFI Query,
issu ing a vali d ad dr ess r etu rn s corr espo ndi ng d ata. If th e ot her par tit ion is not in a r ead state , on e of
the rea d commands must be issued to the partition befor e data can be r ead.
During an erase suspend, deas s erting CE# places th e device in standby, re ducing active current.
VPP must remain at a valid level, and WP# must remain unchanged while in erase suspend. If
RST# is ass erted, the device is reset.
12.3 Erase Resume
The Erase Resume command instructs the device to continue erasing, and automatically clears
status register bit s S R[7,6]. T his command can be written to any partition. Wh en read at the
partition that’s erasing , the device outputs dat a c orresponding to the partition’s last state. I f s tatus
regi ster error bits are set, the Status Register sh ould be cleared befo re issuing the next instruction.
RST# must remain deasserted (see Figure 40, “Progr a m Suspe nd/Resume Flowc har t” on page 86).
12.4 Erase Protection
Whe n VPP = VIL, absolute hardware erase protection is provided for all device block s. If VPP is
below VPPLK, erase operations halt and SR[3 ] is s e t indicating a VPP-l evel er ror.
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13.0 Security Modes
The device featur es security modes used to protect the in formation sto red in the flash memory
array. The following section s de scribe each security mode in detail.
13.1 Block Locking
Individua l instant block locki ng is used to protect user code a nd/or da ta withi n the flash memory
array. All blocks power up in a locked stat e to prote c t a rray data from being altered during power
transitions. Any block can be locked or unlocked with no latency. Locked blocks cannot be
programmed or erased; they can only be read.
Software-controlled security is implemented using the Block Lock and Block Unlock commands.
Hardware-controlled s ecur ity can be implemented using the Bloc k Lock-Down command along
wit h asserting WP#. Also, VPP data security can be us e d to inhibit program an d e rase operations
(see Section 11.6, “Program P rotection” on pa ge 63 and Sectio n 12.4, “Erase Pr ote c tion” on
page 65).
13.1.1 Lo ck Block
T o lock a block, issue the Lock Block Setup command . The next command must be the Lock Block
command issued to the desired blo ck’s address (see S ection 9.2, “Device Commands” on page 47
and Figure 45, “Block Lock Operations Flowchart” on page 91). If the S e t Read Configuration
Regist er command is issued after the Block Lock Setup command, the device configures the RCR
instead.
Block loc k and un loc k opera tions are not affected by the vo lta ge level on VPP. The block lock bits
may be modified and/or read even if VPP is below VPPLK.
13.1.2 Unlock Block
The Unlock Block comman d is used to un lock blocks (see Section 9.2, “Device Commands” on
page 47). Unlocked blocks can be read, programmed, and erased. Unlocked blocks return to a
locked state w hen the device is reset or power e d do wn. If a block is in a lock-down state, W P#
mus t be deass e rted before it can be unloc ked (see Figure 28, “Block Lockin g S tate Diagram” on
page 67).
13.1.3 Loc k-Down Block
A loc ke d or unloc ked blo c k c a n be l oc ked- down by writing the Lock-Down Bloc k command
sequence (see Section 9.2, “ Device Com mands” on page 47). Blo c ks in a lock-down s t a te c a nnot
be programmed or erased; they can only be read. Howev er , unlike locked blocks , their locked state
cannot be cha nged by softw a re c omma nds alone. A locked-down block c a n only be unlock e d by
issuin g the Unlock Block comm a nd wi th W P# deasserted. To return an unlocked block to locked-
down state, a Lock-Do wn command must be issued prior to changing WP# to VIL. Locked-down
blocks revert to the locked sta te upo n reset or powe r up the device (se e Figure 28, “Blo ck Locking
State Diagram” on page 67).
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13.1.4 Block Lock Status
The Read Device Id entifier command is used to det ermine a block’s lock status (see Secti on 15.2,
“Read D evice Identifier” on page 76) . Data bits DQ[1:0] displa y the addres sed block’s loc k status;
DQ0 is the a ddress ed block’s lock bit, while DQ1 is the addressed block’s lock-down bit.
13.1.5 Block Locking During Suspend
Bloc k lock and unloc k c hanges can be perform e d duri ng a n e rase suspend . To change bloc k
locki ng during an erase operation, first issue the Erase Suspend command. Monito r the Status
Register until SR[7 ] and SR[6] are set, indicating the device is suspended and ready to accept
another co mmand .
Next, wr ite the desired lock command sequence to a bloc k, w hich changes the lock s tate of that
block . A fter completing block lock or unlock operation s , r esu me the erase operation using the
Erase Resume command.
Note: A Lock Block Setup comma nd followed by an y command other than Lock Block, Unlock Block,
or Lock-Down Block pro duces a command sequence error and set Status Regi s ter bits SR[4] and
SR[5] . If a comma nd sequence error occurs during an erase susp end, SR[4] an d S R[5] remains s et,
even after the erase operation is resumed. Unless the St atus Register is cleared using the Clea r
Status Register command before resumi ng the erase operation, possible erase errors may be
masked by the comman d se quen ce err or.
Figure 28. Block Locking State Diagram
[X00]
[X01]
Power-Up/Reset
Unlocked
Locked
[011]
[111] [110]
Locked-
Down4,5
Software
Locked
[011]
Ha rd w a re
Locked5
Unlocked
W P# H a rd w a re C o n tro l
No tes : 1. [a,b,c] re pres en ts [WP# , D Q 1 , D Q 0 ]. X = D o n’t C a re.
2. DQ 1 ind ica tes B loc k L oc k -D o w n s tatu s . DQ1 = ‘0 ’, Loc k-Dow n h as no t be en iss ue d
to this b lock. D Q 1 = ‘1 ’, Loc k -D o w n h as be e n iss ue d to th is blo ck.
3. DQ0 indicates block lock status. DQ0 = ‘0’, block is unlocked. DQ0 = ‘1’, block is
locked .
4. Locked-down = Hardware + Software locked.
5. [011 ] sta tes sh ou ld b e tra ck ed b y sy ste m s oftware to d e termine d iffere nc e b etwee n
Har dw a re Lo ck ed a nd Lo ck ed-D o w n s tate s .
Software B lock Loc k (0x60/0x01) or S o ftware Block U nlock (0x60 /0xD 0)
Software B lock Loc k -Down (0x 60/0x2F)
W P# hardware control
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If a block is lock ed or locked-down duri ng an e rase s us pend of the same block, the lock s tatus bits
change imme diately. However, the erase operati on completes when it is resumed. Block lock
ope ra tion s cannot occur during a program s uspend. See Appendix A, “Write St ate Machine
(WSM)” on pa ge 78, which shows va lid commands during an er a se sus pe nd.
13.2 Prote ction Regis te rs
The device contains 17 Protection Registers (PRs) that can be used to implement system security
measure s and/or device identification. Each Protection Regi st er can be individually locked.
The first 12 8-bit Protect ion Regist er is c ompris e d of two 64-bit (8-word ) s e gments. The lo we r 64-
bit segment is pre-programm e d a t the fa c tory with a unique 64-bit number. The othe r 64-bit
segment, as well as the other sixteen 128-bit Protection Registers, ar e blank. Users can progr am
these registers as needed. When pro gr a mmed, us ers can then lock the Prote ction Register(s ) to
prevent addi tional b it programming (s ee Figure 29, “Prot e c tion Register Ma p” on page 69).
The us e r-pro gramm a ble Protec tion Registers contain one- time programmable (OT P) bits; when
programme d, r egister bits cann ot be er ased. Each Protection Register can be access ed m ultiple
times to program individual bits, as long as the register rema ins unlocked.
Each Protecti on Reg is ter has an associated Lock Regis ter bit. When a Lock Register bit is
progr amme d, the asso ciat ed Prote c tion Re gist er can on ly be read; it can no lo nger be pr ogram med.
Additionally, because the Lock Register bits thems elves are OTP, when pro gr a mmed, Lock
Register b its cannot be erased. Therefore, when a Protection Register is locked, it cannot be
unlocked
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.
13.2.1 Reading the Protection Registers
The Protect ion Registers can be read from within any partition’s address s pace. To read the
Protection Register , f irst issue the Read Device Ident ifier command at any parti tions’ addres s to
place that partition in the Read Device Id entifier state (see Section 9.2, “Device Commands ” on
page 47). Next, perform a re ad operation at that partition’s base address plus the address offset
co rresponding to the register to be read. Table 17, “Device Ide ntifier Inf ormation” on pa ge 77
shows the address offsets of the Protection Registers and Lock Regi st ers. Register data is read 16
bits at a time.
Note: If a program or erase operation occurs within the device while it is reading a Protectio n Register,
ce rta in re str icti ons may appl y. See Table 15, “Simul tane ous Ope ratio n Res tri ct ions ” on page 74 for
details.
Figure 29. P rotection R egister Map
0x89 Lock Regis ter 1
15 14 13 12 11 10 9876543210
0x102
0x109
0x8A
0x91
128-bi t Protection Register 16
(User-Programmable)
128-bit P ro tection Register 1
(User-Programmable)
0x88
0x85
64-bit S egment
(User-Programmable)
0x84
0x81
0x80 Lock Register 0
64-bit S egment
(Factory-Programmed)
15 14 13 12 11 10 9876543210
128-Bit P r otection Register 0
Intel StrataFlash® Wireless Memory (L18)
August 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
70 Order Numb er: 251902, Re vi sion: 010
13.2.2 Programming the Protection Registers
To program any of th e Pr otection Registers, first iss ue the Program Protection Register com m a nd
at the parameter partition’s base address plus the offset to the desired Protection Register (see
Section 9.2, “Devic e Commands” on page 47). Ne xt, write t he de sire d Prote c tion Register data to
the sam e Protection Regi ster address (se e Figure 29 , “P ro t e ct i on Re g ister Ma p” on pa ge 6 9).
The device pr ograms the 64-bit and 128-bit user-programmable Protect ion Regist er data 16 bits at
a time (see Figure 46, “Protection Regi ster Programming Flowchart” on page 92). Issuing the
Program Prot ection Register command outside of the Protecti on Reg is ter’s address space caus es a
program err or (S R[4 ] set). Attempting to program a locked Protection Register causes a program
error (SR[ 4] set) and a lock error (SR[1] set).
Note: If a program or erase operatio n occu rs when program mi ng a Prot ection Register, certain
restrictions may apply. See Table 15, “S imult aneou s Oper ati on Res tric t ions ” on pag e 74 fo r de ta il s.
13.2.3 Locking the Protection Registers
Each Protecti on Register can be locked by programming its respective lock bit in the Lock
Regi ster. To lock a Protection Regi ster, pr ogram the corresp onding bit in the Lock Register by
issuin g the P ro gram Lock Register command , followed by the desired Lock Regis ter data (see
Section 9.2, “Devic e Commands” on page 47). The physical addresses of the Lock Registers are
0x80 for re giste r 0 and 0x89 fo r register 1. Thes e a ddresses are used whe n progra mming the lo ck
registers (see Table 17, “Device Identifier Inf ormation” on pa ge 77).
Bit 0 of Loc k Register 0 is alre a dy programmed at the fa c tory, loc king the lower, pre-programmed
64-bi t reg ion of the fi rst 1 28- bit Pr ote ctio n Regi st er co nta ini ng the unique ide nti fic ati on nu mber of
the dev ice. Bi t 1 of Lock Regist er 0 ca n be p rogrammed by the user t o l ock the user -pro grammable,
64-bit region of the first 1 28-bit Protec tion Register. The other bits in Loc k Re gister 0 are not used.
Lock Register 1 c ontrols the locking of the uppe r sixteen 128-bit Prot e c tion Registers. Each of the
16 bits of Lock Re gister 1 correspond to each of the uppe r sixteen 128-bit Protection Registers.
Programming a bit in Lock Register 1 locks the corresponding 128-bit Protection Register.
Caution: After being locked, the Protection Registers cannot be unlocked.
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel S trata F lash® W i rel ess M em ory (L18) August 2005
Order Num ber: 251902, Re visio n: 010 71
14.0 Dual-Operation Considerations
Th e multi-partition archite cture of the device allows bac kground programming (or erasing) to
occur in one part ition while data reads (or code execution) take place in another partition.
14.1 Memory Partitioning
Th e L 18 flas h memory array is div ided into mu ltiple 8-Mbit partitions, which allows simultaneous
rea d-while-write operations. Simultaneou s progr a m and era se is not all owed. Only one part ition at
a time can be in program or erase mode.
Th e f lash dev ice supp orts read -whil e-wri te operati ons wi th bu s cycl e g ranularity a nd no t c omman d
granular ity. In oth er wo rds, i t is not assumed th at b oth bu s cy cles o f a tw o cycle command (an e rase
command for example) will always occur as back to back bus cycles to the flash device. In
pract ice, code fetches (reads) may be interspersed between write cycles to the flas h dev ice, and
they w ill like ly be dir ected to a dif feren t par titio n tha n the one be ing wri tte n. This is especia lly true
when a processor is executing code from one partition that in s tructs the proces sor to program or
erase in another partition.
14.2 Read-While-Write Command Sequences
When issuing commands to the device, a read operation can occur between 2-cycle Write
command’s (Figu re 30, and Figu re 31). How ever, a write operation issued betw een a 2- cycle
commands write s equence causes a command sequence error. (See Figure 32)
When readi ng f rom the same partition after issui ng a Set up command, S tatus Register data is
returned, regardless of the read mode of the partition prior to issuing the Setup command.
Figure 30. Operating Mode with Correc t Command Sequence Example
Partition A Parti ti o n A Partition B
0x20 0xD0 0xFF
A
ddress [A]
WE# [W ]
OE# [G]
Da ta [D/Q]
Intel StrataFlash® Wireless Memory (L18)
August 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
72 Order Numb er: 251902, Re vi sion: 010
14.2.1 Simultaneous Operati on Details
The Intel StrataFlash® Wireles s Memory (L18 ) s upports simultaneous read from one partit ion
while progra mming or erasing in any ot he r partition. Certain fea tures like the Protection Re gisters
and Query da ta have special re quirements with respect to simultaneous operatio n capability. These
will be detailed in the follow ing sections.
14.2.2 Synchronous and Asynchronous RWW Characteristics and
Waveforms
This sect ion describes the transi tion of write operation to asynchronous read, wr ite to synchr ono us
read, and write operatio n wit h clock active.
14.2.2.1 Write operation to asynchronous read transition
W18 - tWHAV
The AC p ara me t er W1 8 ( t WHAV-WE# High to Add ress Va lid) is requi red when trans ition ing from a
write cycle (W E# go ing high) to perform an asy nchr onous read (only address valid is requ ired).
Figure 31. Opera ting Mode with Correct Command Sequence Exampl e
Figure 32. Opera ting Mode wit h Illegal Comm and Se quenc e Exa mp le
Partition A Pa rti ti on B Parti ti o n A
0x20 Val id Array Data 0xD0
A
ddress [A]
WE# [W ]
OE# [G]
Data [D/Q]
Partition A Pa rti tio n B Partition A Partition A
0x20 0xFF 0xD0 SR[7:0]
A
ddress [A]
WE# [W]
OE# [G]
Da ta [D/Q]
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel S trata F lash® W i rel ess M em ory (L18) August 2005
Order Num ber: 251902, Re visio n: 010 73
14.2.2.2 Write to synchronous read operation transition
W19 an d W20 - tWHCV and tWHVH
Th e AC pa ramete rs W19 or W20 (tWHCV-WE# High to Clock Valid, and tWHVH - WE# High to
ADV# High) is required whe n tra nsitioning from a write cycle (WE# going high) to pe rform a
synchronous burst re a d. A delay from WE# going high to a va lid clock edge or ADV# going high
to latch a new address must be met.
14.2.2.3 Write Operation with Clock Active
W21 - tVHWL
W22 - tCHWL
Th e AC pa ramete rs W21 (tVHWL- ADV# High to WE# Low) and W22 (tCHWL -Clock high to
WE# low) are re quire d duri ng write ope rations whe n the de vic e i s in a synchronous mode and the
clock is active. A write bus cycle consis ts of two parts:
•the host provides an address to the flash devic e; and
•the host then pro vides data to the flash device.
The flash device in turn binds the receiv e d dat a with the received address . W hen operating
syn chron ously (RCR[15 ] = 0), th e addres s of a write cy cle may be pr ovi ded to the flash by th e firs t
active clock edge with ADV# low, or rising edge of ADV# as lo ng as the applicable cycle
separation conditions are met between each cycle.
If neith er a clock edge nor a risin g ADV# edge is used to prov ide a new addres s at the begin ning of
a writ e cycle (the clock is st opped and ADV# is lo w), th e address may also be prov ided to th e flash
device b y holding the ad dress b us s table for the re quired amount of tim e (W5, tAVWH) before the
rising WE# edge.
Alternatively, the host may choose not to provide an address to the flash device during subsequent
wri te cycles (if ADV# is high and only CE# or WE # is toggled t o s eparate the p rior cycle fr om the
current write cycle) . In this ca se , the flash device will use the m ost recently provided address from
the host.
Refer to Figure 20, “Write to Asynchronous Rea d Timing” on page 39, Figure 21, “Synch ronous
Read to Write Timing” on page 39, and Figure 22, “Write to Synchronous Read T iming” on
page 40, for represent ation of these timings.
14.2.3 Read Operation Du ring Buffered Programming
Th e multi-partition archite cture of the device allows bac kground programming (or erasing) to
occur in one part ition while data reads (or code execution) take place in another partition.
To perform a read while buffered programm ing operation, first issue a Buffered Program set up
command in a partition. When a read operation occurs in the same partition after issuing a setup
comman d, Status Reg ister data wi ll be retur ned, regar dless of th e read mod e o f the pa rti tion pr ior t o
is s ui n g the se t u p command.
Intel StrataFlash® Wireless Memory (L18)
August 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
74 Order Numb er: 251902, Re vi sion: 010
To read data from a block in other partitio n and the other partitio n already in read array mode, a
new bl ock add res s m ust be iss ued . Ho weve r, if t he oth er par tit ion is not alre a dy in rea d arr ay m od e,
issuing a read array command will cause the bu ffered program operation to abort and a com mand
sequence er ror would be posted in the Status Register. See Figure 41, “Buf fer Program Flowchart”
on pa ge 87 for more details.
Note: Simultaneous r e a d-while-Buffe re d EFP is not supported.
14.3 Simultaneous Operation Restrictions
Since the Int e l StrataFlash® Wire le ss Memory (L18) supports sim ultaneous read from one
partition whil e programming or erasi ng in another partitio n, certain f eatures like the Protecti on
Regi sters and C FI Query data have special require ments with respect to sim ultaneous opera tion
capability. (Table 15 provides deta ils on res trictions during simulta ne ous operations.)
Table 15. Simultaneous Ope ration Restrictions
Protection
Register or
CFI data
Parameter
Partition
Array Data
Other
Partitions Notes
Read (See Notes) Write/Erase
While programming or erasing in a main partition, the Protection Register or CFI
data may be read from any other partition.
Reading the parameter partition array data is not allowed if the Protection Register
or Query data is being read from addresses within the parameter partition.
(See Notes) R ead W rite/Erase
While programming or erasing in a main partition, read operati ons are allowed in th e
parameter partition.
Accessing the Protection Registers or CFI data from parameter partition addresses
is not allowed when reading array data from the parameter partition.
Read Read Write/Erase
While programming or erasing in a main partition, read operati ons are allowed in th e
parameter partition.
Accessing the Protection Registers or CFI data in a partition that is different from the
one being programed/erased, and also different from the parameter partition is
allowed.
Write No Access
Allowed Read
While programming the Protection Register, reads are only allowed in the other
main partitions.
Access to array data in the parameter partition is not allowed. Programming of the
Protection Register can only occur in the parameter partition, which means this
partition is in Read Status.
No Access
Allowed Write/Erase Read While programming or erasing the parameter partition, reads of the Protection
Registers or CFI data are not allowed in any partition.
Reads in partitions other than the parameter partition are supported.
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel S trata F lash® W i rel ess M em ory (L18) August 2005
Order Num ber: 251902, Re visio n: 010 75
15.0 Special Read S tates
The follow ing sections describe non-array read states. Non-array reads ca n be perf ormed in
asy nchr on ous r ead or synch ron ou s bur st m ode. A non -ar r ay re ad o pera tion o cc urs as a synch ro nou s
single-word mode. When non-array re a ds are pe rform e d in async hronous page mode only the first
data is valid a nd al l subseq ue nt da ta a re unde fined. When a non-a rray rea d operation occurs as
syn chr onous bu rst m ode , the sam e wor d of da ta re que st ed wi ll be outp ut o n succe ss ive clo ck edg es
until the burst length requirements are satis fied.
Each p artiti on can be in on e o f its read stat es indep endent of o ther part itions’ m odes. See Figure 1 1,
“Asynchronous Single-Word Read with ADV# Low” on page 33 and Figure 14, “ Synch ronous
Single-Word Array or Non-array Read Timing” on page 35 for details.
15.1 Read Status Register
The status of any partition is determined by rea ding the Status Register from the add ress of that
part icul ar par tition. To read th e St atus Re giste r, issue t he Read S t atus Re gister command wit hin the
des ired partit ion’s addr ess range . S tatus Register informat ion is availab le at the parti tion addr ess to
which the Read Status Register, Wor d P rog ram, or Block Erase command was issued. Status
Register data is automatically made available following a Word Progra m, Block Erase, or Bloc k
Lock command sequence. Reads from a partition after any of th ese comman d se quen ces outputs
that partition’s status until another valid command is written to that partition (e.g. Read Arr ay
command).
The Status Register is read using single asynchronous -mode or synchronous burst mode reads.
Statu s Register dat a is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In async hronous
mode the falling edge of OE#, or CE # (whic he ver occurs first) updates and l a tc hes the Sta t us
Regis ter con tent s. H owev er , r eadi ng th e Sta t us Reg ist er in s yn chrono us burs t mode , CE# o r A DV#
must be togg led to update statu s data. The Status Register read op erations do not af fect the read
state of t he other partitions.
Th e De vice Write Sta tus bit (SR[7]) provide s overa ll status of the dev ic e . The Par t ition Status bit
(SR[0]) indicates wh e ther the addr e ssed partition or some other par t ition is actively programming
or eras ing. Status register bits SR[ 6:1] present status and error information about the program ,
erase, suspend, VPP, and block-locked operations.
Table 16. Status Register Description (Sh eet 1 of 2)
Status Register (SR) Default Value = 0x80
Device
Write Status Erase
Suspend
Status Erase
Status Program
Status VPP Status Program
Suspend
Status
Block-
Locked
Status Partition
Status
DWS ESS ES PS VPPS PSS BLS PWS
76543210
Bit Name Description
7Device Write Status
(DWS) 0 = Device is busy; program or erase cycle in progress; SR[0] valid.
1 = Device is ready; SR[6:1] are valid.
6Erase Suspend Status
(ESS) 0 = Erase suspend not in effect.
1 = Erase suspend in effect.
Intel StrataFlash® Wireless Memory (L18)
August 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
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Always clear the Statu s Regis ter prior to resuming erase operati ons. This avoids Status Register
ambiguity when is suing commands durin g Erase Sus pend . If a com m and sequence error occurs
during an eras e-suspend state, the Status Regi ster contains the command sequence error status
(SR[7,5, 4] set). When the erase operation resumes and finishes, possible erro rs dur ing the erase
operat ion cannot be detected via the Status Register because it contains th e previous error status.
15.1.1 C lear Status Register
The Clear Status Register command clears the status regi st er, leaving all par tition read states
unc hanged. It functions indepe ndent of VPP. The Write State Machine (WSM) sets and clear s
SR[7,6,2, 0], but it sets b its SR[5:3,1 ] w ithout clearing them. The Status Regis ter should be cleared
before starting a command sequence to avo id any ambiguity. A device r eset also clear s the Status
Register.
15.2 Read Device Identifier
The Read Device Iden tifier command in st ructs the addressed partition to output manufacturer
code, device identifier code, block-lock status, protection register data, or configuration register
data when that partit ion’s addresses ar e read (see S ection 9.2, “Dev ice Commands” on page 47 for
details on issuin g the Read Devic e Identifier comman d). Table 17, “Device Identi fier Informati on”
on pa ge 77 and Table 18, “Device ID c odes” on page 77 sh ow the add ress offsets and data values
for t his device.
Issuing a Read Device I dentif ier comman d to a partition that is program ming or erasi ng places that
partit ion in the Read Identifier state while the partition continues to pr ogr am or erase in the
background.
5 Erase Status (ES) 0 = Erase successful.
1 = Erase fail or program sequence error when set with SR[4,7].
4 Program Status (PS) 0 = Program successful.
1 = Program fail or program sequence error when set with SR[5,7]
3V
PP Status (VPPS) 0 = VPP within acceptable limits during program or erase operation.
1 = VPP < VPPLK during program or erase operation.
2Program Suspend Status
(PSS) 0 = Program suspend not in effect.
1 = Program suspend in effect.
1Block-Locked Status
(BLS) 0 = Block not locked during program or erase.
1 = Block locked during program or erase; operation aborted.
0Partition Write Status
(PWS)
DWS PWS
0 0 = Program or erase operation in addressed partition.
0 1 = Program or erase operation in other partition.
1 0 = No active program or erase operations.
1 1 = Reserved.
(Non-buffered EFP operation. For B uffered EFP operation, see
Section 11.3, “Buffered Enhanced Factory Programming” on
page 60).
Table 16. St atus Registe r Descript ion (Sheet 2 of 2)
Status Register (SR) Default Value = 0x80
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel S trata F lash® W i rel ess M em ory (L18) August 2005
Order Num ber: 251902, Re visio n: 010 77
15.3 CFI Query
The CFI Query command instructs the device to output Common Flash Interface (CFI) data when
part ition addresses are read. See Section 9.2, “Device Commands” on page 47 for det a i ls on
issu ing the CFI Query command. Appe ndix C, “Common Flash Interface” on page 93 show s CFI
inf ormation and address offsets within the CFI data bas e.
Iss uing t he CFI Quer y comm and to a partit ion that is p rogr amming o r er asing places that parti tio n’s
outp uts i n the CFI Q uery st ate, wh ile the part ition continu es to program or er ase in the backg round.
Th e CFI Query command is subject to read restrictions depe ndent on pa ramete r partition
availability, as described in Table 15.
Table 17. Device Id entifi er Informatio n
Item Address(1,2) Data
Manufacturer Code PBA + 0x00 0089h
Device ID Code PBA + 0x01 ID (see Table 18)
Block Lock Configuration:
BBA + 0x02
Lock Bit:
• Block Is Unlocked DQ0 = 0b0
• Block Is Locked DQ0 = 0b1
• Block Is not Locked-Down DQ1 = 0b0
• Block Is Locked-Down DQ1 = 0b1
Configuration Register PBA + 0x05 Configuration Register Data
Lock Register 0 PBA + 0x80 PR-LK0
64-bit Factory-Programmed Protection Register PBA + 0x81–0x84 Factory Protection Register Data
64-bit User-Programmable Protection Register PBA + 0x85–0x88 User Protection Register Data
Lock Register 1 PBA + 0x89 Protection Register Data
16x128-bit User-Programmable Protection
Registers PBA + 0x8A–0x109 PR-LK1
Notes:
1. PBA = Partition Base Address.
2. BBA = Block Base Address.
Table 18. Device ID codes
ID Code Type Device Density Device Identifier Codes
–T
(Top Parameter) –B
(Bottom Parameter)
Device Code 64 Mbit 880B 880E
128 Mbit 880C 880F
256 Mbit 880D 8810
Intel StrataFlash® Wireless Memory (L18)
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78 Order Numb er: 251902, Re vi sion: 010
Appendix A Write State Machine (WSM)
Figure 33 through Figure 38 show the command state transitions ( Next State Table) based on
incoming commands. Only one par tition can be actively pro gramming or erasing at a time. Each
partit ion stays in its last r ead state (Read Array, Read Device ID, CFI Query or Read Status
Regi ster) until a new command changes it. The ne xt WS M state doe s not depend on the parti tion’s
output state.
Figure 33. Write St ate Machine—Next State Table (Sheet 1 of 6)
Read
Arra y (2) Word
Program (3,4)
Buffered
Program
(BP)
Erase
Setup (3,4)
Buffered
Enhanced
Factory Pgm
Setup (3, 4)
BE Confirm,
P/E
Resume,
ULB,
Confirm (8)
BP / Prg /
Erase
Suspend
Read
Status
Clear
Status
Register (5)
Read
ID/Query
Lock, Unlock ,
Lock-down,
C R setup (4)
(FFH) (10H/40H) (E8H) (20H) (80H) (D0H) (B0H) (70H) (50H) (90H, 98H) (60H)
Ready Program
Setup BP Setup Erase
Setup BEFP Setup Lock/CR
Setup
Read y
(Unlock
Block)
Setup
Busy
Setup
Busy Word
Program
Suspend
Suspend Word
Program
Busy
Setup
BP Load 1
BP Load 2
BP
Confirm BP Busy
BP Busy BP Suspend
BP
Suspend BP Busy
Setup Erase Busy
Busy Erase
Suspend
Suspend Erase
Suspend
Word
Program
Setup in
Erase
Suspend
BP Setup in
Erase
Suspend Erase Busy
Lock/CR
Setup in
Erase
Suspend
BP Sus p en d
Erase
BP Busy
Erase Busy
Erase Suspend Erase Suspend
Ready (Error)
Erase Busy
BP Suspend
Ready (Error)
Word
Program
Program B usy
Word Program Suspend
Wor d Progr am Busy
OTP
Ready (Lock Error)
Ready Ready
Ready (Lock Error)
OT P Bu sy
Current Chip
State (7)
Command Input to Chip and resulting Chip Next State
BP
BP Busy
Lock /C R Set up
BP Load 2
Ready (Error)Ready (Error)
Word Program Busy
BP Confirm if Data load into Program Buffer is complete; Else BP Load 2
Word Program Suspend
BP Load 1
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel S trata F lash® W i rel ess M em ory (L18) August 2005
Order Num ber: 251902, Re visio n: 010 79
Fig ur e 34. Write State M achine— Next State Table ( Sheet 2 of 6)
Setup
Busy
Word
Program
Sus p en d in
Erase
Suspend
Suspend
Word
Program
Busy in
Erase
Suspend
Setup
BP Load 1
BP Load 2
BP
Confirm
BP Busy in
Erase
Suspend
BP Busy BP Suspe nd
in Erase
Suspend
BP
Suspend
BP Busy in
Erase
Suspend
Erase
Suspend
(Unlock
Block)
Setup BEFP
Loading
Da ta (X =32 )
Erase Sus p en d (Er ror)
Erase Sus p en d (L ock Err or [Bot c h] )
Ready (Error) Ready (Error)
BP Susp en d in Er ase Sus p en d
Ready (Er ro r in Erase Sus p en d )
BP Busy in Er ase Sus p en d
BP Suspend in Erase Suspend
BP Busy in Erase Suspend
Word Program Busy in Erase Suspend
Word
Program in
Erase
Suspend
Word Progra m Bu sy in Era se Suspend
Word Program Suspend in Erase Suspend
Lock/CR Setup in Erase
Suspend Erase Suspend (Lock Error)
BP Confirm if Data load into Program Buff er is complete; Else BP Load 2
BP in Erase
Suspend
BP Load 2
Word Progr am Bu sy in Era se Sus p en d Busy
Word Program Suspend in Erase Suspend
BEFP Progr am and Ver ify Bus y (if Block Address given m atches address given on BEFP Setup comman d). Commands tr eated as data. (7)
BEFP
Busy
Buffered
Enhanced
Factory
Program
Mode
BP Load 1
Read
Array
(
2
)
Word
Program (3,4)
Buffered
Program
(BP)
Erase
Setup (3,4)
Buffered
Enhanced
Fa ctory P gm
Setup (3, 4)
BE Confir m,
P/E
Resume,
ULB,
Confirm (8)
BP / Prg /
Erase
Suspend
Read
Status
Clear
Status
Register (5)
Read
ID/Query
Lock, Unlock,
Lock-down,
CR setup (4)
(FFH) (10H/40H) (E8H) (20H) (80H) (D0H) (B0H) (70H) (50H) (90H, 98H) (60H)
Cu rr ent Chi p
State (7)
Com m a nd I nput to Chi p a nd r es ul t ing Chip Next State
Intel StrataFlash® Wireless Memory (L18)
August 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
80 Order Numb er: 251902, Re vi sion: 010
Figure 35. Write St ate Machine—Next State Table (Sheet 3 of 6)
Setup
Busy
Setup
Busy
Suspend
Setup
BP Load 1
BP Load 2
BP
Confirm
BP Bu sy
BP
Suspend
Setup
Busy
Suspend
Erase
Word
Program
OTP
Ready
Current Chip
State (7)
BP
Lock/CR Setup
OTP
Setup (4)
Lock
Block
Confirm (8)
Lock-Down
Block
Confi rm (8)
Writ e RCR
Confirm (8) Block Add ress
(?WA0) 9 Illegal Cmds or
BEFP Data (1)
(C0H) (01H) ( 2FH) (03H) (XXXXH) (all other codes)
OTP
Setup
Ready
(Lock
Error)
Ready
(Lock
Block)
Ready
(Lock Down
Blk)
Ready
(Set CR)
Ready
N/A
Ready
Ready (BP Load 2 BP Load 2
Ready
BP Confirm if
Data l oad into
Pr o gram Buffer i s
complete; ELSE
BP Load 2
Ready (Error)
(Proc eed if
unlocked or lock
error)
Ready (E r ror )
Ready
Ready
N/A
BP Confirm if Data load into Program Buffer is
compl ete; ELSE BP load 2
Ready (Error)
BP Busy
Erase Bu sy
Word P r ogram Susp end
BP Load 1
BP Load 2
OTP Bus y
Word Program Busy
Word Program Busy
WSM
Operation
Completes
Command Input to Chip and resultin
g
Chip Next State
N/A
Ready (Lock E r ror )
Ready
BP Susp en d
Ready (Err or)
Erase Su spend
N/A
N/A
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel S trata F lash® W i rel ess M em ory (L18) August 2005
Order Num ber: 251902, Re visio n: 010 81
Fig ur e 36. Write State M achine— Next State Table ( Sheet 4 of 6)
OTP
Setup (4)
Lock
Block
Confirm (8)
Lock-Down
Block
Confirm (8)
Writ e RCR
Confirm (8) Block Address
(?WA0) 9 Illegal Cmds or
BEFP Data (1)
(C0H) (01H) (2F H) (03H) (XXXXH) (all other codes)
WSM
Operati on
Completes
Command Input to Chip and resulting Chip Next State
Current Chip
State (7)
NA
Erase Suspend
N/A
Ready (BP Load 2 BP Load 2
Ready
BP Confirm if
Data load into
Program Buffer is
complete; Else
BP Load 2
Ready (Error)
(Proceed if
unlocked or lock
error)
Ready (Error)
Erase Suspend
Erase
Suspend
(Lock
Error)
Erase
Suspend
(Lock
Block)
Erase
Suspend
(Lock Down
Block)
Erase
Suspend
(Set CR)
Ready (BEFP
Loading Data) Ready (Error)
BEFP Program and Verify Busy (if Block Address
given matches address given on BEFP Setup
command). Commands treated as data. (7)
BP Load 1
Ready (Error)
BP Confirm if Data load into Program Buffer is
complete; Else BP Load 2
Ready (Error in Erase Suspend)
Word Program Suspend in Erase Suspend
BP Load 2
Ready
Word Program Busy in Erase Suspend Busy
Word Program Busy in Erase Suspend
BEFP Busy
Ready
Erase Suspend ( Lock Error) N/A
BP Busy in Erase Suspend
BP Suspend in Erase Su spend
N/A
Setup
Busy
Suspend
Setup
BP Load 1
BP Load 2
BP
Confirm
BP Busy
BP
Suspend
Setup
BEFP
Busy
Buffered
Enhanced
Factory
Program
Mode
Lock/CR Setup in Erase
Suspend
BP in Erase
Suspend
Word
Pr ogram in
Erase
Suspend
Intel StrataFlash® Wireless Memory (L18)
August 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
82 Order Numb er: 251902, Re vi sion: 010
Figure 37. Write St ate Machine—Next State Table (Sheet 5 of 6)
Read
Arra y
(
2
)
Word
Program
Setup (3 ,4) BP Setup Erase
Setup (3,4)
Buffered
Enhanced
Factory Pgm
Setup (3, 4)
BE Confirm,
P/E
Resume,
ULB Confirm
(8)
Program/
Erase
Suspend
Read
Status
Clear
Status
Register (5)
Read
ID/Query
Lock , Un l ock ,
Lock-down,
CR s etup (4)
(FFH) (10H /40 H) (E8H) (20H) (30H) (D0H) (B0H ) (70H) (50H ) (90H, 98H) (60H)
Status Read
Command Input to Chip and resulting Output Mux Next State
Output Next State Table
Status Read
Output mux
does not
change.
Status
Read
ID Read Status Read
Ready,
Er as e Suspend,
BP Suspend
Status Read
Lock/ C R Se tup,
Lock/ C R Se tup in
Er as e Susp
Output does n ot chan ge. Statu s Read
BEFP Setup,
BEFP Pgm & Verify
Busy,
Er as e Setup,
OTP Setup ,
BP: Setup, Load 1,
Load 2, Co nfir m,
Word Pgm Setup,
Wo rd Pg m S etup in
Er as e Susp,
BP Setup, Load1,
Load 2, Co nfir m in
Erase Suspend
Current chip state
OTP Busy
BP B usy,
Wo rd Pr og ra m
Busy,
Er as e Busy ,
BP Busy
BP Busy in Erase
Suspend
Wo rd Pg m
Suspend,
Word Pgm Busy in
Er as e Suspend,
Pgm Suspend In
Er as e Sus
p
end
Read Array
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel S trata F lash® W i rel ess M em ory (L18) August 2005
Order Num ber: 251902, Re visio n: 010 83
Notes:
1. "Illegal commands" include commands outside of the allowed command set (allowed commands: 40H
[pgm], 20H [erase], etc.)
2. If a "Read Array" is attempted from a busy partition, the result will be invalid data. The ID and Query
data are located at different locations in the address map.
3. 1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or
unexpected results will occur.
4. To protect memory contents against erroneous command sequences, there are specific instances in a
multi-cycle command sequence in which the second cycle will be ignored. For example, when the
device is program suspended and an erase setup command (0x20) is given followed by a confirm/
Fig ur e 38. Write State M achine— Next State Table ( Sheet 6 of 6)
OTP Busy
BP Busy,
Word Program
Busy,
Erase Busy,
BP Busy
BP Busy in Erase
Suspend
Wo rd Pg m
Suspend,
Wo rd Pg m Bus y in
Erase Suspend,
Pgm Suspend In
Erase Sus
p
end
BEFP Setup,
BEFP Pgm & Verify
Bus y,
Erase Setup,
OTP Setup,
BP: Setup, Load 1,
Load 2, Confirm,
Word Pgm Setup,
Word Pgm Setup in
Erase Susp,
BP Setup, Load1,
Load 2, Confir m in
Erase Suspend
Current chip state
Ready,
Erase Suspend,
BP Suspend
Lock/CR Setup,
Lock/CR Setup in
Erase Susp
OTP
Setup (4)
Lock
Block
Confirm (8)
Lock-Down
Block
Confirm (8)
Write CR
Confirm (8) Block Address
(?WA0) Illegal Cmds o r
BEFP Data (1)
(C0H ) (01H) (2FH) (03H ) (FFFFH) (all o ther codes)
WSM
Operation
Completes
Outp ut does
not change.
A
rray
Read Status Read
Array Read O ut put does not
change.
Output does not change.
Status
Read
Statu s Read
Statu s Read
Command Input t o Chip and re s ulti ng Output Mux Next Stat e
Output Next State Table
Intel StrataFlash® Wireless Memory (L18)
August 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
84 Order Numb er: 251902, Re vi sion: 010
resume command (0xD0), the second command will be ignored because it is unclear whether the user
intends to erase the block or resume the program operation.
5. The Clear Status command only clears the error bits in the status register if the device is not in the
following modes : WS M running (Pgm Busy, Erase Busy, Pgm Busy In Er ase S uspend, OTP Bus y, BEFP
modes).
6. BEFP writes are only allowed when the status register bit #0 = 0, or else the data is ignored.
7. The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which
output (Array, ID/CFI or Status) it was last pointed to on the last instruction to the "chip", but the next
state of the chip does not depend on where the partition's output mux is presently pointing to.
8. Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register) perform the
operation and then move to the Ready State.
9. WA0 refers to the block address latched during the first write cycle of the current operation.
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel S trata F lash® W i rel ess M em ory (L18) August 2005
Order Num ber: 251902, Re visio n: 010 85
Appendix B Flowcharts
Figure 39. Word Pro gram Fl owchart
Program
Suspend
Loop
Start
Write 0x40,
Word Address
Write Data,
Word Address
Read Status
Register
SR [7 ] =
Full Status
Check
(if desired )
Program
Complete
Suspend?
1
0
No
Yes
WORD PROGRAM PROCED URE
Repeat for subsequent Word Progr am operations.
Full Status Register check can be done after each program, or
aft er a sequence of program op era t io ns.
Write 0xFF after the las t operation to se t to th e Read Array
state.
Comments
Bus
Operation Command
Data = 0x40
Addr = Location to program
Write Program
Setup
Data = Data to program
Addr = Location to program
Write Data
Status register dataRead None
Check SR[7]
1 = W S M Re ad y
0 = WSM Busy
Idle None
(Setup)
(Confirm)
FULL STATUS CHECK PROCEDURE
Read Status
Register
Program
Successful
SR [3 ] =
SR [1 ] =
0
0
S R[4] =
0
1
1
1VPP Range
Error
Device
Protect E rro r
Program
Error
If an error is detected, clear the Status Register before
contin uing operations - only the Clear St aus Register
command clears the Status Register error bits.
Idle
Idle
Bus
Operation
None
None
Command
Check SR[3]:
1 = VPP Error
Check SR[4]:
1 = D ata Program Error
Comments
Idle None Check SR[1]:
1 = Block lock ed; operation aborted
Intel StrataFlash® Wireless Memory (L18)
August 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
86 Order Numb er: 251902, Re vi sion: 010
Figure 40. Prog ram Suspend/Resume Flowchart
Read Status
Register
SR.7 =
SR.2 =
Write FFh
Susp Pa rtition
Read Array
Data
Program
Completed
Done
Reading
Write FFh
Pgm'd Partition
Write D0h
Any Address
Program
Resumed Read Array
Data
0
No
0
Yes
1
1
PR OGR AM SU SPEND / RESUM E PROC ED U RE
Write Program
Resume Data = D0h
Addr = Suspe nd ed block (BA)
Bus
Operation Command Comments
Write Program
Suspend Da ta = B0h
Addr = Blo ck to susp end (BA)
Standby Check SR. 7
1 = WSM ready
0 = WSM busy
Standby Check SR. 2
1 = Program su spended
0 = Program completed
Write Read
Array
Data = FFh
Addr = Any a dd ress within the
suspended partition
Read Read array data from block other than
the on e being prog rammed
Read Status register data
Addr = Suspe nd ed block (BA)
PGM_SUS.WMF
Start
Write B0h
Any Address
Program Suspend
Read Stat us
Program Resume Read A rray
Read Array
Write 70h
Same Partition Write Read
Status Data = 70h
Addr = Same partition
If the suspended partition was placed in Read Array mode:
Write Read
Status
Return pa rtition t o S tatus mode:
Dat a = 70h
Addr = Same partition
Write 70h
Same Partition
Read Stat us
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel S trata F lash® W i rel ess M em ory (L18) August 2005
Order Num ber: 251902, Re visio n: 010 87
Figure 41. Buffer Program Flowchart
Buffer Program m ing Procedure
Start
Get Next
Target Address
Issue Buffer Prog. Cmd.
0xE8,
Word Address
Read Status Register
at W o rd Ad dress
Write Buffer
Available?
SR[7] =
1 = Ye s
Device
S up po rts B u ffer
Writes?
S et T ime o ut or
Loop Counter
Timeout
or Count
Expired?
W rite Co nfirm 0x D 0
and Word Address
(Note 5)
Yes
No
Buffer Program Data,
Start W ord Address
X = 0
0 = N o Y es
U se S ing le W o rd
Programming
A bo rt B uffer
Program?
No
X = N?
Write Buffer Data,
W ord Address
X = X + 1
Write to another
Block Address
B uffe r Pro g ram Aborte d
No
Yes
Yes
Write Word Count,
Word Address
Suspend
Program
Loop
Read Status R egister
(Note 7)
Is BP finished?
SR[7] =
F u ll Stat u s
Check if Desired
Program Complete
Suspend
Program ?
1=Yes
0=No Yes
No
Issu e Re ad
Status Register
Command
No
1. W ord count value on D[7:0] is loaded into the word count
reg ister. Coun t rang es for this d evice ar e N = 0x0 0 to 0x1F.
2. The device outputs the Status Register when read.
3. W rite Buffer contents will be programmed at the issued word
address.
4. Align the start address on a Write Buffer boundary for
maximum program ming perform ance (i.e., A[4:0] of the Start
W ord Address = 0x00).
5. The Buffered Programming Confirm com mand must be
issu ed to a n a d d res s in the sa me block, fo r ex a m p le, the
original Start W ord Address, or the last address used during the
loop that loaded the buffer data.
6. The Status Register indicates an im proper command
sequence if the Buffer Program command is aborted; use the
Clea r Sta tus Re gis ter com mand to clea r error bits.
7. The Status Register can be read from any addresses within
the pr ogra m m ing partitio n.
Full status check can be done after all erase and write
sequenc es complete. Write 0 xFF after the last o peration to
place the partition in the Read Array state.
Bus
Operation
Idle
Read
Command
None
None
Write Buffe r Pr og .
Setup
Read None
Idle None
Comments
C heck SR [7]:
1 = WSM Ready
0 = WSM Busy
Status re gister Da ta
Ad d r = No te 7
Da ta = 0 xE8
Addr = W ord Address
SR [7] = Valid
Addr = Word Address
Ch e ck SR[7]:
1 = Write Buffer available
0 = No W rite Buffer available
Write
(Notes 5, 6) B uffe r Pr og .
Conf. Data = 0xD0
Addr = O riginal Word Address
Write
(Notes 1, 2) None Data = N-1 = W ord Count
N = 0 corresponds to count = 1
Addr = W ord Address
Write
(Notes 3, 4) None Data = Write Bu ffer D a ta
Addr = Start W ord Address
Write
(No te 3) None Da ta = Write Bu ffer D a ta
Addr = W ord Address
Other partitions of the device can be read by addressing those partitions
and driving OE# low. (Any write commands are not allowed during this
period.)
0xFF commands can be issued to read from
any blocks in other partitions
Intel StrataFlash® Wireless Memory (L18)
August 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
88 Order Numb er: 251902, Re vi sion: 010
Figure 42. Buffere d EF P Flowc hart
Write Data @ 1ST
Word Address
Last
Data?
Write 0 xFFFF,
A ddress Not wi thin
Current Block
Program
Done?
Read Status Reg.
Y
No (SR[7]=0)
Full Sta tus Check
Procedure
Program
Complete
Read Status Reg.
BEFP
Exited?
Yes (SR[7]=1)
Start
Write 0x80 @
1ST Word Address
VPP applied,
Block unlocked
Write 0xD0 @
1STWordAddress
BEFP Setup
Done?
Read Status Reg.
Exit
N
Progr am & Verify Phase Exit PhaseSetup Phase
BUFFERED ENHANCED FACTORY PROGRAMMING (Buffered-EFP) PROCEDURE
X = 32?
In itiali ze Coun t:
X = 0
Increment Count:
X = X+1
Y
NOTES:
1. First-word address to be programmed within the target block must be aligned on a write-buffer boundary.
2. Write-buffer contents are programmed sequentially to the flash array starting at the first word address;WSM internally increments addressing.
N
Check VPP, Lock
Errors (SR[3,1])
Yes (SR[7]=0)
Comments
Bus
State Operation
BEFP setup delay
Data Stream
Ready?
Read Status Reg.
No (SR[0]=1)
Repeat for subsequent blocks;
After BEFP exit, a full Status Register check can
determine if any program error occurred;
See full Status Register check procedure in the
Word Program flowchart.
Write 0x FF t o enter Read Array state.
Check SR[7]:
0 = Exit Not Completed
1 = Exit Completed
Check Exit
Status
Read Status
Register Data = Status Reg. Data
Address = 1ST Word Addr
BEFP Exit
Standby
If SR[7] is set, check:
SR[3] set = VPP Error
SR[1] set = Locked Block
Error
Condition
Check
Standby
Check SR[7]:
0 = BEFP Ready
1 = BEFP Not Ready
BEFP
Setup
Done?
Standby
Data = S tatu s Reg. Data
Address = 1ST
Word Addr
Status
Register
Read
Data = 0xD0 @
1ST Word
Address
BEFP
Confirm
Write
Data = 0x80 @ 1ST Word
Address
BEFP
Setup
Write
(Note 1)
VPPH
applied to VPP
Unlock
Block
Write
BEFP Setup
Bus
State CommentsOperation
No (SR[0]=1)
Yes (SR[0]=0)
No (SR[7]=1)
Yes (SR[0]=0)
BEFP Program & Verify
CommentsBus State Operation
Write
(Note 2) Load
Buffer
Standby Increment
Count
Standby Initialize
Count Data = Data to Program
Address = 1
ST Wo r d Addr.
X = X+1
X = 0
Standby Buffer
Full?
X = 32?
Yes = Read SR[0]
No = Load Next Data Word
Read
Standby
Status
Register
Data Stream
Ready?
Data = Status Register Data
Address = 1
ST Wo r d Addr.
Check SR[0]:
0 = Ready for Data
1 = Not Ready for Data
Read
Standby
Standby
Write
Status
Register
Program
Done?
Last
Data?
Exit Prog &
Verify Phase
Data = Status Reg. data
Address = 1
ST Wo r d Addr.
Check SR[0]:
0 = Program Done
1 = Program in Progress
No = Fill buffer again
Yes = Exit
Data = 0xFFFF @ address not in
current block
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel S trata F lash® W i rel ess M em ory (L18) August 2005
Order Num ber: 251902, Re visio n: 010 89
Figure 43. Block Er ase Flowcha rt
Start
FULL ERASE STATUS CHECK PROCEDURE
Repeat for sub sequent bloc k erasures.
Full Status register check can be done after each block erase
or after a sequence of block erasures.
Write 0xFF after the last operation to enter read array mode.
Only the Clea r Status Register co mmand clears SR[1, 3, 4, 5].
If an error is detected, clear the Status register before
attempting an erase retry or other error recovery.
No
Suspend
Erase
1
0
0
0
1
1,1
1
1
0Yes
Suspend
Erase
Loop
0
Write 0x20,
Block Address
Write 0xD0,
Block Address
Read Status
Register
SR [7 ] =
Full Eras e
Status Check
(if desired )
Block Erase
Complete
Read Status
Register
Block Erase
Successful
SR [1 ] = Block Locked
Error
BLOCK E RASE PROCEDURE
Bus
Operation Command Comments
Write Block
Erase
Setup
Data = 0x20
Addr = Block to be erased (BA)
Write Erase
Confirm Data = 0xD0
Addr = Block to be erased (BA)
Read None Status Register data.
Idle None Check SR[7]:
1 = W S M ready
0 = W S M bus y
Bus
Operation Command Comments
SR [3 ] = VPP Range
Error
SR [ 4,5 ] = Command
Sequence Error
SR [5 ] = Bloc k E r as e
Error
Idle None Check SR[3]:
1 = VPP Range Error
Idle None Check SR[4,5]:
Both 1 = C om m and Se qu en ce Error
Idle None Check SR[5]:
1 = Block Erase Err or
Idle None Check SR[1]:
1 = Attempted erase of locked block;
erase aborted .
(Block Erase)
(Erase Confirm)
Intel StrataFlash® Wireless Memory (L18)
August 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
90 Order Numb er: 251902, Re vi sion: 010
Figure 44. Erase Suspend/Resume Flowchart
Erase
Completed
Read Array
Data
0
0
No
Read
1
Program
Program
Loop
Read Array
Data
1
Start
Read Status
Register
S R[7] =
S R[6] =
Erase
Resumed
Read or
Program?
Done
Write
Write
Idle
Idle
Write
Erase
Suspend
Read Array
or Program
None
None
Program
Resume
Data = 0xB0
Addr = Same partition address as
above
Data = 0xFF or 0x40
Addr = Any address within the
suspended partition
Check S R[7]:
1 = WSM ready
0 = WSM busy
Check S R[6]:
1 = Erase suspended
0 = Erase complet ed
Data = 0xD0
Addr = Any address
Bus
Operation Command Comments
Read None Status Register data.
Addr = Same partition
Read or
Write None Read array or program data from/to
block other than the one being erased
ERASE SUSP END / RE SUME PROCEDURE
If the suspended partition was placed in
Read Array mode or a Program Loop:
Write 0xB0,
Any Address
(Erase Suspend)
Write 0x70,
Same Partition
(Read S t at us)
Write 0xD0,
Any Address
(Erase Resume)
Write 0x70,
Same Partition
(Read Status)
Write 0xFF,
Erased Partition
(Rea d Arra y)
Write Read
Status Data = 0x70
Addr = Any partition address
Write Read
Status
Register
Return partition to Status mode:
Data = 0x70
Addr = Same partition
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel S trata F lash® W i rel ess M em ory (L18) August 2005
Order Num ber: 251902, Re visio n: 010 91
Figure 45. Block Lock O pera tions Flowchart
No
Start
W ri te 0x60,
Block Address
Write 0x90
Read Block
Lock Status
Locking
Change?
Lock Change
Complete
Write either
0x01/0xD0/0x2F,
Block Address
Write 0xFF
Partition Address
Yes
Write
Write
Write
(Optional)
Read
(Optional)
Idle
Write
Lock
Setup
Lock,
Unlock, or
Lock-Down
Confirm
Read
Device ID
Block Lock
Status
None
Read
Array
Data = 0x60
Addr = Block to lock/unlock/lo ck-down
Data = 0x01 (Block Lock)
0x D0 ( Block Un loc k)
0x2F ( Lock- Dow n Bl ock)
Addr = Block to lock/unlock/lo ck-down
Data = 0x90
Addr = Block address + offset 2
Block Lock status data
Addr = Block address + offset 2
Confirm locking change on D[1,0].
Data = 0xFF
Addr = Block address
Bus
Operation Command Comments
LOCKING OPERATIONS P ROCEDURE
(Lock Confirm)
(R ead Device ID)
(Read Array)
Optional
(L ock S etup)
Intel StrataFlash® Wireless Memory (L18)
August 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
92 Order Numb er: 251902, Re vi sion: 010
Figure 46. Protec tion Registe r Programm i ng Flo wcha rt
FULL STATUS CHECK PROC EDURE
Program Protection Register operation addresses must be
within the Protection Register address space. Addresses
outside this space will return an error.
Rep ea t fo r sub sequent pro gramming ope ratio ns .
Full Status Register check can be done after each program, or
after a se quence of pro gram operations .
Write 0xFF a fter the last op erati on to set Read Array state.
Only the Clear Stau s R e gis ter c o mman d cl e ars SR[1, 3, 4] .
If an error is detected, clear the Status register before
attempting a program retry or other error recovery.
1
0
1
1
1
PROTECTION REGISTER PROGRAMMING PROCEDURE
Start
Write 0xC0,
PR Address
Wr ite PR
Address & Dat a
Read Status
Register
SR[7] =
Full Status
Check
(if des ired)
Program
Complete
Read Status
Register Data
Program
Successful
SR[3] =
SR[4] =
SR[1] =
VPP Range Error
Prog ram Error
Register Locked;
Program Aborted
Idle
Idle
Bus
Operation
None
None
Command
Check SR[3]:
1 =VPP Range E rro r
Check SR[4]:
1 =Progr ammin g Error
Comments
Write
Write
Idle
Program
PR Setu p
Protection
Program
None
Data = 0xC0
Addr = First Location to Program
Data = Data to Program
Ad dr = Locat i on to Pro gram
Check SR[7]:
1 = WSM Ready
0 = WSM Busy
Bus
Operation Command Comments
Read None Status Register Data.
Idle None Check SR[1]:
1 =Block lo cked; operation abort ed
(Program Setup)
(Confirm Data)
0
0
0
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel S trata F lash® W i rel ess M em ory (L18) August 2005
Order Num ber: 251902, Re visio n: 010 93
Appendix C Common Flash Interface
The Common Fla sh Interface (CFI) is part of an ov erall specificat ion f or multiple command-set
and control-interface descriptions. This appendix describes the da tabas e structur e containing the
data re turned by a read operati on after issuing the CFI Query command (see Sectio n 9. 2, “Device
Comma nds” on page 47). System softwar e can parse this database structure to ob tain information
about the fl as h dev ice, such as block size, density, bus width, and electrical specifications. The
system softw a re will then know which command se t(s) to use to properly perform flas h writes,
block erases , reads and otherwis e control the flash de vice.
C.1 Query Structure Output
Th e Que ry dat a ba se all ows syste m soft wa re to ob ta in information for controlling the flash devic e .
This sect ion describes the device’s CFI-compliant interface th at allows access to Query data.
Quer y d ata a re p res en ted on the l owe st-o rd er data out put s (D Q7-0) o nly. The n umerical o ff set v alue
is the address rela tive to the maximum bus width suppo rted by the de vice. On this family of
de vices, the Query tabl e de vice s ta rting a ddress is a 10h, which is a word address fo r x16 devices.
For a word- wide ( x16) device, the first two Query-structure bytes, AS CII “Q” and “R,” appear on
the low byte a t word addresses 10h and 11h. This CFI-complia nt dev i c e outputs 0 0h data on upper
bytes. The device outputs A SCI I “Q” in the low byte (DQ7-0) and 00h in the h igh byte (DQ15-8).
At Query addresses contai ning two or more bytes of information, the least significan t data byte is
presented at the lo wer address, and the m os t signifi cant data byte is presented at the higher address.
In all of the following tables, addresses and data are repres e nted in hexadec imal nota tion, so the
“h ” suff i x has be e n droppe d. In addition, since the upper byte of word-wide devices is always
“00h,” the leading “00” has been dropped from the tab le notation and only the low er byte value is
shown. An y x16 devi c e outputs can be a ssumed to ha ve 00h on the uppe r byte in this mode.
Table 19. Summary of Query Structure Output as a Function of Device and Mode
Device Hex
Offset Hex
Code ASCII
Value
Device Addresses
00010: 51 “Q”
00011: 52 “R”
00012: 59 “Y”
Intel StrataFlash® Wireless Memory (L18)
August 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
94 Order Numb er: 251902, Re vi sion: 010
Table 20. Examp le of Quer y Str u cture Output of x16- Devi ces
C.2 Query Structure Overview
The Query command causes the f las h component to display the Common Flash Interface (CFI)
Query stru ctur e or “database.” The structure sub-sections a nd address locations are summarized in
Table 21.
Table 21. Query Structure
Notes:
1. Refer to the Query S t ructure O utput s ection and of fse t 28h for the detai led definitio n of o ffs et address as
a function of device bus width and mode.
2. BA = Block Address beginning location (i.e., 08000h i s block 1’s beginning location when the bl ock size
is 16-Kword).
3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.
Word Addressin
g
: B
y
te Addressin
g
:
Offset Hex Code Value Offset Hex Code Value
A
X
–A
0 D15
–
D0
A
X
–A
0 D7
–
D0
00010h 0051 "Q" 00010h 51 "Q"
00011h 0052 "R" 00011h 52 "R"
00012h 0059 "Y" 00012h 59 "Y"
00013h P_IDLO PrVendor 00013h P_IDLO PrVendo
r
00014h P_IDHI ID # 00014h P_IDLO ID #
00015h PLO PrVendor 00015h P_IDHI ID #
00016h PHI TblAd
r
00016h ... ...
00017h
A
_IDLO AltVendor 00017h
00018h
A
_IDHI ID # 00018h
... ... ... ...
Offset Sub-Section Name Descri
p
tion(1)
00001-Fh Reserved Reserved for vendor-specific information
00010h CFI query identification string Command set ID and vendor data offset
0001Bh System interface information Device timing & voltage information
00027h Device geometry defin ition Flash device layout
P(3) Primar
y
Intel-specific Extended Quer
y
Table Vendor-defined additional information specific
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel S trata F lash® W i rel ess M em ory (L18) August 2005
Order Num ber: 251902, Re visio n: 010 95
C.3 CFI Query Identification String
The Identification String provides verification that the comp onent supports the Common Flash
Int erf ace specification. It also indicates the specification ve rsion and supported vendor-specified
comman d se t(s).
Table 22. CF I Identif ication
Tabl e 23. System In terface I n fo rmatio n
Offset Length Description Add. Hex
Code Value
10h 3 Query-unique ASC II string “QRY“ 10: --51 "Q"
11: --52 "R"
12: --59 "Y"
13h 2 Primary vendor command set and control interface ID code. 13: --01
16-bit ID code for vendor-s
p
ecified al
g
orithms 14: --00
15h 2 Extended Query Table primary algorithm address 15: --0A
16: --01
17h 2 Alternate vendor command set and control interface ID code. 17: --00
0000h means no second vendor-specified algorithm exists 18: --00
19h 2 Secondary algorithm Extended Query Table address. 19: --00
0000h means none exists 1A: --00
Offset Length Description Add. Hex
Code Value
1Bh 1 1B: --17 1.7V
1Ch 1 1C: --20 2.0V
1Dh 1 1D: --85 8.5V
1Eh 1 1E: --95 9.5V
1Fh 1 “n” such that t
yp
ical sin
g
le word
p
ro
g
ram time-out = 2n
µ
-sec 1F: --08 256µs
20h 1 “n” such that t
yp
ical max. buffer write time-out = 2n
µ
-sec 20: --09 512µs
21h 1 “n” such that t
yp
ical block erase time-out = 2n m-sec 21: --0A 1s
22h 1 “n” such that t
yp
ical full chi
p
erase time-out = 2n m-sec 22: --00 NA
23h 1 “n” such that maximum word
p
ro
g
ram time-out = 2n times t
yp
ical 23: --01 512µs
24h 1 “n” such that maximum buffer write time-out = 2n times t
yp
ical 24: --01 1024µs
25h 1 “n” such that maximum block erase time-out = 2n times t
yp
ical 25: --02 4s
26h 1 “n” such that maximum chi
p
erase time-out = 2n times t
yp
ical 26: --00 NA
VPP [programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
VPP [programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
VCC logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VCC logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
Intel StrataFlash® Wireless Memory (L18)
August 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
96 Order Numb er: 251902, Re vi sion: 010
C.4 Device Geo metry D efinition
Table 24. Device Geometry De finition
Offset Len
g
th Description Code
27h 1“n” such that device size = 2nin number of bytes 27: See table below
76543210
28h 2 — — — — x64 x32 x16 x8 28: --01 x16
15 14 13 12 11 10 9 8
————————29:--00
2Ah 2“n” such that maximum number of bytes in write buffer = 2n2A: --06 64
2B: --00
2Ch 1 2C:
2Dh 4 Erase Block Region 1 Information 2D:
bits 0–15 = y, y+1 = number of identical-size erase blocks 2E:
bits 16–31 = z, region erase block(s) size are z x 256 bytes 2F:
30:
31h 4 Erase Block Region 2 Information 31:
bits 0–15 = y, y+1 = number of identical-size erase blocks 32:
bits 16–31 = z, region erase block(s) size are z x 256 bytes 33:
34:
35h 4 Reserved for future eras e block region inf ormation 35:
36:
37:
38:
See table belo w
See table belo w
See table belo w
See table belo w
Flash device interface code assignment:
"n" such that n+1 specifies the bit field that represents the flash
device width capabilities as described in the table:
Number of erase block regions (x) within device:
1. x = 0 means no erase blocking; the device erases in bulk
2. x specifies the number of device regions with one or
more contiguous same-size erase blocks.
3. Symmetrically blocked partitions have one blocking region
Address 64 Mbit
–B –T –B –T –B –T
27: --17 --17 --18 --18 --19 --19
28: --01 --01 --01 --01 --01 --01
29: --00 --00 --00 --00 --00 --00
2A: --06 --06 --06 --06 --06 --06
2B: --00 --00 --00 --00 --00 --00
2C: --02 --02 --02 --02 --02 --02
2D: --03 --3E --03 --7E --03 --FE
2E: --00 --00 --00 --00 --00 --00
2F: --80 --00 --80 --00 --80 --00
30: --00 --02 --00 --02 --00 --02
31: --3E --03 --7E --03 --FE --03
32: --00 --00 --00 --00 --00 --00
33: --00 --80 --00 --80 --00 --80
34: --02 --00 --02 --00 --02 --00
35: --00 --00 --00 --00 --00 --00
36: --00 --00 --00 --00 --00 --00
37: --00 --00 --00 --00 --00 --00
38: --00 --00 --00 --00 --00 --00
128 Mbit 256 Mbit
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel S trata F lash® W i rel ess M em ory (L18) August 2005
Order Num ber: 251902, Re visio n: 010 97
C.5 Intel-Specific Extended Query Table
Table 25. Prima ry Vendor-Sp ecific Ex tend ed Que ry
Offset(1) Len
g
th Description Hex
P = 10Ah (Optional flash features and commands)
A
dd. Code
V
alue
(P+0)h 3 Primary extended query table 10A --50 "P"
(P+1)h Unique ASCII string “PRI“ 10B: --52 "R"
(P+2)h 10C: --49 "I"
(P+3)h 1 Major version number, ASCII 10D: --31 "1"
(P+4)h 1 Minor version number, ASCII 10E: --33 "3"
(P+5)h 4 Optional feature and command support (1=yes, 0=no) 10F: --E6
(P+6)h bits 10–31 are reserved; undefined bits are “0.” If bit 31 is 110: --03
(P+7)h “1” then another 31 bit field of Optional features follows at 111: --00
(P+8)h the end of the bit–30 field. 112: --00
bit 0 Chip erase supported bit 0 = 0 No
bit 1 Suspend erase supported bit 1 = 1 Yes
bit 2 S uspend program supported bit 2 = 1 Yes
bit 3 Legacy lock/unlock supported bit 3 = 0 No
bit 4 Queued erase supported bit 4 = 0 No
bit 5 Instant individual block locking supported bit 5 = 1 Yes
bit 6 Protection bits supported bit 6 = 1 Yes
bit 7 Pagemode read supported bit 7 = 1 Yes
bit 8 S ynchronous read supported bit 8 = 1 Yes
bit 9 Simultaneous operations supported bit 9 = 1 Yes
(P+9)h 1 113: --01
bit 0 Pro
g
ram supported after erase suspend bit 0 = 1 Yes
(P+A)h 2 Block status registe r mask 114: --03
(P+B)h bits 2–15 are Reserved; undefined bits are “0” 115: --00
bit 0 B lock Lock-Bit Status register active bit 0 = 1 Yes
bit 1 Block Lock-Down Bit Status active bit 1 = 1 Yes
(P+C)h 1 116: --18 1.8V
(P+D)h 1 117: --90 9.0V
Supported functions after suspend: read Array, Status, Query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0”
VCC logic supply highest performance program/erase voltage
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
VPP optimum program/erase supply voltage
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
Intel StrataFlash® Wireless Memory (L18)
August 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
98 Order Numb er: 251902, Re vi sion: 010
Table 26. P rot ec tion Re giste r Inform at ion
Table 27. Burst Read In formati on
Offset(1) Len
g
th Description Hex
P = 10Ah (Optional flash features and commands)
A
dd. Code
V
alue
(P+E)h 1 118: --02 2
(P+F)h 4 Protection Field 1: Protection Description 119: --80 80h
(P+10)h This field describes user-available One Time Programmable 11A: --00 00h
(P+11)h
(
OTP
)
Protection re
g
ister b
y
tes. Some are pre-pro
g
rammed 11B: --03 8 byte
(P+12)h 11C: --03 8 byte
(P+13)h 10 Protection Field 2: Protection Description 11D: --89 89h
(P+14)h 11E: --00 00h
(P+15)h 11F: --00 00h
(P+16)h 120: --00 00h
(P+17)h 121: --00 0
(P+18)h bits 40–47 = “n” ∴n = factory pgm 'd groups (high byte) 122: --00 0
(P+19)h 123: --00 0
(P+1A)h 124: --10 16
(P+1B)h 125: --00 0
(P+1C)h 126: --04 16
bits 48–55 = “n” \ 2n = factory programmable bytes/group
bits 56–63 = “n” ∴ n = user pgm'd groups (low byte)
bits 64–71 = “n” ∴n = user
pg
m'd
g
rou
p
s
(
hi
g
h b
y
te
)
bits 72–79 = “n” ∴ 2n = user programmable bytes/group
with device-unique serial numbers. Others are user
programmabl e. Bits 0–15 point to the Protecti on register Lock
byte, the section’s first byte. The following bytes are factory
pre-programmed and user-programmable.
bits 0–7 = Lock/bytes Jedec-plane physica l low address
bits 8–15 = Lock/bytes Jedec-plane physical high address
bits 16–23 = “n” such that 2n = factory pre-programmed bytes
bits 24–31 = “n” such that 2n = user programmable bytes
Bits 0–31 point to the Protection register physical Lock-word
address in the Jedec-plane.
Following bytes are factory or user-programmable.
bits 32–39 = “n” ∴ n = factory pgm'd groups (low byte)
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection fields are available
Offset(1) Len
g
th Description Hex
P = 10Ah (Optional flash features and commands)
A
dd. Code
V
alue
(P+1D)h 1 127: --03 8 byte
(P+1E)h 1 128: --04 4
(P+1F)h 1 129: --01 4
(P+20)h 1 Synchronous mode read capability configuration 2 12A: --02 8
(P+21)h 1 Synchronous mode read capability configuration 3 12B: --03 16
(P+22)h 1 Synchronous mode read capability configuration 4 12C: --07 Cont
Page Mode Read capability
bits 0–7 = “n” such that 2n HEX value represents the number of
read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
read
p
a
g
e buffer.
Number of synchronous mode read configuration fields that
follow. 00h indicates no burst capability.
Synchronous mode read capability configuration 1
Bits 3–7 = Reserved
bits 0–2 “n” such that 2n+1 HEX value represents the
maximum number of continuous synchronous reads when
the device is configured for its maximum word width. A value
of 07h indicates that the device is capable of continuous
linear bursts that will output data until the internal burst
counter reaches the end of the device’s burstable address
space. This field’s 3-bit value can be written directly to the
Read Configuration Register bits 0–2 if the device is
configured for its maximum word width. See offset 28h for
word width to determine the burst data out
p
ut widt h.
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel S trata F lash® W i rel ess M em ory (L18) August 2005
Order Num ber: 251902, Re visio n: 010 99
Table 28. Part ition and Eras e-b lock Regi on Inform at io n
Offset
(1) See table below
P= 10Ah Description
A
ddress
Bottom To
p
(
O
p
tional flash features and commands
)
Len Bot Top
(P+23)h (P+23)h 1 12D: 12D:Number of device hardware-partition regions within the device.
x = 0: a single hardware partition device (no fields follow).
x specifies the number of device partition regions containing
one or more contiguous erase block regions.
Intel StrataFlash® Wireless Memory (L18)
August 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
100 Order Num ber: 251902, Revis i on: 010
Table 29. P artition Region 1 Informati on
Offset
(1) See table below
P = 10Ah Descri
p
tion
A
ddress
Bottom To
p
(
O
p
tional flash fe atures and comma nds
)
Len Bot Top
(P+24)h (P+24)h Number of identical partitions within the partition region 2 12E: 12E:
(P+25)h (P+25)h 12F: 12F:
(P+26)h (P+26)h 1 130: 130:
(P+27)h (P+27)h 1 131: 131:
(P+28)h (P+28)h 1 132: 132:
(P+29)h (P+29)h 1 133: 133:
(P+2A)h (P+2A)h Partition Region 1 Erase Block Type 1 Information 4 134: 134:
(P+2B)h (P+2B)h bits 0–15 = y, y+1 = numbe r of iden ti cal -s iz e erase blocks 135: 135 :
(P+2C)h (P+2C)h bits 16– 31 = z, r egi on erase block(s) size are z x 256 bytes 136: 136:
(P+2D)h (P+2D)h 137: 137:
(P+2E)h (P+2E)h Partition 1 (Erase Block Type 1) 2 138: 138:
(P+2F)h (P+2F)h Minimum block erase cycles x 1000 139: 139:
(P+30)h (P+30)h 1 13A: 13A:
(P+31)h (P+31)h 1 13B: 13B:
(P+32)h Partition Region 1 Erase Block Type 2 Information 4 13C:
(P+33)h bits 0–15 = y, y+1 = numbe r of identical-size erase blocks 13D:
(P+34)h bits 16–31 = z, region erase bl ock(s) size are z x 256 byte s 13 E:
(P+35)h (bottom parameter device only) 13F:
(P+36)h Partition 1 (Erase block Type 2) 2 140:
(P+37)h Minimum block erase cycles x 1000 141:
(P+38)h 1 142:
(P+39)h 1 143:
Partition 1 (e rase block Typ e 1) bi ts per cel l; internal ECC
bits 0–3 = bits per cel l in erase r egion
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = rese rve fo r fu tu re us e
Partition 1 (erase block Type 1) page mod e and synchronous
mode capab ilities defined in Table 10.
bit 0 = page-m ode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reser ved for futur e use
Partition 1 (Erase block Type 2) bits per cell
bits 0–3 = bits per cel l in erase r egion
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = rese rve fo r fu tu re us e
Partition 1 (Er ase blo ck Type 2) pagemod e and synchronous
mode capab ilities defined in Table 10
bit 0 = page-m ode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reser ved for futur e use
Number of program or erase operations allowed i n a partition
bits 0–3 = numbe r of simultan eous Progr am ope ra ti ons
bits 4–7 = numbe r of simultan eous Erase oper ations
Simultaneous program or erase operations allowed in ot her
partitions while a partition in this region is in Program mode
bits 0–3 = numbe r of simultan eous Progr am ope ra ti ons
bits 4–7 = numbe r of simultan eous Erase oper ations
Simultaneous program or erase operations allowed in ot her
part i t ions whi le a par titio n in th i s r e gion i s in Er a se m ode
bits 0–3 = numbe r of simultan eous Progr am ope ra ti ons
bits 4–7 = numbe r of simultan eous Erase oper ations
Types of er ase block regions in this Partition Regio n.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel S trata F lash® W i rel ess M em ory (L18) August 2005
Order Num ber: 251902, Re visio n: 010 101
Table 30. Part ition Region 2 Informa tion
Offset(1) See table below
P = 10Ah Description
A
ddress
Bottom Top
(
Optional flash features and commands
)
Len Bot Top
(P+3A)h (P+32)h Number of identical partitions within the partition region 2 144: 13C:
(P+3B)h (P+33)h 145: 13D:
(P+3C)h (P+34)h 1 146: 13E:
(P+3D)h (P+35)h 1 147: 13F:
(P+3E)h (P+36)h 1 148: 140:
(P+3F)h (P+37)h 1 149: 141:
(P+40)h (P+38)h Partition Region 2 Erase Block Type 1 Information 4 14A: 142:
(P+41)h (P+39)h bi ts 0–15 = y, y+1 = number of identical-s ize erase blocks 14B: 143:
(P+42)h (P+3A)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 14C: 144:
(P+43)h (P+3B)h 14D: 145:
(P+44)h (P+3C)h Partition 2
(
Erase block T
y
pe 1
)
2 14E: 146:
(P+45)h (P+3D)h Minimum block erase cycles x 1000 14F: 147:
(P+46)h (P+3E)h 1 150: 148:
(P+47)h (P+3F)h 1 151: 149:
(P+40)h Partition Region 2 Erase Block Type 2 Information 4 14A:
(P+41)h bits 0–15 = y, y+1 = num ber of identical-size erase blocks 14B:
(P+42)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 14C:
(P+43)h 14D:
(P+44)h Partition 2
(
Erase block T
y
pe 2
)
2 14E:
(P+45)h Minimum block erase cycles x 1000 14F:
(P+46)h 1 150:
(P+47)h 1 151:
Partition 2 (Erase block Type 1) bits per cell
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
Partition 2 (erase block Type 1) pagemode and synchronous
mode capabilities as defined in Table 10.
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
Partition 2 (Erase block Type 2) bits per cell
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
Partition 2 (erase block Type 2) pagemode and synchronous
mode capabilities as defined in Table 10.
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in P rogram mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-s ize
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
Intel StrataFlash® Wireless Memory (L18)
August 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
102 Order Num ber: 251902, Revis i on: 010
Table 31. P artition and Erase Block Region Informat i on
Address 64 Mbit
–B –T –B –T –B –T
12D: --02 --02 --02 --02 --02 --02
12E: --01 --07 --01 --0F --01 --0F
12F: --00 --00 --00 --00 --00 --00
130: --11 --11 --11 --11 --11 --11
131: --00 --00 --00 --00 --00 --00
132: --00 --00 --00 --00 --00 --00
133: --02 --01 --02 --01 --02 --01
134: --03 --07 --03 --07 --03 --0F
135: --00 --00 --00 --00 --00 --00
136: --80 --00 --80 --00 --80 --00
137: --00 --02 --00 --02 --00 --02
138: --64 --64 --64 --64 --64 --64
139: --00 --00 --00 --00 --00 --00
13A: --02 --02 --02 --02 --02 --02
13B: --03 --03 --03 --03 --03 --03
13C: --06 --01 --06 --01 --0E --01
13D: --00 --00 --00 --00 --00 --00
13E: --00 --11 --00 --11 --00 --11
13F: --02 --00 --02 --00 --02 --00
140: --64 --00 --64 --00 --64 --00
141: --00 --02 --00 --02 --00 --02
142: --02 --06 --02 --06 --02 --0E
143: --03 --00 --03 --00 --03 --00
144: --07 --00 --0F --00 --0F --00
145: --00 --02 --00 --02 --00 --02
146: --11 --64 --11 --64 --11 --64
147: --00 --00 --00 --00 --00 --00
148: --00 --02 --00 --02 --00 --02
149: --01 --03 --01 --03 --01 --03
14A: --07 --03 --07 --03 --0F --03
14B: --00 --00 --00 --00 --00 --00
14C: --00 --80 --00 --80 --00 --80
14D: --02 --00 --02 --00 --02 --00
14E: --64 --64 --64 --64 --64 --64
14F: --00 --00 --00 --00 --00 --00
150: --02 --02 --02 --02 --02 --02
151: --03 --03 --03 --03 --03 --03
128 Mb it 256 M bit
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel S trata F lash® W i rel ess M em ory (L18) August 2005
Order Num ber: 251902, Re visio n: 010 103
Appendix D Additional Information
Order/Document
Number Document/Tool
251903 Intel StrataFlash® Wireless Memory (L30) Datasheet
290701 Intel® Wireless Flash Memory (W18) Datasheet
290702 Intel® Wireless Flash Memory (W30) Datasheet
290737 Intel StrataFlash® Synchronous Memory (K3/K18) Datasheet
251908 Migration Guide for 1.8 Volt Intel® Wireless Flash Memory (W18/W30) to 1.8 Volt Intel
StrataFlash® Wireless Memory (L18/L30), Application Note 753
251909 Migration Guide for 3 V olt Synchronous Intel StrataFlash® Memory (K3/K18) to 1.8 Volt
Intel StrataFlash® Wireless Memory (L18/L30), Application Note 754
298161 Intel® Flash Memory Chip Scale Package User’s Guide
297833 Intel® Flash Data Integrator (FDI) User’s Guide
298136 Intel® Persistent Storage Manager User Guide
Notes:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel docum entat ion. International
customers should contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and
tools.
3. For the most current information on Intel StrataFlash® memory, visit our website at http://
developer.intel.com/design/flash/isf.
Intel StrataFlash® Wireless Memory (L18)
August 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
104 Order Num ber: 251902, Revis i on: 010
Appendix E Ordering Information
E.1 Ordering Information for VF BGA Package
Figure 47. Ordering I nfor ma tion for L18 in VF BGA
F 6 4 1 8 T 88E 2G 0 L 5
Product Line Designator
for all Intel® Flash prod ucts
Pack ag e D esignator
Expanded Temperature
(-25 C to +85 C)
G E = leaded , 0.75 m m V F BG A
P H = le ad -free, 0.75 m m V F BGA Param eter L ocation
T = Top Parameter Blocking
B = Bottom Param eter Blocking
Device D ensity
640 = x16 (64 -M bit)
128 = x 16 (12 8-M b it)
256 = x 16 (25 6-M b it)
Product Family
L18 = Intel Strataflas h® Wireless Memory
VCC = 1.7 V - 2.0 V
VCCQ = 1.35 V - 2.0 V or 1.7 V -2.0 V
Access S p ee d (ns)
85
Intel StrataFlash® Wireless Memory (L18)
Datasheet Intel S trata F lash® W i rel ess M em ory (L18) August 2005
Order Num ber: 251902, Re visio n: 010 105
E.2 Ordering Information for SCSP
Figure 48 and Table 32 show the ordering information for the Intel S trataFlash® wireless memory
in QUAD+ ba llout products.
Figure 48. Ordering Inform at ion for L18 in QUAD+
Table 32. L18 SCSP Packa ge Ordering Information
I/O
Voltage Flash Component RAM Component Package
Part Order Number
(V) Density in Mbit and
Family Density in Mbit and
Type Size
(mm) Ball Type Type
1.8
128 L18 0 8x10x1.2 Leaded QUAD+
SCSP NZ48F3000L0YTQ0
NZ48F3000L0YBQ0
128 L18 0 8x10x1.2 Lead-Free QUAD+
SCSP JZ48F3000L0YTQ0
JZ48F3000L0YBQ0
256 L18 0 8x11x1.0 Leaded QUAD+
SCSP NZ48F4000L0YTQ0
NZ48F4000L0YBQ0
256 L18 0 8x11x1.0 Lead-Free QUAD+
SCSP JZ48F4000L0YTQ0
JZ48F4000L0YBQ0
F 4 0 L 0 Y B8Z 4N 0 0 Q
Product Line Designator
48F = Flash Memory only
Package Desi gnator
NZ = Intel® SCSP, lead ed
JZ = Intel® SCSP, lead-free
Flash Density
0 = No die
3 = 128-Mbit
4 = 256-Mbit
Fl a s h #1
Fl a s h #2
Fl a s h #3
Flash #4
Flash Family 1 /2
Flash Family 3 /4
0
Product Famil y
L = Intel StrataFlash® Wireless Family Memory
0 = No die
Device Details
0 = Original version of the
products (refer to the latest
versio n of the datasheet
fo r details ).
Pinout Indica tor
Q = QUAD+ ballout
B = x16D Performance
Parameter Location
B = Bottom Pa rameter
T = Top Paramete r
Voltage
Z = 3.0 V I/O
Y = 1.8 V I/O
Intel StrataFlash® Wireless Memory (L18)
August 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet
106 Order Num ber: 251902, Revis i on: 010