MR4A16B
1M x 16 MRAM
FEATURES
• +3.3Voltpowersupply
• Fast35nsread/writecycle
• SRAMcompatibletiming
• Unlimitedread&writeendurance
• Dataalwaysnon-volatilefor>20-yearsattemperature
• RoHS-compliantsmallfootprintBGAandTSOP2package
• AEC-Q100Grade1optioninTSOP2package.
INTRODUCTION
TheMR4A16Bisa16,777,216-bitmagnetoresistiverandomaccessmemory(MRAM)deviceorganizedas
1,048,576wordsof16bits.TheMR4A16BoersSRAMcompatible35nsread/writetimingwithunlimited
endurance.Dataisalwaysnon-volatileforgreaterthan20-years.Dataisautomaticallyprotectedonpower
lossbylow-voltageinhibitcircuitrytopreventwriteswithvoltageoutofspecication.Tosimplifyfault
tolerantdesign,MR4A16Bincludesinternalsinglebiterrorcorrectioncodewith7ECCparitybitsforevery
64databits.TheMR4A16Bistheidealmemorysolutionforapplicationsthatmustpermanentlystoreand
retrievecriticaldataandprogramsquickly.
TheMR4A16Bisavailableinsmallfootprint48-pinballgridarray(BGA)packageanda54-pinthinsmall
outlinepackage(TSOPII).Thesepackagesarecompatiblewithsimilarlow-powerSRAMproductsand
othernonvolatileRAMproducts.
TheMR4A16Bprovideshighlyreliabledatastorageoverawiderangeoftemperatures.Theproductis
oeredwithcommercialtemperature(0to+70°C),industrialtemperature(-40to+85°C),andAEC-Q100
Grade1(-40to+125°C)temperaturerangeoptions.
DocumentNumber:MR4A16BRev.7,10/20111
RoHS
CONTENTS
1.DEVICEPINASSIGNMENT.........................................................................3
2.ELECTRICALSPECIFICATIONS.................................................................4
3.TIMINGSPECIFICATIONS.......................................................................... 7
4.ORDERINGINFORMATION.......................................................................12
5.MECHANICALDRAWING..........................................................................13
6.REVISIONHISTORY......................................................................................15
HowtoReachUs..........................................................................................15
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BENEFITS
• OnememoryreplacesFLASH,SRAM,EEPROMandBBSRAMinsystems
forsimpler,moreecientdesigns
• Improvesreliabilitybyreplacingbattery-backedSRAM
DocumentNumber:MR4A16BRev.7,10/20112
CHIP
ENABLE
BUFFER
OUTPUT
ENABLE
BUFFER
ADDRESS
BUFFER
WRITE
ENABLE
BUFFER
G
E
20
UPPER BYTE OUTPUT ENABLE
LOWER BYTE OUTPUT ENABLE
1M x 16
BIT
MEMORY
ARRAY
ROW
DECODER
COLUMN
DECODER
SENSE
AMPS
LOWER
BYTE
WRITE
DRIVER
LOWER
BYTE
OUTPUT
BUFFER
UPPER
BYTE
OUTPUT
BUFFER
FINAL
WRITE
DRIVERS
UPPER BYTE WRITE ENABLE
LOWER BYTE WRITE ENABLE
W
BYTE
ENABLE
BUFFER
UB
A[19:0]
10
10
16
8
8
8
8
8
8
16
8
DQL[7:0]
8DQU[15:8]
LB
UPPER
BYTE
WRITE
DRIVER
UB
LB
1. DEVICE PIN ASSIGNMENT
Figure 1.1 Block Diagram
Table 1.1 Pin Functions
Signal Name Function
A AddressInput
EChipEnable
W WriteEnable
G OutputEnable
UB UpperByteEnable
LB LowerByteEnable
DQ DataI/O
VDD PowerSupply
VSS Ground
DC DoNotConnect
NC NoConnection
MR4A16B
EverspinTechnologies©2011
123456
LB G A0 A1 A2 NC A
DQU8 UB A3 A4 E DQL0 B
DQU9 DQU10 A5 A6 DQL1 DQL2 C
VSS DQU11
A15
DQL3 VDD D
VDD DQU12 DC A16 DQL4 VSS E
DQU14 DQU13 A14
A13
DQL5 DQL6 F
DQU15
A10
A17
A11
WDQL7 G
A7
A9A8
A12
H
A
18
NC
A19
NC
NC
NC
NC
A19
A0
A1
A2
A3
W
A5
A6
A7
A8
A9
A4
E
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
V
DD
V
SS
NC
NC
NC
NC
A18
A17
A16
A15
G
DC
A14
A13
A12
A11
A10
UB
LB
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
V
SS
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
DocumentNumber:MR4A16BRev.7,10/20113
Figure 1.2 Pin Diagrams for Available Packages (Top View)
48-Pin BGA 54-Pin TSOP2
Table 1.2 Operating Modes
DEVICE PIN ASSIGNMENT MR4A16B
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E1G1W1LB1UB1Mode VDD Current DQL[7:0]2DQU[15:8]2
HXXXXNotselected ISB1,ISB2 Hi-Z Hi-Z
L H H X X Outputdisabled IDDR Hi-Z Hi-Z
LX X H H Outputdisabled IDDR Hi-Z Hi-Z
L L H L H LowerByteRead IDDR DOut Hi-Z
L L H H L UpperByteRead IDDR Hi-Z DOut
L L H L L WordRead IDDR DOut DOut
LXL L H LowerByteWrite IDDW Din Hi-Z
LXL H L UpperByteWrite IDDW Hi-Z Din
LXL L L WordWrite IDDW Din Din
1H=high,L=low,X=don’tcare
2Hi-Z=highimpedance
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Thisdevicecontainscircuitrytoprotecttheinputsagainstdamagecausedbyhighstaticvoltagesor
electricelds;however,itisadvisedthatnormalprecautionsbetakentoavoidapplicationofany
voltagegreaterthanmaximumratedvoltagestothesehigh-impedance(Hi-Z)circuits.
Thedevicealsocontainsprotectionagainstexternalmagneticelds.Precautionsshouldbetaken
toavoidapplicationofanymagneticeldgreaterthanthemaximumeldintensityspecied
inthemaximumratings.
DocumentNumber:MR4A16BRev.7,10/20114
Parameter Symbol Value Unit
Supplyvoltage2VDD -0.5to4.0 V
Voltageonanpin2VIN
-0.5toVDD+0.5 V
Outputcurrentperpin IOUT ±20 mA
Packagepowerdissipation PD0.600 W
Temperatureunderbias
MR4A16B(Commercial)
MR4A16BC(Industrial)
MR4A16BM(AEC-Q100Grade1)
TBIAS
-10to85
-45to95
-45to130
°C
StorageTemperature Tstg -55to150 °C
Leadtemperatureduringsolder(3minutemax) TLead 260 °C
Maximummagneticeldduringwrite
MR4A16B(AllTemperatures) Hmax_write 8000 A/m
Maximummagneticeldduringreadorstandby Hmax_read 8000 A/m
1Permanentdevicedamagemayoccurifabsolutemaximumratingsareexceeded.Functionalopera-
tionshouldberestrictedtorecommendedoperatingconditions.Exposuretoexcessivevoltagesor
magneticeldscouldaectdevicereliability.
2AllvoltagesarereferencedtoVSS.TheDCvalueofVINmustnotexceedactualappliedVDDbymore
than0.5V.TheACvalueofVINmustnotexceedappliedVDDbymorethan2Vfor10nswithIINlimited
tolessthan20mA.
3 Powerdissipationcapabilitydependsonpackagecharacteristicsanduseenvironment.
Table 2.1 Absolute Maximum Ratings1
MR4A16B
EverspinTechnologies©2011
DocumentNumber:MR4A16BRev.7,10/20115
Parameter Symbol Min Typical Max Unit
Powersupplyvoltage VDD 3.0i3.3 3.6 V
Writeinhibitvoltage VWI 2.5 2.7 3.0i V
Inputhighvoltage VIH 2.2 - VDD+0.3ii V
Inputlowvoltage VIL -0.5iii - 0.8 V
Temperatureunderbias
MR4A16B(Commercial)
MR4A16BC(Industrial)
MR4A16BM(AEC-Q100Grade1)iv
TA
0
-40
-40
70
85
125
°C
i Thereisa2msstartuptimeonceVDDexceedsVDD,(max).SeePower Up and Power Down Sequencing below.
ii VIH(max)=VDD+0.3VDC;VIH(max)=VDD+2.0VAC(pulsewidth≤10ns)forI≤20.0mA.
iiiV
IL(min)=-0.5VDC;VIL(min)=-2.0VAC(pulsewidth≤10ns)forI≤20.0mA.
iv AEC-Q100Grade1temperatureprofileassumes10%dutycycleatmaximumtemperature(2-yearsoutof20-yearlife)
Table 2.2 Operating Conditions
Power Up and Power Down Sequencing
MRAMisprotectedfromwriteoperationswheneverVDDislessthanVWI.AssoonasVDDexceedsVDD(min),
thereisastartuptimeof2msbeforereadorwriteoperationscanstart.Thistimeallowsmemorypower
suppliestostabilize.
TheEandWcontrolsignalsshouldtrackVDDonpoweruptoVDD-0.2VorVIH(whicheverislower)andremain
highforthestartuptime.Inmostsystems,thismeansthatthesesignalsshouldbepulledupwitharesis-
torsothatsignalremainshighifthedrivingsignalisHi-Zduringpowerup.AnylogicthatdrivesEandW
shouldholdthesignalshighwithapower-onresetsignalforlongerthanthestartuptime.
DuringpowerlossorbrownoutwhereVDDgoesbelowVWI,writesareprotectedandastartuptimemustbe
observedwhenpowerreturnsaboveVDD(min).
BROWNOUT OR POWER LOSS
NORMAL OPERATION NORMAL OPERATION
STARTUP TIME STARTUP TIME
VWI VWI
VDD
VDD
WRITES INHIBITED
W
E
Figure 2.1 Power Up and Power Down Diagram
MR4A16B
Electrical Specications
EverspinTechnologies©2011
DocumentNumber:MR4A16BRev.7,10/20116
Parameter Symbol Min Typical Max Unit
Inputleakagecurrent Ilkg(I) - - ±1 μA
Outputleakagecurrent Ilkg(O) - - ±1 μA
Outputlowvoltage
(IOL=+4mA)
(IOL=+100μA)
VOL - - 0.4
VSS+0.2
V
Outputhighvoltage
(IOH=-4mA)
(IOH=-100μA)
VOH 2.4
VDD-0.2
--V
Table 2.3 DC Characteristics
Table 2.4 Power Supply Characteristics
Parameter Symbol Typical Max Unit
ACactivesupplycurrent-readmodes1
(IOUT=0mA,VDD=max) IDDR 60 68 mA
ACactivesupplycurrent-writemodes1
(VDD=max)
MR4A16B(Commercial)
MR4A16BC(Industrial)
MR4A16BV(AEC-Q100Grade1)
IDDW 152
152
152
180
180
180
mA
ACstandbycurrent
(VDD=max,E=VIH)
no other restrictions on other inputs
ISB1 9 14 mA
CMOSstandbycurrent
(E≥VDD-0.2VandVIn≤VSS+0.2Vor≥VDD-0.2V)
(VDD=max,f=0MHz)
ISB2 5 9 mA
1 Allactivecurrentmeasurementsaremeasuredwithoneaddresstransitionpercycleandatminimumcycletime.
MR4A16B
Electrical Specications
EverspinTechnologies©2011
DocumentNumber:MR4A16BRev.7,10/20117
MR4A16B
3. TIMING SPECIFICATIONS
Table 3.1 Capacitance1
Parameter Symbol Typical Max Unit
Addressinputcapacitance CIn - 6 pF
Controlinputcapacitance CIn - 6 pF
Input/Outputcapacitance CI/O - 8 pF
1 f=1.0MHz,dV=3.0V,TA=25°C,periodicallysampledratherthan100%tested.
Table 3.2 AC Measurement Conditions
Figure 3.1 Output Load Test Low and High
Figure 3.2 Output Load Test All Others
Parameter Value Unit
Logicinputtimingmeasurementreferencelevel 1.5 V
Logicoutputtimingmeasurementreferencelevel 1.5 V
Logicinputpulselevels 0or3.0 V
Inputrise/falltime 2 ns
Outputloadforlowandhighimpedanceparameters SeeFigure3.1
Outputloadforallothertimingparameters SeeFigure3.2
V
Output
L= 1.5 V
RL= 50 Ω
ZD= 50 Ω
Output
435 Ω
590 Ω
5 pF
3.3 V
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MR4A16B
Timing Specications
DocumentNumber:MR4A16BRev.7,10/20118
Parameter Symbol Min Max Unit
Readcycletime tAVAV 35 - ns
Addressaccesstime tAVQV - 35 ns
Enableaccesstime2tELQV - 35 ns
Outputenableaccesstime tGLQV - 15 ns
Byteenableaccesstime tBLQV - 15 ns
Outputholdfromaddresschange tAXQX 3- ns
Enablelowtooutputactive3tELQX 3- ns
Outputenablelowtooutputactive3tGLQX 0 - ns
Byteenablelowtooutputactive3tBLQX 0 - ns
EnablehightooutputHi-Z3tEHQZ 0 15 ns
OutputenablehightooutputHi-Z3tGHQZ 0 10 ns
BytehightooutputHi-Z3tBHQZ 0 10 ns
1 Wishighforreadcycle.Powersuppliesmustbeproperlygroundedanddecoupled,andbuscontentionconditionsmustbe
minimizedoreliminatedduringreadorwritecycles.
2 AddressesvalidbeforeoratthesametimeEgoeslow.
3 Thisparameterissampledandnot100%tested.Transitionismeasured±200mVfromthesteady-statevoltage.
Table 3.3 Read Cycle Timing1
Read Mode
Figure 3.3A Read Cycle 1
Figure 3.3B Read Cycle 2
A (ADDRESS)
Q (DATA OUT)
t
AVAV
t
AXQX
t
AVQV
Previous Data Valid
Note: Device is continuously selected (E≤V
IL
, G≤V
IL
).
Data Valid
A (ADDRESS)
E (CHIP ENABLE)
G (OUTPUT ENABLE)
Q (DATA OUT) Data V alid
t
AVAV
t
AVQV
t
ELQV
t
ELQX
t
BHQZ
t
GHQZ
t
EHQZ
t
BLQV
t
BLQX
t
GLQV
t
GLQX
LB, UB (BYTE ENABLE)
EverspinTechnologies©2011
MR4A16B
Timing Specications
DocumentNumber:MR4A16BRev.7,10/20119
Table 3.4 Write Cycle Timing 1 (W Controlled)1
Parameter Symbol Min Max Unit
Writecycletime2tAVAV 35 - ns
Addressset-uptime tAVWL 0 - ns
Addressvalidtoendofwrite(Ghigh) tAVWH 20 - ns
Addressvalidtoendofwrite(Glow) tAVWH 20 - ns
Writepulsewidth(Ghigh) tWLWH
tWLEH
15 - ns
Writepulsewidth(Glow) tWLWH
tWLEH
15 - ns
Datavalidtoendofwrite tDVWH 10 - ns
Dataholdtime tWHDX 0 - ns
WritelowtodataHi-Z3tWLQZ 0 15 ns
Writehightooutputactive3tWHQX 3- ns
Writerecoverytime tWHAX 12 - ns
1 AllwriteoccursduringtheoverlapofElowandWlow.Powersuppliesmustbeproperlygroundedanddecoupledandbus
contentionconditionsmustbeminimizedoreliminatedduringreadandwritecycles.IfGgoeslowatthesametimeorafter
Wgoeslow,theoutputwillremaininahighimpedancestate.AfterW,EorUB/LBhasbeenbroughthigh,thesignalmust
remaininsteady-statehighforaminimumof2ns.TheminimumtimebetweenEbeingassertedlowinonecycletoEbeing
assertedlowinasubsequentcycleisthesameastheminimumcycletimeallowedforthedevice.
2 Allwritecycletimingsarereferencedfromthelastvalidaddresstothersttransitionaddress.
3 Thisparameterissampledandnot100%tested.Transitionismeasured±200mVfromthesteady-statevoltage.Atanygiven
voltageortemperate,tWLQZ(max)<tWHQX(min)
W (WRITE ENABLE)
A (ADDRESS)
E (CHIP ENABLE)
UB, LB (BYTE ENABLED)
tAVAV
tAVWH tWHAX
tAVWL
tWLEH
tWLWH
DATA VALID
tDVWH tWHDX
Q (DATA OUT)
D (DATA IN)
tWLQZ
tWHQX
Hi -Z Hi -Z
Figure 3.4 Write Cycle Timing 1 (W Controlled)
EverspinTechnologies©2011
MR4A16B
Timing Specications
EverspinTechnologies©2011 DocumentNumber:MR4A16BRev.7,10/201110
Table 3.5 Write Cycle Timing 2 (E Controlled)1
Figure 3.5 Write Cycle Timing 2 (E Controlled)1
Parameter Symbol Min Max Unit
Writecycletime2tAVAV 35 - ns
Addressset-uptime tAVEL 0 - ns
Addressvalidtoendofwrite(Ghigh) tAVEH 20 - ns
Addressvalidtoendofwrite(Glow) tAVEH 20 - ns
Enabletoendofwrite(Ghigh) tELEH
tELWH
15 - ns
Enabletoendofwrite(Glow)3tELEH
tELWH
15 - ns
Datavalidtoendofwrite tDVEH 10 - ns
Dataholdtime tEHDX 0 - ns
Writerecoverytime tEHAX 12 - ns
1 AllwriteoccursduringtheoverlapofElowandWlow.Powersuppliesmustbeproperlygroundedanddecoupledandbus
contentionconditionsmustbeminimizedoreliminatedduringreadandwritecycles.IfGgoeslowatthesametimeorafter
Wgoeslow,theoutputwillremaininahighimpedancestate.AfterW,EorUB/LBhasbeenbroughthigh,thesignalmust
remaininsteady-statehighforaminimumof2ns.TheminimumtimebetweenEbeingassertedlowinonecycletoEbeing
assertedlowinasubsequentcycleisthesameastheminimumcycletimeallowedforthedevice.
2 Allwritecycletimingsarereferencedfromthelastvalidaddresstothersttransitionaddress.
3 IfEgoeslowatthesametimeorafterWgoeslow,theoutputwillremaininahigh-impedancestate.IfEgoeshighatthe
sametimeorbeforeWgoeshigh,theoutputwillremaininahigh-impedancestate.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
Q (DATA OUT)
D (DATA IN)
t
AVAV
t
AVEH
t
EHAX
t
ELEH
t
EHDX
t
DVEH
t
AVEL
Hi-Z
t
ELWH
Data Valid
UB, LB (BYTE ENABLE)
MR4A16B
Timing Specications
DocumentNumber:MR4A16BRev.7,10/201111
Table 3.6 Write Cycle Timing 3 (LB/UB Controlled)1
Figure 3.6 Write Cycle Timing 3 (LB/UB Controlled)
Parameter Symbol Min Max Unit
Writecycletime2tAVAV 35 - ns
Addressset-uptime tAVBL 0 - ns
Addressvalidtoendofwrite(Ghigh) tAVBH 20 - ns
Addressvalidtoendofwrite(Glow) tAVBH 20 - ns
Writepulsewidth(Ghigh) tBLEH
tBLWH
15 - ns
Writepulsewidth(Glow) tBLEH
tBLWH
15 - ns
Datavalidtoendofwrite tDVBH 10 - ns
Dataholdtime tBHDX 0 - ns
Writerecoverytime tBHAX 12 - ns
1 AllwriteoccursduringtheoverlapofElowandWlow.Powersuppliesmustbeproperlygroundedanddecoupledandbus
contentionconditionsmustbeminimizedoreliminatedduringreadandwritecycles.IfGgoeslowatthesametimeorafter
Wgoeslow,theoutputwillremaininahighimpedancestate.AfterW,EorUB/LBhasbeenbroughthigh,thesignalmust
remaininsteady-statehighforaminimumof2ns.Ifbothbytecontrolsignalsareasserted,thetwosignalsmusthaveno
morethan2nsskewbetweenthem.TheminimumtimebetweenEbeingassertedlowinonecycletoEbeingassertedlowin
asubsequentcycleisthesameastheminimumcycletimeallowedforthedevice.
2 Allwritecycletimingsarereferencedfromthelastvalidaddresstothersttransitionaddress.
W (WRITE ENABLE)
A (ADDRESS)
E (CHIP ENABLE)
UB, LB (BYTE ENABLED)
tAVAV
tAVEH tBHAX
tAVBL tBLEH
tBLWH
Data Valid
tDVBH tBHDX
Q (DATA OUT)
D (DATA IN)
Hi-Z Hi -Z
EverspinTechnologies©2011
DocumentNumber:MR4A16BRev.7,10/201112
MR4A16B
4. ORDERING INFORMATION
Figure 4.1 Part Numbering System
Carrier Blank = Tray, R = Tape & Reel
Speed 35 ns
Package MA = FBGA, YS = TSOP
Temperature Range Blank= Commercial (0 to +70 °C,
C= Industrial (-40 to +85°C,
M= AEC-Q100 Grade 1 (-40 to
+125 °C)
Revision
Data Width 16 = 16-bit
Type A = Asynchronous
Density 4 =16Mb
Magnetoresistive RAM
MR 4 A 16 B C MA 35 R
Part Number Description Package Ship Pack Temp Range
MR4A16BMA3513.3V1Mx16MRAMCommercial 48-BGA Tray 0 to +70 °C
MR4A16BCMA3513.3V1Mx16MRAMIndustrial 48-BGA Tray -40 to +85°C
MR4A16BMA35R13.3V1Mx16MRAMCommercial 48-BGA Tape&Reel 0 to +70 °C
MR4A16BCMA35R13.3V1Mx16MRAMIndustrial 48-BGA Tape&Reel -40 to +85°C
MR4A16BYS35 3.3V1Mx16MRAMCommercial 54-TSOP2 Tray 0 to +70 °C
MR4A16BCYS35 3.3V1Mx16MRAMIndustrial 54-TSOP2 Tray -40 to +85°C
MR4A16BMYS3523.3V1Mx16MRAMAEC-Q100Grade1 54-TSOP2 Tray -40 to +125 °C
MR4A16BYS35R 3.3V1Mx16MRAMCommercial 54-TSOP2 Tape&Reel 0 to +70 °C
MR4A16BCYS35R 3.3V1Mx16MRAMIndustrial 54-TSOP2 Tape&Reel -40 to +85°C
MR4A16BMYS35R23.3V1Mx16MRAMAEC-Q100Grade1 54-TSOP2 Tape&Reel -40 to +125 °C
Table 4.1 Available Parts
EverspinTechnologies©2011
1 MSL-6 only. MSL-3 qualication underway. Please check with Everspin sales for current MSL rating at the time of your order.
2 Preliminary Products: These products are classied as Preliminary until the completion of all qualication tests. The specications in this data sheet are intended to be nal but
are subject to change. Please check the Everspin web site www.everspin.com for the latest information on product status.
DocumentNumber:MR4A16BRev.7,10/201113
MR4A16B
5. MECHANICAL DRAWING
EverspinTechnologies©2011
123456
(DATUM A)
(DATUM B)
SEATING PLANE
PIN A1
INDEX
PIN A1
INDEX
A
B
C
D
E
F
G
H
BOTTOM VIEW TOP VIEW
SOLDER BALL DIAMETER REFERS
TO POST REFLOW CONDITION.
THE PRE-REFLOW DIAMETER IS
ø
0.35mm
Figure 5.1 48-FBGA
Print Version Not To Scale
1. DimensionsinMillimeters.
2. The‘e’representsthebasicsolderballgridpitch.
3. ‘b’ismeasurableatthemaximumsolderballdiameter
inaplaneparalleltodatumC.
4. Dimension‘ccc’ismeasuredparalleltoprimarydatum
C.
5. PrimarydatumC(seatingplane)isdenedbythe
crowns
ofthesolderballs.
6. PackagedimensionsrefertoJEDECMO-205Rev.G.
Ref Min Nominal Max
A1.19 1.27 1.35
A1 0.22 0.27 0.32
b0.31 0.36 0.41
D10.00BSC
E10.00BSC
D1 5.25BSC
E1 3.75BSC
DE 0.375BSC
SE 0.375BSC
e0.75BSC
Ref Tolerance of, from and position
aaa 0.10
bbb 0.10
ddd 0.12
eee 0.15
f 0.08
DocumentNumber:MR4A16BRev.7,10/201114
MR4A16B
5. MECHANICAL DRAWING
EverspinTechnologies©2011
D
C
C
0.10
SEATING PLANE
0.71 REF.
54 28
A2 A1
A
θ
3
θ
2
θ
1
θ
1
e
c
b
27
R1
0.21(0.008)REF.
GAGE PLANE
0.25 mm
0.665(0.026)REF.
R2
E1
E
L1
⊕0.20(0.008) M
Figure 5.2 54-TSOP2
Print Version Not To Scale
1. DimensionsinMillimeters.
2. PackagedimensionsrefertoJEDECMS-024
Ref Min Nominal Max
A1.20
A1 0.05 0.10 0.15
A2 0.95 1.00 1.05
b0.30 0.35 0.45
c0.12 0.21
D22.10 22.22 22.35
E11.56 11.76 11.95
E1 10.03 10.16 10.29
e0.80BSC
L0.40 0.50 0.60
L1 0.80REF
R1 0.12 - -
R2 0.12 - 0.25
θ0° - 8°
θ1 0.40 - -
θ2 15°REF
θ3 15°REF
MR4A16B
DocumentNumber:MR4A16BRev.7,10/201115
Revision Date Description of Change
1 May29,2009 EstablishSpeedandPowerSpecications
2 July27,2009 IncreaseBGAPackageto11mmx11mm
3Nov26,2009 ChangedballdenitionofH6toA19andG2toNCinFigure1.2.
4 Mar10,2010 Changedspeedmarkingandtimingspecsto35nspart.ChangedBGApackageto10mmx
10mm
5 Apr7,2010 Added54-TSOPpackageoptions.
6 Oct7,2011
AddedAEC-Q100Grade1productoption.Max.magneticeldduringwrite(Hmax_write)in-
creasedto8000A/m.RevisedIDDWtypicalfrom110to152mA,maxfromTBDto180mA;IDDR
maxfromTBDto68mA;ISB1typicalfrom11to9ma;ISB2fromtypical7to5mA.
7 Oct28,2011 AddednotetoBGApackageoptionproductsareMSL-6only,MSL-3qualicationunder-
way.FixedtypoonBGAdrawing:TopViewincorrectlylabeledBottomView.
6. REVISION HISTORY
Information in this document is provided solely to enable system and software implementers
to use Everspin Technologies products. There are no express or implied licenses granted here-
under to design or fabricate any integrated circuit or circuits based on the information in this
document. Everspin Technologies reserves the right to make changes without further notice to
any products herein. Everspin makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Everspin Technologies assume
any liability arising out of the application or use of any product or circuit, and specically
disclaims any and all liability, including without limitation consequential or incidental dam-
ages. “Typical” parameters, which may be provided in Everspin Technologies data sheets and/
or specications can and do vary in dierent applications and actual performance may vary
over time. All operating parameters including “Typicals” must be validated for each customer
application by customer’s technical experts. Everspin Technologies does not convey any
license under its patent rights nor the rights of others. Everspin Technologies products are not
designed, intended, or authorized for use as components in systems intended for surgical im-
plant into the body, or other applications intended to support or sustain life, or for any other
application in which the failure of the Everspin Technologies product could create a situation
where personal injury or death may occur. Should Buyer purchase or use Everspin Technolo-
gies products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Everspin Technologies and its ocers, employees, subsidiaries, aliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with
such unintended or unauthorized use, even if such claim alleges that Everspin Technologies
was negligent regarding the design or manufacture of the part. Everspin™ and the Everspin
logo are trademarks of Everspin Technologies, Inc. All other product or service names are the
property of their respective owners.
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MR4A16B,Revision7,10/2011
Document Control Number:
MR4A16B_Datasheet_EST352_Rev7
EverspinTechnologies©2011