MR4A16B FEATURES 1M x 16 MRAM * +3.3 Volt power supply * Fast 35 ns read/write cycle * SRAM compatible timing * Unlimited read & write endurance * Data always non-volatile for >20-years at temperature * RoHS-compliant small footprint BGA and TSOP2 package * AEC-Q100 Grade 1 option in TSOP2 package. RoHS BENEFITS * One memory replaces FLASH, SRAM, EEPROM and BBSRAM in systems for simpler, more efficient designs * Improves reliability by replacing battery-backed SRAM INTRODUCTION The MR4A16B is a 16,777,216-bit magnetoresistive random access memory (MRAM) device organized as 1,048,576 words of 16 bits. The MR4A16B offers SRAM compatible 35 ns read/write timing with unlimited endurance. Data is always non-volatile for greater than 20-years. Data is automatically protected on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification. To simplify fault tolerant design, MR4A16B includes internal single bit error correction code with 7 ECC parity bits for every 64 data bits. The MR4A16B is the ideal memory solution for applications that must permanently store and retrieve critical data and programs quickly. The MR4A16B is available in small footprint 48-pin ball grid array (BGA) package and a 54-pin thin small outline package (TSOPII). These packages are compatible with similar low-power SRAM products and other nonvolatile RAM products. The MR4A16B provides highly reliable data storage over a wide range of temperatures. The product is offered with commercial temperature (0 to +70 C), industrial temperature (-40 to +85 C), and AEC-Q100 Grade 1 (-40 to +125 C) temperature range options. CONTENTS 1. DEVICE PIN ASSIGNMENT......................................................................... 3 2. ELECTRICAL SPECIFICATIONS................................................................. 4 3. TIMING SPECIFICATIONS.......................................................................... 7 4. ORDERING INFORMATION....................................................................... 12 5. MECHANICAL DRAWING.......................................................................... 13 6. REVISION HISTORY...................................................................................... 15 How to Reach Us.......................................................................................... 15 Everspin Technologies (c) 2011 1 Document Number: MR4A16B Rev. 7, 10/2011 MR4A16B 1. DEVICE PIN ASSIGNMENT Figure 1.1 Block Diagram OUTPUT ENABLE BUFFER G A[19:0] 20 UPPER BYTE OUTPUT ENABLE LOWER BYTE OUTPUT ENABLE 10 ADDRESS BUFFER 10 ROW DECODER CHIP ENABLE BUFFER E FINAL WRITE DRIVERS UPPER BYTE WRITE ENABLE LB LOWER BYTE OUTPUT BUFFER 8 8 16 BYTE ENABLE BUFFER LB SENSE AMPS 1M x 16 BIT MEMORY ARRAY UB UB 8 16 WRITE ENABLE BUFFER W COLUMN DECODER UPPER BYTE OUTPUT BUFFER 8 UPPER BYTE WRITE DRIVER LOWER BYTE WRITE DRIVER 8 8 8 8 DQU[15:8] DQL[7:0] LOWER BYTE WRITE ENABLE Table 1.1 Pin Functions Signal Name Function A Address Input E Chip Enable W Write Enable G Output Enable UB Upper Byte Enable LB Lower Byte Enable DQ Data I/O VDD Power Supply VSS Ground DC Do Not Connect NC No Connection Everspin Technologies (c) 2011 2 Document Number: MR4A16B Rev. 7, 10/2011 MR4A16B DEVICE PIN ASSIGNMENT Figure 1.2 Pin Diagrams for Available Packages (Top View) 1 2 3 4 5 6 LB G A0 A1 A2 NC A DQU8 UB A3 A4 E DQL0 B DQU9 DQU10 A5 A6 DQL1 DQL2 C VSS DQU11 A17 A7 DQL3 VDD D VDD DQU12 DC A16 DQL4 VSS E DQU14 DQU13 A14 A15 DQL5 DQL6 F DQU15 NC A12 A13 W DQL7 G A18 A8 A9 A10 A11 A19 H 1 2 3 4 54 53 52 51 5 6 7 50 49 48 8 9 47 46 10 11 12 13 45 44 43 42 14 15 16 17 18 19 41 40 39 38 37 36 20 21 22 35 34 33 23 32 24 25 26 27 31 30 29 28 NC A19 A0 A1 A2 A3 A4 E DQ0 DQ1 DQ2 DQ3 VDD VSS DQ4 DQ5 DQ6 DQ7 W A5 A6 A7 A8 A9 NC NC NC 48-Pin BGA NC A18 A17 A16 A15 G UB LB DQ15 DQ14 DQ13 DQ12 VSS VDD DQ11 DQ10 DQ9 DQ8 DC A14 A13 A12 A11 A10 NC NC NC 54-Pin TSOP2 Table 1.2 Operating Modes E1 G1 W1 LB1 UB1 Mode VDD Current DQL[7:0]2 DQU[15:8]2 H X X X X Not selected ISB1, ISB2 Hi-Z Hi-Z L H H X X Output disabled IDDR Hi-Z Hi-Z L X X H H Output disabled IDDR Hi-Z Hi-Z L L H L H Lower Byte Read IDDR DOut Hi-Z L L H H L Upper Byte Read IDDR Hi-Z DOut L L H L L Word Read IDDR DOut DOut L X L L H Lower Byte Write IDDW Din Hi-Z L X L H L Upper Byte Write IDDW Hi-Z Din L X L L L Word Write IDDW Din Din H = high, L = low, X = don't care 1 Hi-Z = high impedance 2 Everspin Technologies (c) 2011 3 Document Number: MR4A16B Rev. 7, 10/2011 MR4A16B 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field greater than the maximum field intensity specified in the maximum ratings. Table 2.1 Absolute Maximum Ratings1 Parameter Symbol Value Unit Supply voltage2 VDD -0.5 to 4.0 V Voltage on an pin2 VIN -0.5 to VDD + 0.5 V Output current per pin IOUT 20 mA Package power dissipation PD 0.600 W Temperature under bias MR4A16B (Commercial) MR4A16BC (Industrial) MR4A16BM (AEC-Q100 Grade 1) TBIAS -10 to 85 -45 to 95 -45 to 130 Storage Temperature Tstg -55 to 150 C Lead temperature during solder (3 minute max) TLead 260 C Maximum magnetic field during write MR4A16B (All Temperatures) Hmax_write 8000 A/m Maximum magnetic field during read or standby Hmax_read 8000 A/m C 1 Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2 All voltages are referenced to VSS. The DC value of VIN must not exceed actual applied VDD by more than 0.5V. The AC value of VIN must not exceed applied VDD by more than 2V for 10ns with IIN limited to less than 20mA. 3 Power dissipation capability depends on package characteristics and use environment. Everspin Technologies (c) 2011 4 Document Number: MR4A16B Rev. 7, 10/2011 MR4A16B Electrical Specifications Table 2.2 Operating Conditions Parameter Symbol Min Typical Max Unit Power supply voltage VDD 3.0 i 3.3 3.6 V Write inhibit voltage VWI 2.5 2.7 3.0 i V Input high voltage VIH 2.2 - VDD + 0.3 ii V Input low voltage VIL -0.5 iii - 0.8 V Temperature under bias MR4A16B (Commercial) TA MR4A16BC (Industrial) MR4A16BM (AEC-Q100 Grade 1)iv i ii iii iv 0 -40 -40 70 85 125 C There is a 2 ms startup time once VDD exceeds VDD,(max). See Power Up and Power Down Sequencing below. VIH(max) = VDD + 0.3 VDC ; VIH(max) = VDD + 2.0 VAC (pulse width 10 ns) for I 20.0 mA. VIL(min) = -0.5 VDC ; VIL(min) = -2.0 VAC (pulse width 10 ns) for I 20.0 mA. AEC-Q100 Grade 1 temperature profile assumes 10% duty cycle at maximum temperature (2-years out of 20-year life) Power Up and Power Down Sequencing MRAM is protected from write operations whenever VDD is less than VWI. As soon as VDD exceeds VDD(min), there is a startup time of 2 ms before read or write operations can start. This time allows memory power supplies to stabilize. The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and remain high for the startup time. In most systems, this means that these signals should be pulled up with a resistor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W should hold the signals high with a power-on reset signal for longer than the startup time. During power loss or brownout where VDD goes below VWI, writes are protected and a startup time must be observed when power returns above VDD(min). Figure 2.1 Power Up and Power Down Diagram STARTUP TIME STARTUP TIME VDD VDD VWI VWI BROWNOUT OR POWER LOSS WRITES INHIBITED E W NORMAL OPERATION Everspin Technologies (c) 2011 NORMAL OPERATION 5 Document Number: MR4A16B Rev. 7, 10/2011 MR4A16B Electrical Specifications Table 2.3 DC Characteristics Parameter Symbol Min Typical Max Unit Input leakage current Ilkg(I) - - 1 A Output leakage current Ilkg(O) - - 1 A Output low voltage (IOL = +4 mA) (IOL = +100 A) VOL - - 0.4 VSS + 0.2 V Output high voltage (IOH = -4 mA) (IOH = -100 A) VOH 2.4 VDD - 0.2 - - V Table 2.4 Power Supply Characteristics 1 Parameter Symbol Typical Max Unit AC active supply current - read modes1 (IOUT= 0 mA, VDD= max) IDDR 60 68 mA AC active supply current - write modes1 (VDD= max) MR4A16B (Commercial) MR4A16BC (Industrial) MR4A16BV (AEC-Q100 Grade 1) IDDW 152 152 152 180 180 180 mA AC standby current (VDD= max, E = VIH) no other restrictions on other inputs ISB1 9 14 mA CMOS standby current (E VDD - 0.2 V and VIn VSS + 0.2 V or VDD - 0.2 V) (VDD = max, f = 0 MHz) ISB2 5 9 mA All active current measurements are measured with one address transition per cycle and at minimum cycle time. Everspin Technologies (c) 2011 6 Document Number: MR4A16B Rev. 7, 10/2011 MR4A16B 3. TIMING SPECIFICATIONS Table 3.1 Capacitance1 1 Parameter Symbol Typical Max Unit Address input capacitance CIn - 6 pF Control input capacitance CIn - 6 pF Input/Output capacitance CI/O - 8 pF Parameter Value Unit Logic input timing measurement reference level 1.5 V Logic output timing measurement reference level 1.5 V Logic input pulse levels 0 or 3.0 V Input rise/fall time 2 ns Output load for low and high impedance parameters See Figure 3.1 Output load for all other timing parameters See Figure 3.2 f = 1.0 MHz, dV = 3.0 V, TA = 25 C, periodically sampled rather than 100% tested. Table 3.2 AC Measurement Conditions Figure 3.1 Output Load Test Low and High ZD= 50 Output RL = 50 VL = 1.5 V Figure 3.2 Output Load Test All Others 3.3 V 590 Output 5 pF 435 Everspin Technologies (c) 2011 7 Document Number: MR4A16B Rev. 7, 10/2011 MR4A16B Timing Specifications Read Mode Table 3.3 Read Cycle Timing1 Parameter Symbol Min Max Unit Read cycle time tAVAV 35 - ns Address access time tAVQV - 35 ns Enable access time2 tELQV - 35 ns Output enable access time tGLQV - 15 ns Byte enable access time tBLQV - 15 ns Output hold from address change tAXQX 3 - ns tELQX 3 - ns tGLQX 0 - ns Byte enable low to output active3 tBLQX 0 - ns Enable high to output Hi-Z tEHQZ 0 15 ns Output enable high to output Hi-Z3 tGHQZ 0 10 ns Byte high to output Hi-Z tBHQZ 0 10 ns Enable low to output active3 Output enable low to output active 1 2 3 3 3 3 W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during read or write cycles. Addresses valid before or at the same time E goes low. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. Figure 3.3A Read Cycle 1 t AVAV A (ADDRESS) t AXQX Q (DATA OUT) Previous Data Valid Data Valid t AVQV Note: Device is continuously selected (EVIL, GVIL). Figure 3.3B Read Cycle 2 t AVAV A (ADDRESS) t AVQV E (CHIP ENABLE) t ELQV t EHQZ t ELQX G (OUTPUT ENABLE) t GLQX t GHQZ t GLQV LB, UB (BYTE ENABLE) Q (DATA OUT) Everspin Technologies (c) 2011 t BLQX t BHQZ t BLQV Data Valid 8 Document Number: MR4A16B Rev. 7, 10/2011 MR4A16B Timing Specifications Table 3.4 Write Cycle Timing 1 (W Controlled)1 Parameter Symbol Min Max Unit Write cycle time2 tAVAV 35 - ns Address set-up time tAVWL 0 - ns Address valid to end of write (G high) tAVWH 20 - ns Address valid to end of write (G low) tAVWH 20 - ns 15 - ns 15 - ns tWLWH tWLEH tWLWH tWLEH Write pulse width (G high) Write pulse width (G low) Data valid to end of write tDVWH 10 - ns Data hold time tWHDX 0 - ns tWLQZ 0 15 ns tWHQX 3 - ns tWHAX 12 - ns Write low to data Hi-Z3 Write high to output active 3 Write recovery time 1 2 3 All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. At any given voltage or temperate, tWLQZ(max) < tWHQX(min) Figure 3.4 Write Cycle Timing 1 (W Controlled) t AVAV A (ADDRESS) t AVWH t WHAX E (CHIP ENABLE) t WLEH t WLWH W (WRITE ENABLE) t AVWL UB, LB (BYTE ENABLED) t DVWH D (DATA IN) t WHDX DATA VALID t WLQZ Q (DATA OUT) Hi -Z Hi -Z t WHQX Everspin Technologies (c) 2011 9 Document Number: MR4A16B Rev. 7, 10/2011 MR4A16B Timing Specifications Table 3.5 Write Cycle Timing 2 (E Controlled)1 1 2 3 Parameter Symbol Min Max Unit Write cycle time2 tAVAV 35 - ns Address set-up time tAVEL 0 - ns Address valid to end of write (G high) tAVEH 20 - ns Address valid to end of write (G low) tAVEH 20 - ns Enable to end of write (G high) tELEH tELWH 15 - ns Enable to end of write (G low)3 tELEH tELWH 15 - ns Data valid to end of write tDVEH 10 - ns Data hold time tEHDX 0 - ns Write recovery time tEHAX 12 - ns All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W, E or UB/ LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the same time or before W goes high, the output will remain in a high-impedance state. Figure 3.5 Write Cycle Timing 2 (E Controlled)1 t AVAV A (ADDRESS) t EHAX t AVEH t ELEH E (CHIP ENABLE) t AVEL t ELWH W (WRITE ENABLE) UB, LB (BYTE ENABLE) t DVEH D (DATA IN) Data Valid Hi-Z Q (DATA OUT) Everspin Technologies (c) 2011 t EHDX 10 Document Number: MR4A16B Rev. 7, 10/2011 MR4A16B Timing Specifications Table 3.6 Write Cycle Timing 3 (LB/UB Controlled)1 Parameter Symbol Min Max Unit Write cycle time2 tAVAV 35 - ns Address set-up time tAVBL 0 - ns Address valid to end of write (G high) tAVBH 20 - ns Address valid to end of write (G low) tAVBH 20 - ns 15 - ns 15 - ns tBLEH tBLWH tBLEH tBLWH Write pulse width (G high) Write pulse width (G low) 1 2 Data valid to end of write tDVBH 10 - ns Data hold time tBHDX 0 - ns Write recovery time tBHAX 12 - ns All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. If both byte control signals are asserted, the two signals must have no more than 2 ns skew between them. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. Figure 3.6 Write Cycle Timing 3 (LB/UB Controlled) t AVAV A (ADDRESS) t AVEH t BHAX E (CHIP ENABLE) W (WRITE ENABLE) t AVBL t BLEH t BLWH UB, LB (BYTE ENABLED) t DVBH D (DATA IN) Q (DATA OUT) t BHDX Data Valid Hi -Z Everspin Technologies (c) 2011 Hi -Z 11 Document Number: MR4A16B Rev. 7, 10/2011 MR4A16B 4. ORDERING INFORMATION Figure 4.1 Part Numbering System MR 4 A 16 B C MA 35 R Carrier Speed Package Temperature Range Revision Data Width Type Blank = Tray, R = Tape & Reel 35 ns MA = FBGA, YS = TSOP Blank= Commercial (0 to +70 C, C= Industrial (-40 to +85C, M= AEC-Q100 Grade 1 (-40 to +125 C) 16 = 16-bit A = Asynchronous Density 4 =16Mb Magnetoresistive RAM Table 4.1 Available Parts Part Number Description Package Ship Pack MR4A16BMA35 1 MR4A16BCMA35 1 MR4A16BMA35R 1 MR4A16BCMA35R 1 MR4A16BYS35 MR4A16BCYS35 MR4A16BMYS352 MR4A16BYS35R MR4A16BCYS35R MR4A16BMYS35R2 3.3 V 1Mx16 MRAM Commercial 3.3 V 1Mx16 MRAM Industrial 3.3 V 1Mx16 MRAM Commercial 3.3 V 1Mx16 MRAM Industrial 3.3 V 1Mx16 MRAM Commercial 3.3 V 1Mx16 MRAM Industrial 3.3 V 1Mx16 MRAM AEC-Q100 Grade 1 3.3 V 1Mx16 MRAM Commercial 3.3 V 1Mx16 MRAM Industrial 3.3 V 1Mx16 MRAM AEC-Q100 Grade 1 48-BGA 48-BGA 48-BGA 48-BGA 54-TSOP2 54-TSOP2 54-TSOP2 54-TSOP2 54-TSOP2 54-TSOP2 Tray Tray Tape & Reel Tape & Reel Tray Tray Tray Tape & Reel Tape & Reel Tape & Reel Temp Range 0 to +70 C -40 to +85C 0 to +70 C -40 to +85C 0 to +70 C -40 to +85C -40 to +125 C 0 to +70 C -40 to +85C -40 to +125 C MSL-6 only. MSL-3 qualification underway. Please check with Everspin sales for current MSL rating at the time of your order. Preliminary Products: These products are classified as Preliminary until the completion of all qualification tests. The specifications in this data sheet are intended to be final but are subject to change. Please check the Everspin web site www.everspin.com for the latest information on product status. 1 2 Everspin Technologies (c) 2011 12 Document Number: MR4A16B Rev. 7, 10/2011 MR4A16B 5. MECHANICAL DRAWING Figure 5.1 48-FBGA BOTTOM VIEW TOP VIEW (DATUM B) PIN A1 INDEX PIN A1 INDEX 6 5 4 3 2 1 A (DATUM A) B C D E F G H SEATING PLANE SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS o 0.35mm Ref Min Nominal Max A 1.19 1.27 1.35 A1 0.22 0.27 0.32 b D E D1 E1 DE SE e 0.31 0.36 0.41 Ref aaa bbb ddd eee fff Tolerance of, from and position Print Version Not To Scale 1. 2. 3. 10.00 BSC 10.00 BSC 4. 5.25 BSC 5. 3.75 BSC 0.375 BSC 6. 0.375 BSC Dimensions in Millimeters. The `e' represents the basic solder ball grid pitch. `b' is measurable at the maximum solder ball diameter in a plane parallel to datum C. Dimension `ccc' is measured parallel to primary datum C. Primary datum C (seating plane) is defined by the crowns of the solder balls. Package dimensions refer to JEDEC MO-205 Rev. G. 0.75 BSC 0.10 0.10 0.12 0.15 0.08 Everspin Technologies (c) 2011 13 Document Number: MR4A16B Rev. 7, 10/2011 MR4A16B 5. MECHANICAL DRAWING Figure 5.2 54-TSOP2 A2 D 54 A1 A 28 3 L1 E E1 2 c 27 1 0.20(0.008) M b e R1 R2 0.71 REF. 0.21(0.008)REF. C 0.665(0.026)REF. GAGE PLANE SEATING PLANE 0.25 mm 0.10 C 1 Ref Min Nominal A Max 1.20 A1 0.05 0.10 0.15 A2 b c D E E1 e L L1 R1 R2 1 2 3 0.95 1.00 1.05 0.30 0.35 0.45 0.12 Print Version Not To Scale 1. 2. 0.21 22.10 22.22 22.35 11.56 11.76 11.95 10.03 10.16 10.29 Dimensions in Millimeters. Package dimensions refer to JEDEC MS-024 0.80 BSC 0.40 0.50 0.60 0.80 REF 0.12 - - 0.12 - 0.25 0 - 8 0.40 - - 15 REF 15 REF Everspin Technologies (c) 2011 14 Document Number: MR4A16B Rev. 7, 10/2011 MR4A16B 6. REVISION HISTORY Revision Date Description of Change 1 May 29, 2009 Establish Speed and Power Specifications 2 July 27, 2009 Increase BGA Package to 11 mm x 11 mm 3 Nov 26, 2009 Changed ball definition of H6 to A19 and G2 to NC in Figure 1.2. 4 Mar 10, 2010 Changed speed marking and timing specs to 35 ns part. Changed BGA package to 10 mm x 10mm 5 Apr 7, 2010 Added 54-TSOP package options. 6 Oct 7, 2011 Added AEC-Q100 Grade 1 product option. Max. magnetic field during write (Hmax_write ) increased to 8000 A/m. Revised IDDW typical from110 to 152mA, max from TBD to 180mA; IDDR max from TBD to 68mA; ISB1 typical from 11 to 9ma; ISB2 from typical 7 to 5mA. 7 Oct 28, 2011 Added note to BGA package option products are MSL-6 only, MSL-3 qualification under- way. Fixed typo on BGA drawing: Top View incorrectly labeled Bottom View. How to Reach Us: Home Page: www.everspin.com E-Mail: support@everspin.com orders@everspin.com sales@everspin.com USA/Canada/South and Central America Everspin Technologies 1347 N. Alma School Road, Suite 220 Chandler, Arizona 85224 +1-877-347-MRAM (6726) +1-480-347-1111 Europe, Middle East and Africa support.europe@everspin.com Japan support.japan@everspin.com Asia Pacific support.asia@everspin.com Information in this document is provided solely to enable system and software implementers to use Everspin Technologies products. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuit or circuits based on the information in this document. Everspin Technologies reserves the right to make changes without further notice to any products herein. Everspin makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Everspin Technologies assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters, which may be provided in Everspin Technologies data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters including "Typicals" must be validated for each customer application by customer's technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights of others. Everspin Technologies products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Everspin Technologies product could create a situation where personal injury or death may occur. Should Buyer purchase or use Everspin Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and hold Everspin Technologies and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Everspin Technologies was negligent regarding the design or manufacture of the part. EverspinTM and the Everspin logo are trademarks of Everspin Technologies, Inc. All other product or service names are the property of their respective owners. MR4A16B, Revision 7, 10/2011 Document Control Number: MR4A16B_Datasheet_EST352_Rev7 Everspin Technologies (c) 2011 15 Document Number: MR4A16B Rev. 7, 10/2011