Errata SLAZ039G - November 2007 - Revised July 2011 MSP430x23x, MSP430x24x(1), MSP430x2410 Device Erratasheet 1 Current Version See Appendix A for prior silicon revisions. Device Rev: ADC25 BCL12 CPU8 CPU19 FLASH19 FLASH24 FLASH27 FLASH36 PORT12 TA12 TA16 TAB22 TB2 TB16 USCI20 USCI22 USCI23 USCI24 USCI25 USCI26 The checkmark means that the issue is present in that revision. MSP430F233 E MSP430F235 E MSP430F2410 E MSP430F248 E MSP430F2481 E MSP430F249 E MSP430F2491 E Device XOSC6 XOSC5 USCI30 E USCI28 E Rev: MSP430F247 MSP430F2471 MSP430F233 E MSP430F235 E MSP430F2410 E MSP430F247 E MSP430F2471 E MSP430F248 E MSP430F2481 E MSP430F249 E MSP430F2491 E SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback MSP430x23x, MSP430x24x(1), MSP430x2410 Device Erratasheet Copyright (c) 2007-2011, Texas Instruments Incorporated 1 Package Markings 2 www.ti.com Package Markings PM64 LQFP (PM), 64 Pin YMLLLLS G4 M430Fxxx REV # RGC64 2 YM LLLL S # = Year and Month Date Code = LOT Trace Code = Assembly Site Code = DIE Revision = Pin 1 QFN (RGC), 64 pin MSP430x23x, MSP430x24x(1), MSP430x2410 Device Erratasheet SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback Copyright (c) 2007-2011, Texas Instruments Incorporated Detailed Bug Description www.ti.com 3 Detailed Bug Description ADC25 ADC12 Module Function Write to ADC12CTL0 triggers ADC12 when CONSEQ = 00 Description If ADC conversions are triggered by the Timer_B module and the ADC12 is in single-channel single-conversion mode (CONSEQ = 00), ADC sampling is enabled by write access to any bit(s) in the ADC12CTL0 register. This is contrary to the expected behavior that only the ADC12 enable conversion bit (ADC12ENC) triggers a new ADC12 sample. Workaround When operating the ADC12 in CONSEQ = 00 and a Timer_B output is selected as the sample and hold source, temporarily clear the ADC12ENC bit before writing to other bits in the ADC12CTL0 register. The following capture trigger can then be re-enabled by setting ADC12ENC = 1. BCL12 Basic Clock Module Function Switching RSEL can cause DCO dead time Description After switching RSELx bits (located in register BCSCTL1) from a value of >13 to a value of <12 OR from a value of <12 to a value of >13, the resulting clock delivered by the DCO can stop before the new clock frequency is applied. This dead time is approximately 20 s. In some instances, the DCO may completely stop, requiring a power cycle. Workaround * When switching RSEL from >13 to <12, use an intermediate frequency step. The intermediate RSEL value should be 13. CURRENT RSEL TARGET RSEL 15 14 Switch directly to target RSEL 14 or 15 13 Switch directly to target RSEL 14 or 15 0 to 12 Switch to 13 first, and then to target RSEL (two step sequence) 0 to 13 0 to 12 Switch directly to target RSEL * RECOMMENDED TRANSITION SEQUENCE When switching RSEL from <12 to >13, ensure that the maximum system frequency is not exceeded during the transition. This can be achieved by clearing the DCO bits first (DCOCTL control register, bits 7-5), then increasing the RSEL value, and finally applying the target frequency DCO bit values. For more details, see the examples in the "TLV Structure" chapter in the MSP430x2xx Family User's Guide (SLAU144). CPU8 CPU Module Function Using odd values in the SP register Description The SP can be written with odd values. In the original CPU, an odd SP value could be combined with an odd offset (for example, mov. #value, 5(SP)). In the new CPU, the SP can be written with an odd value, but the first time the SP is used, the LSB is forced to 0. Workaround Do not use odd values with the SP. SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback MSP430x23x, MSP430x24x(1), MSP430x2410 Device Erratasheet Copyright (c) 2007-2011, Texas Instruments Incorporated 3 Detailed Bug Description www.ti.com CPU19 CPU Module Function CPUOFF can change register values Description If a CPUOFF command is followed by an instruction with an indirect addressed operand (for example, mov @R8, R9, and RET), an unintentional register-read operation can occur during the wakeup of the CPU. If the unintentional read occurs to a read-sensitive register (for example, UCB0RXBUF or TAIV), which changes its value or the value of other registers (IFGs), the bug leads to lost interrupts or wrong register read values. Workaround Insert a NOP instruction after each CPUOFF instruction. FLASH19 Flash Module Function EEI feature does not work for code execution from RAM Description When the program is executed from RAM, the flash controller EEI feature does not work. The erase cycle is suspended, and the interrupt is serviced, but there is a problem while resuming with the erase cycle. Addresses applied to flash are different from the actual values while resuming erase cycle after ISR execution. Workaround None FLASH24 Flash Module Function Write or erase emergency exit can cause failures Description When a flash write or erase is abruptly terminated, the following flash accesses by the CPU may be unreliable and result in erroneous code execution. The abrupt termination can be the result of one the following events: 1. The Flash Controller Clock is configured to be sourced by an external crystal. An oscillator fault occurs thus stopping this clock abruptly. or 2. The Emergency Exit bit (EMEX in FCTL3) when set forces a write or an erase operation to be terminated before normal completion. or 3. The Enable Emergency Interrupt Exit bit (EEIEX in FCTL1) when set with GIE = 1 can lead to an interrupt causing an emergency exit during a Flash operation. Workaround 1. Use the internal DCO as the flash controller clock provided from MCLK or SMCLK. or 2. After setting EMEX = 1, wait for a sufficient amount of time before flash is accessed again. or 3. No workaround. Do not use EEIEX bit. 4 MSP430x23x, MSP430x24x(1), MSP430x2410 Device Erratasheet SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback Copyright (c) 2007-2011, Texas Instruments Incorporated Detailed Bug Description www.ti.com FLASH27 Flash Module Function EEI feature can disrupt segment erase Description When a flash segment erase operation is active with EEI feature selected (EEI = 1 in FLCTL1) and GIE = 0, the following can occur: An interrupt event causes the flash erase to be stopped, and the flash controller expects an RETI to resume the erase. Because GIE = 0, interrupts are not serviced and RETI never happens. Workaround * * Do not set bit EEI = 1 when GIE = 0. or Force an RETI instruction during the erase operation during the check for BUSY=1 (FCLTL3). Sample Code: LOOP: SUB_RETI: MOV BIT JMP JNZ R5, 0(R5) #BUSY, &FCTL3 SUB_RETI LOOP PUSH RETI SR ; ; ; ; Dummy write, erase segment test busy bit Force RETI instruction loop while BUSY=1 FLASH36 Flash Module Function Flash content may degrade due to aborted page erases Description If a page erase is aborted by EEIEX, the flash page containing the last instruction before erase operation starts to degrade. This effect is incremental and, after repetitions, may lead to corrupted flash content. Workaround * * * Use the EEI (interrupt erasing) feature instead of EEIEX (abort erasing). or A PSA checksum can be calculated over affected flash page using the marginal read mode (marginal 0). If the PSA sum differs from expected PSA value, the affected flash page must be reprogrammed. or Start flash erasing from RAM and limit system frequency to <1 MHz ( to ensure a 6-s delay after EEIEX). If the last instruction before erasing is located in RAM, flash cell degradation does not occur. PORT12 Digital I/O Module, Port 1 and 2 Function PxIFG is set on PUC Description The PxIN register is cleared when a PUC is asserted, and it regains the original value after the PUC is de-asserted. If the PxIN register bits read high, asserting a PUC causes clearing of the register, which results in a high-to-low transition. Once the PUC is de-asserted, the PxIN register is restored to high, which results in a low-to-high transition. This behavior results in the PxIFG being set regardless of the PxIES setting. Workaround Prior to setting PxIE bits, ensure that corresponding PxIFG bits are cleared. SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback MSP430x23x, MSP430x24x(1), MSP430x2410 Device Erratasheet Copyright (c) 2007-2011, Texas Instruments Incorporated 5 Detailed Bug Description www.ti.com TA12 Timer_A Module Function Interrupt is lost (slow ACLK) Description Timer_A counter is running with slow clock (external TACLK or ACLK) compared to MCLK. The compare mode is selected for the capture/compare channel and the CCRx register is incremented by one with the occurring compare interrupt (if TAR = CCRx). Due to the fast MCLK, the CCRx register increment (CCRx = CCRx + 1) happens before the Timer_A counter has incremented again. Therefore, the next compare interrupt should happen at once with the next Timer_A counter increment (if TAR = CCRx + 1). This interrupt is lost. Workaround Switch capture/compare mode to capture mode before the CCRx register increment. Switch back to compare mode afterward. TA16 Timer_A Module Function First increment of TAR erroneous when IDx > 00 Description The first increment of TAR after any timer clear event (POR/TACLR) happens immediately following the first positive edge of the selected clock source (INCLK, SMCLK, ACLK, or TACLK). This is independent of the clock input divider settings (ID0, ID1). All following TAR increments are performed correctly with the selected IDx settings. Workaround None TAB22 Timer_A/Timer_B Module Function Timer_A/B register modification after Watchdog Timer PUC Description Unwanted modification of the Timer_A/B registers TACTL and TAIV can occur when a PUC is generated by the Watchdog Timer (WDT) in watchdog mode and any Timer_A/B counter register TACCRx/TBCCRx is incremented/decremented (Timer_A/B does not need to be running). Workaround Initialize TACTL/TBCTL register after the reset occurs using a MOV instruction (BIS/BIC may not fully initialize the register). TAIV/TBIV is automatically cleared following this initialization. Example code: MOV.W #VAL, &TACTL or MOV.W #VAL, &TBCTL Where, VAL = 0, if Timer is not used in application; otherwise, user defined per desired function. 6 MSP430x23x, MSP430x24x(1), MSP430x2410 Device Erratasheet SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback Copyright (c) 2007-2011, Texas Instruments Incorporated Detailed Bug Description www.ti.com TB2 Timer_B Module Function Interrupt is lost (slow ACLK) Description Timer_B counter is running with slow clock (external TBCLK or ACLK) compared to MCLK. The compare mode is selected for the capture/compare channel and the CCRx register is incremented by 1 with the occurring compare interrupt (if TBR = CCRx). Due to the fast MCLK, the CCRx register increment (CCRx = CCRx + 1) happens before the Timer_B counter has incremented again. Therefore, the next compare interrupt should happen at once with the next Timer_B counter increment (if TBR = CCRx + 1). This interrupt is lost. Workaround Switch capture/compare mode to capture mode before the CCRx register increment. Switch back to compare mode afterward. TB16 Timer_B Module Function First increment of TBR erroneous when IDx > 00 Description The first increment of TBR after any timer clear event (POR/TBCLR) happens immediately following the first positive edge of the selected clock source (INCLK, SMCLK, ACLK, or TBCLK). This is independent of the clock input divider settings (ID0, ID1). All following TBR increments are performed correctly with the selected IDx settings. Workaround None USCI20 USCI Module Function I2C mode multi-master transmitter issue Description When configured for I2C master-transmitter mode and used in a multi-master environment, the USCI module can cause unpredictable bus behavior if all of the following conditions are true: 1. Two masters are generating SCL. and 2. The slave is stretching the SCL low phase of an ACK period while outputting NACK on SDA. and 3. The slave drives ACK on SDA after the USCI has already released SCL, and then the SCL bus line is released. and 4. The transmit buffer has not been loaded before the other master continues communication by driving SCL low. The USCI remains in the SCL high phase until the transmit buffer is written. After the transmit buffer has been written, the USCI interferes with the current bus activity and may cause unpredictable bus behavior. Workaround * * * Ensure that slave does not stretch the SCL low phase of an ACK period. or Ensure that the transmit buffer is loaded in time. or Do not use the multi-master transmitter mode. SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback MSP430x23x, MSP430x24x(1), MSP430x2410 Device Erratasheet Copyright (c) 2007-2011, Texas Instruments Incorporated 7 Detailed Bug Description www.ti.com USCI22 USCI Module Function I2C master receiver with 10-bit slave addressing Description Unexpected behavior of the USCI_B can occur when configured in I2C master receive mode with 10-bit slave addressing under the following conditions: 1. The USCI sends first byte of slave address, the slave sends an ACK and when second address byte is sent, the slave sends a NACK. 2. Master sends a repeat start condition (if UCTXSTT = 1). 3. The first address byte following the repeated start is acknowledged. However, the second address byte is not sent; instead, the master incorrectly starts to receive data and sets UCBxRXIFG = 1. Workaround Do not use a repeated start condition; instead, set the stop condition UCTXSTP = 1 in the NACK ISR prior to the following start condition (USTXSTT = 1). USCI23 USCI Module Function UART transmit mode with automatic baud rate detection Description Erroneous behavior of the USCI_A can occur when configured in UART transmit mode with automatic baud rate detection. During transmission if a "Transmit break" is initiated (UCTXBRK = 1), the USCI_A does not deliver a stop bit of logic high; instead, it sends a logic low during the subsequent synch period. Workaround * * 8 Follow user's guide instructions for transmitting a break/synch field following UCSWRST = 1. or Set UCTXBRK = 1 before an active transmission; that is, check for bit UCBUSY = 0 and then set UCTXBRK = 1. MSP430x23x, MSP430x24x(1), MSP430x2410 Device Erratasheet SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback Copyright (c) 2007-2011, Texas Instruments Incorporated Detailed Bug Description www.ti.com USCI24 USCI Module Function Incorrect baud rate information during UART automatic baud rate detection mode Description Erroneous behavior of the USCI_A can occur when configured in UART mode with automatic baud rate detection. After automatic baud rate measurement is complete, the UART updates UCAxBR0 and UCAxBR1. Under oversampling mode (UCOS16 = 1), for baud rates that should result in UCAxBRx = 0x0002, the UART incorrectly reports it as UCAxBRx = 0x5555. Workaround When break/synch is detected following the automatic baud rate detection, the flag UCBRK flag is set to 1. Check if UCAxBRx = 0x5555 and correct it to 0x0002. USCI25 USCI Module Function TXIFG is not reset when NACK is received in I2C mode Description When the USCI_B module is configured as an I2C master transmitter, the TXIFG is not reset after a NACK is received if the master is configured to send a restart (UCTXSTT = 1 and UCTXSTP = 0). Workaround Reset TXIFG in software within the NACKIFG interrupt service routine. USCI26 USCI Module Function tbuf parameter violation in I2C multi-master mode Description In multi-master I2C systems, the timing parameter tbuf (bus free time between a stop condition and the following start) is not ensured to match the I2C specification of 4.7 s in standard mode and 1.3 s in fast mode. If the UCTXSTT bit is set during a running I2C transaction, the USCI module waits and issues the start condition on bus release, causing the violation to occur. NOTE: It is recommended to check if UCBBUSY bit is cleared before setting UCTXSTT = 1. Workaround None SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback MSP430x23x, MSP430x24x(1), MSP430x2410 Device Erratasheet Copyright (c) 2007-2011, Texas Instruments Incorporated 9 Detailed Bug Description www.ti.com USCI28 USCI Module Function Timing of USCI interrupts may cause device reset due to automatic clear of an IFG. Description When certain USCI I2C interrupt flags (IFGs) are set and an automatic flag-clearing event on the I2C bus occurs, it results in an errant ISR call to the reset vector. This happens only when the IFG is cleared within a critical time window (~6 CPU clock cycles) after a USCI interrupt request occurs and before the interrupt servicing is initiated. The affected interrupts are UCBxTXIFG, UCSTPIFG, UCSTTIFG, and UCNACKIFG. The automatic flag-clearing scenarios occur in the following situations: * A pending UCBxTXIFG interrupt request is cleared on the falling SCL clock edge following a NACK. * A pending UCSTPIFG, UCSTTIFG, or UCNACKIFG interrupt request is cleared by a following Start condition. Workaround * * * Poll the affected flags instead of enabling the interrupts. or Ensure the above mentioned flag-clearing events occur after a time delay of 6 CPU clock cycles has elapsed since the interrupt request occurred and was accepted. or At program start, check any applicable enabled IE bits such as UCBxTXIE, UCBxRXIE, UCSTTIE, UCSTPIE, or UCNACKIE for a reset (A PUC clears all of the IE bits of interest). If no PUC occurred, then the device ran into the above mentioned errant condition, and the program counter needs to be restored using an RETI instruction. ; ------- Workaround (3) example for TXIFG -----------NOTE: For assembly code, use code shown here and insert prior to user code. main bit.b #UCBxTXIE ,&IE2 jz start_normal reti start_normal ... ; if TXIE is set, errant call occurred ; if not start main program ; else return from interrupt call ; Application code continues NOTE: For C code, the workaround needs to be executed prior to the CSTARTUP routine. The steps for modifying the CSTARTUP routine are IDE dependent. Examples for Code Composer and IAR Embedded Workbench are shown. IAR Embedded Workbench 1. The file cstartup.s43 is found at: ...\IAR Systems\<Current Embedded Workbench Version>\430\src\lib\430 2. Create a local copy of this file and link it to the project. Do not rename the file. 3. In the copy, insert the following code prior to stack pointer initialization: #define IE2 (0x0001) BIT.B #0x08,&IE2 ; if TXIE is set, errant call occurred JZ Start_Normal ; if not start main program RETI ; else return from interrupt call // Initialize SP to point to the top of the stack. Start_Normal MOV #SFE(CSTACK), SP 10 MSP430x23x, MSP430x24x(1), MSP430x2410 Device Erratasheet SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback Copyright (c) 2007-2011, Texas Instruments Incorporated Detailed Bug Description www.ti.com // Ensure that main is called. Code Composer 1. The file boot.c is found at ...\Texas Instruments\<Current Code Composer Version> \tools\compiler\MSP430\lib\rtssrc.zip 2. Extract the file from rtssrc.zip and create a local copy. Link the copy to the project. Do not rename this file. 3. In the copy, insert the following code prior to stack pointer initialization: __asm("\t BIT.B\t #0x08,&0x0001"); // if TXIE is set, errant call occurred __asm("\t JZ\t Start_Normal"); // if not start main program __asm("\t RETI"); // else return from interrupt call __asm("Start_Normal"); // insert label /*------------------------------------------------------------------ */ /* Initialize stack pointer. Stack grows toward lower memory*/ /*-------------------------------------------------------------------*/ SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback MSP430x23x, MSP430x24x(1), MSP430x2410 Device Erratasheet Copyright (c) 2007-2011, Texas Instruments Incorporated 11 Detailed Bug Description www.ti.com USCI30 USCI Module Function I2C mode master receiver / slave receiver Description The USCI I2C module, when configured as a receiver (master or slave), performs a double-buffered receive operation. For example, in a transaction of two bytes, after the first byte is moved from the receive shift register to the receive buffer, the byte is acknowledged and the state machine allows the reception of the next byte. If the receive buffer has not been cleared of its contents by reading the UCBxRXBUF register by the time the seventh bit of the following data byte is received, an error condition may occur on the I2C bus. Depending on the USCI configuration, the following may occur: * If the USCI is configured as an I2C master receiver, an unintentional repeated start condition can be triggered or the master can switch into an idle state (I2C communication aborted). The reception of the current data byte is not successful in this case. * If the USCI is configured as I2C slave receiver, the slave can switch to an idle state, stalling I2C communication. The reception of the current data byte is not successful in this case. The USCI I2C state machine notifies the master of the aborted reception with a NACK. Note that the error condition described above occurs only within a limited window of the seventh bit of the current byte being received. If the receive buffer is read outside of this window (before or after), then the error condition does not occur. Workaround The error condition can be avoided by servicing the UCBxRXIFG in a timely manner. This can be done by (a) servicing the interrupt and ensuring UCBxRXBUF is read promptly or (b) using the DMA to automatically read bytes from receive buffer upon UCBxRXIFG being set. OR If the receive buffer cannot be read out in time, test the I2C clock line before the UCBxRXBUF is read out to ensure that the critical window has elapsed. This is done by checking if the clock line low status indicator bit UCSCLLOW is set for at least three USCI bit clock cycles; that is, 3 x tBitClock. NOTE: The last byte of the transaction must be read directly from UCBxRXBUF. For all other bytes, follow the workaround. Code flow for workaround: 1. Enter RX ISR for reading receiving bytes 2. Check if UCSCLLOW.UCBxSTAT == 1 3. If no, repeat step 2 until set. 4. If yes, repeat step 2 for a time period > 3 x tBitClock, where tBitClock = 1/ fBitClock 5. If window of 3 x tBitClock cycles has elapsed, it is safe to read UCBxRXBUF. 12 MSP430x23x, MSP430x24x(1), MSP430x2410 Device Erratasheet SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback Copyright (c) 2007-2011, Texas Instruments Incorporated Detailed Bug Description www.ti.com XOSC5 LFXT1 Module Function LF crystal failures may not be properly detected by the oscillator fault circuitry Description The oscillator fault error detection of the LFXT1 oscillator in low-frequency mode (XTS = 0) may not work reliably, causing a failing crystal to go undetected by the CPU; that is, OFIFG is not set. Workaround None XOSC6 XT2 Module Function XT2 crystal failures may not be properly detected by the oscillator fault circuit Description The XT2OF flag should be set if the XT2 frequency falls below 30 kHz. If there is no oscillation at all, the flag operates properly. However, 0 kHz to 30 kHz produces an undefined state on XT2OF. When this occurs, OFIFG is not set. Workaround Do not depend on the fault detection circuitry to accurately detect all failures. SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback MSP430x23x, MSP430x24x(1), MSP430x2410 Device Erratasheet Copyright (c) 2007-2011, Texas Instruments Incorporated 13 14 MSP430x23x, MSP430x24x(1), MSP430x2410 Device Erratasheet SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback Copyright (c) 2007-2011, Texas Instruments Incorporated Appendix A www.ti.com Appendix A Prior Versions MSP430F233 MSP430F235 MSP430F2410 MSP430F247 MSP430F2471 MSP430F248 MSP430F2481 MSP430F249 FLASH24 FLASH25 FLASH27 FLASH36 PORT11 PORT12 TA12 TA16 TAB22 TB2 TB16 USCI20 USCI21 FLASH19 CPU19 BCL13 CPU8 BCL12 A COMP2 ADC25 Device Rev: The checkmark means that the issue is present in the specified revision. B C D E A B C D E A B C D E A B C D E A B C D E A B C D E A B C D E A B C D E SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback Copyright (c) 2007-2011, Texas Instruments Incorporated Prior Versions 15 Appendix A 16 Prior Versions BCL12 BCL13 COMP2 CPU8 CPU19 FLASH19 FLASH24 FLASH25 FLASH27 FLASH36 PORT11 PORT12 TA12 TA16 TAB22 TB2 TB16 USCI20 USCI21 MSP430F2491 ADC25 Device Rev: www.ti.com A B C D E SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback Copyright (c) 2007-2011, Texas Instruments Incorporated Appendix A MSP430F235 MSP430F2410 MSP430F247 MSP430F2471 MSP430F248 MSP430F2481 MSP430F249 MSP430F2491 USCI23 USCI24 USCI25 USCI26 USCI28 USCI30 XOSC5 XOSC6 XOSC8 MSP430F233 USCI22 Device Rev: www.ti.com A B C D E A B C D E A B C D E A B C D E A B C D E A B C D E A B C D E A B C D E A B C D E SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback Copyright (c) 2007-2011, Texas Instruments Incorporated Prior Versions 17 Detailed Bug Description A.1 www.ti.com Detailed Bug Description BCL13 Basic Clock Module Function Exiting reset state with slow VCC rise time Description When subject to very slow VCC rise times, the device may enter a state in which the DCO does not oscillate. No JTAG access or program execution is possible, and the device remains in the reset state until the supply voltage is disconnected. Workaround Apply a VCC power-on ramp 10 V/s under all power-on/power-cycle scenarios. COMP2 Comparator_A+ Module Function Configuring the port disable register (CAPD) Description According to the user's guide, each bit in the CAPD register should correspond with its associated port I/O number. For example, when bit 0 of CAPD is set, the port disable function of pin Px.0 is enabled, bit 1 controls Px.1, and so on (where Px is the port that contains the comparator inputs). However, on this device, the bits of the CAPD register correspond with the Comparator_A input number. For example, bit 0 of CAPD controls the CA0 input, bit 1 controls CA1, etc. This difference matters when the port I/O number is not the same as the comparator input number. If the wrong CAPD bit is set, the port I/O function for the wrong pin is disabled. Also, the analog signal applied to the comparator input pin being used may cause a parasitic current to flow from VCC to GND. See the Comparator_A+ chapter of the MSP430x2xx Family User's Guide (SLAU144) for more information on CAPD. Workaround None FLASH25 Flash Module Function Marginal read mode is not functional Description The control bits for marginal read mode contained in the FCTL4 register are automatically cleared by any flash access. This prevents the marginal read mode from being used. Workaround It is possible to read out memory contents in marginal read mode if the indexed addressing mode X(Ry) is used to access the flash memory. In this case, the FCTL4 control bits are not cleared, and the marginal read mode works as expected. It is recommended to write the code for reading the flash memory contents in assembler, as this allows full control over the used addressing mode. Note that certain assemblers may optimize an indexed addressing source operation of 0(Ry) to an indirect register mode @Ry operation, which does not work. The following is an example of reading the word memory location 0x4000 in marginal read mode, preventing a possible assembler optimization: mov.w dec.w mov.w 18 Prior Versions #0x4000,R15 R15 1(R15),R12 ; Pointer to target address ; Decrement pointer ; Read memory contents at R15+1, store result in R12 SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback Copyright (c) 2007-2011, Texas Instruments Incorporated Detailed Bug Description www.ti.com PORT11 Digital I/O Module, Port 3 Function Pullup for P3.6 controlled by bit 0 Description According to the user's guide, the internal pullup of an I/O should be enabled when a corresponding bit from PxREN and PxOUT are both set. For example, in the case of P3.6, this should be bit 6. However, P3.6 is currently controlled by bit 0 instead. Bit 0 also controls P3.0, as expected. The pulldown resistors operate properly and are not affected by this errata. Workaround If bit 6 of PxREN is set, bits 0 and 6 of PxOUT should be set/cleared together. If P3.6 is to be configured for pullup/pulldown, P3.0 must have the same configuration. The workaround options are: * Configure both P3.0 and P3.6 with pulldowns (bits 0/6 of PxREN set, bits 0/6 of PxOUT cleared). * Configure both P3.0 and P3.6 with pullups (bits 0/6 of PxREN set/cleared, bits 0/6 of PxOUT set). * Do not use the pullup/pulldown feature on these pins (bits 0/6 of PxREN cleared). SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback Copyright (c) 2007-2011, Texas Instruments Incorporated Prior Versions 19 Detailed Bug Description www.ti.com USCI21 USCI Module Function UART IrDA receiver filter Description The IrDA receive filter can be used to filter pulses with length UCAIRRXFL configured in UCAxIRRCTL register. If UCIRRXFE is set the IrDA receive decoder may filter out pulses longer than the configured filter length depending on frequency of BRCLK. This results in framing errors or corrupted data on the receiver side. Workaround Depending on the used baud rate and the configured filter length, a maximum frequency for BRCLK needs to be set to avoid this issue: Max BRCLK = Filter Length + 64 Baud Rate x 16 x 2 3 x 106 Baud Rate 9600 19200 38400 56000 20 Prior Versions Filter Length UCIRRXFL (dec) Max BRCLK (MHz) 64 3.28 32 2.46 16 2.05 8 1.84 4 1.74 2 1.69 1 1.66 0 1.64 64 6.55 32 4.92 16 4.1 8 3.69 4 3.48 2 3.38 1 3.33 0 3.28 64 13.11 32 9.83 16 8.19 8 7.37 4 6.96 2 6.76 1 6.66 0 6.55 64 19.11 32 14.34 16 11.95 8 10.75 4 10.15 2 9.86 1 9.71 0 9.56 SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback Copyright (c) 2007-2011, Texas Instruments Incorporated Detailed Bug Description www.ti.com XOSC8 LFXT1 Module Function ACLK failure when crystal ESR is below 40 k Description When ACLK is sourced by a low-frequency crystal with an ESR below 40 k, the duty cycle of ACLK may fall below the specification; the OFIFG may become set or, in some instances, ACLK may stop completely. Workaround See the application report XOSC8 Guidance (SLAA423) for information regarding working with this erratum. SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback Copyright (c) 2007-2011, Texas Instruments Incorporated Prior Versions 21 Revision History www.ti.com Revision History Changes from F Revision (May 2011) to G Revision ...................................................................................................... Page * * * * Changed silicon rev to E in Current Version; removed USCI21 and XOSC8 .................................................... 1 Added silicon rev E to Prior Versions ................................................................................................ 15 Moved USCI21 description to Prior Versions ....................................................................................... 20 Moved XOSC8 description to Prior Versions ........................................................................................ 21 NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 22 Revision History SLAZ039G - November 2007 - Revised July 2011 Submit Documentation Feedback Copyright (c) 2007-2011, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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