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by MC68336/376PP/D
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This document contains information on a new product. Specifications and information herein are subject to change without notice.
© MOTOROLA INC., 1996
MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
MC68336/376
Product Preview
32-Bit Modular Microcontroller
Features
• Central Processing Unit (CPU32)
— 32-bit architecture
— Virtual memory implementation
— Table look-up and interpolate instruction
— Improved exception handling for controller applications
— High level language support
— Background debugging mode
— Fully static operation
• System Integration Module (SIM)
— External bus support
— Programmable chip select outputs
— System protection logic
— Watchdog timer, clock monitor and bus monitor
— Two 8-bit dual function input/output ports
— One 7-bit dual function output port
— Phase-locked loop (PLL) clock system
• Standby RAM Module (SRAM)
— 4-Kbytes of static RAM
— No standby supply
• Masked ROM Module (MRM)
— 8-Kbyte array, accessible as bytes or words
— User selectable default base address
— User selectable bootstrap ROM function
— User selectable ROM verification code
• 10-Bit Queued Analog-to-Digital Converter (QADC)
— 16 channels internally; up to 44 directly accessible channels with external multiplexing
— Six automatic channel selection and conversion modes
— Two channel scan queues of variable length, each with a variable number of sub-queues
— 40 result registers and three result alignment formats
— Programmable input sample time
— Direct control of external multiplexers
• Queued Serial Module (QSM)
— Enhanced serial communications interface (SCI)
— Modulus baud rate generator
— Parity detection
— Queued serial peripheral interface (QSPI)
— 80-byte static RAM to perform queued operations
— Up to 16 automatic transfers
— Continuous cycling, 8 to 16 bits per transfer, LSB or MSB first
— Dual function I/O pins
MOTOROLA MC68336/376
2 MC68336/376PP/D
• Configurable Timer Module Version 4 (CTM4)
— Two 16-bit modulus counter submodules (MCSMs)
— 16-bit free-running counter submodule (FCSM)
— Four double-action submodules (DASMs)
— Four pulse-width submodules (PWMSMs)
• Time Processor Unit (TPU)
— Dedicated micro-engine operating independently of the CPU32
— 16 independent programmable channels and pins
— Each channel has an event register consisting of a 16-bit capture register, a 16-bit compare
register and a 16-bit comparator
— Any channel can perform any time function
— Each channel has six or eight 16-bit parameter registers
— Each timer function may be assigned to more than one channel
— Two timer counter registers with programmable prescalers
— Each channel can be synchronized to one or both counters
— Selectable channel priority levels
• Static RAM Module with TPU Emulation Capability (TPURAM)
— 3.5 Kbytes of static RAM
— External V
STBY
pin for separate standby supply
— May be used as normal RAM or TPU microcode emulation RAM
• CAN 2.0B Controller Module (TouCAN™)
— Full implementation of CAN protocol specification, version 2.0 A and B
— 16 receive/transmit message buffers of 0 to 8 bytes data length
— Global mask register for message buffers 0 to 13
— Independent mask registers for message buffers 14 and 15
— Programmable transmit-first scheme: lowest ID or lowest buffer number
— 16-bit free-running timer for message time-stamping
— Low-power sleep mode with programmable wake-up on bus activity
MC68336/376 MOTOROLA
MC68336/376PP/D 3
Figure 1 MC68336/376 Block Diagram
TXD/PQS7
PCS3/PQS6
PCS2/PQS5
PCS1/PQS4
PCS0/SS/PQS3
SCK/PQS2
MOSI/PQS1
MISO/PQS0
CS[10:0]
QSM
PORT QS
CTM4
1
FCSM
2
MCSMs
DASMs
PWMSMs
4
4
3.5
KBYTE
TPU
CPU32
CHIP
SELECTS
EBI
CLOCK
TEST
CONTROL
PORT C
RXD
BGACK
BR
BG
FC0
FC1
FC2
ADDR
ADDR21/CS8/PC5
ADDR22/CS9/PC6
ADDR23/CS10/ECLK
ADDR20/CS7/PC4
ADDR19/CS6/PC3
FC2/CS5/PC2
FC1/CS4/PC1
FC0/CS3/PC0
DSACK0
DSACK1
AVEC
RMC
DS
AS
SIZ0
SIZ1
SIZ1/PE7
SIZ0/PE6
AS/PE5
DS/PE4
RMC/PE3
AVEC/PE2
DSACK1/PE1
DSACK0/PE0
ADDR[18:0]
DATA[15:0]
IRQ[7:1]
R/W
RESET
HALT
BERR
MODCLK/PF0
IRQ7/PF7
IRQ6/PF6
IRQ5/PF5
IRQ4/PF4
IRQ3/PF3
IRQ2/PF2
IRQ1/PF1
MODCLK
CLKOUT
XTAL
EXTAL
XFC
VDDSYN
TSTME
QUOT
FREEZE
BKPT
IFETCH
IPIPE
DSI
DSO
DSCLK
FREEZE/QUOT
TSTME/TSC
BKPT/DSCLK
IFETCH/DSI
IPIPE/DSO
CONTROL
CONTROLCONTROL CONTROL
PORT EPORT F
BGACK/CS2
BG/CS1
BR/CS0
IMB
CPWM[8:5]
CTD[10:9]/CTD[4:3]
VSTBY
T2CLK
TPUCH[15:0]
CSBOOT
VDD
VSS
CTM2C
336/376 BLOCK
[23:19]
1. PORT A PINS INCORPORATE OPEN DRAIN PULL DOWN DRIVERS
4K
SRAM
QADC
PORT QB
PORT QA
VRH
VRL
PQB[7:0]
PQA[7:0]1
VSSA
VDDA
CANRX0
CANTX0
TSC
TPURAM
TOUCAN
MC68376 ONLY
8K
MRM
MC68376
ONLY
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