Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single Read/Write control pin
• Clock controlled, registered address,
data and control
• Interleaved or linear burst sequence control us-
ing MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 119-ball PBGA, and 165-
ball PBGA packages
• Power supply:
NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%)
NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
• Industrial temperature available
• Lead-free available
DESCRIPTION
The 4 Meg 'NLF/NVF' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
networking and communications applications. They are
organized as 128K words by 36 bits and 256K words by
18 bits, fabricated with ISSI's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the ADV
input. When the ADV is HIGH the internal burst counter
is incremented. New external addresses can be loaded
when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
128K x 36 and 256K x 18
4Mb, FLOW THROUGH 'NO WAIT'
STATE BUS SRAM AUGUST 2011
FAST ACCESS TIME
Symbol Parameter 6.5 7.5 Units
tkq Clock Access Time 6.5 7.5 ns
tkc Cycle Time 7.5 8.5 ns
Frequency 133 117 MHz
2 Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
BLOCK DIAGRAM
ADV
WE }
BW
Ÿ
X
(X= a-d, or a,b)
CE
CE2
CE2
CONTROL
LOGIC
128Kx36;
256Kx18
MEMORY ARRAY
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
CONTROL
LOGIC
BUFFER
ADDRESS
REGISTER
x 36: A [0:16] or
x 18: A [0:17]
CLK
CKE
A2-A16 or A2-A17
A0-A1 A'0-A'1
BURST
ADDRESS
COUNTER
MODE
DATA-IN
REGISTER
DATA-IN
REGISTER
CONTROL
REGISTER
OE
ZZ
36 or 18
K
K
DQx/DQPx
K
K
Integrated Silicon Solution, Inc. — www.issi.com 3
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
Bottom View
165-Ball, 13 mm x 15mm BGA
Bottom View
119-Ball, 14 mm x 22 mm BGA
4 Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
1 2 3 4 5 6 7 8 9 10 11
A NC A CE BWcBWbCE2CKE ADV NC A NC
B NC A CE2 BWdBWaCLK WE OE NC A NC
C DQPc NC Vddq VSS VSS VSS VSS VSS Vddq NC DQPb
D DQc DQc Vddq Vdd VSS VSS VSS Vdd Vddq DQb DQb
E DQc DQc Vddq Vdd VSS VSS VSS Vdd Vddq DQb DQb
F DQc DQc Vddq Vdd VSS VSS VSS Vdd Vddq DQb DQb
G DQc DQc Vddq Vdd VSS VSS VSS Vdd Vddq DQb DQb
H NC NC NC Vdd VSS VSS VSS Vdd NC NC ZZ
J DQd DQd Vddq Vdd VSS VSS VSS Vdd Vddq DQa DQa
K DQd DQd Vddq Vdd VSS VSS VSS Vdd Vddq DQa DQa
L DQd DQd Vddq Vdd VSS VSS VSS Vdd Vddq DQa DQa
M DQd DQd Vddq Vdd VSS VSS VSS Vdd Vddq DQa DQa
N DQPd NC Vddq VSS NC NC NC VSS Vddq NC DQPa
P NC NC A A NC A1* NC A A A NC
R MODE NC A A NC A0* NC A A A A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol Pin Name
A Address Inputs
A0, A1 Synchronous Burst Address Inputs
ADV Synchronous Burst Address Advance/
Load
WE Synchronous Read/Write Control
Input
CLK Synchronous Clock
CKE Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
BWx (x=a-d) Synchronous Byte Write Inputs
OE Output Enable
ZZ Power Sleep Mode
MODE Burst Sequence Selection
VDD 3.3V/2.5V Power Supply
NC No Connect
DQx Data Inputs/Outputs
DQPx Parity Data I/O
VDDQ Isolated output Power Supply
3.3V/2.5V
VSS Ground
PIN CONFIGURATION — 128K x 36, 165-Ball PBGA (TOP VIEW)
Integrated Silicon Solution, Inc. — www.issi.com 5
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
119-PIN PBGA PACKAGE CONFIGURATION 128K x 36 (TOP VIEW)
1234567
AA
BWb
BNC
CNC
DDQc DQPc Vss
EDQc DQc Vss
F
VDDQ DQc
GDQc DQc
HDQc DQc
J
VDDQ VDD
KDQd DQd
L
DQd DQd
MVDDQ DQd
NDQd DQd
Vss
P
NC
DQPd
RA
CE2
MODE
A0*
A
A
A
VSS
VSS
VSS
VSS
BWd
V
SS
VSS
VSS
NC
NC
VDD
VDD VDD
VDD
NC
Vss
Vss
Vss
Vss
Vss
NC
CE2
NCA
NC
T
UVDDQ
NC
VDDQ
DQd
A
NC
NC NC
A
A
BWc
NC
A1*
CKE
NC
CLK
NC
WE
NC
OE
CE
NC
ADV
NC
A
NC
BWa
A
A
A
DQPa
DQa
DQa
DQa
DQa
DQb
DQb
DQb
DQb
DQPb
A
A
VDDQ
ZZ
DQa
DQa
VDDQ
DQa
DQa
VDDQ
DQb
DQb
VDDQ
DQb
DQb
NC
VDDQ
VSS
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol Pin Name
A Address Inputs
A0, A1 Synchronous Burst Address Inputs
ADV Synchronous Burst Address Advance/
Load
WE Synchronous Read/Write Control
Input
CLK Synchronous Clock
CKE Clock Enable
CE Synchronous Chip Select
CE2 Synchronous Chip Select
CE2 Synchronous Chip Select
BWx (x=a-d) Synchronous Byte Write Inputs
OE Output Enable
ZZ Power Sleep Mode
MODE Burst Sequence Selection
Vdd Power Supply
VSS Ground
NC No Connect
DQa-DQd Data Inputs/Outputs
DQPa-Pd Parity Data I/O
Vddq Output Power Supply
6 Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
165-PIN PBGA PACKAGE CONFIGURATION 256K x 18 (TOP VIEW)
PIN DESCRIPTIONS
Symbol Pin Name
A Address Inputs
A0, A1 Synchronous Burst Address Inputs
ADV Synchronous Burst Address Advance/
Load
WE Synchronous Read/Write Control
Input
CLK Synchronous Clock
CKE Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
BWx (x=a,b) Synchronous Byte Write Inputs
OE Output Enable
ZZ Power Sleep Mode
1234567891011
AABWbCKE
B NC A WE OE
C NC NC Vss Vss
D NC DQb Vss Vss NC
E NC DQb Vss Vss Vss
F
NC DQb NC
G NC DQb
NC
NC
H NC NC
VDDQ
J
DQb NC DQa
KDQb NC
L
DQb NC Vss
M DQb NC Vss
N DQPb NC Vss Vss NC
P NC NC A1* NC
R MODE ANC
CE2
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
AA
A
A
A
A
A
A
AA
A
NC
NC A
A
CE
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
NC
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
NC
CE2
CLK
Vss
NC
A0*
NC
Vss
Vss
Vss
Vss
Vss
Vss
ADV
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQa
DQa
DQa
NC
NC
NC
NC
NC
NC
NC
ZZ
DQa
DQa
DQa
DQa
DQPa
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
MODE Burst Sequence Selection
VDD 3.3V/2.5V Power Supply
NC No Connect
DQx Data Inputs/Outputs
DQPx Parity Data I/O
VDDQ Isolated output Power Supply
3.3V/2.5V
VSS Ground
Integrated Silicon Solution, Inc. — www.issi.com 7
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
119-PIN PBGA PACKAGE CONFIGURATION 256K x 18 (TOP VIEW)
PIN DESCRIPTIONS
Symbol Pin Name
A Address Inputs
A0, A1 Synchronous Burst Address Inputs
ADV Synchronous Burst Address Advance/
Load
WE Synchronous Read/Write Control
Input
CLK Synchronous Clock
CKE Clock Enable
CE Synchronous Chip Select
CE2 Synchronous Chip Select
CE2 Synchronous Chip Select
BWx (x=a,b) Synchronous Byte Write Inputs
OE Output Enable
ZZ Power Sleep Mode
MODE Burst Sequence Selection
Vdd Power Supply
VSS Ground
NC No Connect
DQa-DQb Data Inputs/Outputs
DQPa-Pb Parity Data I/O
Vddq Output Power Supply
1234567
AA
BNC
CNC
DDQb Vss
EDQb Vss
F
VDDQ
GDQb
HDQb
J
VDDQ VDD
KDQb
L
DQb
MVDDQ DQb
NDQb NC
Vss
P
NC
DQPb
RA
CE2
MODE
A
A0*
A
A
V
SS
V
SS
V
SS
V
SS
NC
V
SS
V
SS
NC
NC
VDD
VDD VDD
VDD
NC
Vss
Vss
Vss
Vss
Vss
NC
CE2
NCA
NC
T
UVDDQ
NC
VDDQ
A
NC
NC NC
A
A
BWb
NC
A1*
CKE
NC
CLK
NC
WE
NC
OE
CE
NC
ADV
NC
A
NC
BWa
A
A
A
DQPa
DQa
DQa
DQa
DQa
A
A
VDDQ
ZZ
DQa
DQa
VDDQ
DQa
DQa
VDDQ
VDDQ
NC
VDDQ
NC
NC
NC
NC
NC
NC
NC
NC
A
V
SS
V
SS
NC
NC
NC
NC
NC
NC
NC
NC
NC
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
8 Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
PIN CONFIGURATION
100-Pin TQFP
256K x 18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
NC
NC
V
DDQ
Vss
NC
DQPa
DQa
DQa
Vss
V
DDQ
DQa
DQa
Vss
NC
V
DD
ZZ
DQa
DQa
V
DDQ
Vss
DQa
DQa
NC
NC
Vss
V
DDQ
NC
NC
NC
NC
NC
NC
V
DDQ
Vss
NC
NC
DQb
DQb
Vss
V
DDQ
DQb
DQb
NC
V
DD
NC
Vss
DQb
DQb
V
DDQ
Vss
DQb
DQb
DQPb
NC
Vss
V
DDQ
NC
NC
NC
A
A
CE
CE2
NC
NC
BWb
BWa
CE2
V
DD
Vss
CLK
WE
CKE
OE
ADV
NC
NC
A
A
MODE
A
A
A
A
A1
A0
NC
NC
Vss
V
DD
NC
NC
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb
DQb
DQb
V
DDQ
Vss
DQb
DQb
DQb
DQb
Vss
V
DDQ
DQb
DQb
Vss
NC
V
DD
ZZ
DQa
DQa
V
DDQ
Vss
DQa
DQa
DQa
DQa
Vss
V
DDQ
DQa
DQa
DQPa
DQPc
DQc
DQc
V
DDQ
Vss
DQc
DQc
DQc
DQc
Vss
V
DDQ
DQc
DQc
NC
V
DD
NC
Vss
DQd
DQd
V
DDQ
Vss
DQd
DQd
DQd
DQd
Vss
V
DDQ
DQd
DQd
DQPd
A
A
CE
CE2
BW
d
BWc
BW
b
BW
a
CE2
V
DD
Vss
CLK
WE
CKE
OE
ADV
NC
NC
A
A
MODE
A
A
A
A
A1
A0
NC
NC
Vss
V
DD
NC
NC
A
A
A
A
A
A
A
128K x 36
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A Synchronous Address Inputs
CLK Synchronous Clock
ADV Synchronous Burst Address Advance
BWa-BWd Synchronous Byte Write Enable
WE Write Enable
CKE Clock Enable
Vss Ground for Core
NC Not Connected
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd Synchronous Data Input/Output
DQPa-DQPd Parity Data I/O
MODE Burst Sequence Selection
Vdd +3.3V/2.5V Power Supply
VSS Ground for output Buffer
Vddq
Isolated Output Buffer Supply: +3.3V/2.5V
ZZ Snooze Enable
Integrated Silicon Solution, Inc. — www.issi.com 9
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
SYNCHRONOUS TRUTH TABLE(1)
Address
Operation Used CE CE2 CE2 ADV WE BWx OE CKE CLK
Not Selected N/A H X X L X X X L ↑
Not Selected N/A X L X L X X X L ↑
Not Selected N/A X X H L X X X L ↑
Not Selected Continue N/A X X X H X X X L ↑
Begin Burst Read External Address L H L L H X L L ↑
Continue Burst Read Next Address X X X H X X L L ↑
NOP/Dummy Read External Address L H L L H X H L ↑
Dummy Read Next Address X X X H X X H L ↑
Begin Burst Write External Address L H L L L L X L ↑
Continue Burst Write Next Address X X X H X L X L ↑
NOP/Write Abort N/A L H L L L H X L ↑
Write Abort Next Address X X X H X H X L ↑
Ignore Clock Current Address X X X X X X X H ↑
Notes:
1. "X" means don't care.
2. The rising edge of clock is symbolized by ↑
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WE = L means Write operation in Write Truth Table.
WE = H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and OE).
BURST
READ
DESELECT
BURST
WRITE
BEGIN
READ
BEGIN
WRITE
READ
WRITE
READ WRITE
BURST
BURST
BURST
DS
DS
DS
READ
DSDS
READ WRITE
WRITE
BURST BURST
WRITE
READ
STATE DIAGRAM
10 Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
ASYNCHRONOUS TRUTH TABLE(1)
Operation ZZ OE I/O STATUS
Sleep Mode H X High-Z
Read L L DQ
L H High-Z
Write L X Din, High-Z
Deselected L X High-Z
Notes:
1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data
bus contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x18)
Operation WE BWa BWb
READ H X X
WRITE BYTE a L L H
WRITE BYTE b L H L
WRITE ALL BYTEs L L L
WRITE ABORT/NOP L H H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
Integrated Silicon Solution, Inc. — www.issi.com 11
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or NC)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
WRITE TRUTH TABLE (x36)
Operation WE BWa BWb BWc BWd
READ H X X X X
WRITE BYTE a L L H H H
WRITE BYTE b L H L H H
WRITE BYTE c L H H L H
WRITE BYTE d L H H H L
WRITE ALL BYTEs L L L L L
WRITE ABORT/NOP L H H H H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
12 Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
OPERATING RANGE (IS61NLFx)
Range Ambient Temperature VDD VDDq
Commercial 0°C to +70°C 3.3V ± 5% 3.3V / 2.5V ± 5%
Industrial -40°C to +85°C 3.3V ± 5% 3.3V / 2.5V ± 5%
LINEAR BURST ADDRESS TABLE (MODE = VSS)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
TSTG Storage Temperature –65 to +150 °C
Pd Power Dissipation 1.6 W
IouT Output Current (per I/O) 100 mA
VIn, VouT Voltage Relative to VSS for I/O Pins –0.5 to Vddq + 0.3 V
VIn Voltage Relative to VSS for –0.3 to 4.6 V
for Address and Control Inputs
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precau-
tions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
0,0
1,0
0,1A1', A0' = 1,1
Integrated Silicon Solution, Inc. — www.issi.com 13
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
6.5 7.5
MAX MAX
Symbol Parameter Test Conditions
Temp. range x18 x36 x18 x36 Uni
t
Icc AC Operating Device Selected, Com. 175 175 155 155 mA
Supply Current OE = VIh, ZZ ≤ VIl, Ind. 180 180 160 160
All Inputs ≤ 0.2V or ≥ Vdd – 0.2V,
Cycle Time ≥ tkc min. typ.(2) 120 110
ISb Standby Current Device Deselected, com. 90 90 90 90 mA
TTL Input Vdd = Max., Ind. 100 100 100 100
All Inputs ≤ VIl or ≥ VIh,
ZZ ≤ VIl, f = Max.
ISbI Standby Current Device Deselected, Com. 70 70 70 70 mA
cmoS Input Vdd = Max., Ind. 75 75 75 75
VIn
≤
VSS + 0.2V or ≥ Vdd – 0.2V
f = 0 typ.(2) 40 40
ISb2 Sleep Mode ZZ > VIh Com. 30 30 30 30 mA
Ind. 35 35 35 35
typ.(2) 20 20
Note:
1. MODE pin has an internal pullup and should be tied to Vdd or VSS. It exhibits ±100 µA maximum leakage current when tied to ≤
VSS + 0.2V or ≥ Vdd – 0.2V.
2. Typical values are measured at Vdd = 3.3V, TA = 25oC and not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
3.3V 2.5V
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
Voh Output HIGH Voltage Ioh = –4.0 mA (3.3V) 2.4 — 2.0 — V
Ioh = –1.0 mA (2.5V)
Vol Output LOW Voltage Iol = 8.0 mA (3.3V) — 0.4 — 0.4 V
Iol = 1.0 mA (2.5V)
VIh Input HIGH Voltage 2.0 Vdd + 0.3 1.7 Vdd + 0.3 V
VIl Input LOW Voltage –0.3 0.8 –0.3 0.7 V
IlI Input Leakage Current VSS ≤ VIn ≤ Vdd(1) –5 5 –5 5 µA
Ilo Output Leakage Current VSS ≤ VouT ≤ Vddq, OE = VIh –5 5 –5 5 µA
OPERATING RANGE (IS61NVFx)
Range Ambient Temperature VDD VDDq
Commercial 0°C to +70°C 2.5V ± 5% 2.5V ± 5%
Industrial -40°C to +85°C 2.5V ± 5% 2.5V ± 5%
14 Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
3.3V I/O AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
317 Ω
5 pF
Including
jig and
scope
351 Ω
OUTPUT
+3.3V
Figure 1 Figure 2
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
cIn Input Capacitance VIn = 0V 6 pF
couT Input/Output Capacitance VouT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°c, f = 1 MHz, Vdd = 3.3V.
3.3V I/O OUTPUT LOAD EQUIVALENT
1.5V
OUTPUT
Zo= 50Ω
50Ω
Integrated Silicon Solution, Inc. — www.issi.com 15
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
2.5V I/O AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 2.5V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.25V
and Reference Level
Output Load See Figures 3 and 4
Z
O
= 50Ω
1.25V
50Ω
OUTPUT
1,667 Ω
5 pF
Including
jig and
scope
1,538 Ω
OUTPUT
+2.5V
Figure 3 Figure 4
2.5V I/O OUTPUT LOAD EQUIVALENT
16 Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
6.5 7.5
Symbol Parameter Min. Max. Min. Max. Unit
fmax Clock Frequency — 133 — 117 MHz
tkc Cycle Time 7.5 — 8.5 — ns
tkh Clock High Time 2.2 — 2.5 — ns
tkl Clock Low Time 2.2 — 2.5 — ns
tkq Clock Access Time — 6.5 — 7.5 ns
tkqx(2) Clock High to Output Invalid 2.5 — 2.5 — ns
tkqlZ(2,3) Clock High to Output Low-Z 2.5 — 2.5 — ns
tkqhZ(2,3) Clock High to Output High-Z — 3.8 — 4.0 ns
toeq Output Enable to Output Valid — 3.2 — 3.4 ns
toelZ(2,3) Output Enable to Output Low-Z 0 — 0 — ns
toehZ(2,3) Output Disable to Output High-Z — 3.5 — 3.5 ns
tAS Address Setup Time 1.5 — 1.5 — ns
twS Read/Write Setup Time 1.5 — 1.5 — ns
tceS Chip Enable Setup Time 1.5 — 1.5 — ns
tSe Clock Enable Setup Time 1.5 — 1.5 — ns
tAdVS Address Advance Setup Time 1.5 — 1.5 — ns
tdS Data Setup Time 1.5 — 1.5 — ns
tAh Address Hold Time 0.5 — 0.5 — ns
the Clock Enable Hold Time 0.5 — 0.5 — ns
twh Write Hold Time 0.5 — 0.5 — ns
tceh Chip Enable Hold Time 0.5 — 0.5 — ns
tAdVh Address Advance Hold Time 0.5 — 0.5 — ns
tdh Data Hold Time 0.5 — 0.5 — ns
tPdS ZZ High to Power Down — 2 — 2 cyc
tPuS ZZ Low to Power Down — 2 — 2 cyc
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
Integrated Silicon Solution, Inc. — www.issi.com 17
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
SLEEP MODE TIMING
SLEEP MODE ELECTRICAL CHARACTERISTICS
Symbol Parameter Conditions Min. Max. Unit
ISb2 Current during SLEEP MODE ZZ ≥ VIh 35 mA
tPdS ZZ active to input ignored 2 cycle
tPuS ZZ inactive to input sampled 2 cycle
tZZI ZZ active to SLEEP current 2 cycle
trZZI ZZ inactive to exit SLEEP current 0 ns
Don't Care
Deselect or Read Only Deselect or Read Only
tRZZI
CLK
ZZ
Isupply
All Inputs
(except ZZ)
Outputs
(Q)
ISB2
ZZ setup cycle ZZ recovery cycle
Normal
operation
cycle
tPDS tPUS
tZZI
High-Z
18 Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
READ CYCLE TIMING
CLK
ADV
Address
W
RITE
C
KE
C
E
O
E
Data Out
A1 A2 A3
tKH tKL
tKC
Don't Care
Undefined
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
tSE tHE
tAS tAH
tWS tWH
tCES tCEH
tADVS tADVH
tKQX
Q3-3 Q3-4Q3-2Q3-1Q2-4Q2-3Q2-2Q2-1
tOEHZ tKQHZ
tKQ
tOEQ
Q1-1
tOEHZ
Integrated Silicon Solution, Inc. — www.issi.com 19
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
WRITE CYCLE TIMING
CLK
ADV
Address
W
RITE
C
KE
C
E
O
E
Data In
Data Out
A1 A2 A3
t
KH
t
KL
t
KC
t
SE
t
HE
Don't Care
Undefined
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Q0-4
t
DS
t
DH
D3-3 D3-4D3-2
D3-1
D2-4
D2-3
D2-2D2-1D1-1
t
OEHZ
20 Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
SINGLE READ/WRITE CYCLE TIMING
CLK
C
KE
Address
W
RITE
C
E
ADV
O
E
Data Out
Data In
t
SE
t
HE
t
KH
t
KL
t
KC
Don't Care
Undefined
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
A1 A2 A3 A4 A5 A6 A7 A8 A9
D5
D2
t
OELZ
t
OEQ
Q1 Q3 Q4 Q6 Q7
t
DS
t
DH
Integrated Silicon Solution, Inc. — www.issi.com 21
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
CKE OPERATION TIMING
A1 A2 A3 A4 A5 A6
Q1
CLK
CKE
Address
WRITE
CE
ADV
OE
Data Out
Data In D2
t
SE
t
HE
t
KH
t
KL
t
KC
t
KQLZ
t
KQHZ
t
KQ
t
DH
t
DS
Don't Care
Undefined
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Q3 Q4
D5
22 Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
CE OPERATION TIMING
Don't Care
Undefined
CLK
CKE
Address
WRITE
CE
ADV
OE
Data Out
Data In
t
SE
t
HE
t
KH
t
KL
t
KC
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
A1 A2 A3 A4 A5
D5
D3
t
DH
t
DS
t
OELZ
t
OEQ
Q1 Q2 Q4
t
KQHZ
t
KQLZ
t
KQ
Integrated Silicon Solution, Inc. — www.issi.com 23
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
ORDERING INFORMATION (VDD = 3.3V/VDDq = 2.5V/3.3V)
Commercial Range: 0°C to +70°C
Access Time Order Part Number Package
128Kx36
6.5 IS61NLF12836A-6.5TQ 100 TQFP
IS61NLF12836A-6.5B2 119 PBGA
IS61NLF12836A-6.5B3 165 PBGA
7.5 IS61NLF12836A-7.5TQ 100 TQFP
IS61NLF12836A-7.5B2 119 PBGA
IS61NLF12836A-7.5B3 165 PBGA
256Kx18
6.5 IS61NLF25618A-6.5TQ 100 TQFP
IS61NLF25618A-6.5B2 119 PBGA
IS61NLF25618A-6.5B3 165 PBGA
7.5 IS61NLF25618A-7.5TQ 100 TQFP
IS61NLF25618A-7.5B2 119 PBGA
IS61NLF25618A-7.5B3 165 PBGA
Industrial Range: -40°C to +85°C
Access Time Order Part Number Package
128Kx36
6.5 IS61NLF12836A-6.5TQI 100 TQFP
IS61NLF12836A-6.5B2I 119 PBGA
IS61NLF12836A-6.5B3I 165 PBGA
7.5 IS61NLF12836A-7.5TQI 100 TQFP
IS61NLF12836A-7.5TQLI 100 TQFP, Lead-free
IS61NLF12836A-7.5B2I 119 PBGA
IS61NLF12836A-7.5B3I 165 PBGA
IS61NLF12836A-7.5B3LI 165 PBGA, Lead-free
256Kx18
6.5 IS61NLF25618A-6.5TQI 100 TQFP
IS61NLF25618A-6.5B2I 119 PBGA
IS61NLF25618A-6.5B3I 165 PBGA
7.5 IS61NLF25618A-7.5TQI 100 TQFP
IS61NLF25618A-7.5TQLI 100 TQFP, Lead-free
IS61NLF25618A-7.5B2I 119 PBGA
IS61NLF25618A-7.5B3I 165 PBGA
24 Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
ORDERING INFORMATION (VDD = 2.5V/VDDq = 2.5V)
Commercial Range: 0°C to +70°C
Access Time Order Part Number Package
128Kx36
6.5 IS61NVF12836A-6.5TQ 100 TQFP
IS61NVF12836A-6.5B2 119 PBGA
IS61NVF12836A-6.5B3 165 PBGA
7.5 IS61NVF12836A-7.5TQ 100 TQFP
IS61NVF12836A-7.5B2 119 PBGA
IS61NVF12836A-7.5B3 165 PBGA
256Kx18
6.5 IS61NVF25618A-6.5TQ 100 TQFP
IS61NVF25618A-6.5B2 119 PBGA
IS61NVF25618A-6.5B3 165 PBGA
7.5 IS61NVF25618A-7.5TQ 100 TQFP
IS61NVF25618A-7.5B2 119 PBGA
IS61NVF25618A-7.5B3 165 PBGA
Industrial Range: -40°C to +85°C
Access Time Order Part Number Package
128Kx36
6.5 IS61NVF12836A-6.5TQI 100 TQFP
IS61NVF12836A-6.5B2I 119 PBGA
IS61NVF12836A-6.5B3I 165 PBGA
7.5 IS61NVF12836A-7.5TQI 100 TQFP
IS61NVF12836A-7.5B2I 119 PBGA
IS61NVF12836A-7.5B3I 165 PBGA
256Kx18
6.5 IS61NVF25618A-6.5TQI 100 TQFP
IS61NVF25618A-6.5B2I 119 PBGA
IS61NVF25618A-6.5B3I 165 PBGA
7.5 IS61NVF25618A-7.5TQI 100 TQFP
IS61NVF25618A-7.5B2I 119 PBGA
IS61NVF25618A-7.5B3I 165 PBGA
Integrated Silicon Solution, Inc. — www.issi.com 25
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
26 Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
Integrated Silicon Solution, Inc. — www.issi.com 27
Rev. D
08/11/2011
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
1. CONTROLLING DIMENSION : MM .
NOTE :
Package Outline 08/28/2008
