Ordering number : EN45706 No, 4570 | | Thick Film Hybrid IC STK6215 Unidirectional DC Motor Driver with Constant-Speed Digital Servo Controller (output current: 5 A) Overview The STK6215 is a hybrid IC that combines in a single package a unidirectional DC motor driver, a PLL constant-speed controller (the LC7991) and associated peripheral components, including a separately excited oscillator, a comparator, and an FG amplifier. The motor controller uses a PLL circuit for precise motor conurol. The wide range of the STK6215s FG lock frequency allows it to handle a wide range of <Motor Driver Block> * MOSFET power elements provide high output currents (rush current), * Low loss PWM speed controller (built-in externally excited oscillator: 25 kHz) * Wide power supply voltage range (Vpss = 60 V) * Built-in motor startup overcurrent limiter function Package Dimensions applications, Since the motor driver block uses unit: mm MOSFET devices as power elements, it features high 4138 output currents (rush current) and low loss. Applications 6 * Plain paper copier DC motor drivers 60 * FAX paper transport motor drivers a) . . : wo } Other DC motor applications a | 4 w Features o- Y | 7 <Motor Controller Block> ! TT * High FG frequency upper limit (locking range: 200 to 2-3.6 0 2500 Hz) . Lal 22n20s42.0 * Built-in FG divider (FG lock upper limit with divider in use: 5000 Hz) * Speed lock indicator output directly drives an external LED. * TTL level compatible ROT input Specifications Absolute Maximum Ratings at Ta = 25C Parameter Symbol Condition Rating Unit Maximum supply voltage 1 Veol max | No signal 52 v Maximum supply voltage 2 Vec2 max | No signal 7 v Maximum motor rush current io peak max; Duty 1%, period s 100 msec 12 A Maximum input voltage Vin max 7 V Storage temperature Tatg ~40 fo +125 Cc Junction temperature Tj max 150 c Operating case temperature Te max 105 C SANYO Electric Co., Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOK YO,110 JAPAN 83093 YO 5-3096 No. 4570-1/11STK6215 Allowable Operating Ranges at Ta = 25C Parameter Symbol Condition Rating Unit Operating supply voltage 1 Vel Input active 10 to 42 v Operating supply voltage 2 Veo2 Input active 545% Vv Motor output current lo DC (Te = 25C) 5 A FET withstand voltage Voss 60 min v Input voltage Vin Vec2 v Operating Characteristics at Ta = 25C, Vecl = 24 V, Vec2 =5.0V Rating Parameter Symbol Condition " Unit tin typ max Voo2 current dissipation lec When the ROT input is used 10 18 mA Output FET saturation voltage VsaT RL =4.5 8 0.65 12 v Built-in osciltator frequency fo 2t 25 EE kHz OSC output amplitude Vop.p 19 2.3 27 Vp-p OSC output effective amplitude Vorms Pin 7 output voltage 0.54 0.66 0.80 Vims Common mode input voltage range Vicm re vole and FG amplifier 0 Voo2-1.5 v FG amplitier feedback resistance Ay 95 100 105 kQ High input level voltage Vu Inputs DIVS, PAI, PR2 and ROT 0.7 Voc2 Vec2 Vv Low input level voltage VIL 0 0.3 Veo? V High input level current hy DIV1 to DIVS, PRt and PR2 inputs 1 pA Low input level current fit aa pA High output level current lon Lock input Voy = Veco? - 0.4 -2 mA Low output level currant lo. Lock input Vg, = 0.4 V 2 mA Input frequency range txt 1 input 0.1 10.5 MHz fra FGI input 50 kHz EG lock frequency fsLock | FG Input divider off 200 2500 Hz frLock | FG input divider on 400 5000 Hz Output cul voltage Vocut Pin 5 input voltage Qo 25 mv Pin Functions Pin No. |) Symbol Function . OUT Motor output : Vis Current detection resistor connection 5 Vrel4 Motor startup current control reference vollage 6 Vec2 Power supply voltage input (+5 V) 7 Vreft HAC built-in oscillator bias voltage setting 8 Vref? Integrating amplifier reference voltage setting 9 Vref3 FG input reference voltage setting 40 FG FG input 1 Ry Integrating amplifier output 12 Mix in Integrating amplifier input 13 Mixout | PO and FO sum output (PO and FO each have a 100 kQ output resistance.) 14 xl Crystal oscillator connection (input) 15 XO Crystal oscillator connection {output} 16 DIV1 - 7 DIV2 Variable divider setting 18 DIV3 8 PRI Phase comparison range select 20 PR2 21 ROT Motor rotate/stop input; H: stop, L: rotate 22. Tock Lock output: Outputs a low level when locked 23 3G Ground No. 4570-2/11STK6215 //O Formats Pin No. Format 16, 17, 18,19 44, 15 AfSiMa QO xr xO 21 Voce fe 22 Yec2 13 -Wy Po AA Vr 100k Fo Aa THE 100k Unit (resistance: 9} No. 4570-3/11STK6215 Equivalent Circuit Voce 6O Ose 25kHz poe Od [Se out Vrefi 70 BH > AF 4110 I Yref2 a0 + O3 vre Hix in 120 : tea -_-5 vreta Mix out 130 ' - 10 FG + *|-__-8 Vrefa3 PLL IC 3G 23 Oo. 440061500 4G 7) 4B 648 BO Bape x1 Xo DIV1IO0EV201a PAi PR2@ AOT Cock Unit (resistance: n) Application Circult Example + Vece ++Yoci + 100 470 6 FF ii tak L = 68k f 12 Voce | 13 390k 7 270k STKB2i5 Vecez Woce 3.9k 6.8k 8 5 2.7k . 760 Voce LaZ | 16, 17 16. 19. 20 t aa . 44145 3 4 23 lime 5A On: Rotate: DC motor; R402-011E17 O 33p 33p I I Ot B.2MHz Unit (resistance: , capacitance: F) The circuit shown above locks at an FG frequency of 2000 Hz. Reference frequency: 8.2 MHz Variable divider: V2 FG divider: Off No. 4570-4/11STK6215 Operating Principles 1. Overview Figure 1 shows the block diagram for the STK6215. The PLL control block compares the frequencies and phases of the FG signal frequency fed back from the motor with a reference clock, which is formed by dividing a reference signal. When they agree, the frequency is locked with a 50% duty. The control signals consist of two systems with D/A converted outputs: FO, which is the frequency control output and PO, which is the phase control output. Since PLL control provides a motor speed that is synchronized with a reference clock frequency fref, which is created by dividing a reference signal, the stability of fref directly influences the stability of the rotation. Therefore, quartz precision digital control is possible by using a crystal oscillator for reference signal generation. The control signals are added by an integration circuit, which also functions as an active filter. It is here that the servo system gain and phase compensation are performed. The output of this system is sent to the PWM conversion block and a PWM signal, which is based on the period of an associated oscillator circuit, is input to the unidirectional driver of the final stage, which drives the DC motor. 2. Motor Speed, Resonant Frequency, and Encoder Pulse Count The frequency fgg of the signal generated by the encoder is given by: N feg (Hz) = Aten XP (PIR) seccescssssestssesnstuseinsiessnsinstastnseteseiettiesrieeteen oe Where, N: Motor speed (rpm) P: Number of pulses per encoder rotation Formula @) can be transformed as follows: 60 x frG IN 8 Pen ce ecectecatesessatcnvepavancnevecaenesececnececensesecensesenerseseadesanasenastessessesearenavesnenaes (rpm) = (PR) Alternatively, 60 & fp . P (P/R) = T seccasssenencseuesunusavesnsnsnsasaveeecevunisvavacescererinerevinavansanavannsnuarararavesseensnsnet Here, the relationship with the oscillator resonant frequency is given by: N _ 60 Me fxtal (rpm) = > DIv x 2050 (1025) D050 CLOaS) Tene nerermrstertcecratarnetatnecnetatan Altematively, 60 fxtal P(P/R)= &) Here, DIV: Variable divider ratio See item 3-1, subsection (3). The value (1025) is used when the fro input frequency is divided by 2 (as determined by DIV setting). See item 3-1, subsection (3), Note that the following three methods for increasing the stability of the motor speed can be considered. @ Increasing the number of encoder output pulses for a given motor speed. @) Not using the FG divider if at all possible, since using it decreases the precision of the rotation data. @) Setting the divider ratio to as low a value as possible, so that the oscillator precision is not reduced. No. 4570-5/11STK6215 Control circuit Motor drive supply voltage supply voltage EE OprnreceetenercsccnetennsQonrnereeny Reference signal i (Ixtal frequency) FO : PLL contol Integration ; Pcmo {phase com- circuit OM tes Unidirectional =e M \ | pensation) (active filter) motor driver : Y 7 rn a 3 retes hoo | Do PEt | fo beceeeees Qereee OO Or Opeeeeeceecee Opnnsnnneccreeeeeerecsncncencrenencenttanneneeeeeecnconne Po Vartable divider Lock output Phase compen- i contro! input sation pin ' FG signal (the lrg frequency) FG or encoder Figure 1 STK6215 Block Diagram x1 Xo DIVi Olv2 Diva Reference signal I I } ] : I generation block osc Variable divider Reference clock &-bit DAC a >OFG ON f Follower 12-bit latch F Frequency system -_ae- 12-bit counter Mator speed QO deccder rock S pSe-] 13-bit counter rs Servo control Y block 10-bit latch y Phase system Bbit DAC > Opa Follower - | ~ Phase reference signal 1/2050 counter Control pulse generator 4 Linked to the LT variable divider Control Divide-by-2 circuit Bypass L., | Fot o-fi>-+ ' PRS1 PAS2 ROT BaEV . Feo O_ Figure 2 PLLIC Block Diagram No. 4570-6/L1STK6215 3. Block Functional Descriptions 3-1 Reference Signal Generation Block (1) Crystal oscillator circuit The controller block generates a reference clock using a crystal oscillator and a capacitor connected to the XI and XO pins. It is also possible to leave the XO pin open and input an extemal clock to the XI pin. (2) Crystal resonant frequency calculation Reference oscillator circuit External clock Input aan Ri AAD 5 YF | CJ XI C7 xo | 2 a Oscillator The external clack should + 4+ be a square wave with an tL Lo : amplitude of 5 V and a duty ci ce of approximately 50%. I I ae After determining the FG frequency to be locked, use the following formula to derive the required crystal frequency. a) With the FG divider off fxtal = frGLock x DIV x 2050 (Hz) b) With the FG divider on fxtal = frgtoc, X DIV * 1025 (Hz) Where: fxtal: Crystal resonant frequency frGLock: The FG frequency to be locked DIV: The variable divider ratio (3) Variable divider and the FG divider The controller block includes a 6-setting variable divider and an FG divider (divide-by-2, by-passable) to expand the range of input FG frequencies. These dividers are controlled by the three pins DIV1, DIV2 and DIV3 as shown in table 1, Table 1 Divider Contro} biva DIV Variable divider ratio FG divider High level High level High level 20 OFF High lavel High level Low level 10 OFF High level Low level High level 6 OFF High level Low level Low level 3 OFF Low fevel High level High level 2 OFF Low level High level Low level 1 OFF r~~""Towlevel | ~sLowlevel =| =Ss=WMigh level S]tS~=S 20 OCS Low level Low level Low level 1 ON No. 4570-7/11STK6215 3-2 Servo Control Block The servo block compares the reference clock generated by the reference signal generation block with the FGI input (the FG signal input from the motor) and generates three output signals: FO (frequency system control output), PO (phase system control output) and Lock (the Jock indicator output). The FO and PO outputs are 8-bit D/A converter outputs. The motor drive signal is created from these two outputs. The Lock output indicates whether the motor is within the lock range, (1) Servo Operation Control system operation is divided into the following three aspects depending on the input FG frequency: drive, tracking (locked), and brake. FG input frequency Operation Lock output FO output PO output > frGLock +6% Brake High level! : Low level Low level Overspeed : fFeLock $6% Tracking Low level DA output (frequency- DA output (phase- Lock range voltage conversion) voltage conversion) > frGLoc&k 8% : Drive High level High level High level Underspeed Notes f Prtal (Hz) Caution: The value in parentheses Is used when the FG divider is on PGLock Ty x 2050 (1025) , , frateck: FG frequency when locked; fxtal: Crystal resonant frequency; DIV: Variable divider ratio * The drive operation is performed at startup (under speed) time. * When the FO and PO outputs are set to the high level, the motor is driven at full speed. Braking operation is performed when the motor is in over speed range, + When the FO and PO outputs are set to the low level, the motor brake is applied. * The servo control block controls the motor by using these two operations to pull the motor speed into the lock range. (Note that the operations described up to this point are the rough adjustments performed by the frequency system.) {2} FO and PO outputs (frequency system control output and phase system control output) When the FG input frequency enters the lock range, the servo control switches to tracking operation. Frequency system fine control and phase system control starts, and the FO and PO outputs are switched to voltage outputs from internal D/A converters. Since the internal D/A converters are 8-bit converters, these output voltages have 256 possible levels, The figures below show the FO and PO output characteristics. @ FO Ontput Characteristics P (drive) " (tracking) (brake) Under speed : Lock range : Over speed FO output + as High fevel | ee ea Enlarged view (DA step output} Low level -6% TFG Lock +6% frg (FG input frequency) @ PO Output Characteristics (during tracking) PO output High level f-----s-rr rn rr rc rr eerste teeny LD f---eneeeennene ees Low level - a e 180 360 Phase difference to") a : oe ' (the phase difference between the phase Caution: These characteristics are for units in the standard comparison range. reference signal and the FG signal) No. 4570-8/11STK6215 3-3 Accessory Functions (1) ROT input (rotate/stop) The ROT input turns the motor on or off. ROT input State FO output PO output High level Stop Low level . Low level Low level Operate * : * : Determined by the motor control function. (2) PRS1 and PRS2 inputs (phase comparison range selection) The phase system comparison range can be switched using the PRS1 and PRS2 inputs. Phase System Comparison Range Selection PRS2 input PRS1 input Range name Comparison range Phase output frequency Low level Low level Standard range 2m Once every FG input Low level High level Test mode pene getaeentonee ner mente High level Low level Double range 6x Once every two FG inputs High level High lavel Quadruple range lan Once every four FG Inputs Caution: The phase range becomes more than two and four times the normal range due to the operation of a built- in limiter. These phase output frequency values are divided by two when tha FG divider is used. @ Phase Output Characteristics Standard : (comparison range 2 7) Phase difference Double range (comparison range 6 11} Phase difference Quadruple range (comparison range 14 x) 7 1 ' 1 i 1 ! i 1 : i ; ; } Caution: The phase difference is the phase difference in the FG signal input with respect to the Internal reference signal. The double and quadruple ranges have hysteresis. @ FG Clock Frequencies (examples) . , . | Oscillator resonant frequency (MH2) Variable divider ratio FG divider Unit 2.05 41 6.15 8.2 10.25 20 50 100 150 200 250 Hz 10 100 200 300 400 500 Hz 6 OFF 116 333 500 667 833 Hz 3 333 667 1000 1933 1667 Hz 2 500 1000 1500 2000 2500 Hz ON 1000 2000 3000 4000 5000 Hz Thea following two ceramic oscillators, which are available as commercial products, can be used. CSA6.14MT (Murata) ... Handies FG frequencies of 500, 1000 and 1500 Hz. CSA8.20MT (Murata)... Handles an FG frequency of 2000 Hz. No, 4570-9/11STK6215 4. Rush Current Limiter Circuit 4-1 Circuit Purpose The STK6215 provides a function that can limit the current when the motor starts (or brakes). This function allows the external current (peak) output capacity to be reduced. The rush current limit value can be changed arbitrarily by adjusting the value of an external resistor. 4-2 Setting the Limit Value Figure 3 shows the method for setting the limit value. The Vref voltage is adjusted by changing the value of RO2. Formula 6 is the formula for the limit value, Ir. RO2 1 lum (A) = RO1+ ROD x Vec2 * Rs sbarenevenenseereentetnressagas i LT 4 Vref ROI: 6.8 kQ (fixed) RO2: Variable Vec2: 5V Rs: Current detection resistance (Q) Vecs ot . Inu 1.2 . Tum STK6210s Rod t < Vref Vv Roa ph iV t Figure 3 External Peripheral Circuit and Motor Startup Timing Chart Caution: Here, the Vref voltage must be set in a range that fulfills the following condition. Vref 2 0.025 V (However, Voc2 = 5 V +5% is the alteration condition.) The limiter function will not operate if the above condition is not met. - * Although formula can be used as a rough formula for setting the output current, the actual value will differ due to the influence of voltage drops due to the ground pattern design external to the hybrid IC. Therefore we recommend that I, py final confirmation be performed in a circuit that has a form close to that of the PCB final pattern. 4-3 Value of the Current Detection Resistor (Rs) Rs detects current flowing from the motor, and the voltage drop across Rs is sensed by an internal comparator, When an external Rs is connected to the STK6215, a resistor with a value that fulfills the following condition must be used. Rs x ILM <0.5 V csssssssesssssusscacocscoussevevevasssssssssansecucessssssescessevsseecesenssceneececseeserseseneneenvatsndD) Also, the PCB pattem should be designed so that Rs, RO2 and the STK6215s ground pin (pin 23) are connected to a single ground point as close as possible to the STK6215 in the pattern. In particular, Rs and the STK6215s pins 3 and 4 must not be located any significant distance from the IC. No, 4570-10/11STK6215 . MOSFET Drain-Source Overvoltage When using the STK6215, a diode is connected in parallel with the DC motor as a regenerative diode for the motor. This also functions as a protective measure against excessive MOSFET flyback voltage. Flyback voltage is due to the influence of circuit factors such as lead inductances, and will remain when the MOSFET turns off. (In general, these voltages are a few volts for periods of up to 0.5 j1s.) Therefore, as a final circuit operation check, confirm that the flyback voltage does not exceed Vogs, 6. Thermal Design Applications must be designed so that the temperature of the STK6215s aluminum substrate side never exceeds 105C in any situation, The remainder of this section discusses thermal design for the STK6215. 6-1 Hybrid IC Average Internal Loss Derivation The main component of the average internal loss occurs in the MOSFET, which is the PWM element. The MOSFET loss is expressed as follows: Pd (W) = Voat * Iyy * fp X ton DUD Lene EeDenee Ee eeLOs OES OO SOD ES OSES EEA AD AD ESS EG ROROOEDEDESESEEOGHEOEOEDSDEDESEOED On BORED Vsat: FET saturation voltage Ty: Motor output peak current ig: FET ontime fp: IC internal oscillator frequency 6-2. Deriving the heat sink size Formula G) shows the thermal resistance of the required heat sink. Te max Ta Oc-a CCA) = Ppa Se reterepenenanerere rr rash bh Ave NEHER OE DREOE DN OSES AG ASES DEG EE RD AN OEE EO NBERGRSRRO ERASE SESE ES 9) A heat sink that is appropriate for @c-a must be selected. (Note that 6c-a for the STK6215 is 18.5C/W.) HE No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power contro! systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. M@ Anyone purchasing any products described or contained herein for an above-mentioned use shall: @ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO. LTD.,, its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: @ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO, LTD, its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. @ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guarant- eed for volume production. SANYO beliaves information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. No. 4570-11/11