DLPC300 www.ti.com DLPS023A - JANUARY 2012 - REVISED JULY 2012 DLP(R) Digital Controller for the DLP3000 DMD Check for Samples: DLPC300 FEATURES 1 * 23 * * * * * * Supports Reliable Operation of the DLP3000 DMD Multi-Mode, 24-Bit Input Port: - Supports Parallel RGB With Pixel Clock Up to 33.5 MHz and 3 Input Color Bit-Depth Options: - 24-Bit RGB888 or 4:4:4 YCrCb888 - 18-Bit RGB666 or 4:4:4 YCrCb666 - 16-Bit RGB565 or 4:2:2 YCrCb565 - Supports 8-Bit BT.656 Bus Mode With Pixel Clock Up to 33.5 MHz Supports Input Resolutions 608x684, 864x480, 854x480 (WVGA), 640x480 (VGA), 320x240 (QVGA) Pattern Input Mode - One-to-One Mapping of Input Data to Micromirrors - 1-Bit Binary Pattern Rates up to 4000-Hz - 8-Bit Grayscale Pattern Rates up to 120-Hz Video Input Mode with Pixel Data Processing - Supports 1Hz to 60Hz Frame Rates - Programmable Degamma - Spatial-Temporal Multiplexing (Dithering) - Automatic Gain Control - Color Space Conversion Output Trigger Signal for Synchronizing with Camera, Sensor, or Other Peripherals System Control: - I2C Control of Device Configuration - Programmable Current Control of up to 3 LEDs * * * - Integrated DMD Reset Driver Control - DMD Horizontal and Vertical Display Image Flip Low Power Consumption: Only 93 mW (Typical) External Memory Support: - 166-MHz Mobile DDR SDRAM - 33.3-MHz Serial FLASH 176-Pin, 7 x 7 mm with 0.4-mm Pitch VFBGA Package APPLICATIONS * * * * * * * * * * * * * * * Machine Vision Industrial Inline Inspection 3D Scanning 3D Optical Metrology Automated Fingerprint Identification Face Recognition Augmented Reality Embedded Display Interactive Display Information Overlay Spectroscopy Chemical Analyzers Medical Instruments Photo-Stimulation Virtual Gauges DESCRIPTION The DLPC300 digital controller, part of the DLP 0.3 WVGA chipset, supports reliable operation of the DLP3000 DMD. The DLPC300 controller also provides a convenient, multi-functional interface between user electronics and the DMD, enabling high-speed pattern rates (up to 4 kHz binary), providing LED control and data formatting for multiple input resolutions. The DLPC300 also outputs a trigger signal for synchronizing displayed patterns with a camera, sensor, or other peripherals. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DLP is a registered trademark of Texas Instruments. DLP is a registered trademark of Texas Insturments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2012, Texas Instruments Incorporated DLPC300 DLPS023A - JANUARY 2012 - REVISED JULY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DESCRIPTION CONTINUED The DLPC300 controller enables integration of the DLP 0.3 WVGA chipset into small-form-factor and low-cost light steering applications. Example end equipments for the 0.3 WVGA chipset include 3D scanning or metrology systems with structured light, interactive displays, chemical analyzers, medical instruments, and other end equipments requiring spatial light modulation (or light steering and patterning). The DLPC300 is one of the two devices in the 0.3 WVGA chipset (see Figure 1). The other device is the DLP3000 DMD. After RESET is released, the DLPC300 controller reads the configuration information stored in the serial FLASH. The configuration information is available for download from DLPR300 product folder. See the 0.3 WVGA Chip-Set data sheet (TI literature number DLPZ005) for further details. DLPC300 DATA(14:0) LOADB TRC SCTRL SAC_BUS CONTROL SAC_CLK DRC_BUS SDRAM INTERFACE Serial FLASH FLASH INTERFACE VCC VSS VOFFSET VBIAS VRESET VDD10 VCC18 VCC_INTF GND VDD_PLL RTN_PLL SPICLK SPICSZ0 SPIDOUT SPIDIN VCC_FLSH DRC_OE DRC_STROBE LED DRIVER Memory Interface CAMERA TRIGGER CMOS MEMORY ARRAY MICROMIRROR ARRAY MICROMIRROR ARRAY RESET CONTROL SCL SDA PARK RESET GPIO4_INTF PLL_REFCLK DATA & CONTROL RECEIVER PARALLEL RGB Data Interface DLP3000 VCC VSS Illumination Interface Camera Trigger Figure 1. Chipset Block Diagram In DLP-based solutions, image data is 100% digital from the DLPC300 input port to the image on the DMD. The image stays in digital form and is never converted into an analog signal. The DLPC300 processes the digital input image and converts the data into a format needed by the DLP3000. The DLP3000 then steers light by using binary pulse-width-modulation (PWM) for each pixel mirror. Refer to DLP3000 Data Sheet (TI literature number DLPS022) for further details. 2 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 DLPC300 www.ti.com DLPS023A - JANUARY 2012 - REVISED JULY 2012 Figure 2 is the DLPC300 functional block diagram. As part of the pixel processing functions, the DLPC300 offers format conversion functions: chroma interpolation for 4:2:2 and 4:4:4, color-space conversion, and gamma correction. The DLPC300 also offers several image-enhancement functions: programmable degamma, automatic gain control, and image resizing. Additionally, the DLPC300 offers an artifact migration function through spatialtemporal multiplexing (dithering). Finally, the DLPC300 offers the necessary functions to format the input data to the DMD. The pixel processing functions allow the DLPC300 and DLP3000 to support a wide variety of resolutions including NTSC, PAL, QVGA, QWVGA, VGA, and WVGA. The pixel processing functions can be optionally bypassed with the native 608 x 684 pixel resolution. When accurate pattern display is needed, the native 608x684 input resolution pattern has a one-to-one association with the corresponding micromirror on the DLP3000. The DLPC300 enables high-speed display of these patterns: up to 1440 Hz for binary (1-Bit) patterns and up to 120 Hz for 8-Bit patterns. This functionality is well-suited for techniques such as structured light, rapid manufacturing, or digital exposure. mDDR I/F RGB Data 24 FORMAT CONVERSION IMAGE ENHANCEMENT ARTIFACT MIGRATION - Chroma Interpolation - Color Space Conversion - Gamma Correction - Degamma - Automatic Gain Control - Image Scaling - Spatial-Temporal Multiplexing RGB Control DMD FORMATTING - Memory Management - DMD I/F Processing - Horiz and Vert Flip - Display Rotation 15 DMD DDR Data DMD DDR Control Flash I/F DMD Reset Control CONFIGURATION CONTROL 2 I C Bus Reference Clock RESET SYSTEM CLOCK AND RESET SUPPORT PARK Figure 2. DLPC300 Functional Block Diagram Commands can be input to the DLPC300 over an I2C interface. The DLPC300 takes as input 16-, 18- or 24-bit RGB data at up to 60-Hz frame rate. This frame rate is composed of three colors (red, green, and blue) with each color equally divided in the 60-Hz frame rate. Thus, each color has a 5.55 ms time slot allocated. Because each color has 5-, 6-, or 8-bit depth, each color time slot is further divided into bit-planes. A bit-plane is the 2-Dimensional arrangement of one-bit extracted from all the pixels in the full color 2D image. See Figure 3. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 3 DLPC300 DLPS023A - JANUARY 2012 - REVISED JULY 2012 www.ti.com 8-bit Red Image 8 Red Bit-Planes 8-bit Green Image 24-bit RGB Image 8 Green Bit-Planes 8-bit Blue Image 8 Blue Bit-Planes Figure 3. Bit Slices The length of each bit-plane in the time slot is weighted by the corresponding power of 2 of its binary representation. This provides a binary pulse-width modulation of the image. For example, a 24-bit RGB input has three colors with 8-bit depth each. Each color time slot is divided into eight bit-planes, with the sum of all bit planes in the time slot equal to 256. See Figure 4 for an illustration of this partition of the bits in a frame. b1 b 3 b0 b2 bit 4 16 bit 5 32 bit 6 bit 7 bit plane 64 128 256 Figure 4. Bit Partition in a Frame for an 8-Bit Color Therefore, a single video frame is composed of a series of bit-planes. Because the DMD mirrors can be either on or off, an image is created by turning on the mirrors corresponding to the bit set in a bit-plane. With the binary pulse-width modulation, the intensity level of the color is reproduced by controlling the amount of time the mirror is on. For a 24-bit RGB frame image inputted to the DLP300, the DLPC300 creates twenty-four bit planes, stores them on the mDDR, and sends them to the DLP3000 DMD, one bit-plane at a time. Depending on the bit weight of the bit-plane, the DLPC300 controls the time this bit-plane is exposed to light, controlling the intensity of the bit-plane. To improve image quality in video frames, these bit-planes, time slots, and color frames are intertwined and interleaved with spatial-temporal algorithms by the DLPC300. For other applications where this image enhancement is not desired, the video processing algorithms can be bypassed and replaced with a specific set of bit-planes. The bit-depth of the pattern is then allocated into the corresponding time slots. Futhermore, an output trigger signal is also synchronized with these time slots to indicate when the image is displayed. For structured light applications this mechanism provides the capability to display a set of patterns and signal a camera to capture these patterns overlayed on an object. 4 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 DLPC300 www.ti.com DLPS023A - JANUARY 2012 - REVISED JULY 2012 Figure 5 illustrates the bit planes and corresponding output triggers for 3-bit, 6-bit, and 12-bit RBG. Table 1 shows the allowed pattern combinations in relation to the bit depth of the pattern. Figure 5. Bit Planes and Output Trigger for 3-, 6-, and 12-Bit RGB Input Table 1. Allowed Pattern Combinations External Video Sequence 1 bit per pixel 24 2 bits per pixel 12 3 bits per pixel 4 bits per pixel Monochrome FRAME RATE 15, 30, 40, or 60 Hz PATTERN RATE 24 x Frame Rate 12 x Frame Rate 8 15, 30, 45, or 60 Hz 8 x Frame Rate 6 15, 30, 40, or 60 Hz 6 x Frame Rate 5 bits per pixel 4 6 bits per pixel 4 7 bits per pixel RGB NUMBER OF IMAGES PER FRAME 3 15, 30, 45, or 60 Hz 15, 30, 40, or 60 Hz 4 x Frame Rate 4 x Frame Rate 3 x Frame Rate 8 bits per pixel 2 2 x Frame Rate 1-bit per color pixel (3-bit per pixel) 8 8 x Frame Rate 2-bit per color pixel (6-bit per pixel) 4 4 x Frame Rate 4-bit per color pixel (12-bit per pixel) 2 15, 30, 45, or 60 Hz 2 x Frame Rate 5/6/5-bit RGB pixel (16-bit per pixel) 6-bit per color pixel (18-bit per pixel) 1 Frame Rate 8-bit per color pixel (24-bit per pixel) An optional FPGA (see the DLPR300 Software Folder) can be added to the system to manage the bit-planes stored in the mDDR. The mDDR accomodates four 608 x 684 images of 24-bit RGB data or 96 bit-planes (24 bitplanes x 4 images). By pre-loading the mDDR with these bit-planes, faster frame rates can be achieved. The 96 bit-plane buffer is arranged in a circular buffer style, meaning that the last bit-plane addition to the buffer replaces the oldest stored bit-plane. Figure 6 shows the overall system with the optional FPGA. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 5 DLPC300 DLPS023A - JANUARY 2012 - REVISED JULY 2012 www.ti.com With this FPGA, the pattern frame rate can be calculated with the following equation: (1) where: typical first bit plane load time = 215 s typical buffer rotate overhead = 135 s Table 2 shows the maximum pattern rate that can be achieved by using a single FPGA internal buffer in continuous mode. Table 2. Maximum Pattern Rate with Optional FPGA MAXIMUM NUMBER OF PATTERNS MAXIMUM PATTERN RATE 1 bit per pixel 96 4000 Hz 2 bits per pixel 48 1100 Hz 3 bits per pixel 32 590 Hz 4 bits per pixel 24 550 Hz 5 bits per pixel 16 450 Hz 6 bits per pixel 16 365 Hz 7 bits per pixel 12 210 Hz 8 bits per pixel 12 115 Hz COLOR MODE Monochrome 6 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 DLPC300 www.ti.com DLPS023A - JANUARY 2012 - REVISED JULY 2012 Figure 6 illustrates the chipset with the optional FPGA. Data Interface DATA(14:0) LOADB TRC FLASH INTERFACE BUFFER_SWAP Serial FLASH SAC_BUS CONTROL SAC_CLK DRC_BUS SDRAM INTERFACE Memory Interface DRC_OE DRC_STROBE VOFFSET VBIAS VDD10 VCC18 VCC_INTF GND VDD_PLL RTN_PLL SPICS0 SPIDOUT SPIDIN VCC_FLSH LED DRIVER Serial FLASH FLASH INTERFACE SPICLK VCC VSS VRESET CAMERA TRIGGER MICROMIRROR ARRAY RESET CONTROL SCL SDA PARK RESET GPIO4_INTF PLL_REFCLK SCTRL DATA AND CONTROL RECEIVER Data Interface RD_BUF(1:0) Optional FPGA PARALLEL RGB PARALLEL RGB 2 Data Interface DLPC300 PARALLEL RGB 1 DLP3000 CMOS MEMORY ARRAY MICROMIRROR ARRAY VCC VSS Illumination Interface Output Trigger Figure 6. DLP3000 Chipset With Optional FPGA The digital RGB input interface operates at 1.8 V, 2.5 V, or 3.3 V nominal, depending on the VCC_INTF supply. The SPI flash interface operates at 1.8 V, 2.5 V, or 3.3 V nominal, depending on the VCC_FLSH supply. The DMD and mDDR interface operates at 1.8 V nominal (VCC18). The core transistors operates at 1 V nominal (VDD10). The analog PLL operates at 1 V nominal (VDD_PLL). Typical System Application A typical embedded system application using the DLPC300 is shown in Figure 7. In this configuration, the DLPC300 controller supports a 24-bit parallel RGB, typical of LCD interfaces, from the main processor chip. This system supports both still and motion video sources. For this configuration, the controller only supports periodic sources. This is ideal for motion video sources, but can also be used for still images by maintaining periodic syncs but only sending a frame of data when needed. The still image must be fully contained within a single video frame and meet frame timing constraints. The DLPC300 refreshes the displayed image at the source frame rate and repeats the last active frame for intervals in which no new frame has been received. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 7 DLPC300 DLPS023A - JANUARY 2012 - REVISED JULY 2012 www.ti.com Mobile DDR RAM Optical Sensor ADDR(13) DATA (16) CTL(9) Connectivity (USB, Ethernet, etc.) PWM(3) PCLK Volatile and Non-Volatile Storage HSYNC, VSYNC, PDM, DATAEN RGB_EN(3) DATA (16/18) LS_Ctrl(2) Main Processor LS_OUT I2C(2) LEDs Illumination Optics LED Sensor CLK, Control(3) DLPC300 User Interface LED Drivers Data(15) CLK, BSA, DAD Ctl(3) OSC DLP3000 BAT DMDTM Voltage Supplies - + Data(2) VBIAS VOFF CTL FLASH VRESET CTL PARK Power Management DC_IN Figure 7. Typical Embedded System Block Diagram Related Documents DOCUMENT TI LITERATURE NUMBER DLP3000 0.3 WVGA Series 220 DMD data sheet DLPS022 DLP(R) 0.3 WVGA Chipset DLPZ005 DLPC300 Programmer's Guide DLPU004 Device Part Number Nomenclature Figure 8 provides a legend for reading the complete device name for any DLP device. DLPC300ZVB Package Type Device Descriptor Figure 8. Device Nomenclature 8 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 DLPC300 www.ti.com DLPS023A - JANUARY 2012 - REVISED JULY 2012 Device Marking The device marking consists of the fields shown in Figure 9. DLPC300ZVB DLP Device Name DLP Logo LLLLLLLL.ZZ KOREAYYWW Trace Code Assembly Lot Number G8 Ball Material Pin #1 ID Figure 9. Device Marking SIGNAL FUNCTIONAL DESCRIPTIONS This section describes the input/output characteristics of signals that interface to the DLPC300 by functional groups. Table 3 includes I/O power and type characteristic references which are further described in subsequent sections. Table 3. Functional Pin Descriptions TERMINAL NAME RESET NO. J14 I/O POWER VCC18 I/O TYPE I1 CLK SYSTEM Async DESCRIPTION DLPC300 power-on reset. Self configuration starts when a low-to-high transition is detected on this pin. All device power and clocks must be stable and within recommended operating conditions before this reset is deasserted. Note that the following 7 signals are highimpedance while RESET is asserted: DMD_PWR_EN, LEDDVR_ON, LED_SEL_0, LED_SEL_1, SPICLK, SPIDOUT, SPICS0 External pullups/-downs should be added as needed to these signals to avoid floating inputs where these signals are driven. PARK B8 VCC_ INTF I3 Async DMD park control (active-low). Is set high to enable normal operation. PARK must be set high within 500 s after releasing RESET. PARK must be set low a minimum of 500 s before any power is to be removed from the DLPC300 or DLP3000. See System Power-Up/Down Sequence for more details. PLL_REFCLK_I K15 VCC18 (filter) I4 N/A Reference clock crystal Input. If an external oscillator is used in place of a crystal, then this pin should be used as the oscillator input. PLL_REFCLK_O J15 VCC18 (filter) O14 N/A Reference clock crystal return. If an external oscillator is used in place of a crystal, then this pin should be left unconnected (floating). FLASH INTERFACE (1) (1) Each device connected to the SPI bus must operate from VCC_FLSH. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 9 DLPC300 DLPS023A - JANUARY 2012 - REVISED JULY 2012 www.ti.com Table 3. Functional Pin Descriptions (continued) TERMINAL NO. I/O POWER I/O TYPE CLK SYSTEM SPICLK A4 VCC_FLSH O24 N/A SPIDIN B4 VCC_FLSH I2 SPICLK Serial data input from the external SPI slave FLASH device. SPICS0 A5 VCC_FLSH O24 SPICLK SPI Master Chip Select 0 output. Active-low RESERVED C6 VCC_FLSH O24 SPICLK Not used. Reserved for future use. Should be left unconnected SPIDOUT C5 VCC_FLSH O24 SPICLK Serial data output to the external SPI slave FLASH device. This pin sends address and control information as well as data when programming. RESERVED0 B10 VCC_ INTF I3 SCL Not used. Reserved for future use. Should be pulled up to VCC_INTF. SCL A10 VCC_ INTF B38 N/A I2C clock. Bidirectional, open-drain signal. An external pull-up is required. No I2C activity is permitted for a minimum of 100 ms after PARK and RESET are set high. SDA C10 VCC_ INTF B38 SCL I2C data. Bidirectional, open-drain signal. An external pullup is required. NAME DESCRIPTION SPI Master Clock output. CONTROL GPIO4_INTF C9 VCC_ INTF B34 Async General-purpose I/O 4. Primary usage is to indicate when auto-initialization is complete (also called INIT-DONE, which is when GPIO4 transitions high then low following release of RESET) and to flag a detected error condition in the form of a logic-high, pulsed interrupt flag subsequent to INIT-DONE. RESERVED1 B9 VCC_ INTF B34 Async Reserved for future use. This pin should be left unconnected. PARALLEL RGB INTERFACE PARALLEL RGB MODE BT.656 I/F MODE PCLK D13 VCC_ INTF I3 N/A Pixel clock (2) Pixel clock (2) PDM H15 VCC_ INTF B34 ASYNC Not used, pull-down through an external resistor. Not used, pull-down through an external resistor. VSYNC H14 VCC_ INTF I3 ASYNC VSync (3) Unused (4) HSYNC H13 VCC_ INTF I3 PCLK (3) Unused (4) DATEN G15 VCC_ INTF I3 HSync (2) Unused (4) PCLK Data valid Data0 (5) PDATA[0] G14 VCC_ INTF I3 PCLK Data0 (5) PDATA[1] G13 VCC_ INTF I3 PCLK Data1 (5) Data1 (5) Data2 (5) Data2 (5) (5) Data3 (5) PDATA[2] F15 VCC_ INTF I3 PCLK PDATA[3] F14 VCC_ INTF I3 PCLK Data3 PDATA[4] F13 VCC_ INTF I3 PCLK Data4 (5) PCLK Data5 (5) Data5 Data6 (5) Data6 (5) Data7 (5) Data7 (5) Data8 (5) Unused (4) Data9 (5) Unused (4) PDATA[5] PDATA[6] PDATA[7] PDATA[8] PDATA[9] E15 E14 E13 D15 D14 VCC_ INTF VCC_ INTF VCC_ INTF VCC_ INTF VCC_ INTF I3 I3 I3 I3 I3 PCLK PCLK PCLK PCLK Data4 (5) (5) (5) Unused (4) PDATA[10] C15 VCC_ INTF I3 PCLK Data10 PDATA[11] C14 VCC_ INTF I3 PCLK Data11 (5) Unused (4) PCLK Data12 (5) Unused (4) Unused (4) Unused (4) PDATA[12] C13 VCC_ INTF I3 PDATA[13] B15 VCC_ INTF I3 PCLK Data13 (5) PDATA[14] B14 VCC_ INTF I3 PCLK Data14 (5) (2) (3) (4) (5) 10 Pixel clock capture edge is SW programmable. VSYNC, HSYNC and data valid polarity is SW programmable. Unused inputs should be pulled down to ground through an external resistor. PDATA[23:0] bus mapping is pixel-format and source-mode dependent. See later sections for details. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 DLPC300 www.ti.com DLPS023A - JANUARY 2012 - REVISED JULY 2012 Table 3. Functional Pin Descriptions (continued) TERMINAL NAME PDATA[15] NO. I/O POWER I/O TYPE CLK SYSTEM A15 VCC_ INTF I3 PCLK Data15 (5) Unused (4) (5) Unused (4) DESCRIPTION PDATA[16] A14 VCC_ INTF I3 PCLK Data16 PDATA[17] B13 VCC_ INTF I3 PCLK Data17 (5) Unused (4) PCLK Data18 (5) Unused (4) Data19 (5) Unused (4) (5) Unused (4) PDATA[18] PDATA[19] A13 C12 VCC_ INTF VCC_ INTF I3 I3 PCLK PDATA[20] B12 VCC_ INTF I3 PCLK Data20 PDATA[21] A12 VCC_ INTF I3 PCLK Data21 (5) Unused (4) PCLK Data22 (5) Unused (4) Data23 (5) Unused (4) PDATA[22] PDATA[23] C11 B11 VCC_ INTF VCC_ INTF I3 I3 PCLK DMD INTERFACE DMD_D0 M15 DMD_D1 N14 DMD_D2 M14 DMD_D3 N15 DMD_D4 P13 DMD_D5 P14 DMD_D6 P15 DMD_D7 R15 DMD_D8 R12 d DMD_D9 N11 DMD_D10 P11 DMD_D11 R11 DMD_D12 N10 VCC18 O58 DMD_DCLK DMD data pins. DMD data pins are double data rate (DDR) signals that are clocked on both edges of DMD_DCLK. All 15 DMD data signals are use to interface to the DLP3000. DMD_D13 P10 DMD_D14 R10 DMD_DCLK N13 VCC18 O58 N/A DMD_LOADB R13 VCC18 O58 DMD_DCLK DMD data load signal (active-low). This signal requires an external pullup to VCC18. DMD_SCTRL R14 VCC18 O58 DMD_DCLK DMD data serial control signal DMD_TRC P12 VCC18 O58 DMD_DCLK DMD data toggle rate control DMD data clock (DDR) DMD_DRC_BUS L13 VCC18 O58 DMD_SAC_CL DMD reset control bus data K DMD_DRC_STRB K13 VCC18 O58 DMD_SAC_CL DMD reset control bus strobe K DMD_DRC_OE M13 VCC18 O58 DMD_SAC_BUS L15 VCC18 O58 DMD_SAC_CLK L14 VCC18 O58 DMD_PWR_EN K14 VCC18 O14 Async DMD reset control enable (active-low). This signal requires an external pullup to VCC18. DMD_SAC_CL DMD stepped-address control bus data K N/A Async DMD stepped-address control bus clock DMD power regulator enable (active-high). This is an active-high output that should be used to control DMD VOFFSET, VBIAS, and VRESET voltages. DMD_PWR_EN is driven high as a result of the PARK input signal being set high. However, DMD_PWR_EN is held high for 500 s after the PARK input signal is set low before it is driven low. A weak external pulldown resistor is recommended to keep this signal at a known state during power-up reset. SDRAM INTERFACE Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 11 DLPC300 DLPS023A - JANUARY 2012 - REVISED JULY 2012 www.ti.com Table 3. Functional Pin Descriptions (continued) TERMINAL NAME NO. I/O POWER I/O TYPE CLK SYSTEM MEM_CLK_P D1 VCC18 O74 N/A MEM_CLK_N E1 VCC18 O74 N/A MEM_A0 P1 MEM_A1 R3 MEM_A2 R1 MEM_A3 R2 MEM_A4 A1 MEM_A5 B1 MEM_A6 A2 VCC18 O64 MEM_CLK mDDR memory, multiplexed row and column address MEM_A7 B2 MEM_A8 D2 MEM_A9 A3 MEM_A10 P2 VCC18 O64 MEM_CLK mDDR memory, bank select MEM_A11 B3 MEM_A12 D3 MEM_BA0 M3 MEM_BA1 P3 DESCRIPTION mDDR memory, differential memory clock MEM_RAS P4 VCC18 O64 MEM_CLK mDDR memory, row address strobe (active-low) MEM_CAS R4 VCC18 O64 MEM_CLK mDDR memory, column address strobe (active-low) MEM_WE R5 VCC18 O64 MEM_CLK mDDR memory, write enable (active-low) MEM_CS J3 VCC18 O64 MEM_CLK mDDR memory, chip select (active-low) MEM_CKE C1 VCC18 O64 MEM_CLK mDDR memory, clock enable (active-high) MEM_LDQS J2 VCC18 B64 N/A mDDR memory, lower byte, R/W data strobe MEM_LDM J1 VCC18 O64 MEM_LDQS mDDR memory, lower byte, write data mask MEM_UDQS G1 VCC18 B64 N/A mDDR memory, upper byte, R/W data strobe MEM_UDM H1 VCC18 O64 MEM_UDQS mDDR memory, upper byte, write data mask VCC18 B64 MEM_LDQS mDDR memory, lower byte, bidirectional R/W data VCC18 B64 MEM_UDQS mDDR memory, upper byte, bidirectional R/W data MEM_DQ0 N1 MEM_DQ1 M2 MEM_DQ2 M1 MEM_DQ3 L3 MEM_DQ4 L2 MEM_DQ5 K2 MEM_DQ6 L1 MEM_DQ7 K1 MEM_DQ8 H2 MEM_DQ9 G2 MEM_DQ10 H3 MEM_DQ11 F3 MEM_DQ12 F1 MEM_DQ13 E2 MEM_DQ14 F2 MEM_DQ15 E3 LED DRIVER INTERFACE RPWM N8 VCC18 O14 Async Red LED PWM signal used to control the LED current (6). GPWM P9 VCC18 O14 Async Green LED PWM signal used to control the LED current (6). (6) 12 All LED PWM signals are forced high when LEDDRV_ON = 0, SW LED control is disabled, or the sequence stops. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 DLPC300 www.ti.com DLPS023A - JANUARY 2012 - REVISED JULY 2012 Table 3. Functional Pin Descriptions (continued) TERMINAL NAME BPWM NO. I/O POWER I/O TYPE CLK SYSTEM R8 VCC18 O14 Async DESCRIPTION Blue LED PWM signal used to control the LED current (6). LED enable SELECT. Controlled by DMD sequence timing. LED_SEL_0 R6 VCC18 LED_SEL_1 O14 Async N6 LED_SEL(1:0) Selected LED 00 None 01 Red 10 Green 11 Blue A decode circuit is required to decode the selected LED enable. LEDDRV_ON P7 VCC18 O14 Async LED driver master enable. Active-high output control to external LED driver logic. This signal is driven high 100 ms after LED_ENABLE is driven high. Driven low immediately when either LED_ENABLE or PARK is driven low. LED_ENABLE A11 VCC_ INTF I3 Async LED enable (active-high input). A logic low on this signal forces LEDDRV_ON low and LED_SEL(1:0) = 00b. These signals are enabled 100 ms after LED_ENABLE transitions from low to high. RED_EN B5 When not used with an optional FPGA, this signal should be connected to the RED LED enable circuit. When RED_EN is high, the red LED is enabled. When RED_EN is low, the red LED is disabled. When used with the optional FPGA, this signal should be pulled down to ground through an external resistor. This signal is configured as output and driven low when the DLPR300 serial FLASH PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I2C LED Enable and Buffer Control register. A7 When not used with an optional FPGA, this signal should be connected to the green LED enable circuit. When GREEN_EN is high, the green LED is enabled. When GREEN_EN is low, the green LED is disabled. When used with the optional FPGA, this signal should be pulled down to ground through an external resistor. This signal is configured as output and driven low when the DLPR300 serial FLASH PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I2C LED Enable and Buffer Control register. GREEN_EN VCC18 B18 Async BLUE_EN When not used with an optional FPGA, this signal should be connected to the blue LED enable circuit. When BLUE_EN is high, the blue LED is enabled. When BLUE_EN is low, the blue LED is disabled. When used with the optional FPGA, this signal should be pulled down to ground through an external resistor. This signal is configured as output and driven low when the DLPR300 serial FLASH PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I2C LED Enable and Buffer Control register. C8 WHITE POINT CORRECTION LIGHT SENSOR I/F CMP_OUT A6 VCC18 I1 Async Successive approximation ADC comparator output (DLPC300 input). Assumes a successive approximation ADC is implemented with a light sensor and/or thermocouple feeding one input of an external comparator and the other side of the comparator driven from the DLPC300 CMP_PWM pin. If not used, this signal should be pulled down to ground . Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 13 DLPC300 DLPS023A - JANUARY 2012 - REVISED JULY 2012 www.ti.com Table 3. Functional Pin Descriptions (continued) TERMINAL NAME NO. CMP_PWM GPIO0_CMPPWR B7 P5 I/O POWER VCC18 VCC18 I/O TYPE O14 B14 CLK SYSTEM DESCRIPTION Async Successive approximation comparator pulse-width modulation input. Supplies a PWM signal to drive the successive approximation ADC comparator used in lightto-voltage light sensor applications. Should be left unconnected if this function is not used. Async Power control signal for the WPC light sensor and other analog support circuits using the DLPC300 ADC. Alternatively, it provides general purpose I/O to the WPC microprocessor internal to the DLPC300. Should be left unconnected if not used. Async Trigger output. Indicates that a pattern or image is displayed on the screen and is ready to be captured. With an optional FPGA, this signal is connected to the FPGA trigger input. This signal is configured as output and driven low when the DLPR300 serial FLASH PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I2C LED Enable and Buffer Control register. If not used, this signal should be pulled down to ground through an external resistor. Async Inverts the current 1-bit pattern held in the DLPC300 buffer. When used with an optional FPGA, this signal should be connected to DMC_TRC of the FPGA. This signal is configured as output and driven low when the DLPR300 serial FLASH PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I2C LED Enable and Buffer Control register. If not used, this signal should be pulled down to ground through an external resistor. TRIGGER CONTROL OUTPUT_TRIGGE R N9 VCC18 B18 PATTERN CONTROL PATTERN_INVER T C7 VCC18 B18 OPTIONAL FPGA BUFFER MANAGEMENT INTERFACES 14 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 DLPC300 www.ti.com DLPS023A - JANUARY 2012 - REVISED JULY 2012 Table 3. Functional Pin Descriptions (continued) TERMINAL NAME NO. I/O POWER I/O TYPE CLK SYSTEM RD_BUF0 DESCRIPTION B6 When not used with an optional FPGA, this signal should be pulled down to ground through an external resistor. When used with an optional FPGA, this signal should be connected to RD_PTR_SDC[0] of the FPGA. RD_BUFF1 and RD_BUFF0 indicate to the FPGA one of the four buffers currently in use. This signal is configured as output and driven low when the DLPR300 serial FLASH PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I2C LED Enable and Buffer Control register. R9 This signal is sampled when RESET is de-asserted to choose between two pre-defined 7-bit I2C slave Addresses. If I2C_ADDR_SEL signal is pulled-low, then the DLPC300's I2C slave address is 1Bh. If I2C_ADDR_SEL signal is pulled-high, then the DLPC300's I2C slave address is 1Dh. When used with an optional FPGA, this signal should be connected to RD_PTR_SDC[1] of the FPGA. RD_BUFF1 and RD_BUFF0 indicate to the FPGA one of the four buffers currently in use. This signal is set to input upon deassertion of RESET and configured as output and driven low when the DLPR300 serial FLASH PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I2C LED Enable and Buffer Control register. RD_BUF1/I2C_AD DR_SEL VCC18 B18 Async BUFFER_SWAP When not used with an optional FPGA, this signal should be pulled down to ground through an external resistor. When used with an optional FPGA, this signal should be connected to BUFF_SWAP_SEQ of the FPGA. BUFFER_SWAP indicates to the FPGA when to advance the buffer. This signal is configured as output and driven low when the DLPR300 serial FLASH PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I2C LED Enable and Buffer Control register. A8 CONTROLLER MANUFACTURER TEST SUPPORT TEST_EN A9 VCC_INTF I3 N/A Reserved for test. Should be connected directly to ground on the PCB for normal operation. Includes weak internal pulldown Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 15 DLPC300 DLPS023A - JANUARY 2012 - REVISED JULY 2012 www.ti.com Table 3. Functional Pin Descriptions (continued) TERMINAL NAME NO. I/O POWER I/O TYPE CLK SYSTEM DESCRIPTION BOARD LEVEL TEST AND DEBUG JTAGTDI P6 VCC18 I1 JTAGTCK JTAGTCK N5 VCC18 I1 N/A JTAG, serial data in. Includes weak internal pullup JTAG, serial data clock. Includes weak internal pullup JTAGTMS N7 VCC18 I1 JTAGTCK JTAG, test mode select. Includes weak internal pullup JTAGTDO R7 VCC18 I14 JTAGTCK JTAG, serial data out JTAGRSTZ P8 VCC18 I1 ASYNC JTAG, RESET (active-low). Includes weak internal pullup. This signal must be tied to ground, through an external 15-k or less resistor for normal operation. Power and Ground Pins Power and ground connections to the DLPC300 are made up of the groupings shown in Table 4. Table 4. Power and Ground Pin Descriptions (1) (1) 16 POWER GROUP PIN NUMBER(S) VDD10 D5, D9, F4, F12, J4, J12, M6, M8, M11 VDD_PLL H12 VCC18 C4, D8, E4, G3, K3, K12, L4, M5, M9, M12, N4, N12 VCC_FLSH D6 VCC_INTF D11, E12 GND D4, D7, D10, D12, G4, G12, H4, K4, L12, M4, M7, M10 RTN_PLL J13 Reserved B10, C2, C3, C6, N2, N3 DESCRIPTION 1-V core logic power supply (9) 1-V power supply for the internal PLL (1) 1.8-V power supply for all I/O other than the host/ video interface and the SPI flash buses. (12) 1.8- , 2.5- or 3.3-V power supply for SPI flash bus I/O. (1) 1.8- , 2.5- or 3.3-V power supply for all I/Os on the host/video interface (includes I2C, PDATA, video syncs, PARK and LED_ENABLE pins) (2) Common ground (12) Analog ground return for the PLL (This should be connected to the common ground GND through a ferrite (1) No connects. Other signals can be routed through these pins (vs going around them) to ease routing if desired (6). 132 total signal I/O pins, 38 total power/ground pins, 6 total reserved pins Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 DLPC300 www.ti.com DLPS023A - JANUARY 2012 - REVISED JULY 2012 ABSOLUTE MAXIMUM RATING over operating free-air temperature range (unless otherwise noted). Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. The Absolute Maximum Ratings are stress ratings only, and functional performance of the device at these or any other conditions beyond those indicated under " Recommended Operating Conditions" is not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device reliability. PARAMETER CONDITIONS MIN MAX UNIT Electrical VDD10 Voltage applied to VDD10 (1) -0.5 1.32 V VDD_PLL Voltage applied to VDD_PLL (1) -0.5 1.32 V (1) VCC18 Voltage applied to VCC18 -0.5 2.75 V VCC_FLSH Voltage applied to VCC_FLSH (1) -0.5 3.60 V VCC_INTF Voltage applied to VCC_INTF (1) -0.5 3.60 V -0.5 3.60 V Voltage applied to all other input terminals (1) Environmental TJ Junction temperature -30 105 C Tstg Storage temperature -40 125 C 2000 V 500 V ESD Electrostatic discharge immunity (2) Human Body Model (HBM) Charged Device Model (CDM) (1) (2) All voltages referenced to VSS (ground). Tested in accordance with JESD22-A114-B Electrostatic Discharge (ESD) sensitivity testing Human Body Model (HBM). RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the Recommended Operating Conditions limits. PARAMETER CONDITIONS MIN NOM MAX UNIT Electrical VDD10 Core logic supply voltage 0.95 1 1.05 V VDD_PLL Analog PLL supply voltage 0.95 1 1.05 V VCC18 I/O supply voltage (except FLASH and 24bit RGB interface signals) 1.71 1.8 1.89 VCC_FLSH Configuration and control I/O supply voltage 1.8 V LVCMOS 1.71 1.8 1.89 V 2.5 V LVCMOS 2.375 2.5 2.625 V 3.3 V LVCMOS 3.135 3.3 3.465 V 1.8 V LVCMOS 1.71 1.8 1.89 V 2.5 V LVCMOS 2.375 2.5 2.625 V 3.3 V LVCMOS 3.135 3.3 3.465 V -0.3 VCCIO (1) + 0.3 V 0 VCCIO (1) V -20 85 C VCC_INTF 24-bit RGB interface supply voltage VI Input voltage, all other pins VO Output voltage, all other pins V Environmental TJ (1) Operating junction temperature VCCIO represents the actual supply voltage applied to the corresponding I/O. POWER CONSUMPTION Table 5 lists the typical current and power consumption of the individual supplies. This table assumes the transfer of a 12 x 6 checkerboard image in 864 x 480 landscape mode at periodic 30 frames per second over the Parallel RGB interface at 25C. Note that VCC_FLSH power is zero since the serial FLASH is only accessed upon device configuration and not during normal operation. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 17 DLPC300 DLPS023A - JANUARY 2012 - REVISED JULY 2012 www.ti.com Table 5. Power Consumption PARAMETER CONDITIONS VCC_INTF 1.8 V VCC_FLSH VCC18 MIN NOM MAX UNIT 0.1 mW 2.5 V 0 mW 1.8 V 50.8 mW VDD_PLL 1.0 V 2.8 mW VDD10 1.0 V 39 mW I/O Characteristics Voltage and current characteristics for each I/O type signal listed in Table 3, Functional Pin Descriptions, are summarized in Table 6. All inputs and outputs are LVCMOS. Table 6. I/O Characteristics PARAMETER CONDITIONS B64 inputs VIH VIL High-level input voltage Low-level input voltage VCC = 1.8 V I1, I2, I3, I4, B14, B18, B34, B38 inputs High-level output voltage 1.2 VCC + 0.3 VCC + 0.3 I2, I3, B34, B38 inputs VCC = 3.3 V 2 VCC + 0.3 I1, I2, I3, I4, B14, B18, B34, B38 inputs VCC = 1.8 V -0.3 0.5 B64 inputs -0.3 0.57 I2, I3, B34, B38 inputs VCC = 2.5 V -0.3 0.7 I2, I3, B34, B38 inputs VCC = 3.3 V -0.3 0.8 O14, O24, B14, B34 outputs IOH = -2.58 mA 1.25 O58 outputs IOH = = -6.41 mA 1.25 IOH = = -5.15 mA 1.25 O64, O74, B64 outputs IOH = = -4 mA 1.53 O24, B34 outputs IOH = = -6.2 mA 1.7 IOH = -12.4 mA 1.7 IOH = -10.57 mA 2.4 IOH = -10.57 mA 1.25 IOH = --5.29 mA 2.4 VCC = 1.8 V, VCC = 2.5 V, B38 outputs VCC = 3.3 V, O24, B34 outputs O64, O74, B64 outputs IOL = 4 mA O14, O24, B14, B34 outputs B18, B38 outputs VCC = 1.8 V, O58 outputs O24, B34 outputs B38 outputs O24, B34 outputs B38 outputs 18 VCC + 0.3 1.7 B38 outputs Low-level output voltage 1.19 VCC = 2.5 V B38 outputs VOL MAX I2, I3, B34, B38 inputs B18, B38 outputs VOH MIN VCC = 2.5 V, VCC = 3.3 V, V V V 0.19 IOL = 2.89 mA 0.4 IOL = 5.72 mA 0.4 IOL = 5.78 mA 0.4 IOL = 6.3 mA 0.7 IOL = 12.7 mA 0.7 IOL = 9.38 mA 0.4 IOL = 18.68 mA 0.4 Submit Documentation Feedback UNIT V Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 DLPC300 www.ti.com DLPS023A - JANUARY 2012 - REVISED JULY 2012 Interface Timing Requirements This section defines the timing requirements for the external interfaces for the DLPC300 Controller. I2C Electrical Data/Timing Table 7. I2C INTERFACE TIMING REQUIREMENTS PARAMETER 2 MIN MAX UNIT 400 kHz fscl I C clock frequency 0 tsch I2C clock high time 1 s tscl I2C clock low time 1 s 2 tsp I C spike time tsds I2C serial-data setup time 100 20 ns tsdh I2C serial-data hold time 100 ns 2 ticr I C input rise time tocf I2C output fall time 100 tbuf I2C bus free time between stop and start conditions tsts I2C start or repeat start condition setup 50 pF 30 2 s s s I C start or repeat start condition hold 1 I2C stop condition setup 1 tvd tsch Valid-data time of ACK condition ACK signal from SCL low to SDA (out) low I2C bus capacitive load s 1 0 Product Folder Link(s): DLPC300 s 1 s 100 pF Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated ns 1 tsph SCL low to SDA output valid ns 200 1.3 tsth Valid-data time ns 19 DLPC300 DLPS023A - JANUARY 2012 - REVISED JULY 2012 www.ti.com VCC RL = 1 k SDA DUT CL = 50 pF (see Note A) SDA LOAD CONFIGURATION Three Bytes for Complete Device Programming Stop Condition (P) Start Address Address Condition Bit 7 Bit 6 (S) (MSB) Address Bit 1 tscl R/W Bit 0 (LSB) ACK (A) Data Bit 7 (MSB) Data Bit 0 (LSB) Stop Condition (P) tsch 0.7 x VCC SCL 0.3 x VCC ticr ticf tbuf tsts tPHL tPLH tsp 0.7 x VCC SDA 0.3 x VCC ticf ticr tsth tsdh tsds tsps Repeat Start Condition Start or Repeat Start Condition Stop Condition VOLTAGE WAVEFORMS A. BYTE DESCRIPTION 1 I2C address 2, 3 P-port data CL includes probe and jig capacitance. Figure 10. I2C Interface Load Circuit and Voltage Waveforms Parallel Bus Interface Parallel bus interface supports six data transfer formats: * 16-bit RGB565 * 18-bit RGB666 * 18-bit 4:4:4 YCrCb666 * 24-bit RGB888 * 24-bit 4:4:4 YCrCb888 20 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 DLPC300 www.ti.com * DLPS023A - JANUARY 2012 - REVISED JULY 2012 16-bit 4:2:2 YCrCb (standard sampling assumed to be Y0Cb0, Y1Cr0, Y2Cb2, Y3Cr2, Y4Cb4, Y5Cr4, ...) The required PDATA(23:0) bus mapping for these 6 data transfer formats are as shown in Figure 11 . Parallel Bus Mo de - RGB 4:4:4 Source PD ATA(1 5:0 ) - RG B56 5 Mapping to RGB88 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PDATA(15:0) of the Input Pixel data bus 0 Bus Assignment Mapping R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 Data bit mapping on the DLPC300 PD ATA(17 :0) - RG B666 Ma pping to RG B888 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 PDATA(17:0) of the Input Pixel data bus Bus Assignment Mapping Data bit mapping on the DLPC300 PD ATA(23 :0) - RG B888 Ma pping 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 11 10 9 8 7 6 5 4 3 2 1 0 PDATA(23:0) of the Input Pixel data bus Bus Assignment Mapping Data bit mapping on the DLPC300 Parallel Bus Mo de - YCrCb 4:2:2 Source PD ATA(23 :0) - Cr/CbY8 8 0 Mapping 23 22 21 20 19 18 17 16 Cr/ Cb 7 C r/ Cb 6 Cr/ Cb 5 Cr/ Cb 4 C r/ Cb 3 Cr/ Cb 2 Cr/ Cb 1 Cr/ Cb 0 15 14 13 12 PDATA(23:0) of the Input Pixel data bus Bus Assignment Mapping Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Y 0 n/a n/a n/a n/a n/a n/a n/a n/a Data bit mapping on the pins of the DLPC300 Figure 11. PDATA Bus - Parallel I/F Mode Bit Mapping The parallel bus interface complies with the standard graphics interface protocol, which includes a vertical sync signal (VSYNC), horizontal sync signal (HSYNC), optional data-valid signal (DATAEN), a 24-bit data bus (PDATA), and a pixel clock (PCLK). The polarities of both syncs are programmable, as is the active edge of the clock. The relationship of these signals is shown in Figure 12. The data-valid signal (DATAEN) is optional, in that the DLPC300 provides auto-framing parameters that can be programmed to define the data-valid window, based on pixel and line counting relative to the horizontal and vertical syncs. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 21 DLPC300 DLPS023A - JANUARY 2012 - REVISED JULY 2012 www.ti.com 1 Frame t p _ vsw VSYNC ( This diagram assumes the VSYNC active edge is the Rising edge) tp _ vbp t p _vfp HSYNC DATAEN 1 Line t p _hsw HSYNC t p _ hbp ( This diagram assumes the HSYNC active edge is the Rising edge) t p_ hfp DATAEN PDATA (23 /15 :0) P0 P1 P2 P3 P n-2 P n- 1 Pn PCLK Figure 12. Parallel I/F Frame Timing Table 8. Parallel Interface Frame Timing Requirements PARAMETER TEST CONDITIONS tp_vsw Pulse duration - VSYNC high 50% reference points Vertical back porch - time from the leading edge of VSYNC to the leading edge HSYNC for the first active line (1) 50% reference points tp_vbp Vertical front porch - time from the leading edge of the HSYNC following the last active line in a frame to the leading edge of VSYNC (1) 50% reference points tp_vfp tp_tvb Total vertical blanking - time from the leading edge of 50% reference points HSYNC following the last active line of one frame to the leading edge of HSYNC for the first active line in the next frame. [This is equal to the sum of vertical back porch (tp_vbp) + vertical front porch (tp_vfp)] tp_hsw Pulse duration - HSYNC high 50% reference points tp_hbp Horizontal back porch - time from rising edge of HSYNC to rising edge of DATAEN 50% reference points tp_hfp Horizontal front porch - time from falling edge of DATAEN to rising edge of HSYNC 50% reference points tp_thh Total horizontal blanking - sum of horizontal front and back porches (2) 50% reference points (1) (2) 22 MIN MAX UNIT 1 lines 2 lines 1 lines 12 lines 4 128 PCLKs 4 PCLKs 8 PCLKs PCLKs The programmable parameter Vertical Sync Line Delay (I2C: 0x23) must be set such that: 6 - Vertical Front Porch (tp_vfp) (min 0) Vertical Sync Line Delay Vertical Back Porch (tp_vbp) -2 (max 15). The default value for Vertical Sync Line Delay is set to 5; thus, only a Vertical Back Porch less than 7 requires potential action. Total horizontal blanking is driven by the maximum line rate for a given source, which is a function of resolution and orientation. See Table 10 for the maximum line rate for each source/display combination. tp_thb = Roundup[(1000 x fclock)/LR] - APPL where fclock = pixel clock rate in MHz, LR = line rate in kHz and APPL is the number of active pixels per (horizontal) line. If tp_thb is calculated to be less than tp_hbp + tp_hfp, then the pixel clock rate is too low or the line rate is too high and one or both must be adjusted. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 DLPC300 www.ti.com DLPS023A - JANUARY 2012 - REVISED JULY 2012 tp_clkper tp_wh tp_wi PCLK tp_h tp_su Figure 13. Parallel and BT.656 I/F General Timing Table 9. Parallel Interface General Timing Requirements PARAMETER fclock Clock frequency, PCLK tp_clkper Clock period, PCLK TEST CONDITIONS 50% reference points (1) MIN MAX UNIT 1 33.5 MHz 29.85 1,000 ns tp_clkjit Clock jitter, PCLK tp_wh Pulse duration low, PCLK 50% reference points 10 ns tp_wl Pulse duration high, PCLK 50% reference points 10 ns tp_su Setup time - HSYNC, DATEN, PDATA(23:0) valid before the active edge of PCLK (2) (3) 50% reference points 3 ns tp_h Hold time - HSYNC, DATEN, PDATA(23:0) valid after the active edge of PCLK (2) (3) 50% reference points 3 ns tt Transition time - all signals 20% to 80% reference points (1) (2) (3) Maximum fclock 0.2 4 ns Clock jitter (in ns) should be calculated using this formula: Jitter = [ 1/ fclock - 28.35 ns ]. Setup and hold times must be met during clock jitter. The active (capture) edge of PCLK for HSYNC, DATEN and PDATA(23:0) is SW programmable but defaults to the rising edge. See . Table 10. Parallel I/F Maximum Supported Horizontal Line Rate DMD 0.3 WVGA diamond (1) PARALLEL BUS SOURCE RESOLUTION LANDSCAPE FORMAT PORTRAIT FORMAT RESOLUTION (HxV) MAX LINE RATE (kHz) RESOLUTION (HxV) MAX LINE RATE (kHz) NSTC (1) 720 x 240 17 Not supported N/A PAL (1) 720 x 288 20 Not supported N/A QVGA 320 x 240 17 240 x 320 22 QWVGA 427 x 240 17 240 x 427 (2) 27 3:2 VGA 640 x 430 30 430 x 640 45 4:3 VGA 640 x 480 34 480 x 640 45 WVGA-720 720 x 480 34 480 x 720 51 WVGA-752 752 x 480 34 480 x 752 53 WVGA-800 800 x 480 34 480 x 800 56 WVGA-852 852 x 480 34 480 x 852 56 WVGA-853 853 x 480 34 480 x 853 56 WVGA-854 854 x 480 34 480 x 854 56 WVGA-864 864 x 480 34 480 x 864 56 Optical test 608 x 684 48 Not supported N/A NTSC and PAL are assumed to be interlaced sources. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 23 DLPC300 DLPS023A - JANUARY 2012 - REVISED JULY 2012 www.ti.com BT.656 Interface The DLPC300 controller input interface supports the industry standard BT.656 parallel video interface. See the appropriate ITU-R BT.656 specification for detailed interface timing requirements. Table 11. BT.565 I/F General Timing Requirements (1) PARAMETER fclock Clock frequency, PCLK tp_clkper Clock period, PCLK TEST CONDITIONS 50% reference points (2) MIN MAX UNIT 1 33.5 MHz 29.85 1,000 ns tp_clkjit Clock jitter, PCLK tp_wh Pulse duration low, PCLK 50% reference points 10 ns tp_wl Pulse duration high, PCLK 50% reference points 10 ns tp_su Setup time - HSYNC, DATEN, PDATA(23:0) valid before the active edge of PCLK 50% reference points 3 ns tp_h Hold time - HSYNC, DATEN, PDATA(23:0) valid 50% reference points after the active edge of PCLK 3 ns tt Transition time - all signals (1) (2) Maximum fclock 20% to 80% reference points 0.2 4 ns The BT.656 I/F accepts 8-bit per color, 4:2:2 YCb/Cr data encoded per the industry standard via PDATA(7:0) on the active edge of PCLK (i.e., programmable) as shown in Figure 13. Clock jitter (in ns) should be calculated using this formula: Jitter = [ 1/ fclock - 28.35 ns ]. Setup and hold times must be met during clock jitter. BT.656 data bits should be mapped to the DLPC300 PDATA bus as shown in Figure 14. BT.656 Bus Mode - YCrCb 4:2:2 Source PDATA(23:0) - BT.656 Mapping 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDATA(7:0) of the Input Pixel data bus Bus Assignment Mapping n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Y 0 Data bit mapping on the pins of the ASIC Figure 14. PDATA Bus - BT.656 I/F Mode Bit Mapping 24 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 DLPC300 www.ti.com DLPS023A - JANUARY 2012 - REVISED JULY 2012 Flash Memory Interface DLPC300 uses an external 16-Mbit SPI serial flash slave memory device for configuration support. The contents of this flash memory can be downloaded from the DLPC300 product folder. The DLPC300 uses a single SPI interface, employing SPI mode 0 protocol, operating at a nominal frequency of 33.3 MHz. When RESET is released, the DLPC300 reads the contents of the serial flash memory and executes an auto-initialization routine. During this time, GPIO4_INTF is set high to indicate auto-initialization is busy. Upon completion of the auto-initialization routine, the DLPC300 sets GPIO4_INTF low to indicate that the auto-initialization routine successfully completed. The DLPC300 should support any flash device that is compatible with standard SPI mode 0 protocol and meet the timing requirement shown in Table 14. However, the DLPC300 does not support the normal (slow) read opcode, and thus cannot automatically adapt protocol and clock rate based on the electronic signature ID of the flash. The flash instead uses a fixed SPI clock and assumes certain attributes of the flash have been ensured by PCB design. The DLPC300 also assumes the flash supports address auto-incrementing for all read operations. The specific Instruction opcode and timing compatibility requirements for a DLPC300-compatible flash are listed in Table 12. Table 12. SPI Flash Instruction OpCode and Timing Compatibility Requirements SPI FLASH COMMAND OPCODE (hex) ADDRESS BYTES DUMMY BYTES CLOCK RATE Fast READ (single output) 0x0B 3 1 33.3 MHz All others Can vary Can vary Can vary 33.3 MHz The DLPC300 does not have any specific page, block or sector size requirements except that programming via the I2C interface requires the use of page-mode programming. If, however, the user would like to dedicate a portion of the serial flash for storing external data (such as calibration data) and access it through the DLPC300's I2C interface, then the minimum sector size must be considered, as it drives minimum erase size. Note that use of serial flash for storing external data may impact the number of features that can be supported in Table 13. Note that the DLPC300 does not drive the HOLD (active-low hold) or WP (active-low write protect) pins on the flash device, and thus these pins should be tied to a logic high on the PCB via an external pullup. The DLPC300 supports 1.8-, 2.5- or 3.3-V serial flash devices. To do so, VCC_FLSH must be supplied with the corresponding voltage. Table 13 contains a list of 1.8-, 2.5- and 3.3-V compatible SPI serial flash devices supported by DLPC300. Table 13. Compatible SPI Flash Device Options (1) (1) DENSITY VENDOR PART NUMBER SUPPLY VOLTAGE SUPPORTED 4 Mbit Macronix MX25U4035 1.65 V-2 V MIN CHIP SELECT HIGH TIME (tCSH) MAX FAST READ FREQ TABLE 21 OPCODE AND TIMING COMPATIBLE 30 ns 40 MHz Yes 8 Mbit Macronix MX25U8035 1.65 V-2 V 30 ns 40 MHz Yes 16 Mbit Winbond W25Q16BLxxxx 2.3 V-3.6 V 100 ns 50 MHz Yes 8 Mbit Macronix MX25L8005ZUx-xxG 2.7 V-3.6 V 100 ns 66 MHz Yes All the SPI devices listed have been verified to be compatible with DLPC300. Table 14. Flash Interface Timing Requirements (1) (2) PARAMETER fclock (1) (2) (3) TEST CONDITIONS Clock frequency, SPICLK (3) MIN MAX UNIT 33.3266 33.34 MHz Standard SPI protocol is to transmit data on the falling edge of SPICLK and to capture data on the rising edge. The DLPC300 does transmit data on the falling edge, but it also captures data on the falling edge rather than the rising edge. This provides support for SPI devices with long clock-to-Q timing. DLPC300 hold capture timing has been set to facilitate reliable operation with standard external SPI protocol devices. With the above output timing, DLPC300 provides the external SPI device 14-ns input setup and 14-ns input hold relative to the rising edge of SPICLK. This range includes the 200 ppm of the external oscillator (but no jitter). Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 25 DLPC300 DLPS023A - JANUARY 2012 - REVISED JULY 2012 www.ti.com Table 14. Flash Interface Timing Requirements(1)(2) (continued) MIN MAX tp_clkper Clock period, SPICLK PARAMETER 50% reference points TEST CONDITIONS 29.994 30.006 tp_wh Pulse duration low, SPICLK 50% reference points 10 tp_wl Pulse duration high, SPICLK 50% reference points 10 tt Transition time - all signals 20% to 80% reference points 0.2 tp_su Setup time - SPIDIN valid before SPICLK falling edge 50% reference points tp_h Hold time - SPIDIN valid after SPICLK falling edge 50% reference points tp_clqv SPICLK clock low to output valid time - SPIDOUT and SPICS0 50% reference points tp_clqx SPICLK clock low output hold time - SPI_DOUT and SPICS0 50% reference points UNIT ns ns ns 4 ns 10 ns 0 ns 1.0 -1 ns ns tclkper SPICLK (ASIC Inputs) twh twi tp_su tp_h SPIDIN (ASIC Inputs) tp_ciqv SPIDOUT, SPICS0 (ASIC Outputs) tp_cixv Figure 15. Flash Interface Timing 26 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 DLPC300 www.ti.com DLPS023A - JANUARY 2012 - REVISED JULY 2012 DMD Interface The DLPC300 controller DMD interface consists of a 76.19-MHz (nominal) DDR output-only interface with LVCMOS signaling. Table 15. DMD Interface Timing Requirements (1) PARAMETER TEST CONDITIONS MIN MAX UNIT 76.198 76.206 MHz 50% reference points 13.123 15 Pulse duration low, DMD_DCLK and DMD_SAC_CLK 50% reference points 6.2 Pulse duration high, DMD_DCLK and DMD_SAC_CLK 50% reference points 6.2 tt Transition time - all signals 20% to 80% reference points 0.3 fclock Clock frequency, DMD_DCLK and DMD_SAC_CLK (2) tp_clkper Clock period, DMD_DCLK and DMD_SAC_CLK tp_wh tp_wl ns ns ns 2 ns tp_su Output setup time - DMD_D(14:0), DMD_SCTRL, 50% reference points DMD_LOADB and DMD_TRC relative to both rising and falling edges of DMD_DCLK (3) (4) 1.5 ns Output hold time - DMD_D(14:0), DMD_SCTRL, DMD_LOADB and DMD_TRC signals relative to both rising and falling edges of DMD_DCLK (3) (4) 50% reference points tp_h 1.5 ns DMD data skew - DMD_D(14:0), DMD_SCTRL, DMD_LOADB, and DMD_TRC signals relative to each other (5) 50% reference points tp_d1_skew 0.2 ns tp_clk_skew Clock skew - DMD_DCLK and DMD_SAC_CLK relative 50% reference points to each other 0.2 ns tp_d2_skew DAD/SAC data skew - DMD_SAC_BUS, DMD_DRC_OE, DMD_DRC_BUS, and DMD_DRC_STRB signals relative to DMD_SAC_CLK 0.2 ns (1) (2) (3) (4) (5) 50% reference points Assumes a 30- series termination for all DMD interface signals This range includes the 200 ppm of the external oscillator (but no jitter). Assumes minimum DMD setup time = 1 ns and minimum DMD hold time = 1 ns Output setup/hold numbers already account for controller clock jitter. Only routing skew and DMD setup/hold need be considered in system timing analysis. Assumes DMD data routing skew = 0.1 ns max Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 27 DLPC300 DLPS023A - JANUARY 2012 - REVISED JULY 2012 www.ti.com tp_d1_skew DMD_D(14:0) DMD_SCTRL DMD_TRC DMD_LOADB tp_su tp_h DMD_DCLK tp_wl tp_wh tclk_skew DMD_SAC_CLK tp_d2_skew DMD_SAC_BUS DMD_DRC_OE DMD_DRC_BUS DMD_DRC_STRB Figure 16. DMD Interface Timing Mobile DDR Memory Interface The DLPC300 stores bit plane data in external mobile dual data rate memory (mDDR). The mDDR compatibility requirements for the DLPC300 are: * SDRAM memory type: Mobile-DDR * Size: 128 Mbit minimum. DLPC300 can only address 128 Mb; use of larger memories requires bit A13 to be grounded. * Organization: N x 16-bits wide with 4 equally sized banks * Burst length: 4 * Refresh period: 64 ms * Speed Grade tCK: 6 ns max * CAS latency (CL), tRCD,tRP parameters (clocks): 3, 3, 3 Table 16 shows the mobile-DDR DRAM devices recommended for use with the DLPC300. Table 16. Compatible Mobile DDR DRAM Device Options (6) VENDOR PART NUMBER (7) SIZE ORGANIZATION SPEED GRADE (8) (tCK) CAS LATENCY (CL) tRCD,tRP PARAMETERS (CLOCKS) Elpida EDD25163HBH-6ELS-F 256 Mbit 16M x 16 6 ns 3, 3, 3 Samsung K4X56163PN-FGC6 256 Mbit 16M x 16 6 ns 3, 3, 3 Micron MT46H16M16LFBF-6IT:H 256 Mbit 16M x 16 6 ns 3, 3, 3 Hynix H5MS2562JFR-J3M 256 Mbit 16M x 16 6 ns 3, 3, 3 The DLPC300 controller mobile DDR memory interface consists of a 16-bit wide, mobile DDR interface (i.e., LVCMOS signaling) operated at 133.33 MHz (nominal). (6) (7) (8) 28 All the SDRAM devices listed have been verified to be compatible with the DLPC300. These part numbers reflect a Pb-free package. A 6-ns speed grade corresponds to a 166-MHz mDDR device. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 DLPC300 www.ti.com DLPS023A - JANUARY 2012 - REVISED JULY 2012 Table 17. Mobile DDR Memory Interface Timing Requirements (1) (2) (3) PARAMETER tCYCLE Cycle-time reference (4) MIN MAX UNIT 7500 ps tCH CK high pulse duration 2700 ps tCL CK low pulse duration (4) 2700 ps tDQSH DQS high pulse duration (4) 2700 ps tDQSL DQS low pulse duration (4) 2700 ps tWAC CK to address and control outputs active tQAC CK to DQS output active tDAC DQS to DQ and DM output active tDQSRS (1) (2) (3) (4) (5) Input (read) DQS and DQ skew -2870 -1225 (5) 2870 ps 200 ps 1225 ps 1000 ps This includes the 200 ppm of the external oscillator (but no jitter). Output setup/hold numbers already account for controller clock jitter. Only routing skew and memory setup/hold must be considered in system timing analysis. Assumes a 30- series termination on all signal lines CK and DQS pulse duration specs for the DLPC300 assume it is interfacing to a 166-MHz mDDR device. Even though these memories are only operated at 133.33 MHz, according to memory vendors, the rated tCK spec (i.e., 6 ns) can be applied to determine minimum CK and DQS pulse duration requirements to the memory. Note that DQS must be within the tDQSRS read data-skew window but need not be centered. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 29 DLPC300 DLPS023A - JANUARY 2012 - REVISED JULY 2012 www.ti.com tCYCLE MEM_CK_P MEM_CK_N tCH MEM_ADDRS (12:0) MEM_BA (1:0) MEM_RASZ MEM_CASZ MEM_WES MEM_CSZ MEM_CKE tWAC tCL tWAC mDDR Memory Address and Control Timing tCYCLE MEM_CK_P MEM_CK_N tCH tQAC (tDQSCK) tCL tCYCLE tDQSH tDQSL MEM_xDQS tDAC MEM_xDQ(7:0) MEM_xDQ(15:8) tDAC MEM_xDM mDDR Memory Write Data Timing tCYCLE MEM_xDQS tDQSH tDQSL MEM_xDQ(first) tDQSRS MEM_xDQ(last) MEM_xDQ(7:0) Data Valid Window mDDR Memory Read Data Timing Figure 17. Mobile DDR Memory Interface Timing 30 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 DLPC300 www.ti.com DLPS023A - JANUARY 2012 - REVISED JULY 2012 Power-Up Initialization Sequence It's assumed that an external power monitor holds the DLPC300 in system reset during power up. It must do this by driving RESET to a logic-low state. It should continue to assert system reset until all controller voltages have reached minimum specified voltage levels, PARK is asserted high, and input clocks are stable. During this time, most controller outputs are driven to an inactive state and all bidirectional signals are configured as inputs to avoid contention. Controller outputs that are not driven to an inactive state are in the high-impedance state. These include DMD_PWR_EN, LEDDVR_ON, LED_SEL_0, LED_SEL_1, SPICLK, SPIDOUT, and SPICS0. Once power is stable and the PLL_REFCLK clock input to the DLPC300 is stable, then RESET should be deactivated (set to a logic high). The DLPC300 then performs a power-up initialization routine that first locks its PLL followed by loading self-configuration data from the external flash. On release of RESET, all DLPC300 I/Os become active. Immediately following the release of RESET, the GPIO4_INTF signal is driven high to indicate that the auto initialization routine is in progress. On completion of the auto-initialization routine, the DLPC300 drives GPIO4_INTF low to signal INITIALIZATION DONE (also called INIT DONE). Note that the host processor can start sending standard I2C commands after GPIO4 (INIT_DONE) goes low, or a 100-ms timer expires in the host processor, whichever is earlier. An active-high pulse on GPIO 4_INTF following the initialization period indicates an error condition has been detected. The source of the error is reported in the system status. RESET 100 m s max (ERR IRQ ) (INIT_BUSY) GPIO 4_INFT 3 ms min 0 ms min 5 ms max 2 GPIO 4_INTF is driven high within 5 ms after RESET is released to indicate Auto-Initialization is busy. I C access to DLPC300 should not start until GPIO 4_INTF (INIT_BUSY flag) goes low (this should occur within 100 ms from the release of RESET if the Motor Control function is not used. If Motor Control is used, this may take several seconds.) 2 I C or DBI-C traffic (SCL, SDA, CSZ) Figure 18. Initialization Timeline System Power-Up/Down Sequence Although the DLPC300 requires an array of power supply voltages, (e.g., VDD, VDD_PLL, VCC_18, VCC_FLSH, VCC_INTF), there are no restrictions regarding the relative order of power supply sequencing to avoid damaging the DLPC300. This is true for both power-up and power-down scenarios. Similarly, there is no minimum time between powering up or powering down the different supplies feeding the DLPC300. Note, however, that it is not uncommon for there to be power-sequencing requirements for the devices that share the supplies with the DLPC300. Although there is no risk of damaging the DLPC300 as a result of a given power sequence, from a functional standpoint there is one specific power-sequencing recommendation to ensure proper operation. In particular, all controller power should be applied and allowed to reach minimum specified voltage levels before RESET is deasserted to ensure proper power-up initialization is performed. All I/O power should remain applied as long as 1V core power is applied and RESET is de-asserted. Note that when VDD10 core power is applied but I/O power is not applied, additional leakage current may be drawn. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 31 DLPC300 DLPS023A - JANUARY 2012 - REVISED JULY 2012 VDD10 www.ti.com Point at which ALL supplies reach 95% of the their specified nominal value VDD_PLL VCC_INTF (1.8 V-3.3 V) VCC_FLSH (1.8 V-3.3 V) PARK must be set high within 500 s after RESET is released to support Auto-initialization. VCC18 VCC18 must remain active for a minimum of 100 ms after DMD_PWR_EN is de-asserted to satisfy DMD power sequence requirements. PARK Per DMD Power Sequencing Requirement 500 s Max DMD_PWR_EN (ASIC Output Signal) 500 5 s PARK must be set low a minimum of 500 s before any power is removed, before PLL_REFCLK is stopped, and before RESET is asserted to allow time for the DMD mirrors to be parked. PLL_REFCLK RESET 2 I C (SCL, SDA) GPIO 4_INTF (INIT_BUSY) PLL_REFCLK may be active before power is applied. Tstable 100 ms Min GPIO 4_INTF will be driven high shortly after RESET is released to indicate AutoInitialization is Busy 500 s Min 0 s 500 s Min The minimum requirement to set RESET = 1 is any time after PLL_REFCLK becomes stable. For external oscillator applications, this is oscillator-dependent; for crystal applications, it is crystal-dependent . 2 I C access CAN start immediately after GPIO 4_INTF (INIT_BUSY flag) goes low (this should occur within 100 ms from the release of RESET if the Motor Control function is not used. If Motor Control is used, it may take several seconds.) Figure 19. Power-Up/Down Timing System Power I/O State Considerations Note that: * If VCC18 I/O power is applied when VDD10 core power is not applied, then all mDDR (non fail-safe) and nonmDDR (fail-safe) output signals associated with the VCC18 supply are in a high-impedance state. * If VCC_INTF or VCC_FLSH I/O power is applied when VDD10 core power is not applied, then all output signals associated with these inactive I/O supplies are in a high-impedance state. * If VDD10 core power is applied but VCC_INTF or VCC_FLSH I/O power is not applied, then all output signals associated with these inactive I/O supplies are in a high-impedance state. * If VDD10 Core power is applied but VCC18 I/O power is not applied,, then all mDDR (non fail-safe) and nonmDDR (fail-safe) output signals associated with the VCC18 I/O supply are in a high-impedance state; however, if driven high externally, only the non-mDDR (fail-safe) output signals remain in a high-impedance state, and the mDDR (non fail-safe) signals are shorted to ground through clamping diodes. 32 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 DLPC300 www.ti.com DLPS023A - JANUARY 2012 - REVISED JULY 2012 Power-Good (PARK) Support The PARK signal is defined to be an early warning signal that should alert the controller 500 s before dc supply voltages have dropped below specifications. This allows the controller time to park the DMD, ensuring the integrity of future operation. Note that the reference clock should continue to run and RESET should remain deactivated for at least 500 s after PARK has been deactivated (set to a logic low) to allow the park operation to complete. Hot-Plug Usage Note that the DLPC300 provides fail-safe I/O on all host-interface signal (signals powered by VCC_INTF). This allows these inputs to be driven high even when no I/O power is applied. Under this condition, the DLPC300 does not load the input signal nor draw excessive current that could degrade controller reliability. Thus for example, the I2C bus from the host to other components would not be affected by powering off VCC_INTF to the DLPC300. Note that weak pullups or pulldowns are recommended on signals feeding back to the host to avoid floating inputs. Maximum Signal Transition Time Unless otherwise noted, the maximum recommended 20%-80% rise/fall time to avoid input buffer oscillation is 10 ns. This applies to all DLPC300 input signals. Note, however, that the PARK input signal includes an additional small digital filter that ignores any input-buffer transitions caused by a slower rise/ fall time for up to 150 ns. Configuration Control The primary configuration control mechanism for the DLPC300 is the I2C interface. See the DLPC300 Software Programmer's Guide, TI Literature Number DLPU004, for details on how to configure and control the DLPC300. Thermal Considerations The underlying thermal limitation for the DLPC300 is that the maximum operating junction temperature (TJ) not be exceeded (see Recommended Operating Conditions). This temperature is dependent on operating ambient temperature, airflow, PCB design (including the component layout density and the amount of copper used), power dissipation of the DLPC300, and power dissipation of surrounding components. The DLPC300 package is designed primarily to extract heat through the power and ground planes of the PCB, thus copper content and airflow over the PCB are important factors. Table 18. Package Thermal Resistance PARAMETER MIN NOM MAX UNIT RJC Thermal resistance, junction-to-case 19.52 C/W RJA Thermal resistance, junction-to-air, with no forced airflow 64.96 C/W External Clock Input Crystal Oscillator The DLPC300 requires an external reference clock to feed its internal PLL. This reference may be supplied via a crystal or oscillator. The DLPC300 accepts a reference clock of 16.667 MHz with a maximum frequency variation of 200 ppm (including aging, temperature and trim component variation). When a crystal is used, several discrete components are also required as shown in Figure 20. PLL_REFCLK_I PLL_REFCLK_O CL = Crystal load capacitance (Farads) CL1 = 2 * (CL - Cstray_pll_refclk_i) CL2 = 2 * (CL - Cstray_pll_refclk_o) Where: Cstray_pll_refclk_i = Sum of package and PCB srtay capacitance at the crystal pin associated with the ASIC pin pll_refclk_i. Cstray_pll_refclk_o = Sum of package and PCB srtay capacitance at the crystal pin associated with the ASIC pin pll_refclk_o. RFB RS Crystal C L1 C L2 Figure 20. Recommended Crystal Oscillator Configuration Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 33 DLPC300 DLPS023A - JANUARY 2012 - REVISED JULY 2012 www.ti.com Table 19. Crystal Port Electrical Characteristics NOM UNIT PLL_REFCLK_I TO GND capacitance PARAMETER 4.5 pF PLL_REFCLK_O TO GND capacitance 4.5 pF Table 20. Recommended Crystal Configuration PARAMETER RECOMMENDED Crystal circuit configuration UNIT Parallel resonant Crystal type Fundamental (first harmonic) Crystal nominal frequency 16.667 MHz 200 PPM Crystal drive level 100 max uW Crystal equivalent series resistance (ESR) 80 max Crystal load 12 pF RS drive resistor (nominal) 100 Crystal frequency tolerance (including accuracy, temperature, aging and trim sensitivity) RFB feedback resistor (nominal) 1 M CL1 external crystal load capacitor See Figure 20 pF CL2 external crystal load capacitor See Figure 20 pF PCB layout A ground isolation ring around the crystal is recommended If an external oscillator is used, then the oscillator output must drive the PLL_REFCLK_I pin on the DLPC300 controller, and the PLL_REFCLK_O pins should be left unconnected. The benefit of an oscillator is that it can be made to provide a spread-spectrum clock that reduces EMI. Note, however, that the DLPC300 can only accept between 0% to -2% spreading (i.e., down spreading only) with a modulation frequency between 20kHz and 65 KHz and a triangular waveform. Similar to the crystal option, the oscillator input frequency is limited to the 16.667 MHz. It is assumed that the external crystal or oscillator stabilizes within 50 ms after stable power is applied. PLL The DLPC300 contains one internal PLL that has a dedicated analog supply (VDD_PLL , VSS_PLL). As a minimum, the VDD_PLL power and VSS_PLL ground pins should be isolated using an RC-filter consisting of two 50- series ferrites and two shunt capacitors (to widen the spectrum of noise absorption). It is recommended that one capacitor be a 0.1-f capacitor and the other be a 0.01-f capacitor. All four components should be placed as close to the controller as possible, but it is especially important to keep the leads of the high-frequency capacitors as short as possible. Note that both capacitors should be connected across VDD_PLL and VSS_PLL on the controller side of the ferrites. The PCB layout is critical to PLL performance. It is vital that the quiet ground and power are treated like analog signals. Therefore, VDD_PLL must be a single trace from the DLPC300 to both capacitors and then through the series ferrites to the power source. The power and ground traces should be as short as possible, parallel to each other and as close as possible to each other. 34 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 DLPC300 www.ti.com DLPS023A - JANUARY 2012 - REVISED JULY 2012 Signal VIA PCB Pad VIA to Common Analog Digital Board Power Plane ASIC Pad 11 VIA to Common Analog Digital Board Ground Plane 12 13 14 15 A Local Decoupling for the PLL Digital Supply G 1.0V PWR VDD_ PLL Signal Signal Signal H VDD VSS_ PLL Signal PLL_ REF CLK_O J Signal Signal Signal PLL_ REF CLK_I K GND 0.1uF 0.01uF FB FB Crystal Circuit Figure 21. PLL Filter Layout General Handling Guidelines for Unused CMOS-Type Pins To avoid potentially damaging current caused by floating CMOS input-only pins, it is recommended that unused controller input pins be tied through a pullup resistor to its associated power supply or through a pulldown to ground. For controller inputs with internal pullup or pulldown resistors, it is unnecessary to add an external pullup/pulldown unless specifically recommended. Note that internal pullup and pulldown resistors are weak and should not be expected to drive the external line. The DLPC300 implements very few internal resistors and these are noted in the pin list. Unused output-only pins can be left open. When possible, it is recommended that unused bidirectional I/O pins be configured to their output state such that the pin can be left open. If this control is not available and the pins may become an input, then they should be pulled up (or down) using an appropriate resistor. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 35 DLPC300 DLPS023A - JANUARY 2012 - REVISED JULY 2012 www.ti.com REVISION HISTORY Changes from Original (January 2012) to Revision A Page * Changed Features Item From: Supports Input Resolutions 608x684, 854x480 (WVGA), 640x480 (VGA), 320x240 (QVGA) To: Supports Input Resolutions 608x684, 864x480, 854x480 (WVGA), 640x480 (VGA), 320x240 (QVGA) ......... 1 * Changed ............................................................................................................................................................................... 6 * Changed unit values from ms to s in Table 7. .................................................................................................................. 19 36 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): DLPC300 PACKAGE OPTION ADDENDUM www.ti.com 9-Jun-2012 PACKAGING INFORMATION Orderable Device DLPC300ZVB Status (1) ACTIVE Package Type Package Drawing NFBGA ZVB Pins Package Qty 176 10 Eco Plan (2) Pb-Free (RoHS) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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