Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM DDR SDRAM Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die with 64/72-bit ECC/Non ECC 66 TSOP-II with Pb-Free (RoHS compliant) Revision 0.2 October. 2004 Rev. 0.2 October. 2004 256MB, 512MB, 1GB Unbuffered SODIMM Preliminary DDR SDRAM 512Mb C-die Revision History Revision 0.0 (April, 2004) - First version for internal review Revision 0.1 (September, 2004) - Preliminary spec release. Revision 0.2 (October, 2004) - Changed IDD current. Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM 200Pin Unbuffered SODIMM based on 512Mb C-die (x8, x16) Ordering Information Part Number Density Organization Component Composition Height M470L3324CU0-C(L)CC/B3/A2/B0 256MB 32M x 64 32Mx16 (K4H511638C) * 4EA M470L6524CU0-C(L)CC/B3/A2/B0 512MB 64M x 64 32Mx16 (K4H511638C) * 8EA 1,250mil M485L3324CU0-C(L)CC/B3/A2/B0 256MB 32M x 72 32Mx16 (K4H511638C) * 5EA 1,250mil M485L6523CU0-C(L)CC/B3/A2/B0 512MB 64M x 72 64Mx8 (K4H510838C) * 9EA 1,400mil M485L2829CU0-C(L)A2/B0 1GB 128M x 72 st.128Mx8 (K4H1G0738C) * 9EA 1,400mil 1,250mil Operating Frequencies CC(DDR400@CL=3) B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) - 133MHz 133MHz 100MHz Speed @CL2.5 166MHz 166MHz 133MHz 133MHz Speed @CL3 200MHz - - - CL-tRCD-tRP 3-3-3 2.5-3-3 2-3-3 2.5-3-3 Speed @CL2 Feature * VDD : 2.5V 0.2V, VDDQ : 2.5V 0.2V for DDR266, 333 * VDD : 2.6V 0.1V, VDDQ : 2.6V 0.1V for DDR400 * Double-data-rate architecture; two data transfers per clock cycle * Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16) * Differential clock inputs(CK and CK) * DLL aligns DQ and DQS transition with CK transition * Programmable Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock) * Programmable Burst length (2, 4, 8) * Programmable Burst type (sequential & interleave) * Edge aligned data output, center aligned data input * Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) * Serial presence detect with EEPROM * PCB : Height - 256MB(non ECC/ECC SS, 1250mil), 512MB/1GB(non ECC DS, 1250mil, ECC DS, 1400mil) * SSTL_2 Interface * 66pin TSOP II Pb-Free package * RoHS compliant SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM Pin Configurations (Front side/back side) Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 /CK0 VSS 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 DQ27 VDD CB0 CB1 VSS DQS8 CB2 VDD CB3 DU VSS CK2 /CK2 VDD CKE1 DU A12 A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 /WE /CS0 *DU(A13) VSS DQ32 DQ33 VDD DQS4 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDDSPD VDDID 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7 *DU/(RESET) VSS VSS VDD VDD CKE0 *DU(BA2) A11 A8 VSS A6 A4 A2 A0 VDD BA1 /RAS /CAS /CS1 DU VSS DQ36 DQ37 VDD DM4 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD /CK1 CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU KEY 41 43 45 47 49 51 53 55 57 59 61 63 65 DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 KEY DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 42 44 46 48 50 52 54 56 58 60 62 64 66 Note 1. * : These pins are not used in this module. 2. Pins 71, 72, 73, 74, 77, 78, 79, 80, 83, 84 are not used on x64(M470~ ) module, & used on x72(M485 ~ ) module. 3. Pins 95,122 are NC for 1Row module & used for 2Row moule(M470L6524CU0,M485L2829CU0). Pin Description Pin Name Function Pin Name Function A0 ~ A12 Address input (Multiplexed) DM0 ~ 7, 8(for ECC) Data - in mask BA0 ~ BA1 Bank Select Address VDD Power supply (2.5V for DDR266/333, 2.6V for DDR400) DQ0 ~ DQ63 Data input/output VDDQ Power Supply for DQS (2.5V for DDR266/333, 2.6V for DDR400) DQS0 ~ DQS8 Data Strobe input/output VSS Ground CK0,CK0 ~ CK2, CK2 Clock input VREF Power supply for reference CKE0, CKE1(for double banks) Clock enable input VDDSPD Serial EEPROM Power/Supply ( 2.3V to 3.6V ) CS0, CS1(for double banks) Chip select input SDA Serial data I/O RAS Row address strobe SCL Serial clock CAS Column address strobe SA0 ~ 2 Address in EEPROM WE Write enable NC No connection CB0 ~ CB7 (for x72 module) Check bit(Data-in/data-out) Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM 256MB, 32M x 64 Non ECC Module (M470L3324CU0) (Populated as 1 bank of x16 DDR SDRAM Module) FUNCTIONAL BLOCK DIAGRAM CS0 DQS0 DM0 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 LDQS LDM I/0 15 I/0 14 I/0 13 I/0 12 I/0 8 I/0 9 I/0 10 I/0 11 DQS1 DM1 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 UDQS UDM I/0 3 I/0 2 I/0 1 I/0 0 I/0 4 I/0 5 I/0 6 I/0 7 DQS2 DM2 DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 LDQS LDM I/0 15 I/0 14 I/0 13 I/0 12 I/0 8 I/0 9 I/0 10 I/0 11 DQS3 DM3 DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31 UDQS UDM I/0 3 I/0 2 I/0 1 I/0 0 I/0 4 I/0 5 I/0 6 I/0 7 CS D0 CS D1 BA0 - BA1 BA0-BA1: DDR SDRAMs D0 - D3 A0 - A12 A0-A12: DDR SDRAMs D0 - D3 RAS RAS: SDRAMs D0 - D3 CAS CAS: SDRAMs D0 - D3 CKE0 CKE: SDRAMs D0 - D3 WE WE: SDRAMs D0 - D3 VDDSPD VDD/VDDQ DQS4 DM4 DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39 LDQS LDM I/0 15 I/0 14 I/0 13 I/0 12 I/0 8 I/0 9 I/0 10 I/0 11 DQS5 DM5 DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47 UDQS UDM I/0 3 I/0 2 I/0 1 I/0 0 I/0 4 I/0 5 I/0 6 I/0 7 DQS6 DM6 DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55 LDQS LDM I/0 15 I/0 14 I/0 13 I/0 12 I/0 8 I/0 9 I/0 10 I/0 11 DQS7 DM7 DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63 UDQS UDM I/0 3 I/0 2 I/0 1 I/0 0 I/0 4 I/0 5 I/0 6 I/0 7 CS D2 CS D3 D0/D2/Cap R=120 5% Clock Wiring Clock Input CK0/CK0 CK1/CK1 CK2/CK2 SDRAMs 2 SDRAMs 2 SDRAMs NC Cap/Cap/Cap CK0/1/2 CK0/1/2 Card Edge D1/D3/Cap Cap/Cap/Cap SPD D0 - D3 D0 - D3 Serial PD VREF D0 - D3 SCL VSS D0 - D3 WP A0 A1 A2 SA0 SA1 SA2 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must SDA be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM 512MB, 64M x 64 Non ECC Module (M470L6524CU0) (Populated as 2 bank of x16 DDR SDRAM Module) Functional Block Diagram CS1 CS0 DQS0 DM0 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 LDQS LDM I/0 15 I/0 14 I/0 13 I/0 12 I/0 11 I/0 10 I/0 9 I/0 8 DQS1 DM1 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 UDQS UDM I/0 7 I/0 6 I/0 5 I/0 4 I/0 3 I/0 2 I/0 1 I/0 0 DQS2 DM2 DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 LDQS LDM I/0 15 I/0 14 I/0 13 I/0 12 I/0 11 I/0 10 I/0 9 I/0 8 DQS3 DM3 DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31 UDQS UDM I/0 7 I/0 6 I/0 5 I/0 4 I/0 3 I/0 2 I/0 1 I/0 0 CS D0 LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 CS D4 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15 CS D1 LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 CS D5 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15 DQS4 DM4 DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39 LDQS LDM I/0 15 I/0 14 I/0 13 I/0 12 I/0 11 I/0 10 I/0 9 I/0 8 DQS5 DM5 DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47 UDQS UDM I/0 7 I/0 6 I/0 5 I/0 4 I/0 3 I/0 2 I/0 1 I/0 0 DQS6 DM6 DQ48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55 LDQS LDM I/0 15 I/0 14 I/0 13 I/0 12 I/0 11 I/0 10 I/0 9 I/0 8 DQS7 DM7 DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63 UDQS UDM I/0 7 I/0 6 I/0 5 I/0 4 I/0 3 I/0 2 I/0 1 I/0 0 LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 CS D2 CS D6 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15 LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 CS D3 CS D7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15 *Clock Net Wiring D0/D2/Cap BA0 - BA1 BA0-BA1: DDR SDRAMs D0 - D7 A0 - A12 A0-A12: DDR SDRAMs D0 - D7 RAS RAS: SDRAMs D0 - D7 CAS CAS: SDRAMs D0 - D7 CKE0 CKE: SDRAMs D0 - D3 CKE1 CKE: SDRAMs D4 - D7 WE WE: SDRAMs D0 - D7 VDDSPD VDD/VDDQ D0 - D7 VSS D0 - D7 CK0/1/2 CK0/1/2 Card 4 SDRAMs 4 SDRAMs NC Edge D5/D7/Cap Serial PD SCL SDA WP VREF R=120 SDRAMs D4/D6/Cap SPD D0 - D7 D1/D3/Cap Clock Wiring Clock Input CK0/CK0 CK1/CK1 CK2/CK2 A0 A1 A2 SA0 SA1 SA2 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM 256MB, 32M x 72 ECC Module (M485L3324CU0) (Populated as 1 bank of x16 DDR SDRAM Module) Functional Block Diagram CS0 DQS0 DM0 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 LDQS LDM I/0 15 I/0 14 I/0 13 I/0 12 I/0 8 I/0 9 I/0 10 I/0 11 DQS1 DM1 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 UDQS UDM I/0 3 I/0 2 I/0 1 I/0 0 I/0 4 I/0 5 I/0 6 I/0 7 DQS2 DM2 DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 LDQS LDM I/0 15 I/0 14 I/0 13 I/0 12 I/0 8 I/0 9 I/0 10 I/0 11 DQS3 DM3 DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31 UDQS UDM I/0 3 I/0 2 I/0 1 I/0 0 I/0 4 I/0 5 I/0 6 I/0 7 CS D0 CS D1 DQS4 DM4 DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39 LDQS LDM I/0 15 I/0 14 I/0 13 I/0 12 I/0 8 I/0 9 I/0 10 I/0 11 DQS5 DM5 DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47 UDQS UDM I/0 3 I/0 2 I/0 1 I/0 0 I/0 4 I/0 5 I/0 6 I/0 7 DQS6 DM6 DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55 LDQS LDM I/0 15 I/0 14 I/0 13 I/0 12 I/0 8 I/0 9 I/0 10 I/0 11 DQS7 DM7 DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63 UDQS UDM I/0 3 I/0 2 I/0 1 I/0 0 I/0 4 I/0 5 I/0 6 I/0 7 CS D2 DQS4 DM4 CB 0 CB 1 CB 2 CB 3 CB 4 CB 5 CB 6 CB 7 VDDQ 47K DQS DM I/0 15 I/0 14 I/0 13 I/0 12 I/0 8 I/0 9 I/0 10 I/0 11 CS D4 UDQS UDM I/0 7 I/0 6 I/0 5 I/0 4 I/0 3 I/0 2 I/0 1 I/0 0 CS D3 D0/D2/D4 Cap/Cap/Cap R=120 5% CK0/1/2 CK0/1/2 Card Edge D1/D3/Cap Cap/Cap/Cap Clock Wiring BA0 - BA1 BA0-BA1: DDR SDRAMs D0 - D4 A0 - A12 A0-A12: DDR SDRAMs D0 - D4 RAS RAS: SDRAMs D0 - D4 CAS CAS: SDRAMs D0 - D4 SCL CKE0 CKE: SDRAMs D0 - D4 WP WE VDDSPD VDD/VDDQ Clock Input CK0/CK0 CK1/CK1 CK2/CK2 Serial PD SDA A0 A1 A2 SA0 SA1 SA2 WE: SDRAMs D0 - D4 SDRAMs 2 SDRAMs 2 SDRAMs 1 SDRAMs Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. SPD D0 - D4 D0 - D4 VREF D0 - D4 VSS D0 - D4 Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM 512MB, 64M x 72 ECC Module (M485L6523CU0) (Populated as 1 bank of x8 DDR SDRAM Module) Functional Block Diagram CS0 DQS0 DQS4 DM4 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 7 I/O 5 I/O 0 I/O 2 I/O 6 I/O 4 I/O 1 I/O 3 CS D0 DQS1 DQS5 DM1 DM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 7 I/O 5 I/O 0 I/O 2 I/O 6 I/O 4 I/O 1 I/O 3 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 3 I/O 1 I/O 4 I/O 6 I/O 2 I/O 0 I/O 5 I/O 7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 3 I/O 1 I/O 4 I/O 6 I/O 2 I/O 0 I/O 5 I/O 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 3 I/O 1 I/O 4 I/O 6 I/O 2 I/O 0 I/O 5 I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 3 I/O 1 I/O 4 I/O 6 I/O 2 I/O 0 I/O 5 I/O 7 DQS CS DQS D1 CS DQS D4 CS DQS D5 DQS6 DQS2 DM2 DM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 7 I/O 5 I/O 0 I/O 2 I/O 6 I/O 4 I/O 1 I/O 3 CS DQS D2 DQS3 DQS7 DM3 DM7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 7 I/O 5 I/O 0 I/O 2 I/O 6 I/O 4 I/O 1 I/O 3 CS DQS D3 CS DQS D6 * Clock Wiring CS DQS D7 Clock Input DDR SDRAMs CK0/CK0 CK1/CK1 5 DDR SDRAMs 4 DDR SDRAMs *Clock Net Wiring DQS8 D0/D4/Cap DM8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 7 I/O 6 I/O 5 I/O 4 CS DQS D1/D5/Cap D8 R=120 Serial PD SCL SDA WP A0 A1 A2 SA0 SA1 SA2 CK0/1/2 CK0/1/2 Card Edge D2/D6/Cap D3/D7/Cap D8/Cap/Cap Cap/Cap/Cap BA0 - BA1 BA0-BA1: DDR SDRAMs D0 - D8 A0 - A12 A0-A12: DDR SDRAMs D0 - D8 VDDSPD VDD/VDDQ SPD D0 - D8 RAS RAS: DDR SDRAMs D0 - D8 CAS CAS: DDR SDRAMs D0 - D8 VREF D0 - D8 CKE0 CKE: DDR SDRAMs D0 - D8 VSS D0 - D8 WE WE: DDR SDRAMs D0 - D8 D0 - D8 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%. Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM 1GB, 128M x 72 ECC Module (M485L2829CU0) (Populated as 2 bank of x8 DDR SDRAM Module) Functional Block Diagram CS1 CS0 DQS0 DQS4 DM4 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 7 I/O 5 I/O 0 I/O 2 I/O 6 I/O 4 I/O 1 I/O 3 CS DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 D0 DM I/O 7 I/O 5 I/O 0 I/O 2 I/O 6 I/O 4 I/O 1 I/O 3 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 3 I/O 1 I/O 4 I/O 6 I/O 2 I/O 0 I/O 5 I/O 7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 3 I/O 1 I/O 4 I/O 6 I/O 2 I/O 0 I/O 5 I/O 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 3 I/O 1 I/O 4 I/O 6 I/O 2 I/O 0 I/O 5 I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 3 I/O 1 I/O 4 I/O 6 I/O 2 I/O 0 I/O 5 I/O 7 DQS D9 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 3 I/O 1 I/O 4 I/O 6 I/O 2 I/O 0 I/O 5 I/O 7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 3 I/O 1 I/O 4 I/O 6 I/O 2 I/O 0 I/O 5 I/O 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 3 I/O 1 I/O 4 I/O 6 I/O 2 I/O 0 I/O 5 I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 3 I/O 1 I/O 4 I/O 6 I/O 2 I/O 0 I/O 5 I/O 7 CS DQS D4 CS DQS D13 DQS5 DQS1 DM5 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 7 I/O 5 I/O 0 I/O 2 I/O 6 I/O 4 I/O 1 I/O 3 CS DQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 D1 DM I/O 7 I/O 5 I/O 0 I/O 2 I/O 6 I/O 4 I/O 1 I/O 3 CS DQS D10 CS DQS D5 CS DQS D14 DQS6 DQS2 DM6 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 7 I/O 5 I/O 0 I/O 2 I/O 6 I/O 4 I/O 1 I/O 3 CS DQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 D2 DM I/O 7 I/O 5 I/O 0 I/O 2 I/O 6 I/O 4 I/O 1 I/O 3 CS DQS D11 DQS3 DQS7 DM3 DM7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 7 I/O 5 I/O 0 I/O 2 I/O 6 I/O 4 I/O 1 I/O 3 CS DQS D3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 7 I/O 5 I/O 0 I/O 2 I/O 6 I/O 4 I/O 1 I/O 3 CS DQS D12 CS DQS D6 CS DQS D7 CS DQS D15 CS DQS D16 * Clock Wiring DQS8 DM8 Serial PD CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 7 I/O 6 I/O 5 I/O 4 CS DQS D8 CB8 CB9 CB10 CB11 CB12 CB13 CB14 CB15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 7 I/O 6 I/O 5 I/O 4 CS DQS Clock Input DDR SDRAMs CK0/CK0 CK1/CK1 10 DDR SDRAMs 8 DDR SDRAMs SCL SDA WP D17 A0 A1 A2 SA0 SA1 SA2 *Clock Net Wiring D0(D9) / D4(D13)/Cap D1(D10) / D5(D14)/Cap R=120 CK0/1/2 CK0/1/2 Card Edge D2(D11) / D6(D15)/Cap D3(D12) / D7(D16)/Cap D8(D17) / Cap/Cap BA0 - BA1 BA0-BA1: DDR SDRAMs D0 - D8 A0 - A12 A0-A12: DDR SDRAMs D0 - D8 Cap/Cap/Cap VDDSPD SPD RAS RAS: DDR SDRAMs D0 - D8 CAS CAS: DDR SDRAMs D0 - D8 CKE0/1 CKE: DDR SDRAMs D0 - D8 VREF D0 - D8 WE WE: DDR SDRAMs D0 - D8 VSS D0 - D8 VDD/VDDQ D0 - D8 D0 - D8 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%. Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM Absolute Maximum Ratings Parameter Symbol Value Unit VIN, VOUT -0.5 ~ 3.6 V VDD -1.0 ~ 3.6 V Voltage on VDDQ supply relative to Vss VDDQ -1.0 ~ 3.6 V Storage temperature TSTG -55 ~ +150 C Power dissipation PD 1.5 * # of component W Short circuit current IOS 50 mA Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operating Conditions Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70C) Parameter Symbol Min Max Unit Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333) VDD 2.3 2.7 V Supply voltage(for device with a nominal VDD of 2.6V for DDR400) VDD 2.5 2.7 V I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333) VDDQ 2.3 2.7 V I/O Supply voltage(for device with a nominal VDD of 2.6V for DDR400) VDDQ 2.5 2.7 V I/O Reference voltage VREF 0.49*VDDQ 0.51*VDDQ V 1 I/O Termination voltage(system) VTT VREF-0.04 VREF+0.04 V 2 VIH(DC) VREF+0.15 VDDQ+0.3 V Input logic low voltage VIL(DC) -0.3 VREF-0.15 V Input Voltage Level, CK and CK inputs VIN(DC) -0.3 VDDQ+0.3 V Input Differential Voltage, CK and CK inputs VID(DC) 0.36 VDDQ+0.6 V 3 V-I Matching: Pullup to Pulldown Current Ratio VI(Ratio) 0.71 1.4 - 4 II -2 2 uA 5 Input logic high voltage Input leakage current Output leakage current IOZ -5 Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V IOH -16.8 mA Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V IOL 16.8 mA Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V IOH -9 mA Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V IOL 9 mA Note uA Note : 1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may not exceed +/-2% of the dc value. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0. Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM DDR SDRAM IDD spec table M470L3324CU0 (32M x 64, 256MB Module) (VDD=2.7V, T = 10C) Symbol CC(DDR400@CL=3) B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit IDD0 480 420 380 380 mA IDD1 640 560 520 520 mA IDD2P 20 20 20 20 mA IDD2F 120 120 120 120 mA IDD2Q 100 100 100 100 mA IDD3P 180 120 120 120 mA IDD3N 240 180 180 180 mA IDD4R 760 680 620 620 mA IDD4W 860 740 640 640 mA IDD5 IDD6 880 820 780 780 mA Normal 20 20 20 20 mA Low power 12 12 12 12 mA 1,600 1,520 1,380 1,380 mA IDD7A Notes Optional * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. M470L6524CU0 (64M x 64, 512MB Module) (VDD=2.7V, T = 10C) Symbol IDD6 CC(DDR400@CL=3) B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit IDD0 720 600 560 560 mA IDD1 880 740 700 700 mA IDD2P 40 40 40 40 mA IDD2F 240 240 240 240 mA IDD2Q 200 200 200 200 mA IDD3P 360 240 240 240 mA IDD3N 480 360 360 360 mA IDD4R 1,000 860 800 800 mA IDD4W 1,100 920 820 820 mA IDD5 1,120 1,000 960 960 mA 40 40 40 40 mA Normal Low power IDD7A 24 24 24 24 mA 1,840 1,700 1,560 1,560 mA Notes Optional * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM DDR SDRAM IDD spec table M485L3324CU0 (32M x 72, 1GB Module) (VDD=2.7V, T = 10C) Symbol IDD6 CC(DDR400@CL=3) B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit IDD0 600 530 480 480 mA IDD1 800 700 650 650 mA IDD2P 30 30 30 30 mA IDD2F 150 150 150 150 mA IDD2Q 130 130 130 130 mA IDD3P 230 150 150 150 mA IDD3N 300 230 230 230 mA IDD4R 950 850 780 780 mA IDD4W 1,080 930 800 800 mA IDD5 1,100 1,030 980 980 mA Normal 25 25 25 25 mA Low power 15 15 15 15 mA 2,000 1,900 1,730 1,730 mA IDD7A Notes Optional * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. M485L6523CU0 (64M x 72, 512MB Module) (VDD=2.7V, T = 10C) Symbol IDD6 CC(DDR400@CL=3) B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit IDD0 1,080 950 860 860 IDD1 1,350 1,220 1,130 1,130 mA IDD2P 50 50 50 50 mA IDD2F 270 270 270 270 mA IDD2Q 230 230 230 230 mA IDD3P 410 270 270 270 mA IDD3N 540 410 410 410 mA IDD4R 1,400 1,260 1,130 1,130 mA IDD4W 1,580 1,350 1,170 1,170 mA IDD5 1,980 1,850 1,760 1,760 mA Normal 45 45 45 45 mA Low power 27 27 27 27 mA 3,470 3,240 2,930 2,930 mA IDD7A Notes mA Optional * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM DDR SDRAM IDD spec table M485L2829CU0 (st.128M x 72, 1GB Module) (VDD=2.7V, T = 10C) IDD6 Symbol A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit IDD0 1,260 1,260 mA IDD1 1,530 1,530 mA IDD2P 90 90 mA IDD2F 540 540 mA IDD2Q 450 450 mA IDD3P 540 540 mA IDD3N 810 810 mA IDD4R 1,530 1,530 mA IDD4W 1,580 1,580 mA IDD5 2,160 2,160 mA 90 90 mA Normal Low power IDD7A 54 54 mA 3,330 3,330 mA Notes Optional * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM AC Operating Conditions Parameter/Condition Max Symbol Min Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC) Input Differential Voltage, CK and CK inputs VID(AC) Input Crossing Point Voltage, CK and CK inputs VIX(AC) Unit Note V 3 VREF - 0.31 V 3 0.7 VDDQ+0.6 V 1 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz. Vtt=0.5*VDDQ RT=50 Output Z0=50 VREF =0.5*VDDQ CLOAD=30pF Output Load Circuit (SSTL_2) Input/Output Capacitance Parameter (TA= 25C, f=100MHz) M470L3324CU0 Symbol M470L6524CU0 Unit Min Max Min Max Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) CIN1 41 45 49 57 pF Input capacitance(CKE0, CKE1) CIN2 34 38 42 50 pF Input capacitance( CS0, CS1) CIN3 34 38 42 50 pF Input capacitance( CLK0, CLK1,CLK2) CIN4 25 30 25 30 pF Input capacitance(DM0~DM7) CIN5 6 7 6 7 pF Data & DQS input/output capacitance(DQ0~DQ63) Cout1 6 7 6 7 pF Input/Output Capacitance Parameter (TA= 25C, f=100MHz) Symbol M485L3324CU0 M485L6523CU0 M4852829CU0 Unit Min Max Min Max Min Max Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) CIN1 43 48 51 60 69 87 pF Input capacitance(CKE0, CKE1) CIN2 36 41 44 53 44 53 pF Input capacitance( CS0, CS1) CIN3 36 41 44 53 44 53 pF Input capacitance( CLK0, CLK1,CLK2) CIN4 25 30 25 30 28 34 pF Input capacitance(DM0~DM7, DM8(for ECC)) CIN5 6 7 6 7 10 12 pF Data & DQS input/output capacitance(DQ0~DQ63) Cout1 6 7 6 7 10 12 pF Data input/output capacitance (CB0~CB7) Cout2 6 7 6 7 10 12 pF Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM AC Timming Parameters & Specifications Symbol Parameter Row cycle time CC B3 A2 B0 (DDR400@CL=3.0) (DDR333@CL=2.5) (DDR266@CL=2.0) (DDR266@CL=2.5) Unit Min Max Min Max Min Max Min Max tRC 55 60 65 65 ns tRFC 70 72 75 75 ns Row active time tRAS 40 RAS to CAS delay tRCD 15 18 20 20 ns tRP 15 18 20 20 ns Row active to Row active delay tRRD 10 12 15 15 ns Write recovery time tWR 15 15 15 15 ns tWTR 2 1 1 1 tCK - - 7.5 12 7.5 12 10 12 ns tCK 6 12 6 12 7.5 12 7.5 12 ns 5 10 - - - - - - Clock high level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK Clock low level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK ns Refresh row cycle time Row precharge time Last data in to Read command CL=2.0 Clock cycle time CL=2.5 CL=3.0 DQS-out access time from CK/CK 70K 42 70K 45 120K 45 120K Note ns tDQSCK -0.55 +0.55 -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 Output data access time from CK/CK tAC -0.65 +0.65 -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns Data strobe edge to ouput data edge tDQSQ - 0.4 - 0.45 - 0.5 - 0.5 ns Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.72 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 0 0 ns DQS-in hold time tWPRE 0.25 0.25 0.25 0.25 tCK DQS falling edge to CK rising-setup time tDSS 0.2 0.2 0.2 0.2 tCK DQS falling edge from CK rising-hold time tDSH 0.2 0.2 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 0.35 0.35 0.35 tCK 22 13 Address and Control Input setup time(fast) tIS 0.6 0.75 0.9 0.9 ns 15, 17~19 Address and Control Input hold time(fast) tIH 0.6 0.75 0.9 0.9 ns 15, 17~19 Address and Control Input setup tIS 0.7 0.8 1.0 1.0 ns 16~19 Address and Control Input hold time(slow) tIH 0.7 0.8 1.0 1.0 ns 16~19 Data-out high impedence time from CK/CK tHZ - +0.65 - +0.7 - +0.75 - +0.75 ns 11 Data-out low impedence time from CK/CK tLZ -0.65 +0.65 -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns 11 tMRD 10 Mode register set cycle time 12 15 15 ns DQ & DM setup time to DQS tDS 0.4 0.45 0.5 0.5 ns j, k DQ & DM hold time to DQS tDH 0.4 0.45 0.5 0.5 ns j, k Control & Address input pulse width tIPW 2.2 2.2 2.2 2.2 ns 18 DQ & DM input pulse width tDIPW 1.75 1.75 1.75 1.75 ns 18 Exit self refresh to non-Read command tXSNR 75 75 75 75 ns Exit self refresh to read command tXSRD 200 200 200 200 tCK Refresh interval time tREFI 7.8 7.8 14 - - ns 21 - tCLmin or tCHmin - ns 20, 21 0.75 ns 21 0.6 tCK 12 tCK 23 tHP tCLmin or tCHmin - tWPST 0.4 0.6 Active to Read with Auto precharge command tRAP 15 18 20 20 Autoprecharge write recovery + Precharge time tDAL (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) 0.5 tCLmin or tCHmin us Clock half period tQHS - 7.8 tQH DQS write postamble time tCLmin or tCHmin - tHP -tQHS tHP -tQHS Output DQS valid window Data hold skew factor - tHP -tQHS 7.8 tHP -tQHS 0.55 0.4 0.6 0.75 0.4 0.6 0.4 Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM System Characteristics for DDR SDRAM The following specification parameters are required in systems using DDR333, DDR266 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design. Table 1 : Input Slew Rate for DQ, DQS, and DM AC CHARACTERISTICS DDR333 DDR266 PARAMETER SYMBOL MIN MAX MIN MAX Units Notes DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC) DCSLEW TBD TBD TBD TBD V/ns a, m Table 2 : Input Setup & Hold Time Derating for Slew Rate Input Slew Rate tIS tIH Units 0.5 V/ns 0 0 ps Notes i 0.4 V/ns +50 0 ps i 0.3 V/ns +100 0 ps i Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate Input Slew Rate tDS tDH Units Notes 0.5 V/ns 0 0 ps k 0.4 V/ns +75 +75 ps k 0.3 V/ns +150 +150 ps k Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate Delta Slew Rate tDS tDH Units +/- 0.0 V/ns 0 0 ps Notes j +/- 0.25 V/ns +50 +50 ps j +/- 0.5 V/ns +100 +100 ps j Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only) Slew Rate Characteristic Typical Range (V/ns) Minimum (V/ns) Maximum (V/ns) Notes Pullup Slew Rate 1.2 ~ 2.5 1.0 4.5 a,c,d,f,g,h Pulldown slew 1.2 ~ 2.5 1.0 4.5 b,c,d,f,g,h Table 6 : Output Slew Rate Characteristice (X16 Devices only) Slew Rate Characteristic Typical Range (V/ns) Minimum (V/ns) Maximum (V/ns) Notes Pullup Slew Rate 1.2 ~ 2.5 0.7 5.0 a,c,d,f,g,h Pulldown slew 1.2 ~ 2.5 0.7 5.0 b,c,d,f,g,h Table 7 : Output Slew Rate Matching Ratio Characteristics AC CHARACTERISTICS DDR333 DDR266 PARAMETER MIN MAX MIN MAX Notes Output Slew Rate Matching Ratio (Pullup to Pulldown) TBD TBD TBD TBD e,m Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM Component Notes 1. All voltages referenced to Vss. 2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). VDDQ 50 Output (Vout) 30pF Figure 1 : Timing Reference Load 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac). 5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc input LOW (HIGH) level. 6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE 0.2VDDQ is recognized as LOW. 7. Enables on.chip refresh and address counters. 8. IDD specifications are tested after the device is properly initialized. 9. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals other than CK/CK, is VREF. 10. The output timing reference voltage level is VTT. 11. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ). 12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys tem performance (bus turnaround) will degrade accordingly. 13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 15. For command/address input slew rate 1.0 V/ns 16. For command/address input slew rate 0.5 V/ns and < 1.0 V/ns Rev. 0.2 October. 2004 256MB, 512MB, 1GB Unbuffered SODIMM Preliminary DDR SDRAM Component Notes 17. For CK & CK slew rate 1.0 V/ns 18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 19. Slew Rate is measured between VOH(ac) and VOL(ac). 20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces. 21. tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and pchannel to n-channel variation of the output drivers. 22. tDQSQ Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 23. tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM System Notes : a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1. Test point Output 50 VSSQ Figure 1 : Pullup slew rate test load b. Pulldown slew rate is measured under the test conditions shown in Figure 2. VDDQ 50 Output Test point Figure 2 : Pulldown slew rate test load c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV) Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example : For typical slew rate, DQ0 is switching For minmum slew rate, all DQ bits are switching from either high to low, or low to high. The remaining DQ bits remain the same as for previous state. d. Evaluation conditions Typical : 25 C (T Ambient), VDDQ = 2.5V(for DDR266/333) and 2.6V(for DDR400), typical process Minimum : 70 C (T Ambient), VDDQ = 2.3V(for DDR266/333) and 2.5V(for DDR400), slow - slow process Maximum : 0 C (T Ambient), VDDQ = 2.7V(for DDR266/333) and 2.7V(for DDR400), fast - fast process e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. f. Verified under typical conditions for qualification purposes. g. TSOPII package divices only. h. Only intended for operation up to 266 Mbps per pin. i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)} For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this would result in the need for an increase in tDS and tDH of 100 ps. k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions. m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotony. Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM (V=Valid, X=Dont Care, H=Logic High, L=Logic Low) Command Truth Table COMMAND CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP A0 ~ A9, A11, A12 Note Register Extended MRS H X L L L L OP CODE 1, 2 Register Mode Register Set H X L L L L OP CODE 1, 2 L L L H X Auto Refresh Refresh Entry Self Refresh H H L L H H H H X X X X L L H H V H X L H L H V H X L H L L V H X L H H L H X L L H L Entry H L H X X X L V V V Exit L H X X X X Entry H L H X X X L H H H Exit L H H X X X L V V V L H Bank Active & Row Addr. H Read & Column Address Write & Column Address Exit Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable Burst Stop Precharge Bank Selection All Banks Active Power Down Precharge Power Down Mode DM H No operation (NOP) : Not defined H X X X X X L H H H 3 3 X 3 Row Address L Column Address H L Column Address H X V L X H 4 4 4 4, 6 7 X 5 X X X H 3 X 8 9 9 Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM Physical Dimensions : 32M x64 (M470L3324CU0) Units : Inches (Millimeters) 2.70 (67.60) 2.50 (63.60) 39 41 0.456 11.40 0.086 2.15 0.07 (1.8+/-0.1) 0.79 (20.00) 0.24 (6.0) 1 199 2- 0.07 (1.8+0.1/-0.0) 1.896 (47.40) 0.17 (4.20) 0.096 (2.40+/-0.1) 1.25 (31.75) Full R 2.0 0.16 0.039 (4.00 0.10) Z Y 0.098 2.45 200 0.157 Min (4.00 Min) 0.157 Min (4.00 Min) 0.150 Max (3.80 Max) 0.04 0.0039 (1.00 0.10) 0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.1) Detail Z (2.55 ) 40 42 0.102 Min 2 0.018 0.001 0.01 (0.2+/-0.15) 0.024 TYP (0.60 TYP) Detail Y Tolerances : .006(.15) unless otherwise specified The used device is 32Mx16 SDRAM, TSOPII SDRAM Part No. : K4H511638C-U*** Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM Physical Dimensions : 64M x64 (M470L6524CU0) Units : Inches (Millimeters) 2.70 (67.60) 2.50 (63.60) 39 41 0.456 11.40 0.086 2.15 0.07 (1.8+/-0.1) 0.79 (20.00) 0.24 (6.0) 1 199 2- 0.07 (1.8+0.1/-0.0) 1.896 (47.40) 0.17 (4.20) 0.096 (2.40+/-0.1) 1.25 (31.75) Full R 2.0 0.16 0.039 (4.00 0.10) Z Y 0.098 2.45 200 0.157 Min (4.00 Min) 0.157 Min (4.00 Min) 0.150 Max (3.80 Max) 0.04 0.0039 (1.00 0.10) 0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.1) Detail Z (2.55 ) 40 42 0.102 Min 2 0.018 0.001 0.01 (0.2+/-0.15) 0.024 TYP (0.60 TYP) Detail Y Tolerances : .006(.15) unless otherwise specified The used device is 32Mx16 SDRAM, TSOPII SDRAM Part No. : K4H511638C-U*** Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM Physical Dimensions : 32M x72 (M485L3324CU0) Units : Inches (Millimeters) 2.70 (67.60) 2.50 (63.60) 39 41 0.456 11.40 0.086 2.15 0.07 (1.8+/-0.1) 0.79 (20.00) 0.24 (6.0) 1 199 2- 0.07 (1.8+0.1/-0.0) 1.896 (47.40) 0.17 (4.20) 0.096 (2.40+/-0.1) 1.25 (31.75) Full R 2.0 0.16 0.039 (4.00 0.10) Z Y 0.098 2.45 0.157 Min (4.00 Min) 0.157 Min (4.00 Min) 0.150 Max (3.80 Max) 0.04 0.0039 (1.00 0.10) 0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.1) Detail Z (2.55 ) 200 40 42 0.102 Min 2 0.018 0.001 0.01 (0.2+/-0.15) 0.024 TYP (0.60 TYP) Detail Y Tolerances : .006(.15) unless otherwise specified The used device is 32Mx16 DDR SDRAM, TSOPII DDR SDRAM Part No. : K4H511638C-U*** Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM Physical Dimensions : 64M x72 (M485L6523CU0) Units : Inches (Millimeters) 2.70 (67.60) 2.50 (63.60) 1 199 39 41 0.456 11.40 0.086 2.15 0.07 (1.8) 0.79 (20.00) 0.24 (6.0) 0.16 0.039 (4.00 0.10) 2- 0.07 (1.8+0.1/-0.0) 1.896 (47.40) 0.17 (4.20) 0.096 (2.40) 1.40 (35.56) Full R 2.0 Z Y 0.098 2.45 0.04 0.0039 (1.00 0.10) 0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.1) Detail Z (2.55 ) 0.157 Min (4.00 Min) 0.157 Min (4.00 Min) 0.150 Max (3.80 Max) 0.102 Min 200 2 0.018 0.001 (0.45 0.05) 0.01 (0.2+/-0.15) 0.024 TYP (0.60 TYP) Detail Y Tolerances : .006(.15) unless otherwise specified The used device is 64Mx8 DDR SDRAM, TSOPII DDR SDRAM Part No. : K4H510838C-U*** Rev. 0.2 October. 2004 Preliminary DDR SDRAM 256MB, 512MB, 1GB Unbuffered SODIMM Physical Dimensions : st.128M x72 (M485L2829CU0) Units : Inches (Millimeters) 2.70 (67.60) 2.50 (63.60) 1 199 39 41 0.456 11.40 0.086 2.15 0.07 (1.8) 0.79 (20.00) 0.24 (6.0) 0.16 0.039 (4.00 0.10) 2- 0.07 (1.8+0.1/-0.0) 1.896 (47.40) 0.17 (4.20) 0.096 (2.40) 1.40 (35.56) Full R 2.0 Z Y 0.098 2.45 (4.00) 0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.10) 0.04 0.0039 (1.00 0.1) Detail Z (2.55) (0.157) 0.268 Max (6.81 Max) 0.102 Min 200 2 0.018 0.001 (0.45 0.05) 0.01 (0.2+/-0.15) 0.024 TYP (0.60 TYP) Detail Y Tolerances : .006(.15) unless otherwise specified The used device is stacked 128Mx8 DDR SDRAM, TSOPII DDR SDRAM Part No. : K4H1G0738C-U*** Rev. 0.2 October. 2004