Approximate Scale 1:1
Package LP, 16 pin TSSOP
with Exposed Thermal Pad
Description
Designed for PWM (pulse width modulated) control of DC
motors, the A3950 is capable of peak output currents to ±2.8 A
and operating voltages to 36 V.
PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a DC motor with externally
applied PWM control signals. Internal synchronous rectification
control circuitry is provided to lower power dissipation during
PWM operation.
Internal circuit protection includes motor lead short-to-
supply / short-to-ground, thermal shutdown with hysteresis,
undervoltage monitoring of VBB and VCP, and crossover-current
protection.
The A3950 is supplied in a thin profile (<1.2 mm overall height)
16 pin TSSOP package (LP), and a very thin (0.75 mm nominal
height) QFN package. Both packages provide an exposed pad
for enhanced thermal dissipation, and are lead (Pb) free with
100% matte tin leadframe plating.
A3950DS, Rev. 7
Features and Benefits
▪ LowRDS(on) outputs
▪ Overcurrentprotection
▪ Motorleadshort-to-supplyprotection
▪ Short-to-groundprotection
▪ Sleepfunction
▪ Synchronousrectification
▪ Diagnosticoutput
▪ Internalundervoltagelockout(UVLO)
▪ Crossover-currentprotection
DMOS Full-Bridge Motor Driver
Packages:
Typical Application Diagrams
A3950
PackageEU,16pinQFN
with Exposed Thermal Pad
Package LPPackageEU
V
BB
0.1 µF
50 V
0.22 µF
25 V
100 µF
50 V
0.1 µF
50 V
0.1 µF
50 V
A3950
EU Package
VDD
5 kΩ
NC
OUTA
SENSE
VBB
MODE
NFAULT
VREG
VCP
PHASE
GND
SLEEP
ENABLE
GND
CP2
CP1
OUTB
V
BB
0.1 µF
50 V
0.22 µF
25 V
0.1 µF
50 V
0.1 µF
50 V
100 µF
50 V
A3950
LP Package
VDD
5 kΩ
SLEEP
ENABLE
OUTA
SENSE
NFAULT
MODE
PHASE
GND
OUTB
VBB
VCP
GND
CP2
CP1
VREG
NC
DMOS Full-Bridge Motor Driver
A3950
2
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Selection Guide
Part Number Packing Package
A3950SLPTR-T 13 in. reel, 4000 pieces / reel 16 pin TSSOP with exposed thermal pad
A3950SEUTR-T 7 in. reel, 1500 pieces / reel 16 pin QFN with exposed thermal pad
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Units
Load Supply Voltage VBB 36 V
Output Current IOUT 2.8 A
Transient Output Current IOUT TW < 500 ns 6 A
Sense Voltage VSENSE ±500 mV
VBB to OUTx36 V
OUTx to SENSE 36 V
Logic Input Voltage VIN –0.3 to 7 V
Operating Ambient Temperature TARange S –20 to 85 ºC
Maximum Junction Temperature TJ(max) 150 ºC
Storage Temperature Tstg –40 to 125 ºC
DMOS Full-Bridge Motor Driver
A3950
3
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
UVLO
STB
STG
TSD Warning
VBB
OUTA
OUTB
SENSE
Low-Side
Gate Supply
Charge
Pump
Motor Lead
Protection
Pad
Control Logic
Bias
Supply
GND GND
SLEEP
NFAULT
PHASE
ENABLE
VDD
5 kΩ
5 kΩ
MODE
VREG
0.22 µF
25 V
0.1 µF
0.1 µF
0.1 µF 100 µF
OUTA
VBB
VCP
Load Supply
CP2
CP1
OUTB
SENSE
Functional Block Diagram
Terminal List Table
Name Number Description
EU LP
NFAULT 15 1 Fault output, open drain
MODE 16 2 Logic input
PHASE 1 3 Logic input for direction control
GND 2, 12 4,13 Ground
SLEEP 3 5 Logic input
ENABLE 4 6 Logic input
OUTA 6 7 DMOS full-bridge output A
SENSE 7 8 Power return
VBB 8 9 Load supply voltage
OUTB 9 10 DMOS full-bridge output B
CP1 10 11 Charge pump capacitor terminal
CP2 11 12 Charge pump capacitor terminal
VCP 13 14 Reservoir capacitor terminal
VREG 14 15 Regulator decoupling terminal
NC 5 16 No connection
Pad – – Exposed pad for thermal dissipation connect to GND pins
DMOS Full-Bridge Motor Driver
A3950
4
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
ELECTRICAL CHARACTERISTICS at TJ = 25°C, VBB = 8 to 36 V, unless noted otherwise
Characteristics Symbol Test Conditions Min. Typ. Max. Units
Motor Supply Current IBB
fPWM < 50 kHz – 6 8.5 mA
Charge pump on, outputs disabled – 3 4.5 mA
Sleep mode – – 10 µA
PHASE, ENABLE, MODE Input
Voltage
VIH 2.0 – – V
VIL – – 0.8 V
SLEEP Input Voltage VIH 2.7 – – V
VIL – – 0.8 V
PHASE, MODE Input Current1IIH VIN = 2.0 V – <1.0 20 µA
IIL VIN = 0.8 V –20 <–2.0 20 µA
ENABLE Input Current IIH VIN = 2.0 V – 40 100 µA
IIL VIN = 0.8 V – 16 40 µA
SLEEP Input Current IIH VIN = 2.7 V – 27 50 µA
IIL VIN = 0.8 V – <1 10 µA
NFAULT Output Voltage VOL Isink = 1.0 mA – – 0.4 V
Input Hysteresis, except SLEEP VIHys 100 150 250 mV
Output On Resistance RDS(on)
Source driver, IOUT = -2.8 A, TJ=25°C – 0.35 0.48 Ω
Source driver, IOUT = -2.8 A, TJ=125°C – 0.55 0.8 Ω
Sink driver, IOUT = 2.8 A, TJ=25°C – 0.3 0.43 Ω
Sink driver, IOUT = 2.8 A, TJ=125°C – 0.45 0.7 Ω
Body Diode Forward Voltage1Vf
Source diode, If = –2.8 A – – 1.4 V
Sink diode, If = 2.8 A – – 1.4 V
Propagation Delay Time tpd
PWM, change to source or sink ON – 600 – ns
PWM, change to source or sink OFF – 100 – ns
Crossover Delay tCOD – 500 – ns
Protection Circuitry
UVLO Threshold VUV VBB increasing – 6.5 – V
UVLO Hysteresis VUVHys – 250 – mV
Overcurrent Threshold2IOCP 3 – – A
Overcurrent Protection Period tOCP – 1.2 – ms
Thermal Warning Temperature TJW Temperature increasing – 160 – °C
Thermal Warning Hysteresis TJWHys Recovery = TJW – TJWHys – 15 – °C
Thermal Shutdown Temperature TJTSD Temperature increasing – 175 – °C
Thermal Shutdown Hysteresis TJTSDHys Recovery = TJTSD – TJTSDHys – 15 – °C
1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
2Overcurrent protection is tested at 25°C in a restricted range and guaranteed by characterization.
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RθJA
Preliminary: EU package, 4-layer PCB based on JEDEC standard 30 ºC/W
LP package, 4-layer PCB based on JEDEC standard 34 ºC/W
LP package, 2-layer PCB with 3.8 in.2 copper both sides, connected by
thermal vias 43 ºC/W
*Additional thermal data available on the Allegro Web site.
DMOS Full-Bridge Motor Driver
A3950
5
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Timing Diagram: PWM Control
V
BB
V
BB
1
2
34
67
8
9
ACharge pump and VREG power-on delay (≈200 µs)
OutBOutAOutA OutB
5
A12345 67 98
SLEEP
ENABLE
PHASE
MODE
VOUTA
VBB
0
VBB
0
0
VOUTB
IOUTX
DMOS Full-Bridge Motor Driver
A3950
6
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
BLANK
NFAULT
Motor lead
short condition
Normal dc
motor capacitance
Charge Pump
Counter
ENABLE,
Source
or Sink
High-Z
IOUTx
IPEAK
IOCP
VOUTA
VOUTB
t
BLANK
t
OCP
Timing Diagram: Overcurrent Control
DMOS Full-Bridge Motor Driver
A3950
7
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Device Operation. The A3950 is designed to operate one DC
motor.TheoutputdriversarealllowRDS(on) N-channel DMOS
drivers that feature internal synchronous rectification to reduce
power dissipation. PHASE and ENABLE inputs allow two-wire
control with an additional MODE pin for the brake function. A
low current Sleep mode is provided to minimize power consump-
tion when the driver is disabled. In addition, the driver also has
built-in protection from short-to-ground, short-to-battery, and
shorted load events.
Logic Inputs. If logic inputs are pulled up to VDD
, it is good
practice to use a high value pull-up resistor in order to limit cur-
rent to the logic inputs should an overvoltage event occur. Logic
inputs include: SLEEP, MODE, PHASE, and ENABLE. The
voltage on any logic input cannot exceed the specified maximum
of 7 V.
VREG. This supply voltage is used to run the sink-side DMOS
outputs.VREGisinternallymonitoredandinthecaseofafault
condition,theoutputsofthedevicearedisabled.TheVREGpin
shouldbedecoupledwitha0.22μFcapacitortoground.
Charge Pump. The charge pump is used to generate a sup-
ply above VBB to drive the source-side DMOS gates. A 0.1 µF
ceramic monolithic capacitor should be connected between CP1
and CP2 for pumping purposes. A 0.1 µF ceramic monolithic
capacitor should be connected between VCP and VBB to act as a
reservoir to run the high-side DMOS devices. The VCP voltage
level is internally monitored and, in the case of a fault condition,
the outputs of the device are disabled.
Shutdown. In the event of a fault due to excessive junction
temperature,orlowvoltageonVCPorVREG,theoutputsof
the device are disabled until the fault condition is removed. At
power-ontheUVLOcircuitdisablesthedrivers.
Sleep Mode. Control input SLEEP is used to minimize power
consumption when the A3950 is not in use. This disables much
of the internal circuitry, including the regulator and charge pump.
A logic low setting puts the device into Sleep mode, and a logic
high setting allows normal operation. After coming out of Sleep
mode, provide a 1 ms interval before applying PWM signals, to
allow the charge pump to stabilize.
MODE. Control input MODE is used to toggle between fast
decay mode and slow decay mode. A logic high puts the device in
slow decay mode. Synchronous rectification is always enabled.
Braking. The braking function is implemented by driving the
device in slow decay mode via the MODE setting and applying
an enable chop command. Because it is possible to drive current
in both directions through the DMOS switches, this configuration
effectively shorts out the motor generated BEMF as long as the
ENABLE chop mode is asserted. The maximum current can be
approximated by VBEMF/RL. Care should be taken to insure that
the maximum ratings of the device are not exceeded in worse
case braking situations: high speed and high-inertia loads.
Diagnostic Output.TheNFAULTpinsignalsaproblemwith
the chip via an open drain output. A motor fault, undervoltage
condition, or TJ > 160°C will drive the pin active low. This output
is not valid when SLEEP puts the device into minimum power
dissipation mode.
TSD. Two die temperature monitors are integrated on the chip.
As die temperature increases towards the maximum, a thermal
warning signal will be triggered at 160°C. This fault drives the
Functional Description
Control Logic Table1
Pin Function
PHASE ENABLE MODE SLEEP OUTA OUTB
1 1 X 1 H L Forward
0 1 X 1 L H Reverse
X 0 1 1 L L Brake (slow decay)
1 0 0 1 L H Fast Decay Synchronous Rectification2
0 0 0 1 H L Fast Decay Synchronous Rectification2
X X X 0 Z Z Sleep Mode
1X indicates “don’t care,” Z indicates high impedance.
2To prevent reversal of current during fast decay synchronous rectification, outputs go to the high impedance state as the current approaches 0 A.
DMOS Full-Bridge Motor Driver
A3950
8
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
NFAULTlow,butdoesnotdisabletheoperationofthechip.If
the die temperature increases further, to approximately 175°C, the
full-bridge outputs will be disabled until the internal temperature
falls below a hysteresis of 15°C.
Overcurrent Protection.Referringtothefiguresbelow,the
voltage on the output pins relative to supply are monitored to
ensure that the motor lead is not shorted to supply or ground.
If a short is detected, the full-bridge outputs are turned off, flag
NFAULTisdrivenlow,anda1.2msfaulttimerisstarted.
After this 1.2 ms period, tOCP , the device will then be allowed
to follow the input commands and another turn-on is attempted.
If there is still a fault condition, the cycle repeats. If, after tOCP
expires, it is determined that the short condition is not present, the
NFAULTpinisreleasedandnormaloperationresumes.
Shorted load condition, output current waveform is shown along with the NFAULT output.
Shorted load condition illustrating repetitive cycles with a 1.2 ms delay.
ISHORT
NFAULT
2 µs / div.
2 A / div.
Fault asserted
ISHORT
NFAULT
200 µs / div.
2 A / div.
TOCP = 1.2 ms
Fault asserted
DMOS Full-Bridge Motor Driver
A3950
9
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Power Dissipation. First order approximation of power
dissipation in the A3950 can be calculated by first examining
the power dissipation in the full-bridge during each of the
operation modes. The A3950 features synchronous rectifica-
tion, a feature that effectively shorts out the body diode by
turningonthelowRDS(on) DMOS driver during the decay
cycle. This significantly reduces power dissipation in the
full-bridge. In order to prevent shoot-through, where both
source and sink driver are on at the same time, the A3950
implements a 500 ns typical crossover delay time. For this
period, the body diode in the decay current path conducts
the current until the DMOS driver turns on. This does affect
power dissipation and should be considered in high current,
high ambient temperature applications. In addition, motor
parameters and switching losses can add power dissipation
that could affect critical applications.
Drive Current. This current path is through source DMOS
driver, motor winding, and sink DMOS driver. Power dissi-
pation is I2RlosesinonesourceandonesinkDMOSdriver,
as shown in the following equation:
)(
2
DS(on)Source DS(on)SinkD RRI
P
+=
(1)
Fast Decay with Synchronous Rectification. This
decay mode is equivalent to a phase change where the oppo-
site drivers are switched on. When in fast decay, the motor
current is not allowed to go negative (direction change).
Instead, as the current approaches zero, the drivers turn off.
The power calculation is the same as the drive current calcu-
lation, equation 1:
Slow Decay SR (Brake Mode). In this decay mode, both
sink drivers turn on, allowing the current to circulate through
the sink drivers and the load. Power dissipation is I2Rloses
in the two sink DMOS drivers:
)(
2
DS(on)SinkD RI
P
=
2×
(2)
Applications Information
VBB
Drive current
Fast decay with synchronous rectification (reverse)
Slow decay with synchronous rectification (brake)
2
3
1
2
3
1
Figure 1. Current Decay Patterns
DMOS Full-Bridge Motor Driver
A3950
10
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
SENSE Pin. A low value resistor can be placed between the
SENSE pin and ground for current sensing purposes. To mini-
mizeground-traceIRdropsinsensingtheoutputcurrentlevel,
the current sensing resistor should have an independent ground
return to the star ground point. This trace should be as short as
possible.Forlowvaluesenseresistors,theIRdropsinthePCB
can be significant, and should be taken into account.
When selecting a value for the sense resistor be sure not to
exceed the maximum voltage on the SENSE pin of ±500 mV.
Ground. A star ground should be located as close to the A3950
as possible. The copper ground plane directly under the exposed
thermal pad makes a good location for the star ground point. The
exposed pad can be connected to ground for this purpose.
Layout. The printed circuit board should use a heavy ground-
plane. For optimum electrical and thermal performance, the
A3950 must be soldered directly onto the board. On the under-
side of the A3950 package is an exposed pad, which provides a
path for enhanced thermal dissipation. The thermal pad should be
soldered directly to an exposed surface on the PCB. Thermal vias
are used to transfer heat to other layers of the PCB.
The load supply pin, VBB, should be decoupled with an elec-
trolytic capacitor (typically 100 µF) in parallel with a ceramic
capacitor placed as close as possible to the device. The ceramic
capacitorsbetweenVCPandVBB,connectedtoVREG,and
between CP1 and CP2, should be as close to the pins of the
device as possible, in order to minimize lead inductance.
U1
VBB
OUTB
GND
GND
CVBB1
CVBB2
C2
C3
C1
OUTA
EU package shown
V
BB
C1 C2
C3
CVBB2
PAD
CVBB1
A3950
EU Package
NC
OUTA
SENSE
VBB
MODE
NFAULT
VREG
VCP
PHASE
GND
SLEEP
ENABLE
GND
CP2
CP1
OUTB
DMOS Full-Bridge Motor Driver
A3950
11
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
EU Package, 16 Pin QFN with Exposed Thermal Pad
1.15
C
SEATING
PLANE
C0.08
17X
16
16
2
1
1
2
16
2
1
A
ATerminal #1 mark area
Coplanarity includes exposed thermal pad and terminals
BExposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
For Reference Only
(reference JEDEC MO-220WGGC)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
C
D
D
C
Reference land pattern layout (reference IPC7351
QFN65P400X400X80-17BM)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
3.80
0.35
0.65
3.80
0.65
0.75 ±0.05
2.15
2.15
0.30 ±0.05
0.40 ±0.10
4.00 ±0.15
4.00 ±0.15 2.15
2.15
B
PCB Layout Reference View
DMOS Full-Bridge Motor Driver
A3950
12
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
LP Package, 16 Pin TSSOP with Exposed Thermal Pad
C
SEATING
PLANE
C0.10
16X
6.10
0.65
0.45
1.70
3.00
5.00 ±0.10
3.00
3.00
3.00
1.20 MAX
0.15 MAX
0.65
0.25
(1.00)
4.40 ±0.10 6.40 ±0.20 0.60 ±0.15
4° ±4
0.25 +0.05
–0.06
0.15 +0.05
–0.06
21
16
GAUGE PLANE
SEATING PLANE
B
A
16
21
ATerminal #1 mark area
B
For Reference Only
(reference JEDEC MO-153 ABT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Reference land pattern layout (reference IPC7351 SOP65P640X110-17M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
PCB Layout Reference View
Exposed thermal pad (bottom surface)
C
C
DMOS Full-Bridge Motor Driver
A3950
13
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Copyright ©2005-2014, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
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Revision History
Revision Revision Date Description of Revision
7 June 11, 2014 Added Transient Output Current to Abs. Max. Ratings