Jan. 2009
High Reliability Series Serial EEPROM Series
I2C BUS
Serial EEPROMs
BR24A01A-WM, BR24A02-WM, BR24A04-WM, BR24A08-WM,
BR24A16-WM, BR24A32-WM, BR24A64-WM
●Description
BR24A□□-WM series is a serial EEPROM of I2C BUS interface method.
●Features
・ Completely conforming to the world standard I2C BUS. All controls available by 2 ports of serial clock(SCL) and serial
data(SDA)
・ Other devices than EEPROM can be connected to the same port, saving microcontroller port
・ 2.5V~5.5V single power source action most suitable for battery use
・ Page write mode useful for initial value write at factory shipment
・ Highly reliable connection by Au pad and Au wire
・ Auto erase and auto end function at data rewrite
・ Low current consumption
At write operation (5V) : 1.2mA (Typ.)
*1
At read operation (5V) : 0.2mA (Typ.)
At standby operation (5V) : 0.1μA (Typ.)
・ Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
・ SOP8/SOP-J8 compact package *2
・ Data rewrite up to 1,000,000 times
・ Data kept for 40 years
・ Noise filter built in SCL / SDA terminal
・ Shipment data all address FFh
●BR24A series
Capacity Bit format Type Power source
Voltage SOP8 SOP-J8
1Kbit 128×8 BR24A01A-WM 2.5～5.5V ● ●
2Kbit 256×8 BR24A02-WM 2.5～5.5V ● ●
4Kbit 512×8 BR24A04-WM 2.5～5.5V ● ●
8Kbit 1K×8 BR24A08-WM 2.5～5.5V ● ●
16Kbit 2K×8 BR24A16-WM 2.5～5.5V ● ●
32Kbit 4K×8 BR24A32-WM 2.5～5.5V ● ●
64Kbit 8K×8 BR24A64-WM 2.5～5.5V ● ●
Page write
Number
of
Pages
8Byte 16Byte 32Byte
Product
number
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
*1 BR24A32-WM、BR24A64-WM : 1.5mA
*2 Refer to following list
2/16
●FAST-MODE and STANDARD-MODE
FAST-MODE and STANDARD-MODE are of same actions, and mode is changed. They are distinguished by action speeds.
100kHz action is called STANDARD-MODE, and 400kHz action is called FAST-MODE. This action frequency is the maximum
action frequency, so 100kHz clock may be used in FAST-MODE. At Vcc=2.5V～5.5V , 400kHz, namely, action is made in
FASTMODE. (Action is made also in STANDARD-MODE.)
●Memory cell characteristics (Ta=25℃, Vcc=2.5～5.5V)
Parameter Limits Unit
Min. Typ. Max.
Number of data rewrite times *1 1,000,000 － － Times
Data hold years *1 40
－ － Years
○Shipment data all address FFh
*1
Not 100% TESTED
●Recommended operating conditions
Parameter Symbol Limits Unit
Power source voltage Vcc 2.5～5.5
V
Input voltage VIN 0～Vcc
●Electrical characteristics (Unless otherwise specified, Ta=－40～+105℃, VCC=2.5～5.5V)
Parameter Symbol Limits Unit Conditions
Min. Typ. Max.
“HIGH” input voltage VIH 0.7Vcc － － V
“LOW” input voltage VIL － － 0.3 Vcc V
“LOW” output voltage 1 VOL － － 0.4 V IOL=3.0mA (SDA)
Input leak current ILI －1 － 1 μA VIN=0V～Vcc
Output leak current ILO －1 － 1 μA VOUT=0V～Vcc, (SDA)
Current consumption at
action
ICC1 － － 2.0 *1 mA Vcc=5.5V,fSCL=400kHz, tWR=5ms,
Byte write, Page write
3.0 *2
ICC2 － － 0.5 mA
Vcc=5.5V,fSCL=400kHz
Random read, current read, sequential read
Standby current ISB － － 2.0 μA Vcc=5.5V, SDA・SCL=Vcc
A0, A1, A2=GND, WP=GND
◎Radiation resistance design is not made. *1 BR24A01A/02/04/08/16-WM, *2 BR24A32/64-WM
●Action timing characteristics (Unless otherwise specified, Ta=－40～+105℃, VCC=2.5～5.5V)
Parameter Symbol
FAST-MODE
2.5V≦Vcc≦5.5V
STANDARD-MODE
2.5V≦Vcc≦5.5V Unit
Min. Typ. Max. Min. Typ. Max.
SCL frequency fSCL － － 400 － － 100 kHz
Data clock “HIGH“ time tHIGH 0.6 － － 4.0 － － μs
Data clock “LOW“ time tLOW 1.2 － － 4.7 － － μs
SDA, SCL rise time *1 tR － － 0.3 － － 1.0 μs
SDA, SCL fall time *1 tF － － 0.3 － － 0.3 μs
Start condition hold time tHD:STA 0.6 － － 4.0 － － μs
Start condition setup time tSU:STA 0.6 － － 4.7 － － μs
Input data hold time tHD:DAT 0 － － 0 － － ns
Input data setup time tSU:DAT 100 － － 250 － － ns
Output data delay time tPD 0.1 － 0.9 0.2 － 3.5 μs
Output data hold time tDH 0.1 － － 0.2 － － μs
Stop condition setup time tSU:STO 0.6 － － 4.7 － － μs
Bus release time before transfer start tBUF 1.2 － － 4.7 － － μs
Internal write cycle time tWR － － 5 － － 5 ms
Noise removal valid period (SDA, SCL terminal) tI － － 0.1 － － 0.1 μs
WP hold time tHD:WP 0 － － 0 － － ns
WP setup time tSU:WP 0.1 － － 0.1 － － μs
WP valid time tHIGH:WP 1.0 － － 1.0 － － μs
*1 Not 100% tested
●Absolute maximum ratings (Ta=25℃)
Parameter symbol Limits Unit
Impressed voltage VCC －0.3～+6.5 V
Permissible
dissipation Pd 450 (SOP8) *1 mW
450 (SOP-J8) *2
Storage
temperature range Tst g －65～+125 ℃
Action
temperature range Topr －40～+105 ℃
Terminal voltage － －0.3～Vcc+1.0 V
When using at Ta=25℃ or higher,
4.5mW(*1,*2) to be reduced per 1℃
3/16
●Sync data input / output timing
●Block diagram
●Pin assignment and description
SDA
tSU:STA tSU:STOtHD:STA
START BIT STOP BIT
SCL
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
Fig.1-(a) Sync data input / output timing
Fig.1-(b) Start-stop bit timing
Fig.1-(c) Write cycle timing
Fig.1-(d) WP timing at write execution
Fig.1-(e) WP timing at write cancel
○At write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP=“LOW”.
○By setting WP “HIGH” in the area, write can be cancelled.
When it is set WP=“HIGH” during tWR, write is forcibly ended, and data o
f
address under access is not guaranteed, therefore write it once again.
tHIGH:WP
WP
SDA D1 D0 ACK ACK
DATA(1) DATA(n)
tWR
SCL
SDA
Write data
(n-th address) Stop condition Start condition
SCL
ｔWR
ACK
D0
Fig.2 Block diagram
Terminal
name
Input /
output
Function
BR24A01A-WM BR24A02-WM BR24A04-WM BR24A08-WM BR24A16-WM BR24A32-WM BR24A64-WM
A0 Input Slave address setting Not connected Slave address setting
A1 Input Slave address setting Not connected Slave address setting
A2 Input Slave address setting Not used Slave address setting
GND - Reference voltage of all input / output, 0V
SDA Input /
output Slave and word address, Serial data input serial data output
SCL Input Serial clock input
WP Input Write protect terminal
Vcc - Connect the power source.
1Kbit~64Kbit EEPROM arra
y
Control circuit
High voltage
generating circuit Power source
voltage detection
7bit
8bit
9bit
10bit
11bit
12bit
13bit
Address
decoder
Slave - word
address register
Data
register
8bit
7bit
8bit
9bit
10bit
11bit
12bit
13bit
START STOP
ACK
*1
*1
1
2
3
4
8
7
6
5 SDA
SCL
WP
Vcc
A1
A0
A2
GND
*2
*2
*2
＊1 7bit : BR24A01A-WM
8bit : BR24A02-WM
9bit : BR24A04-WM
10bit : BR24A08-WM
11bit : BR24A16-WM
12bit : BR24A32-WM
13bit : BR24A64-WM
＊2 A0=N.C. : BR24A04-WM
A0, A1=N.C. : BR24A08-WM
A0, A1= N.C. A2=Don’t Use : BR24A16-WM
1
2
3
4
8
6
5
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
A0
7
A1
A2
GND
Vcc
WP
SCL
SDA
SD
A
(入力)
SDA
(出力)
tHD:STA tHD:DAT
tSU:DAT
tBUF tPD tDH
tLOW
tHIGHtR tF
SCL
(input)
(output)
SCL
SDA
WP
ｔHD：WP
ストップコンディション
ｔWR
D1 D0
A
CK
A
CK
DATA(1) DATA(n)
tSU：WP
Stop condition
4/16
●Characteristic data (The following values are Typ. ones.)
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
Vcc[V]
ICC2[mA]
fSCL=400kHz
DATA=AAh
Ta=25℃
Ta=-40℃
Ta=105℃
SPEC
0
0.2
0.4
0.6
0.8
1
1.2
0123456
Vcc[V]
ILI[μA]
Ta=105℃
Ta=25℃
Ta=-40℃
SPEC
0
1
2
3
4
5
6
0123456
Vcc[V]
VIH1,2[V]
Ta=105℃
Ta=-40℃
Ta=25℃
SPEC
0
1
2
3
4
5
6
0123456
Vcc[V]
VIL1,2[V]
Ta=105℃
Ta=-40℃
Ta=25℃
SPEC
Fig.3 H input voltage VIH1,2 (SCL,SDA,WP) Fig.4 L input voltageVIL1,2 (SCL,SDA,WP)
0
0.2
0.4
0.6
0.8
1
0123456
IOL1[mA]
VOL1[V]
Ta=25℃
Ta=-40℃
Ta=105℃
SPEC
0
0.2
0.4
0.6
0.8
1
1.2
0123456
Vcc[V]
ILO[μA]
SPEC
Ta=105℃
Ta=25℃
Ta=-40℃
Fig.5 L output voltage VOL1-IOL1 (VCC=2.5V)
Fig.6 Input leak current ILI (SCL,WP) Fig.7 Output leak current ILO(SDA)
0
0.5
1
1.5
2
2.5
0123456
Vcc[V]
ICC1[mA]
fSCL=400kHz
DATA=AAh
Ta=25℃
Ta=105℃
Ta=-40℃
SPEC
[BR24A01/02/04/08/16 series]
0
0.5
1
1.5
2
2.5
3
3.5
0123456
Vcc[V]
ICC1[mA]
SPEC
Ta=25℃
Ta=105℃
Ta=-40℃
fSCL=100kHz
DATA=AAh
[BR24A32/64 series]
0
0.5
1
1.5
2
2.5
0123456
Vcc[V]
ISB[μA]
Ta=-40℃
Ta=105℃
Ta=25℃
SPEC
1
10
100
1000
10000
0123456
Vcc[V]
fSCL[kHz]
Ta=105℃
Ta=25℃
Ta=-40℃
SPEC2
SPEC1
0
1
2
3
4
5
0123456
Vcc[V]
tHIGH [μs]
SPEC2
Ta=-40℃
Ta=25℃
Ta=105℃ SPEC1
0
1
2
3
4
5
0123456
Vcc[V]
tLOW[μs]
SPEC2
SPEC1
Ta=105℃
Ta=25℃
Ta=-40℃
0
1
2
3
4
5
0123456
Vcc[V]
tHD:STA[μs]
SPEC2
SPEC1
Ta=105℃
Ta=25℃
Ta=-40℃
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
Vcc[V]
ICC2[mA]
SPEC
fSCL=100kHz
DATA=AAh
Ta=-40℃
Ta=105℃
Ta=25℃
Fig.9 Current consumption at WRITE action ICC1
(fSCL=400kHz)
Fig.10 Current consumption at READ action ICC2
(fSCL=400kHz)
Fig.12 Current consumption at WRITE action ICC1
(fSCL=100kHz)
Fig.13 Current consumption at READ action ICC2
(fSCL=100kHz)
Fig.14 Standby current ISB
Fig.15 SCL frequency fSCL Fig.16 Data clock "H" time tHIGH Fig.17 Data clock "L" time tLOW
Fig.18 Start condition hold time tHD:STA
0
1
2
3
4
5
6
0123456
Vcc[V]
tSU:STA[μs]
SPEC2
SPEC1
Ta=-40℃
Ta=25℃
Ta=105℃
-200
-150
-100
-50
0
50
0123456
Vcc[V]
tHD:DAT(HIGH)[ns]
SPEC1,2
Ta=-40℃
Ta=25℃
Ta=105℃
Fig.19 Start condition setup time tSU:STA Fig.20 Input data hold time tHD:DAT(HIGH)
0
0.5
1
1.5
2
2.5
3
3.5
0123456
Vcc[V]
ICC1[mA]
fSCL=400kHz
DATA=AAh
Ta=25℃
Ta=105℃
Ta=-40℃
SPEC
[BR24A32/64 series]
Fig.8 Current consumption at WRITE action ICC1
(fscl=400kHz)
0
0.5
1
1.5
2
2.5
0123456
Vcc[V]
ICC1[mA]
SPEC
Ta=25℃
Ta=105℃
Ta=-40℃
fSCL=100kHz
DATA=AAh
[BR24A01/02/04/08/16 series]
Fig.11 Current consumption at WRITE action ICC1
(fSCL=100kHz)
5/16
●Characteristic data (The following values are Typ. ones.)
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
Vcc[V]
tI(SDA H)[μs]
SPEC1,2
Ta=25℃ Ta=-40℃
Ta=105℃
0
1
2
3
4
0123456
Vcc[V]
tPD1[μs]
SPEC1
SPEC2
SPEC2
Ta=-40℃
Ta=25℃
Ta=105℃
SPEC1
0
1
2
3
4
0123456
Vcc[V]
tPD0[μs]
Ta=105℃
Ta=25℃
Ta=-40℃
SPEC2
SPEC1
SPEC2
SPEC1
-200
-150
-100
-50
0
50
0123456
Vcc[V]
tHD:DAT(LOW)[ns]
SPEC1,2
Ta=-40℃
Ta=105℃
Ta=25℃
-200
-100
0
100
200
300
0123456
Vcc[V]
tSU:DAT(LOW)[ns]
Ta=-40℃
Ta=105℃
Ta=25℃
SPEC1
SPEC2
-200
-100
0
100
200
300
0123456
Vcc[V]
tSU:DAT(HIGH)[ns]
Ta=105℃
Ta=25℃
Ta=-40℃
SPEC1
SPEC2
Fig.21 Input data hold time tHD:DAT(LOW) Fig.22 Input data setup time tSU:DAT(HIGH) Fig.23 Input data setup time tSU:DAT(LOW)
Fig.24 Output data delay time tPD0 Fig.25 Output data delay time tPD1
0
1
2
3
4
5
0123456
Vcc[V]
tBUF[μs]
SPEC2
SPEC1
Ta=-40℃
Ta=25℃
Ta=105℃
0
1
2
3
4
5
6
0123456
Vcc[V]
tWR[ms]
SPEC1,2
Ta=25℃
Ta=-40℃
Ta=105℃
Fig.26 Bus release time before transfer start tBUF
Fig.27 Internal write cycle time tWR
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
Vcc[V]
tI(SCL H)[μs]
SPEC1,2
Ta=-40℃
Ta=25℃
Ta=105℃
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
Vcc[V]
tI(SCL L)[μs]
Ta=-40℃
Ta=25℃
Ta=105℃
SPEC1
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
Vcc[V]
tI(SDA L)[μs]
SPEC1
Ta=-40℃
Ta=105℃
Ta=25℃
-0.6
-0.4
-0.2
0
0.2
0123456
Vcc[V]
tSU:WP[μs]
SPEC1,2
Ta=105℃
Ta=-40℃
Ta=25℃
0
0.2
0.4
0.6
0.8
1
1.2
0123456
Vcc[V]
tHIGH:WP[μs]
SPEC1,2
Ta=-40℃
Ta=25℃
Ta=105℃
Fig.28 Noise removal valid time tI(SCL H) Fig.29 Noise removal valid time tI(SCL L)
Fig.30 Noise removal valid time tI(SDA H) Fig.31 Noise removal valid time tI(SDA L) Fig.32 WP setup time tSU:WP
Fig.33 WP valid time tHIGH:WP
6/16
●I2C BUS communication
○I2C BUS data communication
I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and
acknowledge is always required after each byte. I2C BUS carries out data transmission with plural devices connected by 2
communication lines of serial data (SDA) and serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by address peculiar to devices. EEPROM becomes “slave”. And the device that outputs data to bus during data
communication is called “transmitter”, and the device that receives data is called “receiver”.
○Start condition (Start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is
'HIGH' is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this confdition is
satisfied, any command is executed.
○Stop condition (stop bit recongnition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master
and slave, the device (μ-COM at slave address input of write command, read command, and this IC at data output of read
command) at the transmitter (sending) side releases the bus after output of 8bit data.
・The device (this IC at slave address input of write command, read command, and μ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.
・When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (μ-COM) side, this IC
continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes
stop cindition (stop bit), and ends read action. And this IC gets in status.
○Device addressing
・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'.
・Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same bus
according to the number of device addresses.
・The most insignificant bit (R/W --- READ / WRITE) of slave address is used for designating write or read action, and is as
shown below.
Setting R / W to 0 ------- write (setting 0 to word address setting of random read)
Setting R / W to 1 ------- read
Type Slave address
Maximum number of
connected buses
BR24A01A-WM 1 0 1 0 A2 A1 A0 R/W 8
BR24A02-WM 1 0 1 0 A2 A1 A0 R/W 8
BR24A04-WM 1 0 1 0 A2 A1 PS R/W 4
BR24A08-WM 1 0 1 0 A2 P1 P0 R/W 2
BR24A16-WM 1 0 1 0 P2 P1 P0 R/W 1
BR24A32-WM 1 0 1 0 A2 A1 A0 R/W 8
BR24A64-WM 1 0 1 0 A2 A1 A0 R/W 8
PS, P0～P2 are page select bits.
Note) Up to 4 units BR24A04-WM, up to 2 units of BR24A08-WM, and one unit of BR24A16-WM can be connected.
Device address is set by 'H' and 'L' of each pin of A0, A1, and A2.
Fig.34 Data transfer timing
1
2
3
4
8
6
5
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
A0
7
A1
A2
GND
Vcc
WP
SCL
SDA
89 89 89
S P
condition condition
ACK STOPACKDATA DATAADDRES
S
START R/W ACK
1-7
SDA
SCL 1-7 1-7
7/16
●Write Command
○Write cycle
・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous data of 2 bytes or
more, simultaneous write is possible by page write cycle. The maximum number of write bytes is specified per device of each capacity. Up to
32 arbitrary bytes can be written. (In the case of BR24A32 / A64-WM)
・Data is written to the address designated by word address (n-th address)
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).
・By page write cycle, the following can be written in bulk : Up to 8 bytes ( BR24A01A-WM, BR24A02-WM）
: Up to 16bytes (BR24A04-WM, BR24A08-WM、BR24A16-WM）
: Up to 32bytes (BR24A32-WM, BR24A64-WM）
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment" of "Notes on page write cycle" in P8/16.)
・As for page write cycle of BR24A01A-WM and BR24A02-WM, after the significant 5 bits (4 significant bits in BR24A01A-WM) of word
address are designated arbitrarily, and as for page write command of BR24A04-WM, BR24A08-WM, and BR24A16-WM, after page select
bit (PS) of slave address is designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 4 bits
(insignificant 3 bit in BR24A01A-WM, and BR24A02-WM) is incremented internally, and data up to 16 bytes (up to 8 bytes in
BR24A01A-WM and BR24A02-WM) can be written.
・As for page write cycle of BR24A32-WM and BR24A64-WM, after the significant 7 bits (in the case of BR24A32-WM) of word address, or
the significant 8 bits (in the case of BR24A64-WM) of word address are designated arbitrarily, by continuing data input of 2 byte or more,
the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written.
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
WORD
ADDRESS(n) DAT
A
(n)
SDA
LINE
A
C
K
A
C
K
DATA(n+15)
A
C
K
SLAVE
ADDRESS
10 0
1A0 A1 A2 WA
7 D0D7 D0
WA
0
Note) *1
*2
A1 A2 WA
7 D7
1 1 0 0
W
R
I
T
E
S
T
A
R
T
R
/
W
S
T
O
P
WORD
ADDRESS DATA
SLAVE
ADDRESS
A0 WA
0 D0
A
C
K
SDA
LINE
A
C
K
A
C
K
Note) *1
Fig.35 Byte write cycle (BR24A01A/02/04/08/16-WM)
*1 As for WA7, BR24A01A-WM becomes Don’t care.
A1 A2 1 1 0 0
W
R
I
T
E
S
T
A
R
T
R
/
W
S
T
O
P
1st WORD
ADDRESS DATA
SLAVE
ADDRESS
A0 D0
A
C
K
SDA
LINE
A
C
K
A
C
K
Note)
WA
12
WA
11
* WA
0
A
C
K
2nd WORD
ADDRESS
D7
*1
* *
*1 As for WA12, BR24A32-WM becomes Don’t care.
Fig.36 Byte write cycle (BR24A32/64-WM)
*1 As for WA7, BR24A01A-WM becomes Don’t care.
*2 As for BR24A01A/02-WM becomes (n+7).
Fig.37 Page write cycle (BR24A01A/02/04/08/16-WM)
Fig.38 Page write cycle (BR24A32/64-WM)
*1 As for WA12, BR24A32-WM becomes Don’t care.
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
1st W ORD
ADDRESS(n)
SDA
LINE
A
C
K
A
C
K
DATA(n+31)
A
C
K
SLAVE
ADDRESS
10 0
1A0 A1 A2 D0
Note) *1
DATA(n)
D0D7
A
C
K
2nd WORD
ADDRESS(n)
WA
0
WA
12
WA
11
* * *
Note)
10 0
1A0
A1
A2
*1 *2 *3
Fig.39 Difference of slave address of each type
*1 In BR24A16-WM, A2 becomes P2.
*2 In BR24A08-WM, BR24A16-WM, A1 becomes P1.
*3 In BR24A04-WM, A0 becomes PS, and in BR24A08-WM and
BR24A16-WM, A0 becomes P0.
8/16
○Notes on write cycle continuous input
○Notes on page write cycle ○Internal address increment
Page write mode (in the case of BR24A02-WM)
List of numbers of page write
In the case BR24A02-WM, 1 page=8bytes, but the page
write cycle write time is 5ms at maximum for 8byte bulk write.
It does not stand 5ms at maximum × 8byte=40ms(Max.).
○Write protect (WP) terminal
・Write protect (WP) function
When WP terminal is set Vcc (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data rewrite
of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not use it
open.
At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', mistake write can be prevented.
During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated.
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
WORD
ADDRESS（ｎ） DATA(n)
SDA
LINE
A
C
K
DATA(n+7)
A
C
K
SLAVE
ADDRESS
10 0 1A0 A1 A2 WA
7
D0D7 D0
*1
A
C
K
Note)
WA
0 1 100
Next command
tWR(maximum : 5ms)
Command is not accepted for this period.
At STOP (stop bit),
write starts.
*2
*3
S
T
A
R
T
*1 BR24A01A-WM becomes Don’t care.
*2 BR24A04-WM, BR24A08-W, and BR24A16-WM become (n+15).
*3 BR24A32-WM and BR24A64-WM become (n+31).
10 0
1A0
A1
A2
*1 *2 *3
Fig.42 Difference of each type of slave address
Fig.40 Page write cycle
*1 In BR24A16-WM, A2 becomes P2.
*2 In BR24A08-WM, BR24A16-WM, A1 becomes P1.
*3 In BR24A04-WM, A0 becomes PS, and in BR24A08-WM
and in BR24A16-WM, A0 becomes P0.
Note)
WA7 ----- WA4 WA3 WA2 WA1 WA0
0 ----- 0 0 0 0 0
0 ----- 0 0 0 0 1
0 ----- 0 0 0 1 0
0 ----- 0 0 1 1 0
0 ----- 0 0 1 1 1
0 ----- 0 0 0 0 0
---------
---------
---------
06h
Significant bit is fixed.
No digit up
Increment
For example, when it is started from address 06h,
therefore, increment is made as below,
06h → 07h → 00h → 01h ---, which please note.
＊ 06h･･･06 in hexadecimal, therefore, 00000110 becomes a
binary number.
Number of
Pages 8Byte 16Byte 32Byte
Product
number
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
The above numbers are maximum bytes for respective types.
Any bytes below these can be written.
9/16
●Read Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when to
verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be read
in succession.
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential read
cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (μ-COM) side, the next address
data can be read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H' .
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input
'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
WORD
ADDRESS(n)
SDA
LINE
A
C
K
A
C
K
DATA(n)
A
C
K
SLAVE
ADDRESS
10 0 1 A0 A1 A2 WA
7 A0 D0
SLAVE
ADDRESS
10 0
1A1A2
S
T
A
R
T
D7
R
/
W
R
E
A
D
WA
0
N
ote
)
*1
It is necessary to input 'H' to
the last ACK.
Fig.42 Random read cycle (BR24A01A/02/04/08/16-WM)
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
1st WORD
ADDRESS（ｎ）
SDA
LINE
A
C
K
A
C
K
DATA(n)
A
C
K
SLAVE
ADDRESS
10 0
1A0 A1
A2 D7 D0
*
2nd WORD
ADDRESS（ｎ）
A
C
K
S
T
A
R
T
SLAVE
ADDRESS
100
1A2
A1
R
/
W
R
E
A
D
A0
WA
0
Note) *1
WA
12
WA
11
**
Fig.43 Random read cycle (BR24A32/64 -WM) *1 As for WA12, BR24A32-WM become Don’t care.
*1 As for WA7, BR24A01A-WM become Don’t care.
S
T
A
R
T
S
T
O
P
SDA
LINE
A
C
K
DATA(n)
A
C
K
SLAVE
ADDRESS
10 0 1 A0 A1 A2 D0 D7
R
/
W
R
E
A
D
Note)
Fig.44 Current read cycle
It is necessary to input 'H' to
the last ACK.
R
E
A
D
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
DATA(n)
SDA
LINE
A
C
K
A
C
K
DATA(n+x)
A
C
K
SLAVE
ADDRESS
10 0
1A0
A1
A2 D0 D7 D0D7
Note）
Fig.45 Sequential read cycle (in the case of current read cycle)
*1 In BR24A16-WM, A2 becomes P2.
*2 In BR24A08-WM, BR24A16-WM, A1 becomes P1.
*3 In BR24A04-WM, A0 becomes PS, and in BR24A08-WM
and BR24A16-WM, A0 becomes P0.
10 0
1A0
A1
A2
*1 *2 *3
Note)
Fig.46 Difference of slave address of each type
10/16
●Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset has
several kinds, and 3 kinds of them are shown in the figure below. (Refer to Fig.47(a), Fig.47(b), and Fig.47(c).) In dummy
clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L' level) may
be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to
instantaneous power failure of system power source or influence upon devices.
●Acknowledge polling
During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic
write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then it
means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command
can be executed without waiting for tWR = 5ms.
When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if
ACK signal sends back 'L', then execute word address input and data output and so forth.
1 2 13
14
SCL
Dummy clock×14 Start×2
Fig.47-(a) The case of dummy clock +START+START+ command input
※ Start command from START input.
2
1 8 9
Dumm
y
clock×9 Start
Fig.47-(b) The case of START +9 dummy clocks +START+ command input
Start
Normal command
Normal command
Normal command
Normal command
Start×9
SDA
1 2 3 8 9
7
Fig.47-(c) START×9+ command input
Normal command
Normal command
S
T
A
R
T
First write command
A
C
K
H
Slave
address
Slave
address
Write command
During internal write,
ACK = HIGH is sent back.
tWR
Second write command
S
T
A
R
T
S
T
A
R
T
S
T
O
P
S
T
O
P
A
C
K
H
A
C
K
H
A
C
K
L
A
C
K
L
SCL
SDA
SCL
SDA
Slave
address
Word
address
…
A
C
K
L
Slave
address Data
After completion of internal write,
ACK=LOW is sent back, so input next
word address and data in succession.
tWR
S
T
A
R
T
S
T
A
R
T
S
T
O
P
A
C
K
H
A
C
K
L
A
C
K
L
Fig.48 Case to continuously write by acknowledge polling
11/16
●WP valid timing (write cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP valid
timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte write
cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of data(in page
write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes Don't care. Set the setup time to rise of D0 taken SCL 100ns or more. The area from the rise of
SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR,
write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again. (Refer to Fig.49.) After
execution of forced end by WP, standby status gets in, so there is no need to wait for tWR (5ms at maximum).
●Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled.
(Refer to Fig. 50.)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by
start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in
succession, carry out random read cycle.
・Rise of D0 taken clock
SCL
D0 ACK
Enlarged view
SCL
SDA
Enlarged view
ACK
D0
・Rise of SDA
SDA
WP
WP cancel invalid area WP cancel valid area Write forced end
Data is not written. Data not guaranteed
Fig.49 WP valid timing
D7 D6 D5 D4 D3 D2 D1 D0 Data
tWR
SDA D1
S
T
A
R
T
A
C
K
L
A
C
K
L
A
C
K
L
A
C
K
L
S
T
O
P
Word
address
Fig.50 Case of cancel by start, stop condition during slave address input
SCL
SDA 1 1
0 0
Start condition Stop condition
Slave
address
12/16
●I/O peripheral circuit
○Pull up resistance of SDA terminal
SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to this resistance
value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, action frequency is limited. The smaller the RPU, the
larger the consumption current at action.
○Maximum value of RPU
The maximum value of RPU is determined by the following factors.
(1)SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
(2)The bus electric potential A to be determined by input leak total (IL) of device connected to bus at output of 'H' to SDA bus and RPU
should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended noise margin 0.2Vcc.
○Minimum value of RPU
The minimum value of RPU is determined by the following factors.
(1)When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA.
(2)VOLMAX=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise margin 0.1Vcc.
VOLMAX ≦ V
IL－0.1 VCC
Ex. ) When VCC =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3Vcc
from (1)
Therefore, the condition (2) is satisfied.
○Pull up resistance of SCL terminal
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes 'Hi-Z', add a pull up
resistance. As for the pull up resistance, one of several kΩ ~ several ten kΩ is recommended in consideration of drive performance of
output port of microcontroller.
●A0, A1, A2, WP process
○Process of device address terminals (A0,A1,A2)
Check whether the set device address coincides with device address input sent from the master side or not, and select one among plural
devices connected to a same bus. Connect this terminal to pull up or pull down, or Vcc or GND. And, pins (N, C, PIN) not used as device
address may be set to any of 'H' , 'L', and 'Hi-Z'.
Types with N.C.PIN BR24A16/F/FJ -WM A0, A1, A2
BR24A08/F/FJ-WM A0, A1
BR24A04/F/FJ -WM A0
○Process of WP terminal
WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only READ is available and WRITE of all
address is prohibited. In the case of 'L', both are available. In the case of use it as an ROM, it is recommended to connect it to pull up or Vcc.
In the case to use both READ and WRITE, control WP terminal or connect it to pull down or GND.
RPU ≧ 3－0.4
3×10 -3
≧ 867 [Ω]
And
VOL = 0.4 [V]
VIL = 0.3×3
= 0.9 [V]
∴ R
PU ＝
Ex. ) When VCC =3V, IL=10μA, VIH=0.7 VCC,
from (2)
0.8×3－0.7×3
10×10-6
RPU ≦
≦ 300 [kΩ]
0.8Vcc－VIH
IL
Vcc - ILRPU － 0.2Vcc ≧ V
IH
VC－VOL
IOL
VCC－VOL
RPU ≦ I
OL ∴ R
PU ≦
マイコン
RPU
A
BR24AXX
SDA terminal
IL IL
バスライン容量
CBUS
Fig.51 I/O circuit diagram
Microcontroller
Bus line
capacity
CBUS
13/16
●Cautions on microcontroller connection
○Rs
In I2C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of tri
state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM. This
is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON simultaneously.
Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is open drain input/output,
Rs can be used.
○Maximum value of Rs
The maximum value of Rs is determined by the following relations.
(1)SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
(2)The bus electric potential A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus should
sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc.
○Minimum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source
line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following
relation must be satisfied. Determine the allowable current in consideration of impedance of power source line in set and so
forth. Set the over current to EEPROM 10mA or below.
Microcontroller EEPROM
'L' output
R
S
R
PU
'H' output
Over currentⅠ
Fig.54 I/O circuit diagram
Fig.55 I/O circuit diagram
VCC
RS
VCC
I
≧
≦I
RS≧
300［Ω］
∴
Example）When VCC=3V, I=10mA
RS≧3
10×10-3
Example）When VCC=3V, VIL=0.3VCC, VOL=0.4V, RPU=20kΩ,
≦
×20×103
1.67［kΩ］
RPU+RS
(VCC－VOL)×RS+V
OL+0.1VCC≦VIL
RS≦×R
PU
∴VIL－VOL－0.1VCC
1.1VCC－VIL
1.1×3－0.3×3
0.3×3－0.4－0.1×3
RS≦from(2),
RPU
Microcontroller
RS
Fig.52 I/O circuit diagram Fig.53 Input / output collision timing
EEPROM
'L' output of EEPROM
'H' output of microcontroller
Over current flows to SDA line by 'H'
output of microcontroller and 'L'
output of EEPROM.
SCL
SDA
RPU
Microcontroller
RS
EEPROM
IOL
A
Bus line
capacity CBUS
VOL
VCC
VIL
14/16
●I2C BUS input / output circuit
○Input (A0,A2,SCL)
○Input / output (SDA)
○Input (A1, WP)
●Notes on power ON
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action,
observe the following conditions at power on.
1. Set SDA = 'H' and SCL ='L' or 'H'
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
Fig.56 Input pin circuit diagram
Fig.57 Input / output pin circuit diagram
Fig.58 Input pin circuit diagram
tOFF
tR
Vbot
0
VCC
Fig.59 Rise waveform diagram
Recommended conditions of tR, tOFF,Vbot
tRtOFF Vbot
10ms or below 10ms or longer 0.3V or below
100ms or belo
w
10ms or longer 0.2V or below
15/16
3. Set SDA and SCL so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above condition 1 cannot be observed. When SDA becomes 'L' at power on .
→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
b) In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset(P11).
c) In the case when the above conditions 1 and 2 cannot be observed.
→Carry out a), and then carry out b).
●Low voltage malfunction prevention function
LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it
prevent data rewrite.
●Vcc noise countermeasures
○Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended
to attach a by pass capacitor (0.1μF) between IC Vcc and GND. At that moment, attach it as close to IC as possible.
And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
●Cautions on use
(1)Described numeric values and data are design representative values, and the values are not guaranteed.
(2)We believe that application circuit examples are recommendable, however, in actual use, confirm
characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make
your decision with sufficient margin in consideration of static characteristics and transition characteristics
and fluctuations of external parts and our LSI.
(3)Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI
may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear
exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions
exceeding the absolute maximum ratings should not be impressed to LSI.
(4)GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of
GND terminal.
(5)Terminal design
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
(6)Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong
packaging may destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power
source, terminal and GND owing to foreign matter, LSI may be destructed.
(7)Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
tLOW
tSU:DAT
tDH
A
fter Vcc becomes stable
SCL
VCC
SDA
After Vcc becomes stable tSU:DAT
Fig.60 When SCL= 'H' and SDA= 'L' Fig.61 When SCL='L' and SDA='L'
●Selection of order type
●Package specifications
SOP8/SOP-J8
(Unit:mm)
〈External appearance〉
0.1
0.45Min.
0.42±0.1
4.9±0.2
85
4123
1.27
76
0.2±0.1
0.175 6.0±0.3
3.9±0.2
1.375±0.1
SOP8 SOP-J8
5.0±0.2
85
14
4.4±0.2
6.2±0.3
0.595
0.42±0.1
1.27
1.5±0.1
0.11
0.17 +0.1
-0.05
0.3Min.
0.9±0.15
Package
F:SOP8
FJ:SOP-J8
Package type Emboss taping
Package quantity 2500pcs(SOP8/SOP-J8)
Package direction E2
(When the reel is gripped by the left hand,
and the tape is pulled out by the right hand,
No.1 pin of the product is at the left top.）
〈Package specifications 〉
Reel Pulling side
Pin No.1
※For ordering, specify a number of multiples of the package quantity.
Package specifications
E2：reel shape emboss taping
TR：reel shape emboss taping
ROHM type
name
BUS type
24：I2C
Operating
temperature
L:-40℃～+85℃
S:-40℃～+85℃
A:-40℃～+105℃
Capacity
01=1K
02=2K
04=4K
08=8K
16=16K
32=32K
64=64K
Double cell
B R 2 4 A 0 1 F W E 2 M
1st 2009, January
Catalog No.09001EAT02 '09.1 ROHM © Published by LSI Business Promotion Group
Appendix-Rev4.0
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Appendix
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM
CO.,LTD.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you
wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM
upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account
when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no re-
sponsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples
of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to
use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no re-
sponsibility whatsoever for any dispute arising from the use of such technical information.
The Products specified in this document are intended to be used with general-use electronic equipment
or devices (such as audio visual equipment, office-automation equipment, communication devices, elec-
tronic appliances and amusement devices).
The Products are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or
malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as
derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your
use of any Product outside of the prescribed scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system
which requires an extremely high level of reliability the failure or malfunction of which may result in a direct
threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment,
aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear
no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intend-
ed to be used for any such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled under
the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
