© 2008 Semiconductor Components Industries, LLC. Publication Order Number:
FAN3214 /D
October-2017, Rev.2
FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers
FAN3213 / FAN3214
Dual-4 A, High-Speed, Low-Side Gate Drivers
Features
Industry-Standard Pin Out
4.5 to 18 V Operating Range
5 A Peak Sink/Source at VDD = 12 V
4.3 A Sink / 2.8 A Source at VOUT = 6 V
TTL Input Thresholds
Two Versions of Dual Independent Drivers:
-Dual Inverting (FAN3213)
-Dual Non-Inverting (FAN3214)
Internal Resistors Turn Driver Off If No Inputs
MillerDrive™ Technology
12 ns / 9 ns Typical Rise/Fall Times with 2.2 nF
Load
Typical Propagation Delay Under 20 ns Matched
within 1 ns to the Other Channel
Double Current Capability by Paralleling Channels
Standard SOIC-8 Package
Rated from –40°C to +125°C Ambient
Automotive Qualified to AEC-Q100 (F085 Version)
Applications
Switch-Mode Power Supplies
High-Efficiency MOSFET Switching
Synchronous Rectifier Circuits
DC-to-DC Converters
Motor Control
Automotive-Qualified Systems (F085 version)
Description
The FAN3213 and FAN3214 dual 4 A gate drivers are
designed to drive N-channel enhancement-mode
MOSFETs in low-side switching applications by
providing high peak current pulses during the short
switching intervals. They are both available with TTL
input thresholds. Internal circuitry provides an under-
voltage lockout function by holding the output LOW until
the supply voltage is within the operating range. In
addition, the drivers feature matched internal
propagation delays betw een A and B channels for
applications requiring dual gate drives with critical
timing, such as synchronous rectifiers. This also
enables connecting two drivers in parallel to effectively
double the current capability driving a single MOSFET.
The FA N3213/14 drivers incorporate MillerDrive™
architecture for the final output stage. This bipolar-
MOSFET combination provides high current during the
Miller plateau stage of the MOSFET turn-on / turn-off
process to minimize switching loss, while providing rail-
to-rail voltage swing and reverse current capability.
The FAN3213 offers two inverting drivers and the
FAN3214 offers two non-inverting drivers. Both are
offered in a standard 8-pin SOIC package.
1
NC
INA
GND
NC
VDD
INB
OUTA
OUTB
2
3
4
8
6
5
A7
B
1NC
VDD
OUTA
OUTB
2
3
4
8
6
5
7
A
B
NC
INA
GND
INB
FAN3213
FAN3214
Figure 1. Pin Configurations
www.onsemi.com
2
FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers
Ordering Information
Part Number
Input
Threshold
Package
Packing
Method
Quantity
per Reel
FAN3213TMX
TTL
SOIC-8
Tape & Reel
2,500
FAN3214TMX
FAN3213TMX_F085(1)
FAN3214TMX_F085(1)
Note:
1. Qualified to AEC-Q100
Package Outlines
2
3
8
6
1
4
7
5
Figure 2. SOIC-8 (Top View)
Thermal Characteristics(2)
Package
JL(3)
JT(4)
JA(5)
JB(6)
JT(7)
Unit
8-Pin Small Outline Integrated Circuit (SOIC)
38
29
87
41
2.3
°C/W
Notes:
2. Estimates derived from thermal simulation; actual values depend on the application.
3. Theta_JL (JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads
(including any thermal pad) that are typically soldered to a PCB.
4. Theta_JT (JT): Thermal resistance between the semiconductor junction and the top surface of the package,
assuming it is held at a uniform temperature by a top-side heatsink.
5. Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking,
and airflow. The value given is for natural convection with no heatsink, using a 2S2P board, as specified in
JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate.
6. Psi_JB (JB): Thermal characterization parameter providing correlation between semiconductor junction
temperature and an application circuit board reference point for the thermal environment defined in Note 5. For
the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6.
7. Psi_JT (JT): Thermal characterization parameter providing correlation between the semiconductor junction
temperature and the center of the top of the package for the thermal environment defined in Note 5.
www.onsemi.com
3
FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers
Pin Configurations
1
NC
INA
GND
NC
VDD
INB
OUTA
OUTB
2
3
4
8
6
5
A7
B
1NC
VDD
OUTA
OUTB
2
3
4
8
6
5
7
A
B
NC
INA
GND
INB
FAN3213
FAN3214
Figure 3. Pin Configurations (Repeated)
Pin Definitions
Pin
Name
Pin Description
1
NC
No Connect. This pin can be grounded or left floating.
2
INA
Input to Channel A.
3
GND
Ground. Common ground reference for input and output circuits.
4
INB
Input to Channel B.
5
(FAN3213)
OUTB
Gate Drive Output B (inverted from the input): Held LOW unless required input is
present and VDD is above UVLO threshold.
5
(FAN3214)
OUTB
Gate Drive Output B: Held LOW unless required input(s) are present and VDD is above
UVLO threshold.
6
VDD
Supply Voltage. Provides power to the IC.
7
(FAN3213)
OUTA
Gate Drive Output A (inverted from the input): Held LOW unless required input is
present and VDD is above UVLO threshold.
7
(FAN3214)
OUTA
Gate Drive Output A: Held LOW unless required input(s) are present and VDD is above
UVLO threshold.
8
NC
No Connect. This pin can be grounded or left floating.
Output Logic
FAN3213 (x=A or B)
FAN3214 (x=A or B)
INx
OUTx
INx
OUTx
0
1
0(9)
0
1(9)
0
1
1
Note:
9. Default input signal if no external connection is made.
www.onsemi.com
4
FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers
Block Diagrams
6VDD
7OUTA
VDD_OK
5
INA 2
NC 1
GND 3UVLO
8NC
INB 4OUTB
100k
100k
100k
100k
Figure 4. FAN3213 Block Diagram
6VDD
7OUTA
VDD_OK
5
INA 2
NC 1
GND 3UVLO
8NC
INB 4OUTB
100k
100k
100k
100k
Figure 5. FAN3214 Block Diagram
www.onsemi.com
5
FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VDD
VDD to PGND
-0.3
20.0
V
VIN
INA and INB to GND
GND - 0.3
VDD + 0.3
V
VOUT
OUTA and OUTB to GND
GND - 0.3
VDD + 0.3
V
TL
Lead Soldering Temperature (10 Seconds)
+260
ºC
TJ
Junction Temperature
-55
+150
ºC
TSTG
Storage Temperature
-65
+150
ºC
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor
does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
VDD
Supply Voltage Range
4.5
18.0
V
VIN
Input Voltage INA and INB
0
VDD
V
TA
Operating Ambient Temperature
-40
+125
ºC
www.onsemi.com
6
FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers
Electrical Characteristics
Unless otherwise noted, VDD=12 V, TJ=-40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Supply
FAN321xT
VDD
Operating Range
4.5
18.0
V
IDD
Supply Current, Inputs Not Connected
0.70
0.95
mA
VON
Turn-On Voltage
INA=VDD, INB=0 V
3.5
3.9
4.3
V
VOFF
Turn-Off Voltage
INA=VDD, INB=0 V
3.3
3.7
4.1
V
FAN321xTMX_F085 (Automotive-Qualified Versions)
IDD
Supply Current, Inputs Not Connected(12)
0.70
1.20
mA
VON
Turn-On Voltage(12)
INA=VDD, INB=0 V
3.3
3.9
4.5
V
VOFF
Turn-Off Voltage(12)
INA=VDD, INB=0 V
3.1
3.7
4.3
V
Inputs
VIL_T
INx Logic Low Threshold
0.8
1.2
V
VIH_T
INx Logic High Threshold
1.6
2.0
V
FAN321xT
IIN+
Non-Inverting Input
IN from 0 to VDD
-1.5
175.0
µA
IIN-
Inverting Input
IN from 0 to VDD
-175.0
1.5
µA
VHYS_T
TTL Logic Hysteresis Voltage
0.2
0.4
0.8
V
FAN321xTMX_F085 (Automotive-Qualified Versions)
IINx_T
Non-inverting Input Current(12)
IN=0 V
-1.5
1.5
µA
IINx_T
Non-inverting Input Current(12)
IN=VDD
90
120
175
µA
IINx_T
Inverting Input Current(12)
IN=0 V
-175
-120
-90
µA
IINx_T
Inverting Input Current(12)
IN=VDD
-1.5
1.5
µA
VHYS_T
TTL Logic Hysteresis Voltage(12)
0.1
0.4
0.8
V
Output
ISINK
OUT Current, Mid-Voltage, Sinking(10)
OUTx at VDD/2,
CLOAD=0.22 µF, f=1 kHz
4.3
A
ISOURCE
OUT Current, Mid-Voltage, Sourcing(10)
OUTx at VDD/2,
CLOAD=0.22 µF, f=1 kHz
-2.8
A
IPK_SINK
OUT Current, Peak, Sinking(10)
CLOAD=0.22 µF, f=1 kHz
5
A
IPK_SOURCE
OUT Current, Peak, Sourcing(10)
CLOAD=0.22 µF, f=1 kHz
-5
A
IRVS
Output Reverse Current Withstand(10)
500
mA
TDEL.MATCH
Propagation Matching Between Channels
INA=INB, OUTA and OUTB
at 50% Point
2
4
ns
Continued on the following page…
www.onsemi.com
7
FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers
Electrical Characteristics (Continued)
Unless otherwise noted, VDD=12 V, TJ=-40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
FAN321xT
tRISE
Output Rise Time(11)
CLOAD=2200 pF
12
20
ns
tFALL
Output Fall Time(11)
CLOAD=2200 pF
9
17
ns
tD1, tD2
Output Propagation Delay, TTL Inputs(11)
0 - 5 VIN, 1 V/ns Slew Rate
9
17
29
ns
FAN321xTMX_F085 (Automotive-Qualified Versions)
tRISE
Output Rise Time(11)(12)
CLOAD=2200 pF
12
22
ns
tFALL
Output Fall Time(11)(12)
CLOAD=2200 pF
9
18
ns
tD1, tD2
Output Propagation Delay, TTL Inputs(11)(12)
0 – 5 VIN, 1 V/ns Slew Rate
9
17
32
ns
VOH
High Level Output Voltage(12)
VOH=VDD–VOUT, IOUT=–1 mA
15
35
mV
VOL
Low Level Output Voltage(12)
IOUT=1 mA
10
25
mV
Notes:
10. Not tested in production.
11. See Timing Diagrams of Figure 6 and Figure 7.
12. Apply only to Automotive Version(FAN321xTMX_F085)
90%
10%
Output
Input
tD1 tD2
tRISE tFALL
VINL
VINH
90%
10%
Output
tD1 tD2
tFALL tRISE
VINL
VINH
Input
Figure 6. Non-Inverting Timing Diagram
Figure 7. Inverting Timing Diagram
www.onsemi.com
8
FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at TA=25°C and VDD=12 V unless otherw ise noted.
Figure 8. IDD (Static) vs. Supply Voltage(12)
Figure 9. IDD (Static) vs. Temperature(12)
Figure 10. IDD (No Load) vs. Frequency
Figure 11. IDD (2.2 nF Load) vs. Frequency
Figure 12. Input Thresholds vs. Supply Voltage
Figure 13. Input Thresholds vs. Temperature
www.onsemi.com
9
FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at TA=25°C and VDD=12 V unless otherw ise noted.
UVLO Threshold vs. Temperature
Figure 14. Propagation Delay vs. Supply Voltage
Figure 15. Propagation Delay vs. Supply Voltage
Figure 16. Propagation Delays vs. Temperature
Figure 17. Propagation Delays vs. Temperature
www.onsemi.com
10
FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at TA=25°C and VDD=12 V unless otherw ise noted.
Figure 18. Fall Time vs. Supply Voltage
Figure 19. Rise Time vs. Supply Voltage
Figure 20. Rise and Fall Times vs. Temperature
Figure 21. Rise/Fall Waveforms with 2.2 nF Load
Figure 22. Rise/Fall Waveforms with 10 nF Load
www.onsemi.com
11
FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at TA=25°C and VDD=12 V unless otherw ise noted.
Figure 23. Quasi-Static Source Current
with VDD=12 V(13)
Figure 24. Quasi-Static Sink Current with VDD=12 V(13)
Figure 25. Quasi-Static Source Current
with VDD=8 V(14)
Figure 26. Quasi-Static Sink Current with VDD=8 V(14)
Notes:
13. For any inverting inputs pulled low, non-inverting inputs pulled high, or outputs driven high; static IDD increases
by the current flowing through the corresponding pull-up/down resistor shown in Figure 4 and Figure 5.
14. The initial spike in each current waveform is a measurement artifact caused by the stray inductance of the
current-measurement loop.
Test Circuit
470µF
Al. El.
VDD
VOUT
1µF
ceramic
4.7µF
ceramic
CLOAD
0.22µF
IOUT
IN
1kHz
Current Probe
LECROY AP015
Figure 27. Quasi-Static IOUT / VOUT Test Circuit
www.onsemi.com
12
FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers
Applications Information
Input Thresholds
The FAN3213 and the FAN3214 drivers consist of two
identical channels that may be used independently at
rated current or connected in parallel to double the
individual current capacity.
The input thresholds meet industry-standard TTL-logic
thresholds independent of the VDD voltage, and there is
a hysteresis voltage of approximately 0.4 V. These
levels permit the inputs to be driven from a range of
input logic signal levels for w hich a voltage over 2 V is
considered logic HIGH. The driving signal for the TTL
inputs should have fast rising and falling edges with a
slew rate of 6 V/µs or faster, so a rise time from 0 to
3.3 V should be 550 ns or less. With reduced slew rate,
circuit noise could cause the driver input voltage to
exceed the hysteresis voltage and retrigger the driver
input, causing erratic operation.
Static Supply Current
In the IDD (static) typical performance characteristics
shown in Figure 8 and Figure 9, each curve is produced
with both inputs floating and both outputs LOW to
indicate the lowest static IDD current. For other states,
additional current flows through the 100 k resistors on
the inputs and outputs shown in the block diagram of
each part (see Figure 4 and Figure 5). In these cases,
the actual static IDD current is the value obtained from
the curves plus this additional current.
MillerDrive™ Gate Drive Technology
FAN3213 and FAN3214 gate drivers incorporate the
Miller Drive™ architecture show n in Figure 28. For the
output stage, a combination of bipolar and MOS devices
provide large currents over a wide range of supply
voltage and temperature variations. The bipolar devices
carry the bulk of the current as OUT swings between 1/3
to 2/3 VDD and the MOS devices pull the output to the
HIGH or LOW rail.
The purpose of the MillerDrive™ architecture is to
speed up switching by providing high current during the
Miller plateau region when the gate-drain capacitance of
the MOSFET is being charged or discharged as part of
the turn-on / turn-off process.
For applications with zero voltage switching during the
MOSFET turn-on or turn-off interval, the driver supplies
high peak current for fast switching even though the
Miller plateau is not present. This situation often occurs
in synchronous rectifier applications because the body
diode is generally conducting before the MOSFET is
switched ON.
The output pin slew rate is determined by VDD voltage
and the load on the output. It is not user adjustable, but
a series resistor can be added if a slower rise or fall time
at the MOSFET gate is needed.
Input
stage
VDD
VOUT
Figure 28. MillerDrive™ Output Architecture
Under-Voltage Lockout
The FAN321x startup logic is optimized to drive ground-
referenced N-channel MOSFETs with an under-voltage
lockout (UVLO) function to ensure that the IC starts up
in an orderly fashion. When VDD is rising, yet below the
3.9 V operational level, this circuit holds the output
LOW, regardless of the status of the input pins. After the
part is active, the supply voltage must drop 0.2 V before
the part shuts down. This hysteresis helps prevent
chatter w hen low VDD supply voltages have noise from
the power switching. This configuration is not suitable
for driving high-side P-channel MOSFETs because the
low output voltage of the driver would turn the P-channel
MOSFET on with VDD below 3.9 V.
VDD Bypass Capacitor Guidelines
To enable this IC to turn a device ON quickly, a local
high-frequency bypass capacitor, CBYP, with low ESR and
ESL should be connected between the VDD and GND
pins with minimal trace length. This capacitor is in
addition to bulk electrolytic capacitance of 10 µF to 47 µF
commonly found on driver and controller bias circuits.
A typical criterion for choosing the value of CBYP is to
keep the ripple voltage on the VDD supply to ≤ 5%. This
is often achieved w ith a value ≥ 20 times the equivalent
load capacitance CEQV, defined here as QGATE/VDD.
Ceramic capacitors of 0.1 µF to 1 µF or larger are
common choices, as are dielectrics, such as X5R and
X7R, with good temperature characteristics and high
pulse current capability.
If circuit noise affects normal operation, the value of
CBYP may be increased, to 50-100 times the CEQV, or
CBYP may be split into two capacitors. One should be a
larger value, based on equivalent load capacitance, and
the other a smaller value, such as 1-10 nF mounted
closest to the VDD and GND pins to carry the higher-
frequency components of the current pulses. The
bypass capacitor must provide the pulsed current from
both of the driver channels and, if the drivers are
switching simultaneously, the combined peak current
sourced from the CBYP w ould be twice as large as when
a single channel is switching.
www.onsemi.com
13
FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers
Layout and Connection Guidelines
The FAN3213 and FAN3214 gate drivers incorporate
fast-reacting input circuits, short propagation delays,
and powerful output stages capable of delivering current
peaks over 4 A to facilitate voltage transition times from
under 10 ns to over 150 ns. The following layout and
connection guidelines are strongly recommended:
Keep high-current output and power ground paths
separate from logic input signals and signal ground
paths. This is especially critical for TTL-level logic
thresholds at driver input pins.
Keep the driver as close to the load as possible to
minimize the length of high-current traces. This
reduces the series inductance to improve high-
speed switching, while reducing the loop area that
can radiate EMI to the driver inputs and
surrounding circuitry.
If the inputs to a channel are not externally
connected, the internal 100 k resistors indicated
on block diagrams command a low output. In noisy
environments, it may be necessary to tie inputs of
an unused channel to VDD or GND using short
traces to prevent noise from causing spurious
output switching.
Many high-speed power circuits can be susceptible
to noise injected from their own output or other
external sources, possibly causing output re-
triggering. These effects can be obvious if the
circuit is tested in breadboard or non-optimal circuit
layouts with long input or output leads. For best
results, make connections to all pins as short and
direct as possible.
FAN3213 and FAN3214 are pin-compatible with
many other industry-standard drivers.
The turn-on and turn-off current paths should be
minimized, as discussed in the following section.
Figure 29 shows the pulsed gate drive current path
when the gate driver is supplying gate charge to turn the
MOSFET on. The current is supplied from the local
bypass capacitor, CBYP, and flows through the driver to
the MOSFET gate and to ground. To reach the high
peak currents possible, the resistance and inductance in
the path should be minimized. The localized CBYP acts
to contain the high peak current pulses within this driver-
MOSFET circuit, preventing them from disturbing the
sensitive analog circuitry in the PWM controller.
PWM
VDS
VDD
CBYP
FAN321x
Figure 29. Current Path for MOSFET Turn-On
Figure 30 shows the current path when the gate driver
turns the MOSFET OFF. Ideally, the driver shunts the
current directly to the source of the MOSFET in a small
circuit loop. For fast turn-off times, the resistance and
inductance in this path should be minimized.
PWM
VDS
VDD
CBYP
FAN321x
Figure 30. Current Path for MOSFET Turn-Off
www.onsemi.com
14
FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers
Operational Waveforms
At power-up, the driver output remains LOW until the
VDD voltage reaches the turn-on threshold. The
magnitude of the OUT pulses rises with VDD until
steady-state VDD is reached. The non-inverting
operation illustrated in Figure 31 shows that the output
remains LOW until the UVLO threshold is reached, then
the output is in-phase with the input.
VDD
IN+
IN-
OUT
Turn-on threshold
Figure 31. Non-Inverting Startup Waveforms
The inverting configuration of startup waveforms are
shown in Figure 32. With IN+ tied to VDD and the input
signal applied to IN–, the OUT pulses are inverted with
respect to the input. At power-up, the inverted output
remains LOW until the VDD voltage reaches the turn-on
threshold, then it follows the input with inverted phase.
VDD
IN+
(VDD)
IN-
OUT
Turn-on threshold
Figure 32. Inverting Startup Waveforms
www.onsemi.com
15
FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers
Thermal Guidelines
Gate drivers used to switch MOSFETs and IGBTs at
high frequencies can dissipate significant amounts of
power. It is important to determine the driver power
dissipation and the resulting junction temperature in the
application to ensure that the part is operating within
acceptable temperature limits.
The total power dissipation in a gate driver is the sum of
two components, PGATE and PDYNAMIC:
PTOTAL = PGATE + PDYNAMIC
(1)
PGATE (Gate Driving Loss): The most significant power
loss results from supplying gate current (charge per
unit time) to switch the load MOSFET on and off at
the switching frequency. The power dissipation that
results from driving a MOSFET at a specified gate-
source voltage, VGS, with gate charge, QG, at
switching frequency, fSW, is determined by:
PGATE = QG • VGS • fSW • n
(2)
where n is the number of driver channels in use (1 or 2).
PDYNAMIC (Dynamic Pre-Drive / Shoot-through
Current): A power loss resulting from internal current
consumption under dynamic operating conditions,
including pin pull-up / pull-down resistors. The internal
current consumption (IDYNAMIC) can be estimated using
the graphs in Figure 10 of the Typical Performance
Characteristics to determine the current IDYNAMIC
drawn from VDD under actual operating conditions:
PDYNAMIC = IDYNAMIC • VDD • n
(3)
where n is the number of driver ICs in use. Note that n is
usually be one IC even if the IC has two channels,
unless two or more.driver ICs are in parallel to drive a
large load.
Once the power dissipated in the driver is determined,
the driver junction rise with respect to circuit board can
be evaluated using the following thermal equation,
assuming JB was determined for a similar thermal
design (heat sinking and air flow):
TJ = PTOTAL • JB + TB
(4)
where:
TJ = driver junction temperature;
JB = (psi) thermal characterization parameter
relating temperature rise to total power
dissipation; and
TB = board temperature in location as defined in
the Thermal Characteristics table.
To give a numerical example, assume for a 12 V VDD
(Vibas) system, the synchronous rectifier switches of
Figure 33 have a total gate charge of 60 nC at
VGS = 7 V. Therefore, two devices in parallel would have
120 nC gate charge. At a switching frequency of
300 kHz, the total power dissipation is:
PGATE = 120 nC • 7 V • 300 kHz • 2 = 0.504 W
(5)
PDYNAMIC = 3.0 mA • 12 V • 1 = 0.036 W
(6)
PTOTAL = 0.540 W
(7)
The SOIC-8 has a junction-to-board thermal
characterization parameter of JB = 42°C/W. In a
system application, the localized temperature around
the device is a function of the layout and construction of
the PCB along with airflow across the surfaces. To
ensure reliable operation, the maximum junction
temperature of the device must be prevented from
exceeding the maximum rating of 150°C; with 80%
derating, TJ would be limited to 120°C. Rearranging
Equation 4 determines the board temperature required
to maintain the junction temperature below 120°C:
TB,MAX = TJ - PTOTAL • JB
(8)
TB,MAX = 120°C – 0.54 W • 42°C/W = 97°C
(9)
www.onsemi.com
16
FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers
Typical Application Diagrams
VIN
PWM
1
2
36
7
8
45
Timing/
Isolation
VOUT
FAN3214
Vbias
FAN3214
1
2
36
7
8
45
VDDGND
B
A
Figure 33. High-Current Forward Converter
with Synchronous Rectification
Figure 34. Center-Tapped Bridge Output with
Synchronous Rectifiers
PWM-A
PWM-B
PWM-C
PWM-D
Secondary
Phase Shift
Controller
VIN QA
QB
QC
QD
SR-2
SR-1
FAN3214
FAN3225C
FAN3225C
Figure 35. Secondary Controlled Full Bridge with Current Doubler Output,
Synchronous Rectifiers (Simplified)
www.onsemi.com
17
FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers
Table 1. Related Products
Type
Part
Number
Gate Drive(15)
(Sink/Src)
Input
Threshold
Logic
Package
Single 1 A
FAN3111C
+1.1 A / -0.9 A
CMOS
Single Channel of Dual-Input/Single-Output
SOT23-5, MLP6
Single 1 A
FAN3111E
+1.1 A / -0.9 A
External(16)
Single Non-Inverting Channel with External Reference
SOT23-5, MLP6
Single 2 A
FAN3100C
+2.5 A / -1.8 A
CMOS
Single Channel of Two-Input/One-Output
SOT23-5, MLP6
Single 2 A
FAN3100T
+2.5 A / -1.8 A
TTL
Single Channel of Two-Input/One-Output
SOT23-5, MLP6
Single 2 A
FAN3180
+2.4 A / -1.6 A
TTL
Single Non-Inverting Channel + 3.3 V LDO
SOT23-5
Dual 2 A
FAN3216T
+2.5 A / -1.8 A
TTL
Dual Inverting Channels
SOIC8
Dual 2 A
FAN3217T
+2.5 A / -1.8 A
TTL
Dual Non-Inverting Channels
SOIC8
Dual 2 A
FAN3226C
+2.4 A / -1.6 A
CMOS
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
Dual 2 A
FAN3226T
+2.4 A / -1.6 A
TTL
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
Dual 2 A
FAN3227C
+2.4 A / -1.6 A
CMOS
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
Dual 2 A
FAN3227T
+2.4 A / -1.6 A
TTL
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
Dual 2 A
FAN3228C
+2.4 A / -1.6 A
CMOS
Dual Channels of Two-Input/One-Output, Pin Config.1
SOIC8, MLP8
Dual 2 A
FAN3228T
+2.4 A / -1.6 A
TTL
Dual Channels of Two-Input/One-Output, Pin Config.1
SOIC8, MLP8
Dual 2 A
FAN3229C
+2.4 A / -1.6 A
CMOS
Dual Channels of Two-Input/One-Output, Pin Config.2
SOIC8, MLP8
Dual 2 A
FAN3229T
+2.4 A / -1.6 A
TTL
Dual Channels of Two-Input/One-Output, Pin Config.2
SOIC8, MLP8
Dual 2 A
FAN3268T
+2.4 A / -1.6 A
TTL
20 V Non-Inverting Channel (NMOS) and Inverting
Channel (PMOS) + Dual Enables
SOIC8
Dual 2 A
FAN3278T
+2.4 A / -1.6 A
TTL
30 V Non-Inverting Channel (NMOS) and Inverting
Channel (PMOS) + Dual Enables
SOIC8
Dual 4 A
FAN3213T
+2.5 A / -1.8 A
TTL
Dual Inverting Channels
SOIC8
Dual 4 A
FAN3214T
+2.5 A / -1.8 A
TTL
Dual Non-Inverting Channels
SOIC8
Dual 4 A
FAN3223C
+4.3 A / -2.8 A
CMOS
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
Dual 4 A
FAN3223T
+4.3 A / -2.8 A
TTL
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
Dual 4 A
FAN3224C
+4.3 A / -2.8 A
CMOS
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
Dual 4 A
FAN3224T
+4.3 A / -2.8 A
TTL
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
Dual 4 A
FAN3225C
+4.3 A / -2.8 A
CMOS
Dual Channels of Two-Input/One-Output
SOIC8, MLP8
Dual 4 A
FAN3225T
+4.3 A / -2.8 A
TTL
Dual Channels of Two-Input/One-Output
SOIC8, MLP8
Single 9 A
FAN3121C
+9.7 A / -7.1 A
CMOS
Single Inverting Channel + Enable
SOIC8, MLP8
Single 9 A
FAN3121T
+9.7 A / -7.1 A
TTL
Single Inverting Channel + Enable
SOIC8, MLP8
Single 9 A
FAN3122C
+9.7 A / -7.1 A
CMOS
Single Non-Inverting Channel + Enable
SOIC8, MLP8
Single 9 A
FAN3122T
+9.7 A / -7.1 A
TTL
Single Non-Inverting Channel + Enable
SOIC8, MLP8
Dual 12 A
FAN3240
+12.0 A
TTL
Dual-Coil Relay Driver, Timing Config. 0
SOIC8
Dual 12 A
FAN3241
+12.0 A
TTL
Dual-Coil Relay Driver, Timing Config. 1
SOIC8
Notes:
15. Typical currents with OUTx at 6 V and VDD=12 V.
16. Thresholds proportional to an externally supplied reference voltage.
www.onsemi.com
18
FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers
Physical Dimensions
Figure 36. 8-Lead Small Outline Integrated Circuit (SOIC)
8°
0°
SEE DETAIL A
NOTES:
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M
E) DRAWING FILENAME: M08Arev16
LAND PATTERN RECOMMENDATION
SEATING PLANE
C
GAGE PLANE
x 45°
DETAIL A
SCALE: 2:1
PIN ONE
INDICATOR 4
8
1
B
5
A
5.60
0.65
1.75
1.27
6.00±0.20 3.90±0.10
4.90±0.10
1.27
0.42±0.09
0.175±0.075
1.75 MAX
0.36
(0.86)
R0.10
R0.10
0.65±0.25
(1.04)
OPTION A - BEVEL EDGE
OPTION B - NO BEVEL EDGE
0.25 C B A
0.10
0.22±0.03
(0.635)
www.onsemi.com
19
FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers
ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the
United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A
listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make
changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor
products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by
ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and
actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for
use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or
any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs,
damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax : 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
N. Amer ican Technical Support: 800-282-9855 Toll Free
USA/Canada.
Eur ope, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81-3-5817-1050
ON Semic onductor Website: www.onsemi.com
Or der Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative