www.irf.com 1
06/30/05
IRF7832
HEXFET® Power MOSFET
Notes through are on page 10
Benefits
lVery Low RDS(on) at 4.5V VGS
lUltra-Low Gate Impedance
lFully Characterized Avalanche Voltage
and Current
l20V VGS Max. Gate Rating
l100% tested for Rg
Applications
lSynchronous MOSFET for Notebook
Processor Power
lSynchronous Rectifier MOSFET for
Isolated DC-DC Converters in
Networking Systems
Top View
8
1
2
3
45
6
7
D
D
D
DG
S
A
S
S
A
SO-8
VDSS RDS(on) max Qg
30V 4.0m
:
@VGS = 10V 34nC
Absolute Maximum Ratin
g
s
Parameter Units
VDS Drain-to-Source Voltage V
VGS Gate-to-Source Voltage
ID @ TA = 25°C Continuous Drain Current, VGS @ 10V
ID @ TA = 70°C Continuous Drain Current, VGS @ 10V A
IDM Pulsed Drain Current
c
PD @TA = 25°C Power Dissipation W
PD @TA = 70°C Power Dissipation
Linear Derating Factor W/°C
TJ Operating Junction and °C
TSTG Storage Temperature Range
Thermal Resistance
Parameter Typ. Max. Units
RθJL Junction-to-Drain Lead ––– 20 °C/W
RθJA
J
unct
i
on-to-
A
m
bi
ent
f
––– 50
-55 to + 155
2.5
0.02
1.6
Max.
20
16
160
± 20
30
PD - 94594E
IRF7832
2www.irf.com
S
D
G
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. T
y
p. Max. Units
BVDSS Drain-to-Source Breakdown Voltage 30 ––– ––– V
∆ΒVDSS
/
∆TJ Breakdown Voltage Temp. Coefficient ––– 0.023 ––– V/°C
RDS(on) Static Drain-to-Source On-Resistance ––– 3.1 4.0 mΩ
––– 3.7 4.8
VGS(th) Gate Threshold Voltage 1.39 ––– 2.32 V
∆VGS(th) Gate Threshold Voltage Coefficient ––– 5.7 ––– mV/°C
IDSS Drain-to-Source Leakage Current ––– ––– 1.0 µA
––– ––– 150
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leakage ––– ––– -100
gfs Forward Transconductance 77 ––– ––– S
QgTotal Gate Charge ––– 34 51
Qgs1 Pre-Vth Gate-to-Source Charge ––– 8.6 –––
Qgs2 Post-Vth Gate-to-Source Charge ––– 2.9 ––– nC
Qgd Gate-to-Drain Charge ––– 12 –––
Qgodr Gate Charge Overdrive ––– 10.5 ––– See Fig. 16
Qsw Switch Char
g
e (Qgs2 + Qgd)–––14.9–––
Qoss Output Charge ––– 23 ––– nC
RgGate Resistance ––– 1.2 2.4 Ω
td(on) Turn-On Delay Time ––– 12 –––
trRise Time ––– 6.7 –––
td(off) Turn-Off Delay Time ––– 21 ––– ns
tfFall Time –––13–––
Ciss Input Capacitance ––– 4310 –––
Coss Output Capacitance ––– 990 ––– pF
Crss Reverse Transfer Capacitance ––– 450 –––
Avalanche Characteristics
Parameter Units
EAS
Si
n
gl
e
P
u
l
se
A
va
l
anc
h
e
E
ner
gy
d
mJ
IAR
va
anc
e
urrent
c
A
Diode Characteristics
Parameter Min. T
y
p. Max. Units
ISContinuous Source Current ––– ––– 3.1
(Body Diode) A
ISM Pulsed Source Current ––– ––– 160
(
Bod
y
Diode
)
c
VSD Diode Forward Voltage ––– ––– 1.0 V
trr Reverse Recovery Time ––– 41 62 ns
Qrr Reverse Recovery Charge ––– 39 59 nC
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
–––
ID = 16A
VGS = 0V
VDS = 15V
VGS = 4.5V, ID = 16A
e
VGS = 4.5V
Typ.
–––
VDS = VGS, ID = 250µA
Clamped Inductive Load
VDS = 15V, ID = 16A
VDS = 24V, VGS = 0V, TJ = 125°C
TJ = 25°C, IF = 16A, VDD = 10V
di/dt = 100A/
µ
s
e
TJ = 25°C, IS = 16A, VGS = 0V
e
showing the
integral reverse
p-n junction diode.
MOSFET symbol
VDS = 16V, VGS = 0V
VDD = 15V, VGS = 4.5V
ID = 16A
VDS = 15V
VGS = 20V
VGS = -20V
VDS = 24V, VGS = 0V
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 20A
e
Conditions
Max.
260
16
ƒ = 1.0MHz
IRF7832
www.irf.com 3
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.1 110 100 1000
VDS, Drain-to-Source Voltage (V)
0.01
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
2.25V
20µs PULSE WIDTH
Tj = 25°C
VGS
TOP 10V
5.0V
4.5V
3.5V
3.0V
2.7V
2.5V
BOTTOM 2.25V
2.0 2.5 3.0 3.5 4.0
VGS, Gate-to-Source Voltage (V)
0
1
10
100
1000
ID, Drain-to-Source Current (Α)
TJ = 25°C
TJ = 150°C
VDS = 15V
20µs PULSE WIDTH
0.1 110 100 1000
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
2.25V
20µs PULSE WIDTH
Tj = 150°C
VGS
TOP 10V
5.0V
4.5V
3.5V
3.0V
2.7V
2.5V
BOTTOM 2.25V
-60 -40 -20 020 40 60 80 100 120 140 160
TJ, Junction Temperature (°C )
0.0
0.5
1.0
1.5
2.0
RDS(on) , Drain-to -Source On Resistance
(Normalized)
ID = 16A
VGS = 4.5V
IRF7832
4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
C, Capacitance(pF)
VGS
= 0V, f = 1 MHZ
Ciss
= C
gs
+ C
gd, C
ds
SHORTED
Crss
= C
gd
Coss
= C
ds
+ C
gd
Coss
Crss
Ciss
0 1020304050
QG Total Gate Charge (nC)
0
1
2
3
4
5
6
VGS, Gate-to-Source Voltage (V)
VDS= 24V
VDS= 15V
ID= 16A
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
VSD , Source-to-Drain Voltage (V)
0.1
1
10
100
1000
ISD , Reverse Drain Current (Α)
VGS = 0V
TJ = 150°C
TJ = 25°C
1 10 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 150°C
Single Pulse
1msec
10msec
100µsec
IRF7832
www.irf.com 5
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10. Threshold Voltage Vs. Temperature
25 50 75 100 125 150
TC , Case Temperature (°C)
0
4
8
12
16
20
24
ID, Drain Current (A)
1E-006 1E-005 0.0001 0.001 0.01 0.1 110 100
t1 , Rectangular Pulse Duration (sec)
0.01
0.1
1
10
100
Thermal Response ( Z thJA )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
-60 -40 -20 020 40 60 80 100 120 140 160
TJ , Temperature (°C)
0.5
1.0
1.5
2.0
2.5
VGS(th), Gate Threshold Voltage (V)
ID = 250µA
IRF7832
6www.irf.com
Fig 13. Maximum Avalanche Energy
vs. Drain Current
25 50 75 100 125 150
Starting TJ , Junction Temperature (°C)
0
100
200
300
400
500
600
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 7.0A
13A
BOTTOM 16A
Fig 16. Switching Time Test Circuit Fig 17. Switching Time Waveforms
Fig 12. On-Resistance vs. Gate Voltage
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 15. Gate Charge Test Circuit
Fig 14. Unclamped Inductive Test Circuit
and Waveform
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
VDD
VDS
LD
D.U.T
+
-
VGS
VDS
90%
10%
td(on) td(off)
trtf
2345678910
VGS, Gate -to -Source Voltage (V)
0
2
4
6
8
10
RDS(on), Drain-to -Source On Resistance (mΩ)
ID = 20A
TJ = 125°C
TJ = 25°C
IRF7832
www.irf.com 7
Fig 18. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P. W .
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Fig 19. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
IRF7832
8www.irf.com
Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
P
loss =Irms
2×Rds(on )
()
+I×Qgd
ig
×Vin ×f
⎛
⎝
⎜ ⎞
⎠
⎟ +I×Qgs 2
ig
×V
in ×f
⎛
⎝
⎜ ⎞
⎠
⎟
+Qg×Vg×f
()
+Qoss
2×Vin ×f
⎛
⎝ ⎞
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
Synchronous FET
The power loss equation for Q2 is approximated
by;
P
loss =P
conduction +P
drive +P
output
*
P
loss =Irms
2×Rds(on)()
+Qg×Vg×f
()
+Qoss
2×Vin ×f
⎛
⎝
⎜ ⎞
⎠ +Qrr ×Vin ×f
(
)
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Power MOSFET Selection for Non-Isolated DC/DC Converters
Figure A: Qoss Characteristic
IRF7832
www.irf.com 9
SO-8 Package Details
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IRF7832
10 www.irf.com
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Starting TJ = 25°C, L = 2.0mH, RG = 25Ω, IAS = 16A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
When mounted on 1 inch square copper board.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.06/05
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
FEED DIRECTION
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
SO-8 Tape and Reel