TIBPAL22VP10-20C, TIBPAL22VP10-25M
HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS013 – D2943, FEBRUAR Y 1987 – REVISED JUNE 1991
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1991, Texas Instruments Incorporated
1
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of T exas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
•Functionally Equivalent to the
TIBPAL22V10/10A, with Additional
Feedback Paths in the Output Logic
Macrocell
•Choice of Operating Speeds:
TIBPAL22VP10-20C . . . 20 ns Max
TIBPAL22VP10-25M . . . 25 ns Max
•Variable Product Term Distribution
Allows More Complex Functions to Be
Implemented
•Each Output Is User Programmable for
Registered or Combinational Operation,
Polarity, and Output Enable Control
•TTL-Level Preload for Improved Testability
•Extra Terms Provide Logical Synchronous
Set and Asynchronous Reset Capability
•Fast Programming, High Programming
Yield, and Unsurpassed Reliability Ensured
Using Ti-W Fuses
•AC and DC Testing Done at the Factory
Utilizing Special Designed-In Test Features
•Dependable Texas Instruments Quality and
Reliability
•Package Options Include Plastic
Dual-In-Line and Chip Carrier Packages
description
The TIBPAL22VP10’ is equivalent to the
TIBPAL22V10A but offers additional flexibility in
the output structure. The improved output
macrocell uses the registered outputs as inputs
when in a high-impedance condition. This
provides two additional output configurations for a
total of six possible macrocell configurations all of
which are shown in Figure 1.
These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and
programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered
and inverting or noninverting. In addition, the data may be fed back into the array from either the register or the
I/O port. The ten potential outputs are enabled through the use of individual product terms.
Further advantages can be seen in the introduction of variable product term distribution. This technique
allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This
variable allocation of terms allows far more complex functions to be implemented than in previously available
devices.
These devices are covered by U.S. Patent 4,410,987.
IMPACT-X is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/I
I
I
I
I
I
I
I
I
I
I
GND
VCC
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
3212827
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
I
I
I
NC
I
I
I
426
14 15 16 1718
I
I
GND
NC
I
I/O/Q
I/O/Q
I
I
CLK/I
NC
I/O/Q
I/O/Q
NC –No internal connection
Pin assignments in operating mode
VCC
C SUFFIX . . . NT PACKAGE
M SUFFIX . . . JT PACKAGE
(TOP VIEW)
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
TIBPAL22VP10-20C, TIBPAL22VP10-25M
HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS013 – D2943, FEBRUAR Y 1987 – REVISED JUNE 1991
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
description (continued)
Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These
functions are common to all registers. When the synchronous set product term is a logic 1, the output registers
are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product term
is a logic 1, the output registers are loaded with a logic 0. The output logic level after set or reset depends on
the polarity selected during programming. Output registers can be preloaded to any desired state during testing.
Preloading permits full logical verification during product testing.
With features such as programmable output logic macrocells and variable product term distribution, the
TIBPAL22VP10’ of fers quick design and development of custom LSI functions with complexities of 500 to 800
equivalent gates. Since each of the ten output pins may be individually configured as inputs on either a
temporary or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and
10 outputs are possible.
A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is
applied to the device. Registered outputs selected as active-low power-up with their outputs high. Registered
outputs selected as active-high power-up with their outputs low.
A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once
blown, the verification circuitry is disabled and all other fuses will appear to be open.
The TIBPAL22V10-20C is characterized for operation from 0°C to 75°C. The TIBPAL22V10-25M is
characterized for operation over the full military temperature range of –55°C to 125°C.
TIBPAL22VP10-20C, TIBPAL22VP10-25M
HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS013 – D2943, FEBRUAR Y 1987 – REVISED JUNE 1991
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
functional block diagram (positive logic)
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
10
12
14
EN
16
16
14
12
10
22
22
1
10
&
44 x 132
I/O/Q
I/O/Q
I/O/Q
I/O/Q
EN
EN
EN
EN
EN
EN
EN
EN
EN
10
10
8
8
10
11
CLK/I
I
Set
Reset 1S
R
C1
Output
Logic
Macrocell
denotes fused inputs
TIBPAL22VP10-20C, TIBPAL22VP10-25M
HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS013 – D2943, FEBRUAR Y 1987 – REVISED JUNE 1991
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
0 4 8 1216202428
Increments
First
Fuse
Numbers
32 36 40
Macro-
cell
R = 5809
P = 5808
R = 581 1
P = 5810
R = 5813
P = 5812
R = 5815
P = 5814
R = 5817
P = 5816
logic symbol (positive logic)
Asynchronous Reset
23
22
21
20
19
1
2
3
4
5
(to all registers)
396
0
440
880
924
1452
1496
2112
2156
2860
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I
I
I
CLK/I
Macro-
cell
Macro-
cell
Macro-
cell
Macro-
cell
TIBPAL22VP10-20C, TIBPAL22VP10-25M
HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS013 – D2943, FEBRUAR Y 1987 – REVISED JUNE 1991
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5
Fuse number = First fuse number + Increment
R = 5819
P = 5818
R = 5821
P = 5820
R = 5823
P = 5822
R = 5825
P = 5824
R = 5827
P = 5826
18
6
7
8
9
10
11
17
16
15
14
Synchronous Set
13 (to all registers)
Inside each MACROCELL the ”P” fuse is the polarity fuse and the ”R” fuse is the register fuse.
2904
3608
3652
4268
4312
4840
4884
5324
5368
5720
5764
I
I
I
I
I
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
Macro-
cell
Macro-
cell
Macro-
cell
Macro-
cell
Macro-
cell
TIBPAL22VP10-20C, TIBPAL22VP10-25M
HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS013 – D2943, FEBRUAR Y 1987 – REVISED JUNE 1991
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
output logic macrocell diagram
C1
G0
3
0
1
1
0
3
2MUX
I = 0
1S
1D
R
MUX
1/2/3
SS
AR
From Clock Buffer
S1
S0
AR = asynchronous reset
SS = synchronous set
Output Logic Macrocell
G0
3
0
1
S2†
†This fuse is unique to the Texas Instruments TIBPAL22VP10’. It allows feedback from the I/O port using registered outputs as shown in the
macrocell fusing logic function table.
TIBPAL22VP10-20C, TIBPAL22VP10-25M
HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS013 – D2943, FEBRUAR Y 1987 – REVISED JUNE 1991
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7
C1
1S
1D
R
C1
1S
1D
R
S2 = 0
S1 = 0
S0 = 0
S2 = 0
S1 = 0
S0 = 1
REGISTER FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT REGISTER FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT
C1
1S
1D
R
C1
1S
1D
R
S2 = 1
S1 = 0
S0 = 0
S2 = 1
S1 = 0
S0 = 1
I/O FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT†I/O FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT†
S2 = X
S1 = 1
S0 = 0
S2 = X
S1 = 1
S0 = 1
I/O FEEDBACK, COMBINATIONAL, ACTIVE-LOW OUTPUT I/O FEEDBACK, COMBINATIONAL, ACTIVE-HIGH OUTPUT
†These configurations are unique to the TIBP AL22VP10’ and provide added flexibility when comparing it to the TIBP AL22V10 or TIBP AL22V10A.
Figure 1. Resultant Macrocell Feedback and Output Logic After Programming
FEEDBACK AND OUTPUT CONFIGURATION
tsu Setup time before clock↑
ns
ns
Pulse durationtw
UNIT
TIBPAL22VP10-20C, TIBPAL22VP10-25M
HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS013 – D2943, FEBRUAR Y 1987 – REVISED JUNE 1991
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE
FUSE SELECT
S2 S1 S0
0 0 0 Register feedback Registered Active low
00 1 Register feedback Registered Active high
10 0 I/O feedback Registered Active low
10 1 I/O feedback Registered Active high
X1 0 I/O feedback Combinational Active low
X 1 1 I/O feedback Combinational Active high
0 = unblown fuse, 1 = blown fuse, X = unblown or blown fuse
S2, S1 and S0 are select-function fuses as shown in the output logic macrocell diagram.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range: TIBPAL22VP10-20C 0°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIBPAL22VP10-25M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
TIBPAL22VP10-20C TIBPAL22VP10-25M
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.75 5 5.25 4.5 5 5.5 V
VIH High-level input voltage 2 5.5 2 5.5 V
VIL Low-level input voltage 0.8 0.8 V
IOH High-level output current –3.2 –2 mA
IOL Low-level output current 16 12 mA
fclock Clock frequency†37 25 MHz
Clock high or low 10 20
Asynchronous Reset high or low 20 30
Input 15 20
Feedback 15 20
Synchronous Preset (active) 15 20
Asynchronous Reset (inactive) 20 25
thHold time, input, preset, or feedback after clock↑0 0 ns
TAOperating free-air temperature 0 75 –55 125 °C
†fclock (with feedback)
+
1
tsu
)
tpd (CLK to Q), fclock without feedback can be calculated as
fclock (without feedback)
+
1
twhigh
)
twlow.
IOZL µA
VCC = 5.25 V, VO = 0.4 V
TIBPAL22VP10-20C
HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS013 – D2943, FEBRUAR Y 1987 – REVISED JUNE 1991
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.75 V, II = –18 mA –1.2 V
VOH VCC = 4.75 V, IOH = –3.2 mA 2.4 3.5 V
VOL VCC = 4.75 V, IOL = 16 mA 0.35 0.5 V
IOZH VCC = 5.25 V, VO = 2.7 V 0.1 mA
Any output –100
Any I/O –250
IIVCC = 5.25 V, VI = 5.5 V 1 mA
IIH VCC = 5.25 V, VI = 2.7 V 25 µA
IIL VCC = 5.25 V, VI = 0.4 V –0.25 mA
IOS‡VCC = 5.25 V, VO = 0.5 V –30 –90 mA
ICC VCC = 5.25 V, VI = GND, Outputs open 140 180 mA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITION MIN TYP†MAX UNIT
fmax§37 50 MHz
tpd I, I/O I/O CL = 50 pF, 12 20 ns
tpd I, I/O (reset) QR1 = 300 Ω, 12 20 ns
tpd CLK Q R2 = 390 Ω, 8 12 ns
ten I, I/O I/O, Q See Figure 4 12 20 ns
tdis I, I/O I/O, Q 12 20 ns
†All typical values are at VCC = 5 V, TA = 25°C.
‡Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
§fmax (with feedback)
+
1
tsu
)
tpd (CLK to Q), fmax without feedback can be calculated as
fmax (without feedback)
+
1
twhigh
)
twlow.
TIBPAL22VP10-25M
HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS013 – D2943, FEBRUAR Y 1987 – REVISED JUNE 1991
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.5 V, II = –18 mA –1.2 V
VOH VCC = 4.5 V, IOH = –2 mA 2.4 3.5 V
VOL VCC = 4.5 V, IOL = 12 mA 0.25 0.5 V
IOZH VCC = 5.5 V, VO = 2.7 V 0.1 mA
IOZL VCC = 5.5 V, VO = 0.4 V –0.1 mA
IIVCC = 5.5 V, VI = 5.5 V 1 mA
IIH VCC = 5.5 V, VI = 2.7 V 25 µA
IIL VCC = 5.5 V, VI = 0.4 V –0.25 mA
IOS‡VCC = 5.5 V, VO = 0.5 V –30 –90 mA
ICC VCC = 5.5 V, VI = GND, Outputs open 140 200 mA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITION MIN TYP†MAX UNIT
fmax§25 50 MHz
tpd I, I/O I/O CL = 50 pF, 12 25 ns
tpd I, I/O (reset) QR1 = 390 Ω, 12 25 ns
tpd CLK Q R2 = 750 Ω, 8 15 ns
ten I, I/O I/O, Q See Figure 4 12 25 ns
tdis I, I/O I/O, Q 12 25 ns
†All typical values are at VCC = 5 V, TA = 25°C.
‡Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
§fmax (with feedback)
+
1
tsu
)
tpd (CLK to Q), fmax without feedback can be calculated as
fmax (without feedback)
+
1
twhigh
)
twlow.
TIBPAL22VP10-20C, TIBPAL22VP10-25M
HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS013 – D2943, FEBRUAR Y 1987 – REVISED JUNE 1991
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11
preload procedure for registered outputs (see Notes 2 and 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below:
Step 1. With VCC at 5 V and pin 1 at VIL, raise pin 13 to VIHH.
Step 2. Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Step 3. Pulse pin 1, clocking in preload data.
Step 4. Remove output voltage, then lower pin 13 to VIL. Preload can be verified by observing the voltage level
at the output pin.
tdtsu twtd
VIHH
VIL
VIL
VOL
VOH
VIH
Pin 13
Pin 1
Registered I/O Input Output
VIH
VIL
Figure 2. Preload Waveforms
NOTES: 2. Pin numbers shown are for JT and NT packages only. If chip-carrier socket adapter is not used, pin numbers must be changed
accordingly.
3. td = tsu = tw = 100 ns to 1000 ns. VIHH = 10.25 V to 10.75 V.
TIBPAL22VP10-20C, TIBPAL22VP10-25M
HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS013 – D2943, FEBRUAR Y 1987 – REVISED JUNE 1991
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12
power-up reset
Following power up, all registers are reset to zero. The output level depends on the polarity selected during
programming. This feature provides extra flexibility to the system designer and is especially valuable in
simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of VCC be
monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and
feedback setup times are met.
1.5 V
tsu ‡
tpd †
tw
VOL
VOH
VIL
VIH
5 V
VCC
Active High
Registered Output
Active Low
Registered Output
CLK
4 V
VOH
VOL
1.5 V
1.5 V
(600 ns typ, 1000 ns MAX)
State Unknown
1.5 V
State Unknown
†This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
‡This is the setup time for input or feedback.
Figure 3. Power-Up Reset Waveforms
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
When the additional fuses are not being used, the TIBPAL22VP10 can be programmed using the
TIBP AL22V10/10A programming algorithm. The fuse configuration data can either be from a JEDEC file (format
per JEDEC Standard No. 3-A) or a TIBPAL22V10/10A master.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
TIBPAL22VP10-20C, TIBPAL22VP10-25M
HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS013 – D2943, FEBRUAR Y 1987 – REVISED JUNE 1991
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13
PARAMETER MEASUREMENT INFORMATION
tsu
S1
R2
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
(3.5 V) [3 V]
(0.3 V) [0]
1.5 V
1.5 V
th
1.5 V
tpd
tpd
tpd
tpd
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOH
VOH
VOL
VOL
1.5 V 1.5 V
1.5 V 1.5 V
tw
1.5 V 1.5 V
≈ 3.3 V
VOL
VOH
VOH –0.5 V
≈ 0 V
ten
ten
tdis
tdis
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
R1
VOL +0.5 V
5 V
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
From Output
Under Test Test
Point
Input
Out-of-Phase
Output
(see Note D)
Timing
Input
Data
Input
In-Phase
Output
High-Level
Pulse
Low-Level
Pulse
Output
Control
(low–level
enabling)
W aveform 1
S1 Closed
(see Note B)
W aveform 2
S1 Open
(see Note B)
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: For C suffix, use the voltage levels indicated in parentheses ( ). PRR ≤ 1 MHz,
tr = tf ≤ 2 ns, duty cycle = 50%. For M suffix, use the voltage levels indicated in brackets [ ]. PRR ≤ 10 MHz, tr and tf ≤ 2 ns,
duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 4. Load Circuit and Voltage Waveforms
B0892
1992 Texas Instruments Incorporated
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1992 Texas Instruments Incorporated
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624-9781; Marshall (916) 635-9700; Wyle (916) 638-5282;
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(303) 799-0258; Hall-Mark (303) 790-1662; Marshall (303)
451-8383; Wyle (303) 457-9953.
CONNECTICUT: Anthem (203) 575-1575; Arrow/Schweber
(203) 265-7741; Hall-Mark (203) 271-2844; Marshall (203)
265-3822.
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429-8200; Halll-Mark (305) 971-9280; Marshall (305)
977-4880.
Orlando: Arrow/Schweber (407) 333-9300; Hall-Mark (407)
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Tampa: Hall-Mark (813) 541-7440; Marshall (813)
573-1399.
GEORGIA: Arrow/Schweber (404) 497-1300; Hall-Mark
(404) 623-4400; Marshall (404) 923-5750.
ILLINOIS: Anthem (708) 884-0200; Arrow/Schweber (708)
250-0500; Hall-Mark (312) 860-3800; Marshall (708)
490-0155; Newark (312)784-5100.
INDIANA: Arrow/Schweber (317) 299-2071; Hall-Mark
(317) 872-8875; Marshall (317) 297-0483.
IOWA: Arrow/Schweber (319) 395-7230.
KANSAS: Arrow/Schweber (913) 541-9542; Hall-Mark
(913) 888-4747; Marshall (913) 492-3121.
MARYLAND: Anthem (301) 995-6640; Arrow/Schweber
(301) 596-7800; Hall-Mark (301) 988-9800; Marshall (301)
622-1118; Zeus (301) 997-1118.
MASSACHUSETTS: Anthem (508) 657-5170;
Arrow/Schweber (508) 658-0900; Hall-Mark (508)
667-0902; Marshall (508) 658-0810; Wyle (617) 272-7300;
Zeus (617) 246-8200.
MICHIGAN: Detroit: Arrow/Schweber (313) 462-2290;
Hall-Mark (313) 416-5800; Marshall (313) 525-5850;
Newark (313) 967-0600.
MINNESOTA: Anthem (612) 944-5454; Arrow/Schweber
(612) 941-5280; Hall-Mark (612) 881-2600; Marshall (612)
559-2211.
MISSOURI: Arrow/Schweber (314) 567-6888; Hall-Mark
(314) 291-5350; Marshall (314) 291-4650.
NEW JERSEY: Anthem (201) 227-7960; Arrow/Schweber
(201) 227-7880, (609) 596-8000; Hall-Mark (201) 515-3000,
(609) 235-1900; Marshall (201) 882-0320, (609) 234-9100.
NEW MEXICO: Alliance (505) 292-3360.
NEW YORK: Long Island: Anthem (516) 864-6600;
Arrow/Schweber (516) 231-1000; Hall-Mark (516)
737-0600; Marshall (516) 273-2424; Zeus (914) 937-7400.
Rochester: Arrow/Schweber (716) 427-0300; Hall-Mark
(716) 425-3300; Marshall (716) 235-7620.
Syracuse: Marshall (607) 785-2345.
NORTH CAROLINA: Arrow/Schweber (919) 876-3132;
Hall-Mark (919) 872-0712; Marshall (919) 878-9882.
OHIO: Cleveland: Arrow/Schweber (216) 248-3990;
Hall-Mark (216) 349-4632; Marshall (216) 248-1788.
Columbus: Hall-Mark (614) 888-3313.
Dayton: Arrow/Schweber (513) 435-5563; Marshall (513)
898-4480; Zeus (513) 293-6162.
OKLAHOMA: Arrow/Schweber (918) 252-7537; Hall-Mark
(918) 254-6110.
OREGON: Almac/Arrow (503) 629-8090; Anthem (503)
643-1114; Marshall (503) 644-5050; Wyle (503) 643-7900.
PENNSYLVANIA: Anthem (215) 443-5150;
Arrow/Schweber (215) 928-1800; GRS (215) 922-7037;
(609) 964-8560; Marshall (412) 788-0441.
TEXAS: Austin: Arrow/Schweber (512) 835-4180;
Hall-Mark (512) 258-8848; Marshall (512) 837-1991; Wyle
(512) 345-8853;
Dallas: Anthem (214) 238-7100; Arrow/Schweber (214)
380-6464; Hall-Mark (214) 553-4300; Marshall (214)
233-5200; Wyle (214) 235-9953; Zeus (214) 783-7010;
Houston: Arrow/Schweber (713) 530-4700; Hall-Mark
(713) 781-6100; Marshall (713) 467-1666; Wyle (713)
879-9953.
UTAH: Anthem (801) 973-8555; Arrow/Schweber (801)
973-6913; Marshall (801) 973-2288; Wyle (801) 974-9953.
WASHINGTON: Almac/Arrow (206) 643-9992, Anthem
(206) 483-1700; Marshall (206) 486-5747; Wyle (206)
881-1150.
WISCONSIN: Arrow/Schweber (414) 792-0150; Hall-Mark
(414) 797-7844; Marshall (414) 797-8400.
CANADA: Calgary: Future (403) 235-5325;
Edmonton: Future (403) 438-2858;
Montreal: Arrow/Schweber (514) 421-7411; Future (514)
694-7710; Marshall (514) 694-8142
Ottawa: Arrow/Schweber (613) 226-6903; Future (613)
820-8313.
Quebec: Future (418) 897-6666.
Toronto: Arrow/Schweber (416) 670-7769;
Future (416) 612-9200; Marshall (416) 458-8046.
Vancouver: Arrow/Schweber (604) 421-2333;
Future (604) 294-1166.
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Copyright 1998, Texas Instruments Incorporated
