Octal, 12-Bit, 40/50/65 MSPS
Serial LVDS 1.8 V A/D Converter
AD9222
Rev. C
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006–2010 Analog Devices, Inc. All rights reserved.
FEATURES
8 ADCs integrated into 1 package
114 mW ADC power per channel at 65 MSPS
SNR = 70 dB (to Nyquist)
ENOB = 11.3 bits
SFDR = 80 dBc
Excellent linearity: DNL = ±0.3 LSB (typical),
INL = ±0.4 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar IEEE 1596.3)
Data and frame clock outputs
325 MHz full-power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9222 is an octal, 12-bit, 40/50/65 MSPS analog-to-
digital converter (ADC) with an on-chip sample-and-hold
circuit designed for low cost, low power, small size, and ease of
use. The product operates at a conversion rate of up to 65 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. A data clock output (DCO)
for capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
FUNCTIONAL BLOCK DIAGRAM
SERIAL
LVDS
REF
SELECT
AD9222
AGND
VIN – A
VIN + A
VIN – B
VIN + B
VIN – D
VIN + D
VIN – C
VIN + C
SENSE
VREF
A
V
DD DR
V
DD
12
12
12
12
PD
W
N
REFT
REFB
D – A
D + A
D – B
D + B
D – D
D + D
D – C
D + C
FCO –
FCO +
DCO +
DCO –
CLK+
DR
G
ND
CLK–
SERIAL PORT
INTERFACE
CSB SCLK/
DTP
SDIO/
ODM
RBIAS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
ADC
ADC
ADC
ADC
DATA RATE
MULTIPLIER
0.5V
SERIAL
LVDS
VIN – E
VIN + E
VIN – F
VIN + F
VIN – H
VIN + H
VIN – G
V
IN + G
12
12
12
12
D – E
D + E
D – F
D + F
D – H
D + H
D – G
D + G
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
ADC
ADC
ADC
ADC
05967-001
Figure 1.
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI).
The AD9222 is available in an RoHS compliant, 64-lead LFCSP. It is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Small Footprint. Eight ADCs are contained in a small,
space-saving package.
2. Low power of 114 mW/channel at 65 MSPS.
3. Ease of Use. A data clock output (DCO) is provided that
operates at frequencies of up to 390 MHz and supports
double data rate (DDR) operation.
4. User Flexibility. The SPI control offers a wide range of
flexible features to meet specific system requirements.
5. Pin-Compatible Family. This includes the AD9212 (10-bit)
and AD9252 (14-bit).
AD9222
Rev. C | Page 2 of 60
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Specifications .......................................................................... 4
Digital Specifications ................................................................... 5
Switching Specifications .............................................................. 6
Timing Diagrams .............................................................................. 7
Absolute Maximum Ratings ............................................................ 9
Thermal Impedance ..................................................................... 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Equivalent Circuits ......................................................................... 12
Typical Performance Characteristics ........................................... 14
Theory of Operation ...................................................................... 21
Analog Input Considerations ................................................... 21
Clock Input Considerations ...................................................... 24
Serial Port Interface (SPI) .............................................................. 33
Hardware Interface ..................................................................... 34
Memory Map .................................................................................. 36
Reading the Memory Map Table .............................................. 36
Reserved Locations .................................................................... 36
Default Values ............................................................................. 36
Logic Levels ................................................................................. 36
Evaluation Board ............................................................................ 40
Power Supplies ............................................................................ 40
Input Signals................................................................................ 40
Output Signals ............................................................................ 40
Default Operation and Jumper Selection Settings ................. 41
Alternative Analog Input Drive Configuration...................... 42
Outline Dimensions ....................................................................... 59
Ordering Guide .......................................................................... 60
REVISION HISTORY
1/10—Rev. B to Rev. C
Updated Outline Dimensions ....................................................... 59
Changes to Ordering Guide .......................................................... 60
7/09—Rev. A to Rev. B
Changes to Figure 5 ........................................................................ 10
Changes to Figure 61 and Figure 62 ............................................. 23
Changes to Figure 79 and Figure 80 ............................................. 31
Updated Outline Dimensions ....................................................... 59
Changes to Ordering Guide .......................................................... 59
8/07—Rev. 0 to Rev. A
Added 65 MSPS Models .................................................... Universal
Changes to Features .......................................................................... 1
Changes to Product Highlights ....................................................... 1
Changes to Figure 2 to Figure 4 ...................................................... 7
Added Figure 21 to Figure 24, Figure 27, Figure 28, Figure 30,
Figure 32, Figure 37, Figure 38, Figure 40, Figure 42, Figure 44,
Figure 46, Figure 48, and Figure 51 ............................................. 15
Added Figure 56 and Figure 58..................................................... 22
Added Figure 70 .............................................................................. 25
Added Figure 72 .............................................................................. 26
Added Figure 74 ............................................................................. 27
Added Figure 76 and Figure 78 .................................................... 28
Changes to Digital Outputs and Timing Section ....................... 28
Changes to Table 9 Endnote .......................................................... 29
Added Table 10 ............................................................................... 30
Changes to RBIAS Pin Section ..................................................... 31
Deleted Figure 56 and Figure 57 .................................................. 27
Changes to Table 15 ....................................................................... 35
Change to Input Signals Section ................................................... 40
Change to Output Signals Section ............................................... 40
Changes to Figure 86 ...................................................................... 40
Changes to Default Operation and Jumper Selection
Settings Section ............................................................................... 41
Changes to Alternative Analog Input Configuration Section ......... 42
Added Figure 88 and Figure 89 .................................................... 42
Change to Figure 92 ....................................................................... 45
Changes to Table 17 ....................................................................... 54
Updated Outline Dimensions ....................................................... 59
Changes to Ordering Guide .......................................................... 60
9/06—Revision 0: Initial Version
AD9222
Rev. C | Page 3 of 60
SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 1.
AD9222-40 AD9222-50 AD9222-65
Parameter1
Temp Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION 12 12 12 Bits
ACCURACY
No Missing Codes Full Guaranteed Guaranteed Guaranteed
Offset Error Full ±1 ±8 ±1 ±8 ±1 ±8 mV
Offset Matching Full ±3 ±8 ±3 ±8 ±3 ±8 mV
Gain Error Full ±0.4 ±1.2 ±1.5 ±2.5 ±3.5 ±5 % FS
Gain Matching Full ±0.3 ±0.7 ±0.3 ±0.7 ±0.4 ±0.8 % FS
Differential Nonlinearity (DNL) Full ±0.25 ±0.5 ±0.3 ±0.65 ±0.25 ±0.6 LSB
Integral Nonlinearity (INL) Full ±0.4 ±1 ±0.4 ±1 ±0.4 ±1 LSB
TEMPERATURE DRIFT
Offset Error Full ±2 ±2 ±2 ppm/°C
Gain Error Full ±17 ±17 ±17 ppm/°C
Reference Voltage (1 V Mode) Full ±21 ±21 ±21 ppm/°C
REFERENCE
Output Voltage Error (VREF = 1 V) Full ±2 ±30 ±2 ±30 ±2 ±30 mV
Load Regulation @ 1.0 mA (VREF = 1 V) Full 3 3 3 mV
Input Resistance Full 6 6 6 kΩ
ANALOG INPUTS
Differential Input Voltage Range
(VREF = 1 V)
Full 2 2 2 V p-p
Common-Mode Voltage Full AVDD/2 AVDD/2 AVDD/2 V
Differential Input Capacitance Full 7 7 7 pF
Analog Bandwidth, Full Power Full 325 325 325 MHz
POWER SUPPLY
AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
IAVDD Full 338 348.5 357.5 367.5 450 470 mA
IDRVDD Full 51 53.6 53.5 56.2 56.6 60.5 mA
Total Power Dissipation
(Including Output Drivers)
Full 700 722 740 760 910 950.5 mW
Power-Down Dissipation Full 2 11 2 11 2 11 mW
Standby Dissipation2
Full 83 89 100 mW
CROSSTALK Full −90 −90 −90 dB
CROSSTALK (Overrange Condition)3
Full −90 −90 −90 dB
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 This can be controlled via SPI.
3 Overrange condition is specific with 6 dB of the full-scale input range.
AD9222
Rev. C | Page 4 of 60
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 2.
AD9222-40 AD9222-50 AD9222-65
Parameter1
Temp Min Typ Max Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz Full 70.3 70.4 70.3 dB
fIN = 19.7 MHz Full 69.5 70.3 69.5 70.3 68.5 70.0 dB
fIN = 35 MHz Full 69.9 70.0 69.8 dB
fIN = 70 MHz Full 68.8 69.0 69.5 dB
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
fIN = 2.4 MHz Full 70.0 70.0 69.5 dB
fIN = 19.7 MHz Full 68.7 70.0 68.5 70.0 66.8 69.4 dB
fIN = 35 MHz Full 69.5 69.8 69.3 dB
fIN = 70 MHz Full 68.0 68.5 69 dB
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz Full 11.38 11.4 11.4 Bits
fIN = 19.7 MHz Full 11.25 11.38 11.25 11.38 11.1 11.34 Bits
fIN = 35 MHz Full 11.32 11.33 11.30 Bits
fIN = 70 MHz Full 11.14 11.17 11.25 Bits
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz Full 85 85 83 dBc
fIN = 19.7 MHz Full 73 85 73 84 70.5 80 dBc
fIN = 35 MHz Full 80 83 80 dBc
fIN = 70 MHz Full 76 77 75 dBc
WORST HARMONIC (Second or Third)
fIN = 2.4 MHz Full −85 −85 −83 dBc
fIN = 19.7 MHz Full −85 −74 −84 −73 −80 −70.5 dBc
fIN = 35 MHz Full −80 −83 −80 dBc
fIN = 70 MHz Full −76 −77 −75 dBc
WORST OTHER (Excluding Second or Third)
fIN = 2.4 MHz Full −92 −92 −90 dBc
fIN = 19.7 MHz Full −92 −80 −92 −80 −90 −80 dBc
fIN = 35 MHz Full −92 −92 −90 dBc
fIN = 70 MHz Full −90 −90 −85 dBc
TWO-TONE INTERMODULATION DISTORTION (IMD)—
AIN1 AND AIN2 = −7.0 dBFS
fIN1 = 15 MHz, fIN2 = 16 MHz 25°C 80.0 80.0 80.0 dBc
fIN1 = 70 MHz, fIN2 = 71 MHz 25°C 77.0 77.0 75.0 dBc
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
AD9222
Rev. C | Page 5 of 60
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3.
AD9222-40 AD9222-50 AD9222-65
Parameter1
Temp Min Typ Max Min Typ Max Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL
Differential Input Voltage2
Full 250 250 250 mV p-p
Input Common-Mode Voltage Full 1.2 1.2 1.2 V
Input Resistance (Differential) 25°C 20 20 20 kΩ
Input Capacitance 25°C 1.5 1.5 1.5 pF
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage Full 1.2 3.6 1.2 3.6 1.2 3.6 V
Logic 0 Voltage Full 0 0.3 0.3 0.3 V
Input Resistance 25°C 30 30 30 kΩ
Input Capacitance 25°C 0.5 0.5 0.5 pF
LOGIC INPUT (CSB)
Logic 1 Voltage Full 1.2 3.6 1.2 3.6 1.2 3.6 V
Logic 0 Voltage Full 0 0.3 0.3 0.3 V
Input Resistance 25°C 70 70 70 kΩ
Input Capacitance 25°C 0.5 0.5 0.5 pF
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage Full 1.2 DRVDD + 0.3 1.2 DRVDD + 0.3 1.2 DRVDD + 0.3 V
Logic 0 Voltage Full 0 0.3 0 0.3 0 0.3 V
Input Resistance 25°C 30 30 30 kΩ
Input Capacitance 25°C 2 2 2 pF
LOGIC OUTPUT (SDIO/ODM)3
Logic 1 Voltage (IOH = 800 μA) Full 1.79 1.79 1.79 V
Logic 0 Voltage (IOL = 50 μA) Full 0.05 0.05 0.05 V
DIGITAL OUTPUTS (D + x, D − x),
(ANSI-644)1
Logic Compliance LVDS LVDS LVDS
Differential Output Voltage (VOD) Full 247 454 247 454 247 454 mV
Output Offset Voltage (VOS) Full 1.125 1.375 1.125 1.375 1.125 1.375 V
Output Coding (Default) Offset binary Offset binary Offset binary
DIGITAL OUTPUTS (D + x, D − x),
(Low Power, Reduced Signal
Option)1
Logic Compliance LVDS LVDS LVDS
Differential Output Voltage (VOD) Full 150 250 150 250 150 250 mV
Output Offset Voltage (VOS) Full 1.10 1.30 1.10 1.30 1.10 1.30 V
Output Coding (Default) Offset binary Offset binary Offset binary
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 This is specified for LVDS and LVPECL only.
3 This is specified for 13 SDIO pins sharing the same connection.
AD9222
Rev. C | Page 6 of 60
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
AD9222-40 AD9222-50 AD9222-65
Parameter1Temp Min Typ Max Min Typ Max Min Typ Max Unit
CLOCK2
Maximum Clock Rate Full 40 50 65 MSPS
Minimum Clock Rate Full 10 10 10 MSPS
Clock Pulse Width High (tEH) Full 12.5 10.0 7.5 ns
Clock Pulse Width Low (tEL) Full 12.5 10.0 7.5 ns
OUTPUT PARAMETERS2, 3
Propagation Delay (tPD) Full 1.5 2.3 3.1 1.5 2.3 3.1 1.5 2.3 3.1 ns
Rise Time (tR) (20% to 80%) Full 300 300 300 ps
Fall Time (tF) (20% to 80%) Full 300 300 300 ps
FCO Propagation Delay (tFCO) Full 1.5 2.3 3.1 1.5 2.3 3.1 1.5 2.3 3.1 ns
DCO Propagation Delay (tCPD)4Full tFCO +
(tSAMPLE/24)
tFCO +
(tSAMPLE/24)
tFCO +
(tSAMPLE/24)
ns
DCO to Data Delay (tDATA)4
Full (tSAMPLE/24)
− 300
(tSAMPLE/24) (tSAMPLE/24)
+ 300
(tSAMPLE/24)
− 300
(tSAMPLE/24) (tSAMPLE/24)
+ 300
(tSAMPLE/24)
− 300
(tSAMPLE/24) (tSAMPLE/24)
+ 300
ps
DCO to FCO Delay (tFRAME)4
Full (tSAMPLE/24)
− 300
(tSAMPLE/24) (tSAMPLE/24)
+ 300
(tSAMPLE/24)
− 300
(tSAMPLE/24) (tSAMPLE/24)
+ 300
(tSAMPLE/24)
− 300
(tSAMPLE/24) (tSAMPLE/24)
+ 300
ps
Data to Data Skew
(tDATA-MAX − tDATA-MIN)
Full ±50 ±200 ±50 ±200 ±50 ±200 ps
Wake-Up Time (Standby) 25°C 600 600 600 ns
Wake-Up Time (Power-Down) 25°C 375 375 375 μs
Pipeline Latency Full 8 8 8 CLK
cycles
APERTURE
Aperture Delay (tA) 25°C 750 750 750 ps
Aperture Uncertainty (Jitter) 25°C <1 <1 <1 ps
rms
Out-of-Range Recovery Time 25°C 1 1 1 CLK
cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 This can be adjusted via the SPI interface.
3 Measurements were made using a part soldered to FR4 material.
4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
AD9222
Rev. C | Page 7 of 60
TIMING DIAGRAMS
DCO–
DCO+
D – x
D + x
FCO–
FCO+
CLK–
CLK+
MSB
N – 9
D10
N – 9
D9
N – 9
D8
N – 9
D7
N – 9
D6
N – 9
D5
N – 9
D4
N – 9
D3
N – 9
D2
N – 9
D1
N – 9
D0
N – 9
D10
N – 8
MSB
N – 8
N – 1
N
t
DATA
t
FRAME
t
FCO
t
PD
t
CPD
t
EH
t
A
t
EL
0
5967-002
VIN ± x
Figure 2. 12-Bit Data Serial Stream, MSB First (Default)
DCO+
DCO–
CLK+
FCO+
FCO–
D – x
D + x
CLK–
MSB
N – 9
N – 1
N
D8
N – 9
D7
N – 9
D5
N – 9
t
DATA
t
FRAME
t
FCO
t
PD
D4
N – 9
D6
N – 9
D8
N – 8
D7
N – 8
D5
N – 8
D6
N – 8
D3
N – 9
D1
N – 9
MSB
N – 8
D0
N – 9
D2
N – 9
t
CPD
t
EH
t
A
t
EL
0
5967-003
VIN ± x
Figure 3. 10-Bit Data Serial Stream, MSB First
AD9222
Rev. C | Page 8 of 60
DCO–
DCO+
D – x
D + x
FCO–
FCO+
VIN ± x
CLK–
CLK+
LSB
N – 9
D0
N – 9
D1
N – 9
D2
N – 9
D3
N – 9
D4
N – 9
D5
N – 9
D6
N – 9
D7
N – 9
D8
N – 9
D9
N – 9
D10
N – 9
D0
N – 8
LSB
N – 8
N – 1
t
A
N
t
DATA
t
FRAME
t
FCO
t
PD
t
CPD
t
EH
t
EL
0
5967-004
Figure 4. 12-Bit Data Serial Stream, LSB First
AD9222
Rev. C | Page 9 of 60
ABSOLUTE MAXIMUM RATINGS
Table 5. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
With
Respect To Rating
ELECTRICAL
AVDD AGND −0.3 V to +2.0 V
DRVDD DRGND −0.3 V to +2.0 V
AGND DRGND −0.3 V to +0.3 V
AVDD DRVDD −2.0 V to +2.0 V
Digital Outputs
(D + x, D − x, DCO+,
DCO−, FCO+, FCO−)
DRGND −0.3 V to +2.0 V
CLK+, CLK− AGND −0.3 V to +3.9 V
VIN + x, VIN − x AGND −0.3 V to +2.0 V
SDIO/ODM AGND −0.3 V to +2.0 V
PDWN, SCLK/DTP, CSB AGND −0.3 V to +3.9 V
REFT, REFB, RBIAS AGND −0.3 V to +2.0 V
VREF, SENSE AGND −0.3 V to +2.0 V
ENVIRONMENTAL
Operating Temperature
Range (Ambient)
−40°C to +85°C
Maximum Junction
Temperature
150°C
Lead Temperature
(Soldering, 10 sec)
300°C
Storage Temperature
Range (Ambient)
−65°C to +150°C
THERMAL IMPEDANCE
Table 6.
Air Flow
Velocity (m/s) θJA1 θ
JB θJC
0.0 17.7°C/W
1.0 15.5°C/W 8.7°C/W 0.6°C/W
2.5 13.9°C/W
1 θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad
soldered to PCB.
ESD CAUTION
AD9222
Rev. C | Page 10 of 60
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05967-005
PIN 1
INDICATOR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D – G
D + G
D – F
D + F
D – E
D + E
DCO–
DCO+
FCO–
FCO+
D – D
D + D
D – C
D + C
D – B
D + B
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VIN + F
VIN – F
AVDD
VIN – E
VIN + E
AVDD
REFT
REFB
VREF
SENSE
RBIAS
VIN +
D
VIN – D
AVDD
VIN – C
VIN +
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AVDD
VIN + G
VIN – G
AVDD
VIN – H
VIN + H
AVDD
AVDD
CLK–
CLK+
AVDD
AVDD
DRGND
DRVDD
D – H
D + H
AVDD
VIN + B
VIN – B
AVDD
VIN – A
VIN + A
AVDD
PDWN
CSB
SDIO/ODM
SCLK/DTP
AVDD
DRGND
DRVDD
D + A
D – A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9222
TOP VIEW
(Not to Scale)
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND
Figure 5. 64-Lead LFCSP Pin Configuration, Top View
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
0 AGND Analog Ground (Exposed Paddle)
1, 4, 7, 8, 11,
12, 37, 42, 45,
48, 51, 59, 62
AVDD 1.8 V Analog Supply
13, 36 DRGND Digital Output Driver Ground
14, 35 DRVDD 1.8 V Digital Output Driver Supply
2 VIN + G ADC G Analog Input True
3 VIN − G ADC G Analog Input Complement
5 VIN − H ADC H Analog Input Complement
6 VIN + H ADC H Analog Input True
9 CLK− Input Clock Complement
10 CLK+ Input Clock True
15 D − H ADC H Digital Output Complement
16 D + H ADC H Digital Output True
17 D − G ADC G Digital Output Complement
18 D + G ADC G Digital Output True
19 D − F ADC F Digital Output Complement
20 D + F ADC F Digital Output True
21 D − E ADC E Digital Output Complement
22 D + E ADC E Digital Output True
23 DCO− Data Clock Digital Output Complement
24 DCO+ Data Clock Digital Output True
25 FCO− Frame Clock Digital Output Complement
26 FCO+ Frame Clock Digital Output True
27 D − D ADC D Digital Output Complement
28 D + D ADC D Digital Output True
29 D − C ADC C Digital Output Complement
30 D + C ADC C Digital Output True
31 D − B ADC B Digital Output Complement
32 D + B ADC B Digital Output True
AD9222
Rev. C | Page 11 of 60
Pin No. Mnemonic Description
33 D − A ADC A Digital Output Complement
34 D + A ADC A Digital Output True
38 SCLK/DTP Serial Clock/Digital Test Pattern
39 SDIO/ODM Serial Data Input-Output/Output Driver Mode
40 CSB Chip Select Bar
41 PDWN Power Down
43 VIN + A ADC A Analog Input True
44 VIN − A ADC A Analog Input Complement
46 VIN − B ADC B Analog Input Complement
47 VIN + B ADC B Analog Input True
49 VIN + C ADC C Analog Input True
50 VIN − C ADC C Analog Input Complement
52 VIN − D ADC D Analog Input Complement
53 VIN + D ADC D Analog Input True
54 RBIAS External Resistor to Set the Internal ADC Core Bias Current
55 SENSE Reference Mode Selection
56 VREF Voltage Reference Input/Output
57 REFB Differential Reference (Negative)
58 REFT Differential Reference (Positive)
60 VIN + E ADC E Analog Input True
61 VIN − E ADC E Analog Input Complement
63 VIN − F ADC F Analog Input Complement
64 VIN + F ADC F Analog Input True
AD9222
Rev. C | Page 12 of 60
EQUIVALENT CIRCUITS
V
IN ± x
05967-006
Figure 6. Equivalent Analog Input Circuit
10
10k
10k
CLK–
10
1.25V
C
LK+
05967-007
Figure 7. Equivalent Clock Input Circuit
S
DIO/ODM
350
30k
05967-008
Figure 8. Equivalent SDIO/ODM Input Circuit
DR
V
DD
DRGND
D– D+
V
V
V
V
0
5967-009
Figure 9. Equivalent Digital Output Circuit
SCLK/DTP AND PDWN
30k
1k
05967-010
Figure 10. Equivalent SCLK/DTP and PDWN Input Circuit
100
RBIAS
05967-011
Figure 11. Equivalent RBIAS Circuit
AD9222
Rev. C | Page 13 of 60
CSB
70k1k
A
V
DD
05967-012
Figure 12. Equivalent CSB Input Circuit
SENSE
1k
05967-013
Figure 13. Equivalent SENSE Circuit
VREF
6k
0
5967-014
Figure 14. Equivalent VREF Circuit
AD9222
Rev. C | Page 14 of 60
TYPICAL PERFORMANCE CHARACTERISTICS
05967-015
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–120
0
020
–100
–80
–60
–40
–20
24681012141618
AIN = –0.5dBFS
SNR = 70.79dB
ENOB = 11.47 BITS
SFDR = 84.71dBc
Figure 15. Single-Tone 32k FFT with fIN = 2.3 MHz, AD9222-40
05967-016
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–120
0
020
–100
–80
–60
–40
–20
2 4 6 8 10 12 14 16 18
AIN = –0.5dBFS
SNR = 70.32dB
ENOB = 11.39 BITS
SFDR = 84.28dBc
Figure 16. Single-Tone 32k FFT with fIN = 19.7 MHz, AD9222-40
0
–120
–100
–80
–60
–40
–20
0 5 10 15 20 25
AMPLITUDE (dBFS)
FREQUENCY (MHz)
AIN = –0.5dBFS
SNR = 70.72dB
ENOB = 11.45 BITS
SFDR = 85.79dBc
05967-017
Figure 17. Single-Tone 32k FFT with fIN = 2.3 MHz, AD9222-50
0
–120
–100
–80
–60
–40
–20
0 5 10 15 20 25
AMPLITUDE (dBFS)
FREQUENCY (MHz)
AIN = –0.5dBFS
SNR = 70.35dB
ENOB = 11.40 BITS
SFDR = 83.86dBc
05967-018
Figure 18. Single-Tone 32k FFT with fIN = 35 MHz, AD9222-50
0
–120
–100
–80
–60
–40
–20
0 5 10 15 20 25
AMPLITUDE (dBFS)
FREQUENCY (MHz)
AIN = –0.5dBFS
SNR = 70.02dB
ENOB = 11.45 BITS
SFDR = 86.3dBc
05967-019
Figure 19. Single-Tone 32k FFT with fIN = 70 MHz, AD9222-50
0
–120
–100
–80
–60
–40
–20
0 5 10 15 20 25
AMPLITUDE (dBFS)
FREQUENCY (MHz)
AIN = –0.5dBFS
SNR = 69.25dB
ENOB = 11.21 BITS
SFDR = 72.85dBc
05967-020
Figure 20. Single-Tone 32k FFT with fIN = 120 MHz, AD9222-50
AD9222
Rev. C | Page 15 of 60
0
–120
–100
–80
–60
–40
–20
0 5 10 15 20 25 30
AMPLITUDE (dBFS)
FREQUENCY (MHz)
AIN = –0.5dBFS
SNR = 70.21dB
ENOB = 11.31 BITS
SFDR = 82.37dBc
0
5967-085
Figure 21. Single-Tone 32k FFT with fIN = 2.3 MHz, AD9222-65
0
–120
–100
–80
–60
–40
–20
0 5 10 15 20 25 30
AMPLITUDE (dBFS)
FREQUENCY (MHz)
AIN = –0.5dBFS
SNR = 69.8dB
ENOB = 11.22 BITS
SFDR = 80.61dBc
0
5967-086
Figure 22. Single-Tone 32k FFT with fIN = 35 MHz, AD9222-65
0
–120
–100
–80
–60
–40
–20
0 5 10 15 20 25 30
AMPLITUDE (dBFS)
FREQUENCY (MHz)
AIN = –0.5dBFS
SNR = 69.65dB
ENOB = 11.07 BITS
SFDR = 74.79dBc
05967-087
Figure 23. Single-Tone 32k FFT with fIN = 70 MHz, AD9222-65
0
–120
–100
–80
–60
–40
–20
0 5 10 15 20 25 30
AMPLITUDE (dBFS)
FREQUENCY (MHz)
AIN = –0.5dBFS
SNR = 68.67dB
ENOB = 10.79 BITS
SFDR = 71.49dBc
0
5967-088
Figure 24. Single-Tone 32k FFT with fIN = 120 MHz, AD9222-65
100
90
95
85
80
75
70
65
60
10 5045403530252015
SNR/SFDR (dB)
ENCODE (MSPS)
2V p-p, SFDR
2V p-p, SNR
05967-021
Figure 25. SNR/SFDR vs. fSAMPLE, fIN = 2.61 MHz, AD9222-50
90
85
80
75
70
65
60
10 5045403530252015
SNR/SFDR (dB)
ENCODE (MSPS)
2V p-p, SFDR
2V p-p, SNR
05967-022
Figure 26. SNR/SFDR vs. fSAMPLE, fIN = 20.1 MHz, AD9222-50
AD9222
Rev. C | Page 16 of 60
SNR/SFDR (dB)
ENCODE (MSPS)
60
65
70
75
80
85
90
95
100
10 15 20 25 30 35 40 45 50 55 60 65
2V p-p, SFDR
2V p-p, SNR
05967-089
Figure 27. SNR/SFDR vs. fSAMPLE, fIN = 2.3 MHz, AD9222-65
SNR/SFDR (dB)
ENCODE (MSPS)
60
65
70
75
80
85
90
10 15 20 25 30 35 40 45 50 55 60 65
2V p-p, SFDR
2V p-p, SNR
05967-090
Figure 28. SNR/SFDR vs. fSAMPLE, fIN = 19.7 MHz, AD9222-65
100
90
80
70
60
50
40
30
20
10
0
–60 –50 –40 –30 –20 –10 0
SNR/SFDR (dB)
INPUT AMPLITUDE (dBFS)
80dB
REFERENCE
2V p-p, SFDR
2V p-p, SNR
05967-023
Figure 29. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, AD9222-50
2V p-p, SNR
2V p-p, SFDR
SNR/SFDR (dB)
INPUT AMPLITUDE (dBFS)
0
10
20
30
40
50
60
70
80
90
–60 –50 –40 –30 –20 –10 0
80dB
REFERENCE
LINE
05967-091
Figure 30. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, AD9222-65
100
90
80
70
60
50
40
30
20
10
0
–60 –50 –40 –30 –20 –10 0
SNR/SFDR (dB)
INPUT AMPLITUDE (dBFS)
80dB
REFERENCE
2V p-p, SFDR
2V p-p, SNR
05967-024
Figure 31. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, AD9222-50
2V p-p, SNR
2V p-p, SFDR
SNR/SFDR (dB)
INPUT AMPLITUDE (dBFS)
0
10
20
30
40
50
60
70
80
90
–60 –50 –40 –30 –20 –10 0
80dB
REFERENCE
LINE
0
5967-092
Figure 32. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, AD9222-65
AD9222
Rev. C | Page 17 of 60
0
–120
–100
–80
–60
–40
–20
02468101214161820
AMPLITUDE (dBFS)
FREQUENCY (MHz)
AIN1 AND AIN2 = –7dBFS
SFDR = 89.87dB
IMD2 = 96.07dBc
IMD3 = 90.16dBc
05967-025
Figure 33. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz,
AD9222-40
0
–120
–100
–80
–60
–40
–20
02468101214161820
AMPLITUDE (dBFS)
FREQUENCY (MHz)
AIN1 AND AIN2 = –7dBFS
SFDR = 77.24dB
IMD2 = 91.66dBc
IMD3 = 77.72dBc
05967-026
Figure 34. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz,
AD9222-40
0
–120
–100
–80
–60
–40
–20
0 5 10 15 20 25
AMPLITUDE (dBFS)
FREQUENCY (MHz)
AIN1 AND AIN2 = –7dBFS
SFDR = 84.49dB
IMD2 = 85.83dBc
IMD3 = 84.54dBc
05967-027
Figure 35. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, AD9222-50
0
–120
–100
–80
–60
–40
–20
0 5 10 15 20 25
AMPLITUDE (dBFS)
FREQUENCY (MHz)
AIN1 AND AIN2 = –7dBFS
SFDR = 80.42dB
IMD2 = 83.92dBc
IMD3 = 80.60dBc
05967-032
Figure 36. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz, AD9222-50
0
–120
–100
–80
–60
–40
–20
0 5 10 15 20 25 30
AMPLITUDE (dBFS)
FREQUENCY (MHz)
AIN1 AND AIN2 = –7dBFS
SFDR = 79.5dB
IMD2 = 80.0dBc
IMD3 = 84.1dBc
05967-093
Figure 37. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, AD9222-65
0
–120
–100
–80
–60
–40
–20
0 5 10 15 20 25 30
AMPLITUDE (dBFS)
FREQUENCY (MHz)
AIN1 AND AIN2 = –7dBFS
SFDR = 75.2dB
IMD2 = 79.3dBc
IMD3 = 75.1dBc
0
5967-094
Figure 38. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz, AD9222-65
AD9222
Rev. C | Page 18 of 60
90
85
80
75
70
65
60
1 100010010
SNR/SFDR (dB)
ANALOG INPUT FREQUENCY (MHz)
SFDR
SNR
05967-029
Figure 39. SNR/SFDR vs. fIN, AD9222-50
SNR/SFDR (dB)
FREQUENCY (MHz)
1 10 100 1000
50
55
60
65
70
75
80
85
90
2V p-p, SFDR
2V p-p, SNR
0
5967-095
Figure 40. SNR/SFDR vs. fIN, AD9222-65
100
90
95
85
80
75
70
65
60
–40 –20 0 20 40 60 80
SINAD/SFDR (dB)
TEMPERATURE (°C)
2V p-p, SFDR
2V p-p, SINAD
05967-030
Figure 41. SINAD/SFDR vs. Temperature, fIN = 2.61 MHz, AD9222-50
90
85
80
75
70
65
60
–40 –20 0 20 40 8060
SINAD/SFDR (dB)
TEMPERATURE (°C)
2V p-p, SFDR
2V p-p, SINAD
05967-096
Figure 42. SINAD/SFDR vs. Temperature, fIN = 2.3 MHz, AD9222-65
90
85
80
75
70
65
60
–40 –20 0 20 40 60 80
SINAD/SFDR (dB)
TEMPERATURE (°C)
2V p-p, SFDR
2V p-p, SINAD
05967-031
Figure 43. SINAD/SFDR vs. Temperature, fIN = 20.1 MHz, AD9222-50
90
85
80
75
70
65
60
–40 –20 0 20 40 8060
SINAD/SFDR (dB)
TEMPERATURE (°C)
2V p-p, SFDR
2V p-p, SINAD
05967-097
Figure 44. SINAD/SFDR vs. Temperature, fIN = 19.7 MHz, AD9222-65
AD9222
Rev. C | Page 19 of 60
05967-036
CODE
INL (LSB)
–1.0
1.0
0
–0.8
–0.6
–0.4
–0.2
0
0.8
0.6
0.4
0.2
500 1000 1500 2000 2500 3000 3500 4000
Figure 45. INL, fIN = 2.3 MHz, AD9222-50
CODE
INL (LSB)
–1.0
1.0
0
–0.8
–0.6
–0.4
–0.2
0
0.8
0.6
0.4
0.2
500 1000 1500 2000 2500 3000 3500 4000
0
5967-098
Figure 46. INL, fIN = 35 MHz, AD9222-65
0.6
0.8
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0 4000350030002500200015001000500
DNL (LSB)
CODE
05967-099
Figure 47. DNL, fIN = 2.3 MHz, AD9222-50
0.6
0.8
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0 4000350030002500200015001000500
DNL (LSB)
CODE
05967-099
Figure 48. DNL, fIN = 35 MHz, AD9222-65
05967-056
FREQUENCY (MHz)
CMRR (dB)
–70
–
30
0 5 10 15 20 25 30 35 40
–65
–60
–55
–50
–45
–40
–35
Figure 49. CMRR vs. Frequency, AD9222-50
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
NN – 1N – 2N – 3 N + 1 N + 2 N + 3
NUMBER OF HITS (Millions)
CODE
0.27 LSB rms
05967-038
Figure 50. Input-Referred Noise Histogram, AD9222-50
AD9222
Rev. C | Page 20 of 60
2.5
0
0.5
1.0
1.5
2.0
NUMBER OF HITS (Millions)
CODE
N N + 1 N + 2 N + 3N – 3N – 2N – 1
0.3 LSB rms
0
5967-100
Figure 51. Input-Referred Noise Histogram, AD9222-65
AMPLITUDE (dBFS)
–120
0
–20
–40
–60
–80
–100
05101520 25
FREQUENCY (MHz)
NPR = 60.3dB
NOTCH = 18.0MHz
NOTCH WIDTH = 3.0MHz
05967-041
Figure 52. Noise Power Ratio (NPR), AD9222-50
0
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0545040035030025020015010050
AMPLITUDE (dBFS)
FREQUENCY (MHz)
00
–3dB BANDWIDTH = 325MHz
05967-040
Figure 53. Full-Power Bandwidth vs. Frequency, AD9222-50
AD9222
Rev. C | Page 21 of 60
THEORY OF OPERATION
The AD9222 architecture consists of a pipelined ADC divided
into three sections: a 4-bit first stage followed by eight 1.5-bit
stages and a final 3-bit flash. Each stage provides sufficient
overlap to correct for flash errors in the preceding stage.
The quantized outputs from each stage are combined into a
final 12-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate with a new input
sample while the remaining stages operate with preceding samples.
Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The data is then serialized
and aligned to the frame and data clocks.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9222 is a differential switched-capacitor
circuit designed for processing differential input signals. This
circuit can support a wide common-mode range while maintaining
excellent performance. An input common-mode voltage of
midsupply minimizes signal-dependent errors and provides
optimum performance.
SS
H
CPAR
CSAMPLE
CSAMPLE
CPAR
VIN – x
H
SS
H
VIN + x
H
0
5967-043
Figure 54. Switched-Capacitor Input Circuit
The clock signal alternately switches the input circuit between
sample mode and hold mode (see Figure 54). When the input
circuit is switched into sample mode, the signal source must be
capable of charging the sample capacitors and settling within
one-half of a clock cycle. A small resistor in series with each
input can help reduce the peak transient current injected from
the output stage of the driving source. In addition, low-Q inductors
or ferrite beads can be placed on each leg of the input to reduce
high differential capacitance at the analog inputs and therefore
achieve the maximum bandwidth of the ADC. Such use of low-
Q inductors or ferrite beads is required when driving the converter
front end at high IF frequencies. Either a shunt capacitor or two
single-ended capacitors can be placed on the inputs to provide a
matching passive network. This ultimately creates a low-pass
filter at the input to limit unwanted broadband noise. See the
AN-742 Application Note, the AN-827 Application Note, and the
Analog Dialogue article “Transformer-Coupled Front-End for
Wideband A/D Converters” (Volume 39, April 2005) for more
information. In general, the precise values depend on the
application.
The analog inputs of the AD9222 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide
this bias externally. Setting the device so that VCM = AVDD/2 is
recommended for optimum performance, but the device can
function over a wider range with reasonable performance, as
shown in Figure 55 and Figure 57.
AD9222
Rev. C | Page 22 of 60
90
85
80
75
70
65
60
0.2 1.61.41.21.00.80.60.4
SNR/SFDR (dB)
ANALOG INPUT COMMON-MODE VOLTAGE (V)
SFDR (dBc)
SNR (dB)
05967-044
Figure 55. SNR/SFDR vs. Common-Mode Voltage,
fIN = 2.3 MHz, AD9222-50
90
85
80
75
70
65
60
0.201.61.41.21.00.80.60.4
SNR/SFDR (dB)
ANALOG INPUT COMMON-MODE VOLTAGE (V)
SFDR (dBc)
SNR (dB)
05967-101
Figure 56. SNR/SFDR vs. Common-Mode Voltage,
fIN = 2.3 MHz, AD9222-65
90
85
80
75
70
65
60
0.2 1.61.41.21.00.80.60.4
SNR/SFDR (dB)
ANALOG INPUT COMMON-MODE VOLTAGE (V)
SFDR (dBc)
SNR (dB)
05967-042
Figure 57. SNR/SFDR vs. Common-Mode Voltage,
fIN = 35 MHz, AD9222-50
90
85
80
75
70
65
60
0.2011.41.21.00.80.60.4
SNR/SFDR (dB)
ANALOG INPUT COMMON-MODE VOLTAGE (V)
.6
SFDR (dBc)
SNR (dB)
05967-102
Figure 58. SNR/SFDR vs. Common-Mode Voltage,
fIN = 35 MHz, AD9222-65
AD9222
Rev. C | Page 23 of 60
For best dynamic performance, the source impedances driving
VIN + x and VIN − x should be matched such that common-
mode settling errors are symmetrical. These errors are reduced
by the common-mode rejection of the ADC. An internal
reference buffer creates the positive and negative reference
voltages, REFT and REFB, respectively, that define the span of
the ADC core. The output common-mode of the reference buffer
is set to midsupply, and the REFT and REFB voltages and span
are defined as
REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
It can be seen from these equations that the REFT and REFB
voltages are symmetrical about the midsupply voltage and, by
definition, the input span is twice the value of the VREF voltage.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD9222, the largest input span available is 2 V p-p.
Differential Input Configurations
There are several ways to drive the AD9222 either actively or
passively; however, optimum performance is achieved by
driving the analog input differentially. For example, using the
AD8334 differential driver to drive the AD9222 provides
excellent performance and a flexible interface to the ADC (see
Figure 62) for baseband applications. This configuration is
commonly used for medical ultrasound systems.
For applications where SNR is a key parameter, differential
transformer coupling is the recommended input configuration
(see Figure 59 and Figure 60) because the noise performance of
most amplifiers is not adequate to achieve the true performance
of the AD9222.
Regardless of the configuration, the value of the shunt capacitor,
C, is dependent on the input frequency and may need to be
reduced or removed.
2V p-p
R
R
C
DIFF1
C
1
C
DIFF
IS OPTIONAL.
49.9
0.1F
1k
1k
AGND
AVDD
A
DT1–1WT
1:1 Z RATIO
VIN – x
ADC
AD9222
VIN + x
C
05967-046
Figure 59. Differential Transformer-Coupled Configuration
for Baseband Applications
ADC
AD9222
2V p-p
2.2pF 1k
0.1F
1k
1k
AVDD
A
DT1–1WT
1:1 Z RATIO
16nH 16nH
0.1F
16nH
33
33
499
65
VIN + x
VIN – x
05967-047
Figure 60. Differential Transformer-Coupled Configuration for IF Applications
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance degrade due to the large input common-
mode swing. If the application requires a single-ended input
configuration, ensure that the source impedances on each input
are well matched in order to achieve the best possible performance.
A full-scale input of 2 V p-p can still be applied to the ADC’s
VIN + x pin while the VIN − x pin is terminated. Figure 61 details
a typical single-ended input configuration.
2V p-p
R
R
49.90.1µF
0.1µF
AVDD
1k25
1k
1k
1k
A
V
DD
VIN – x
ADC
AD9222
VIN + x
C
DIFF1
C
1
C
DIFF
IS OPTIONAL.
C
05967-048
Figure 61. Single-Ended Input Configuration
05967-049
AD8334
1.0k
1.0k
374
187R
R
C
0.1F
187
0.1
F
0.1F
0.1F
0.1F10F
0.1F
1V p-
p
0.1F
LNA
120nH
VGA
VOH
VIP
INH
22pF
LMD
VIN
LOP
LON
VOL
18nF 274
VIN – x
ADC
AD9222
VIN + x
1k
1k
AVDD
Figure 62. Differential Input Configuration Using the AD8334
AD9222
Rev. C | Page 24 of 60
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9222 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled to the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
and require no additional biasing.
Figure 63 shows a preferred method for clocking the AD9222. The
low jitter clock source is converted from a single-ended signal
to a differential signal using an RF transformer. The back-to-
back Schottky diodes across the secondary transformer limit
clock excursions into the AD9222 to approximately 0.8 V p-p
differential. This helps prevent the large voltage swings of the
clock from feeding through to other portions of the AD9222,
and it preserves the fast rise and fall times of the signal, which
are critical to low jitter performance.
0.1µF
0.1µF
0.1µF0.1µF
SCHOTTKY
DIODES:
HSM2812
CLK+
50100
CLK–
CLK+
ADC
AD9222
MINI-CIRCUITS
®
ADT1-1WT, 1:1Z
XFMR
05967-050
Figure 63. Transformer-Coupled Differential Clock
Another option is to ac-couple a differential PECL signal to the
sample clock input pins as shown in Figure 64. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515 family of clock
drivers offers excellent jitter performance.
CLK+
100
0.1µF
0.1µF
0.1µF
0.1µF
240240
CLK–
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
50
1
50
1
CLK
CLK
1
50 RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9222
05967-051
PECL DRIVER
Figure 64. Differential PECL Sample Clock
CLK+
CLK–
100
0.1µF
0.1µF
0.1µF
0.1µF
501
LVDS DRIVER
501
CLK
CLK
150 RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9222
05967-052
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
Figure 65. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 F capacitor
in parallel with a 39 kΩ resistor (see Figure 66). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages of up to 3.3 V, making the
selection of the drive logic voltage very flexible.
CLK+
0.1µF
0.1µF
0.1µF
39k
CMOS DRIVER
50
1
OPTIONAL
100
0.1µF
CLK
CLK
1
50 RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
AD9222
05967-053
A
D9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
Figure 66. Single-Ended 1.8 V CMOS Sample Clock
CLK+
0.1µF
0.1µF
0.1µF
CMOS DRIVER
50
1
OPTIONAL
100
CLK
CLK
1
50 RESISTOR IS OPTIONAL.
0.1µF
CLK–
CLK+
ADC
AD9222
05967-054
A
D9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
Figure 67. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9222 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9222. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. However,
some applications may require the DCS function to be off. If so,
keep in mind that the dynamic range performance can be affected
when operated in this mode. See the Memory Map section for
more details on using this feature.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
AD9222
Rev. C | Page 25 of 60
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(fA) due only to aperture jitter (tJ) can be calculated by
SNR Degradation = 20 × log 10(1/2 × π × fA × tJ)
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 68).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9222.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs.
1 10 100 1000
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
SNR (dB)
05967-055
Figure 68. Ideal SNR vs. Input Frequency and Jitter
Power Dissipation and Power-Down Mode
As shown in Figure 69, the power dissipated by the AD9222 is
proportional to its sample rate. The digital power dissipation
does not vary much because it is determined primarily by the
DRVDD supply and bias current of the LVDS output drivers.
05967-057
ENCODE (MSPS)
CURRENT (A)
10 50
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
15 20 25 30 35 40 45
0.500
0.550
0.600
0.650
0.700
0.750
0.800
POWER (W)
TOTAL POWER
AVDD CURRENT
DRVDD CURRENT
Figure 69. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, AD9222- 50
ENCODE (MSPS)
CURRENT (mA)
10 6050
20 30 40
700
750
800
850
900
950
POWER (mW)
TOTAL POWER
AVDD CURRENT
DRVDD CURRENT
0
50
100
150
200
250
300
350
400
450
500
0
5967-103
Figure 70. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, AD9222- 65
AD9222
Rev. C | Page 26 of 60
By asserting the PDWN pin high, the AD9222 is placed into
power-down mode. In this state, the ADC typically dissipates
11 mW. During power-down, the LVDS output drivers are placed
in a high impedance state. The AD9222 returns to normal
operating mode when the PDWN pin is pulled low. This pin is
both 1.8 V and 3.3 V tolerant.
In power-down mode, low power dissipation is achieved by
shutting down the reference, reference buffer, PLL, and biasing
networks. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in the power-down
mode; shorter cycles result in proportionally shorter wake-up
times. With the recommended 0.1 µF and 4.7 µF decoupling
capacitors on REFT and REFB, approximately 1 sec is required
to fully discharge the reference buffer decoupling capacitors,
and approximately 375 µs is required to restore full operation.
There are several other power-down options available when
using the SPI. The user can individually power down each
channel or put the entire device into standby mode. The latter
option allows the user to keep the internal PLL powered when
fast wake-up times (~600 ns) are required. See the Memory
Map section for more details on using these features.
Digital Outputs and Timing
The AD9222 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. This can be changed to a low power,
reduced signal option (similar to the IEEE 1596.3 standard) via the
SDIO/ODM pin or SPI. This LVDS standard can further reduce
the overall power dissipation of the device by approximately 36
mW. See the SDIO/ODM Pin section or Table 16 in the
Memory Map section for more information. The LVDS driver
current is derived on chip and sets the output current at each
output equal to a nominal 3.5 mA. A 100 Ω differential termination
resistor placed at the LVDS receiver inputs results in a nominal
350 mV swing at the receiver.
The AD9222 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 Ω termination resistor
placed as close to the receiver as possible. If there is no far-end
receiver termination or there is poor differential trace routing,
timing errors may result. To avoid such timing errors, it is
recommended that the trace length be no longer than 24 inches
and that the differential output traces be kept close together and
at equal lengths. An example of the FCO and data stream with
proper trace length and position is shown in Figure 71.
CH1 500mV/DIV = FCO
CH2 500mV/DIV = DCO
CH3 500mV/DIV = DATA
5.0ns/DIV
05967-058
Figure 71. LVDS Output Timing Example in ANSI-644 Mode (Default),
AD9222-50
CH1 500mV/DIV = FCO
CH2 500mV/DIV = DCO
CH3 500mV/DIV = DATA
5.0ns/DIV
05967-084
Figure 72. LVDS Output Timing Example in ANSI-644 Mode (Default),
AD9222-65
AD9222
Rev. C | Page 27 of 60
An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histogram
with trace lengths less than 24 inches on standard FR-4 material is
shown in Figure 73 and Figure 74. Figure 75 and Figure 76 show
examples of trace lengths exceeding 24 inches on standard FR-4
material. Notice that the TIE jitter histogram reflects the decrease
of the data eye opening as the edge deviates from the ideal position.
It is the user’s responsibility to determine if the waveforms meet
the timing budget of the design when the trace lengths exceed
24 inches. Additional SPI options allow the user to further increase
the internal termination (increasing the current) of all eight outputs
in order to drive longer trace lengths (see Figure 77 and Figure 78).
Even though this produces sharper rise and fall times on the data
edges and is less prone to bit errors, the power dissipation of the
DRVDD supply increases when this option is used.
In cases that require increased driver strength to the DCO± and
FCO± outputs because of load mismatch, Register 0x15 allows
the user to increase the drive strength by 2×. To do this, set the
appropriate bit in Register 0x5. Note that this feature cannot be
used with Bit 4 and Bit 5 in Register 0x15. Bit 4 and Bit 5 take
precedence over this feature. See the Memory Map section for
more details.
500
400
300
200
100
–500
–400
–300
–200
–100
0
–1.0ns–1.5ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns
EYE DIAGRAM VOLTAGE (mV)
EYE: ALL BITS ULS: 12071/12071
90
50
10
20
30
40
60
70
80
0
–150ps –100ps –50ps 0ps 50ps 100ps 150ps
TIE JITTER HISTOGRAM (Hits)
05967-061
Figure 73. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Less than 24 Inches on Standard FR-4, AD9222-50
600
400
200
–600
–400
–200
0
–1.0ns–1.5ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns
EYE DIAGRAM VOLTAGE (mV)
EYE: ALL BITS ULS: 9596/15596
20
40
60
80
100
140
120
0
–150ps –100ps –50ps 0ps 50ps 100ps 150ps
TIE JITTER HISTOGRAM (Hits)
05967-106
Figure 74. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Less than 24 Inches on Standard FR-4, AD9222-65
60
80
90
70
50
40
20
10
100
30
0
–200ps –100ps 100ps0ps 200ps
TIE JITTER HISTOGRAM (Hits)
500
400
300
200
100
–500
–400
–300
–200
–100
0
–1.0ns –0.5ns 0ns 0.5ns 1.5ns–1.5ns 1.0ns
EYE DIAGRAM VOLTAGE (mV)
EYE: ALL BITS ULS: 12067/12067
0
5967-059
Figure 75. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4, AD9222-50
AD9222
Rev. C | Page 28 of 60
500
400
300
200
100
–500
–400
–300
–200
–100
0
–1.0ns–1.5ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns
EYE DIAGRAM VOLTAGE (mV)
EYE: ALL BITS ULS: 7591/15591
20
40
60
80
100
140
120
0
–300ps –200ps –100ps 0ps 100ps 200ps 300ps
TIE JITTER HISTOGRAM (Hits)
05967-105
Figure 76. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4, AD9222-65
400
300
200
100
–400
–300
–200
–100
0
–0.5ns 0ns 0.5ns
EYE DIAGRAM VOLTAGE (mV)
EYE: ALL BITS ULS: 12072/12072
80
50
10
20
30
40
60
70
0
–150ps –100ps –50ps 0ps 50ps 100ps 150ps
TIE JITTER HISTOGRAM (Hits)
–1.0ns 1.5ns–1.5ns 1.0ns
05967-060
Figure 77. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Termination
on and Trace Lengths Greater than 24 Inches on Standard FR-4, AD9222-50
500
400
300
200
100
–500
–400
–300
–200
–100
0
–1.0ns–1.5ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns
EYE DIAGRAM VOLTAGE (mV)
EYE: ALL BITS ULS: 8000/15600
20
40
60
80
100
140
120
0
–200ps –100ps 0ps 100ps 200ps 300ps
TIE JITTER HISTOGRAM (Hits)
05967-104
Figure 78. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Termination
on and Trace Lengths Greater than 24 Inches on Standard FR-4, AD9222-65
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 8.
To change the output data format to twos complement, see the
Memory Map section.
Table 8. Digital Output Coding
Code
(VIN + x) − (VIN − x),
Input Span = 2 V p-p (V)
Digital Output Offset Binary
(D11 ... D0)
4095 +1.00 1111 1111 1111
2048 0.00 1000 0000 0000
2047 −0.000488 0111 1111 1111
0 −1.00 0000 0000 0000
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 12 bits
times the sample clock rate, with a maximum of 780 Mbps
(12 bits × 65 MSPS = 780 Mbps). The lowest typical conversion
rate is 10 MSPS. However, if lower sample rates are required for
a specific application, the PLL can be set up via the SPI to allow
encode rates as low as 5 MSPS. See the Memory Map section to
enable this feature.
AD9222
Rev. C | Page 29 of 60
Two output clocks are provided to assist in capturing data from
the AD9222. The DCO is used to clock the output data and is
equal to six times the sample clock (CLK) rate. Data is clocked
out of the AD9222 and must be captured on the rising and
falling edges of the DCO that supports double data rate (DDR)
capturing. The FCO is used to signal the start of a new output
byte and is equal to the sample clock rate. See the timing
diagram shown in Figure 2 for more information.
Table 9. Flexible Output Test Modes
Output Test Mode
Bit Sequence Pattern Name Digital Output Word 1 Digital Output Word 2
Subject to Data
Format Select
0000 Off (default) N/A N/A N/A
0001 Midscale short
1000 0000 (8-bit)
10 0000 0000 (10-bit)
1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)
Same Yes
0010 +Full-scale short
1111 1111 (8-bit)
11 1111 1111 (10-bit)
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)
Same Yes
0011 −Full-scale short
0000 0000 (8-bit)
00 0000 0000 (10-bit)
0000 0000 0000 (12-bit)
00 0000 0000 0000 (14-bit)
Same Yes
0100 Checkerboard
1010 1010 (8-bit)
10 1010 1010 (10-bit)
1010 1010 1010 (12-bit)
10 1010 1010 1010 (14-bit)
0101 0101 (8-bit)
01 0101 0101 (10-bit)
0101 0101 0101 (12-bit)
01 0101 0101 0101 (14-bit)
No
0101 PN sequence long1N/A N/A Yes
0110 PN sequence short1
N/A N/A Yes
0111 One-/zero-word toggle
1111 1111 (8-bit)
11 1111 1111 (10-bit)
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)
0000 0000 (8-bit)
00 0000 0000 (10-bit)
0000 0000 0000 (12-bit)
00 0000 0000 0000 (14-bit)
No
1000 User input Register 0x19 to Register 0x1A Register 0x1B to Register 0x1C No
1001 1-/0-bit toggle
1010 1010 (8-bit)
10 1010 1010 (10-bit)
1010 1010 1010 (12-bit)
10 1010 1010 1010 (14-bit)
N/A No
1010 1× sync 0000 1111 (8-bit)
00 0001 1111 (10-bit)
0000 0011 1111 (12-bit)
00 0000 0111 1111 (14-bit)
N/A No
1011 One bit high 1000 0000 (8-bit)
10 0000 0000 (10-bit)
1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)
N/A No
1100 Mixed frequency
1010 0011 (8-bit)
10 0110 0011 (10-bit)
1010 0011 0011 (12-bit)
10 1000 0110 0111 (14-bit)
N/A No
1 All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver.
AD9222
Rev. C | Page 30 of 60
When the SPI is used, the DCO phase can be adjusted in 60°
increments relative to the data edge. This enables the user to
refine system timing margins if required. The default DCO+
and DCO− timing, as shown in Figure 2, is 90° relative to the
output data edge.
An 8-, 10-, and 14-bit serial stream can also be initiated from
the SPI. This allows the user to implement and test compatibility
with lower and higher resolution systems. When changing the
resolution to an 8- or 10-bit serial stream, the data stream is
shortened. See Figure 3 for the 10-bit example. However, when
using the 14-bit option, the data stream stuffs two 0s at the end
of the 14-bit serial data.
When the SPI is used, all of the data outputs can also be
inverted from their nominal state. This is not to be confused
with inverting the serial stream to an LSB-first mode. In default
mode, as shown in Figure 2, the MSB is first in the data output
serial stream. However, this can be inverted so that the LSB is
first in the data output serial stream (see Figure 4).
There are 12 digital output test pattern options available that
can be initiated through the SPI. This is a useful feature when
validating receiver capture and timing. Refer to Tabl e 9 for the
output bit sequencing options available. Some test patterns have
two serial sequential words and can be alternated in various
ways, depending on the test pattern chosen. Note that some
patterns may not adhere to the data format select option. In
addition, user-defined test patterns can be assigned in the 0x19,
0x1A, 0x1B, and 0x1C register addresses. All test mode options
except PN sequence short and PN sequence long can support
8- to 14-bit word lengths in order to verify data capture to the
receiver.
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 29 − 1 or 511 bits. A
description of the PN sequence and how it is generated can be
found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The
only difference is that the starting value must be a specific value
instead of all 1s (see Table 1 0 for the initial values).
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 223 – 1 or 8,388,607 bits. A
description of the PN sequence and how it is generated can be
found in section 5.6 of the ITU-T 0.150 (05/96) standard. The
only differences are that the starting value must be a specific
value instead of all 1s (see Tabl e 10 for the initial values) and the
AD9222 inverts the bit stream with relation to the ITU
standard.
Table 10. PN Sequence
Sequence
Initial
Value
First Three Output Samples
(MSB First)
PN Sequence Short 0x0df 0xdf9, 0x353, 0x301
PN Sequence Long 0x29b80a 0x591, 0xfd7, 0x0a3
Consult the Memory Map section for information on how to
change these additional digital output timing features through
the SPI.
SDIO/ODM Pin
The SDIO/ODM pin is for use in applications that do not require
SPI mode operation. This pin can enable a low power, reduced
signal option (similar to the IEEE 1596.3 reduced range link
output standard) if it and the CSB pin are tied to AVDD during
device power-up. This option should only be used when the
digital output trace lengths are less than 2 inches from the LVDS
receiver. When this option is used, the FCO, DCO, and outputs
function normally, but the LVDS signal swing of all channels is
reduced from 350 mV p-p to 200 mV p-p, allowing the user to
further reduce the power on the DRVDD supply.
For applications where this pin is not used, it should be tied low.
In this case, the device pin can be left open, and the 30 kΩ
internal pull-down resistor pulls this pin low. This pin is only
1.8 V tolerant. If applications require this pin to be driven from a
3.3 V logic level, insert a 1 kΩ resistor in series with this pin to
limit the current.
Table 11. Output Driver Mode Pin Settings
Selected ODM ODM Voltage
Resulting
Output Standard
Resulting
FCO and DCO
Normal
Operation
10 kΩ to AGND ANSI-644
(default)
ANSI-644
(default)
ODM AVDD Low power,
reduced
signal option
Low power,
reduced signal
option
SCLK/DTP Pin
The SCLK/DTP pin is for use in applications that do not require
SPI mode operation. This pin can enable a single digital test
pattern if it and the CSB pin are held high during device power-
up. When the SCLK/DTP is tied to AVDD, the ADC channel
outputs shift out the following pattern: 1000 0000 0000. The
FCO and DCO function normally while all channels shift out the
repeatable test pattern. This pattern allows the user to perform
timing alignment adjustments among the FCO, DCO, and output
data. For normal operation, this pin should be tied to AGND
through a 10 kΩ resistor. This pin is both 1.8 V and 3.3 V
tolerant.
Table 12. Digital Test Pattern Pin Settings
Selected DTP DTP Voltage
Resulting
D + x and D − x
Resulting
FCO and DCO
Normal
Operation
10 kΩ to AGND Normal
operation
Normal operation
DTP AVDD 1000 0000 0000 Normal operation
Additional and custom test patterns can also be observed when
commanded from the SPI port. Consult the Memory Map
section for information about the options available.
AD9222
Rev. C | Page 31 of 60
CSB Pin
The CSB pin should be tied to AVDD for applications that do
not require SPI mode operation. By tying CSB high, all SCLK
and SDIO information is ignored. This pin is both 1.8 V and
3.3 V tolerant.
RBIAS Pin
To set the internal core bias current of the ADC, place a resistor
(nominally equal to 10.0 kΩ) to ground at the RBIAS pin. The
resistor current is derived on-chip and sets the AVDD current of
the ADC to a nominal 450 mA at 65 MSPS. Therefore, it is
imperative that at least a 1% tolerance on this resistor be used to
achieve consistent performance
Voltage Reference
A stable, accurate 0.5 V voltage reference is built into the
AD9222. This is gained up internally by a factor of 2, setting
VREF to 1.0 V, which results in a full-scale differential input span
of 2 V p-p. The VREF is set internally by default; however, the
VREF pin can be driven externally with a 1.0 V reference to
improve accuracy.
When applying the decoupling capacitors to the VREF, REFT,
and REFB pins, use ceramic low-ESR capacitors. These capacitors
should be close to the ADC pins and on the same layer of the
PCB as the AD9222. The recommended capacitor values and
configurations for the AD9222 reference pin are shown in
Figure 79.
Table 13. Reference Settings
Selected Mode SENSE Voltage Resulting VREF (V)
Resulting
Differential
Span (V p-p)
External
Reference
AVDD N/A 2 × external
reference
Internal,
2 V p-p FSR
AGND to 0.2 V 1.0 2.0
Internal Reference Operation
A comparator within the AD9222 detects the potential at the
SENSE pin and configures the reference. If SENSE is grounded,
the reference amplifier switch is connected to the internal
resistor divider (see Figure 79), setting VREF to 1 V.
The REFT and REFB pins establish their input span of the ADC
core from the reference configuration. The analog input full-
scale range of the ADC equals twice the voltage at the reference
pin for either an internal or an external reference configuration.
If the reference of the AD9222 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 81
depicts how the internal reference voltage is affected by loading.
1µF 0.1µF
VREF
SENSE
0.5V
REFT
0.1µF
0.1µF 4.7µF
0.1µF
REFB
SELECT
LOGIC
ADC
CORE
+
VIN – x
VIN + x
05967-064
Figure 79. Internal Reference Configuration
1µF
1
0.1µF
1
VREF
SENSE
AVDD
0.5V
REFT
0.1µF
0.1µF 4.7µF
0.1µF
REFB
SELECT
LOGIC
ADC
CORE
+
VIN – x
VIN + x
EXTERNAL
REFERENCE
1
OPTIONAL.
0
5967-065
Figure 80. External Reference Operation
AD9222
Rev. C | Page 32 of 60
0.02
–0.18
–0.14
–0.10
–0.06
–0.02
–0.16
–0.12
–0.08
–0.04
0
–40
V
REF
ERROR (%)
TEMPERATURE (°C)
05967-028
–200 20406080
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 82 shows the typical drift characteristics of the
internal reference in 1 V mode.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. The external
reference is loaded with an equivalent 6 kΩ load. An internal
reference buffer generates the positive and negative full-scale
references, REFT and REFB, for the ADC core. Therefore, the
external reference must be limited to a nominal of 1.0 V.
01.00.5 2.01.5 3.02.5 3.5
VREF ERROR (%)
CURRENT LOAD (mA)
05727-083
–30
–5
–10
–15
–20
–25
5
0
Figure 82. Typical VREF Drift, AD9222-50
Figure 81. VREF Accuracy vs. Load, AD9222-50
AD9222
Rev. C | Page 33 of 60
SERIAL PORT INTERFACE (SPI)
The AD9222 serial port interface allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. This gives
the user added flexibility and customization, depending on the
application. Addresses are accessed via the serial port and can
be written to or read from via the port. Memory is organized
into bytes that can be further divided down into fields, as doc-
umented in the Memory Map section. Detailed operational
information can be found in the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
There are three pins that define the SPI: SCLK, SDIO, and CSB
(see Table 14 ). The SCLK pin is used to synchronize the read
and write data presented to the ADC. The SDIO pin is a dual-
purpose pin that allows data to be sent to and read from the
internal ADC memory map registers. The CSB pin is an active
low control that enables or disables the read and write cycles.
Table 14. Serial Port Pins
Pin Function
SCLK Serial Clock. The serial shift clock input. SCLK is used to
synchronize serial interface reads and writes.
SDIO Serial Data Input/Output. A dual-purpose pin. The
typical role for this pin is an input or output, depending
on the instruction sent and the relative position in the
timing frame.
CSB Chip Select Bar (Active Low). This control gates the read
and write cycles.
The falling edge of the CSB in conjunction with the rising edge
of the SCLK determines the start of the framing sequence. During
an instruction phase, a 16-bit instruction is transmitted followed by
one or more data bytes, which is determined by Bit Field W0 and
Bit Field W1. An example of the serial timing and its definitions
can be found in Figure 84 and Table 15. During normal operation,
CSB is used to signal to the device that SPI commands are to be
received and processed. When CSB is brought low, the device
processes SCLK and SDIO to process instructions. Normally,
CSB remains low until the communication cycle is complete.
However, if connected to a slow device, CSB can be brought
high between bytes, allowing older microcontrollers enough
time to transfer data into shift registers. CSB can be stalled
when transferring one, two, or three bytes of data. When W0 and
W1 are set to 11, the device enters streaming mode and continues
to process data, either reading or writing, until CSB is taken
high to end the communication cycle. This allows complete
memory transfers without requiring additional instructions.
Regardless of the mode, if CSB is taken high in the middle of a
byte transfer, the SPI state machine is reset and the device waits
for a new instruction.
In addition to the operation modes, the SPI port configuration
influences how the AD9222 operates. For applications that do
not require a control port, the CSB line can be tied and held high.
This places the remainder of the SPI pins into their secondary
modes, as defined in the SDIO/ODM Pin and SCLK/DTP Pin
sections. CSB can also be tied low to enable 2-wire mode. When
CSB is tied low, SCLK and SDIO are the only pins required for
communication. Although the device is synchronized during
power-up, the user should ensure that the serial port remains
synchronized with the CSB line when using this mode. When
operating in 2-wire mode, it is recommended to use a 1-, 2-, or
3-byte transfer exclusively. Without an active CSB line, streaming
mode can be entered but not exited.
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip and read the contents
of the on-chip memory. If the instruction is a readback operation,
performing a readback causes the SDIO pin to change from an
input to an output at the appropriate point in the serial frame.
Data can be sent in MSB- or LSB-first mode. MSB-first mode
is the default at power-up and can be changed by adjusting the
configuration register. For more information about this and
other features, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
AD9222
Rev. C | Page 34 of 60
HARDWARE INTERFACE
The pins described in Table 14 compose the physical interface
between the user’s programming device and the serial port of
the AD9222. The SCLK and CSB pins function as inputs when
using the SPI. The SDIO pin is bidirectional, functioning as an
input during write phases and as an output during readback.
If multiple SDIO pins share a common connection, care should
be taken to ensure that proper VOH levels are met. Assuming the
same load for each AD9222, Figure 83 shows the number of SDIO
pins that can be connected together and the resulting VOH level.
05967-037
NUMBER OF SDIO PINS CONNECTED TOGETHER
V
OH
(V)
1.715
1.720
1.725
1.730
1.735
1.740
1.745
1.750
1.755
1.760
1.765
1.770
1.775
1.780
1.785
1.790
1.795
1.800
0302010 40 50 60 70 80 90 100
Figure 83. SDIO Pin Loading
This interface is flexible enough to be controlled by either serial
PROMS or PIC mirocontrollers, providing the user with an
alternative method, other than a full SPI controller, to program
the ADC (see the AN-812 Application Note).
If the user chooses not to use the SPI, these dual-function pins
serve their secondary functions when the CSB is strapped to
AVDD during device power-up. See the Theory of Operation
section for details on which pin-strappable functions are
supported on the SPI pins.
AD9222
Rev. C | Page 35 of 60
DON’T CARE
DON’T CAREDON’T CARE
DON’T CARE
SDIO
SCLK
CSB
t
S
t
DH
t
HI
t
CLK
t
LO
t
DS
t
H
R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0
05967-068
Figure 84. Serial Timing Details
Table 15. Serial Timing Definitions
Parameter Timing (Minimum, ns) Description
tDS 5 Setup time between the data and the rising edge of SCLK
tDH 2 Hold time between the data and the rising edge of SCLK
tCLK 40 Period of the clock
tS 5 Setup time between CSB and SCLK
tH 2 Hold time between CSB and SCLK
tHI 16 Minimum period that SCLK should be in a logic high state
tLO 16 Minimum period that SCLK should be in a logic low state
tEN_SDIO 10 Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 84)
tDIS_SDIO 10 Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising
edge (not shown in Figure 84)
AD9222
Rev. C | Page 36 of 60
MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map register table (Table 16) has eight
address locations. The memory map is divided into three sections:
the chip configuration register map (Address 0x00 to Address 0x02),
the device index and transfer register map (Address 0x05 and
Address 0xFF), and the ADC functions register map (Address 0x08
to Address 0x22).
The leftmost column of the memory map indicates the register
address number, and the default value is shown in the second right-
most column. The (MSB) Bit 7 column is the start of the default
hexadecimal value given. For example, Address 0x09, the clock
register, has a default value of 0x01, meaning Bit 7 = 0, Bit 6 = 0,
Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or
0000 0001 in binary. This setting is the default for the duty cycle
stabilizer in the on condition. By writing a 0 to Bit 6 of this address,
the duty cycle stabilizer turns off. For more information on this
and other functions, consult the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
RESERVED LOCATIONS
Undefined memory locations should not be written to except
when writing the default values suggested in this data sheet.
Addresses that have values marked as 0 should be considered
reserved and have a 0 written into their registers during power-up.
DEFAULT VALUES
When the AD9222 comes out of a reset, critical registers are
preloaded with default values. These values are indicated in
Table 16, where an X refers to an undefined feature.
LOGIC LEVELS
An explanation of various registers follows: “Bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
AD9222
Rev. C | Page 37 of 60
Table 16. Memory Map Register
Addr.
(Hex) Parameter Name
(MSB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB)
Bit 0
Default
Value
(Hex)
Default Notes/
Comments
Chip Configuration Registers
00 chip_port_config 0 LSB first
1 = on
0 = off
(default)
Soft
reset
1 = on
0 = off
(default)
1 1 Soft
reset
1 = on
0 = off
(default)
LSB first
1 = on
0 = off
(default)
0 0x18 The nibbles
should be
mirrored so that
LSB- or MSB-first
mode is set cor-
rectly regardless
of shift mode.
01 chip_id 8-bit Chip ID Bits 7:0
(AD9222 = 0x07), (default)
Read
only
Default is unique
chip ID, different
for each device.
This is a read-
only register.
02 chip_grade X Child ID [6:4]
(identify device variants of Chip ID)
000 = 65 MSPS
011 = 50 MSPS
001 = 40 MSPS
X X X X Read
only
Child ID used to
differentiate
graded devices.
Device Index and Transfer Registers
04 device_index_2 X X X X Data
Channel
H
1 = on
(default)
0 = off
Data
Channel
G
1 = on
(default)
0 = off
Data
Channel
F
1 = on
(default)
0 = off
Data
Channel
E
1 = on
(default)
0 = off
0x0F Bits are set to
determine which
on-chip device
receives the next
write command.
05 device_index_1 X X Clock
Channel
DCO
1 = on
0 = off
(default)
Clock
Channel
FCO
1 = on
0 = off
(default)
Data
Channel
D
1 = on
(default)
0 = off
Data
Channel
C
1 = on
(default)
0 = off
Data
Channel
B
1 = on
(default)
0 = off
Data
Channel
A
1 = on
(default)
0 = off
0x0F Bits are set to
determine which
on-chip device
receives the next
write command.
FF device_update X X X X X X X SW
transfer
1 = on
0 = off
(default)
0x00 Synchronously
transfers data
from the master
shift register to
the slave.
ADC Functions
08 modes X X X X X Internal power-down mode
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset
0x00 Determines
various generic
modes of chip
operation.
09 clock X X X X X X X Duty cycle
stabilizer
1 = on
(default)
0 = off
0x01 Turns the
internal duty
cycle stabilizer
on and off.
0D test_io User test mode
00 = off (default)
01 = on, single alternate
10 = on, single once
11 = on, alternate once
Reset PN
long gen
1 = on
0 = off
(default)
Reset
PN short
gen
1 = on
0 = off
(default)
Output test mode—see Table 9 in the
Digital Outputs and Timing section
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checkerboard output
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
(format determined by output_mode)
0x00 When this reg-
ister is set, the
test data is placed
on the output
pins in place of
normal data.
AD9222
Rev. C | Page 38 of 60
Addr.
(Hex) Parameter Name
(MSB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB)
Bit 0
Default
Value
(Hex)
Default Notes/
Comments
14 output_mode X 0 = LVDS
ANSI-644
(default)
1 = LVDS
low power,
(IEEE 1596.3
similar)
X X X Output
invert
1 = on
0 = off
(default)
00 = offset binary
(default)
01 = twos
complement
0x00 Configures the
outputs and the
format of the data.
15 output_adjust X X Output driver
termination
00 = none (default)
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
X X X DCO and
FCO
2× Drive
Strength
1 = on
0 = off
(default)
0x00 Determines
LVDS or other
output properties.
Primarily func-
tions to set the
LVDS span and
common-mode
levels in place of
an external
resistor.
16 output_phase X X X X 0011 = output clock phase adjust
(0000 through 1010)
0000 = 0° relative to data edge
0001 = 60° relative to data edge
0010 = 120° relative to data edge
0011 = 180° relative to data edge (default)
0100 = 240° relative to data edge
0101 = 300° relative to data edge
0110 = 360° relative to data edge
0111 = 420° relative to data edge
1000 = 480° relative to data edge
1001 = 540° relative to data edge
1010 = 600° relative to data edge
1011 to 1111 = 660° relative to data edge
0x03 On devices that
utilize global
clock divide,
determines
which phase of
the divider
output is used to
supply the
output clock.
Internal latching
is unaffected.
19 user_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined
pattern, 1 LSB.
1A user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined
pattern, 1 MSB.
1B user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined
pattern, 2 LSB.
1C user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined
pattern, 2 MSB.
21 serial_control LSB first
1 = on
0 = off
(default)
X X X <10
MSPS,
low
encode
rate
mode
1 = on
0 = off
(default)
000 = 12 bits (default, normal bit
stream)
001 = 8 bits
010 = 10 bits
011 = 12 bits
100 = 14 bits
0x00 Serial stream
control. Default
causes MSB first
and the native
bit stream
(global).
22 serial_ch_stat X X X X X X Channel
output
reset
1 = on
0 = off
(default)
Channel
power-
down
1 = on
0 = off
(default)
0x00 Used to power
down individual
sections of a
converter (local).
AD9222
Rev. C | Page 39 of 60
Power and Ground Recommendations
When connecting power to the AD9222, it is recommended
that two separate 1.8 V supplies be used: one for analog (AVDD)
and one for digital (DRVDD). If only one supply is available, it
should be routed to the AVDD first and then tapped off and
isolated with a ferrite bead or a filter choke preceded by
decoupling capacitors for the DRVDD. The user can employ
several different decoupling capacitors to cover both high and
low frequencies. These should be located close to the point of
entry at the PC board level and close to the parts, with minimal
trace lengths.
A single PC board ground plane should be sufficient when
using the AD9222. With proper decoupling and smart parti-
tioning of the PC board’s analog, digital, and clock sections,
optimum performance can be easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9222. An
exposed continuous copper plane on the PCB should mate to
the AD9222 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This provides
several tie points between the ADC and PCB during the reflow
process, whereas using one continuous plane with no partitions
only guarantees one tie point. See Figure 85 for a PCB layout
example. For detailed information on packaging and the PCB
layout of chip scale packages, see the AN-772 Application Note,
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package (LFCSP).
SILKSCREEN P
A
RTITION
PIN 1 INDICATOR
05967-069
Figure 85. Typical PCB Layout
AD9222
Rev. C | Page 40 of 60
EVALUATION BOARD
The AD9222 evaluation board provides all of the support cir-
cuitry required to operate the ADC in its various modes and
configurations. The converter can be driven differentially using a
transformer (default) or an AD8334 driver. The ADC can also be
driven in a single-ended fashion. Separate power pins are provided
to isolate the DUT from the drive circuitry of the AD8334. Each
input configuration can be selected by changing the connection
of various jumpers (see Figure 90 to Figure 94). Figure 86 shows
the typical bench characterization setup used to evaluate the ac
performance of the AD9222. It is critical that the signal sources
used for the analog input and clock have very low phase noise
(<1 ps rms jitter) to realize the optimum performance of the
converter. Proper filtering of the analog input signal to remove
harmonics and lower the integrated or broadband noise at the
input is also necessary to achieve the specified noise performance.
See Figure 90 to Figure 100 for the complete schematics and
layout diagrams demonstrating the routing and grounding
techniques that should be applied at the system level.
POWER SUPPLIES
This evaluation board has a wall-mountable switching power
supply that provides a 6 V, 2 A maximum output. Connect the
supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to
63 Hz. The other end of the supply is a 2.1 mm inner diameter
jack that connects to the PCB at P701. Once on the PC board,
the 6 V supply is fused and conditioned before connecting to
three low dropout linear regulators that supply the proper bias
to each of the various sections on the board.
When operating the evaluation board in a nondefault condition,
L701 to L704 can be removed to disconnect the switching power
supply. This enables the user to bias each section of the board
individually. Use P702 to connect a different supply for each
section. At least one 1.8 V supply is needed for AVDD_DUT and
DRVDD_DUT; however, it is recommended that separate supplies
be used for both analog and digital signals and that each supply
have a current capability of 1 A. To operate the evaluation board
using the VGA option, a separate 5.0 V analog supply (AVDD_5 V)
is needed. To operate the evaluation board using the SPI and alter-
nate clock options, a separate 3.3 V analog supply (AVDD_3.3 V) is
needed in addition to the other supplies.
INPUT SIGNALS
When connecting the clock and analog sources to the evalu-
ation board, use clean signal generators with low phase noise,
such as Rohde & Schwarz SMA or HP8644 signal generators or the
equivalent, as well as a 1 m, shielded, RG-58, 50 Ω coaxial cable.
Enter the desired frequency and amplitude from the ADC specifi-
cations tables. Typically, most Analog Devices, Inc., evaluation
boards can accept approximately 2.8 V p-p or 13 dBm sine wave
input for the clock. When connecting the analog input source, it
is recommended to use a multipole, narrow-band, band-pass
filter with 50 Ω terminations. Good choices of such band-pass
filters are available from TTE, Allen Avionics, and K&L
Microwave, Inc. The filter should be connected directly to the
evaluation board if possible.
OUTPUT SIGNALS
The default setup uses the Analog Devices HSC-ADC-FPGA-8Z
high speed deserialization board to deserialize the digital output
data and convert it to parallel CMOS. These two channels interface
directly with the Analog Devices standard dual-channel FIFO
data capture board (HSC-ADC-EVALB-DCZ). Two of the eight
channels can then be evaluated at the same time. For more infor-
mation on the channel settings and optional settings of these
boards, visit www.analog.com/FIFO.
ROHDE & SCHWARZ,
SMA,
2V p-p SIGNAL
SYNTHESIZER
ROHDE & SCHWARZ,
SMA,
2V p-p SIGNAL
SYNTHESIZER
BAND-PASS
FILTER
XFMR
INPUT
CLK
CH A TO CH H
12-BIT
SERIAL
LVDS
2-CH
12-BIT
PARALLEL
CMOS
USB
CONNECTION
AD9222
EVALUATION BOARD
HSC-ADC-FPGA-8Z
HIGH SPEED
DESERIALIZATION
BOARD
HSC-ADC-EVALB-DCZ
FIFO DATA
CAPTURE
BOARD
PC
RUNNING
ADC
ANALYZER
AND SPI
USER
SOFTWARE
1.8V
–+–+
AVDD_DUT
AVDD_3.3V
DRVDD_DUT
GND
GND
–+
5.0V
GND
AVDD_5V
1.8V
6V DC
2A MAX
WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
SWITCHING
POWER
SUPPLY
–+
GND
3.3V
–+
1.5V_FPGA
3.3V_D
GND
3.3V
–+
GND
1.5V
–+
VCC
GND
3.3V
SPI SPISPI SPI
0
5967-070
Figure 86. Evaluation Board Connection
AD9222
Rev. C | Page 41 of 60
DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
The following is a list of the default and optional settings or
modes allowed on the AD9222 Rev. A evaluation board.
• POWER: Connect the switching power supply that is
provided with the evaluation kit between a rated 100 V ac
to 240 V ac wall outlet at 47 Hz to 63 Hz and P701.
• AIN: The evaluation board is set up for a transformer-
coupled analog input with an optimum 50 Ω impedance
match of 150 MHz of bandwidth (see Figure 87). For more
bandwidth response, the differential capacitor across the
analog inputs can be changed or removed. The common
mode of the analog inputs is developed from the center
tap of the transformer or AVDD_DUT/2.
0
AMPLITUDE (dBFS)
FREQUENCY (MHz)
0
–18
–16
–14
–12
–10
–8
–6
–4
–2
50 100 150 200 250 300 350 400 450 500
–3dB CUTOFF = 150MHz
0
5967-071
Figure 87. Evaluation Board Full-Power Bandwidth, AD9222-50
• VREF: VREF is set to 1.0 V by tying the SENSE pin to ground,
R317. This causes the ADC to operate in 2.0 V p-p full-scale
range. A separate external reference option using the ADR510
or ADR520 is also included on the evaluation board. Populate
R312 and R313 and remove C307. Proper use of the VREF
options is noted in the Voltage Referenc e section.
• RBIAS: RBIAS has a default setting of 10 kΩ (R301) to
ground and is used to set the ADC core bias current.
• CLOCK: The default clock input circuitry is derived from a
simple transformer-coupled circuit using a high bandwidth
1:1 impedance ratio transformer (T401) that adds a very
low amount of jitter to the clock path. The clock input is
50 Ω terminated and ac-coupled to handle single-ended
sine wave types of inputs. The transformer converts the
single-ended input to a differential signal that is clipped
before entering the ADC clock inputs.
A differential LVPECL clock can also be used to clock the
ADC input using the AD9515 (U401). Populate R406 and
R407 with 0 Ω resistors and remove R215 and R216 to
disconnect the default clock path inputs. In addition, populate
C205 and C206 with a 0.1 F capacitor and remove C409 and
C410 to disconnect the default clock path outputs. The
AD9515 has many pin-strappable options that are set to a
default mode of operation. Consult the AD9515 data sheet
for more information about these and other options.
In addition, an on-board oscillator is available on the OSC401
and can act as the primary clock source. The setup is quick
and involves installing R403 with a 0 Ω resistor and setting
the enable jumper (J401) to the on position. If the user wishes
to employ a different oscillator, two oscillator footprint options
are available (OSC401) to check the ADC performance.
• PDWN: To enable the power-down feature, short J301 to
the on position (AVDD) on the PDWN pin.
• SCLK/DTP: To enable the digital test pattern on the digital
outputs of the ADC, use J304. If J304 is tied to AVDD during
device power-up, Test Pattern 1000 0000 0000 is enabled. See
the SCLK/DTP Pin section for details.
• SDIO/ODM: To enable the low power, reduced signal option
(similar to the IEEE 1595.3 reduced range link LVDS output
standard), use J303. If J303 is tied to AVDD during device
power-up, it enables the LVDS outputs in a low power,
reduced signal option from the default ANSI-644 standard.
This option changes the signal swing from 350 mV p-p to
200 mV p-p, reducing the power of the DRVDD supply. See
the SDIO/ODM Pin section for more details.
• CSB: To enable processing of the SPI information on the
SDIO and SCLK pins, tie J302 low in the always enable
mode. To ignore the SDIO and SCLK information, tie J302
to AVDD.
• Non-SPI Mode: For users who wish to operate the DUT
without using SPI, remove Jumpers J302, J303, and J304.
This disconnects the CSB, SCLK/DTP, and SDIO/ODM pins
from the control bus, allowing the DUT to operate in its
simplest mode. Each of these pins has internal termination
and will float to its respective level.
• D + x, D − x: If an alternative data capture method to the setup
shown in Figure 90 is used, optional receiver terminations,
R318 and R320 to R328, can be installed next to the high
speed backplane connector.
AD9222
Rev. C | Page 42 of 60
ALTERNATIVE ANALOG INPUT DRIVE
CONFIGURATION
In this example, a 16 MHz, two-pole low-pass filter was applied
to the AD8334 outputs. The following components need to be
removed and/or changed:
The following is a brief description of the alternative analog
input drive configuration using the AD8334 dual VGA. If this
drive option is in use, some components may need to be
populated, in which case all the necessary components are listed
in Table 17. For more details on the AD8334 dual VGA,
including how it works and its optional pin settings, consult the
AD8334 data sheet.
• Remove L507, L508, L511, L512, L515, L516, L519, L520,
L607, L608, L611, L612, L615, L616, L619, and L620 on the
AD8334 analog outputs.
• Populate L507, L508, L511, L512, L515, L516, L519, L520,
L607, L608, L611, L612, L615, L616, L619, and L620 with
680 nH inductors.
To configure the analog input to drive the VGA instead of the
default transformer option, the following components need to
be removed and/or changed.
• Populate C543, C547, C551, C555, C643, C647, C651, and
C655 with a 68 pF capacitor.
68pF
680nH
680nH
05967-107
• Remove R102, R115, R128, R141, R161, R162, R163, R164,
R202, R208, R218, R225, R234, R241, R252, R259, T101,
T102, T103, T104, T201, T202, T203, and T204 in the
default analog input path.
Figure 88. Example Filter Configured for16 MHz, Two-Pole Low-Pass Filter
0
–120
–100
–80
–60
–40
–20
05.07.52.5 10.0 15.0 17.512.5 20.0 22.5 25.0
AMPLITUDE (dBFS)
FREQUENCY (MHz)
05967-108
fSAMPLE
=50MSPS
AIN = 3.5MHz
AD8334 = MAX GAIN SETTING
• Populate R101, R114, R127, R140, R201, R217, R233, and
R251 with 0 Ω resistors in the analog input path.
• Populate R152, R153, R154, R155, R156, R157, R158, R159,
R215, R216, R229, R230, R247, R248, R263, R264, C103,
C105, C110, C112, C117, C119, C124, C126, C203, C205,
C210, C212, C217, C219, C224, and C226 with 10 kΩ
resistors to provide an input common-mode level to the
ADC analog inputs.
• Populate R105, R113, R118, R124, R131, R137, R151, R160,
R205, R213, R221, R222, R237, R238, R255, and R256 with
0 Ω resistors in the ADC analog input path to connect the
VGA outputs.
Figure 89. AD9222 FFT Example Results Using 16 MHz, Two-Pole Low-Pass
Filter Applied to the AD8334 Outputs (fSAMPLE = 50 MSPS, AIN = 3.5 MHz,
AD8334 = Maximum Gain Setting, Analog Input Signal = −1.03 dBFS, SNR =
60.8 dBc, SFDR = 67.02 dBc)
• Remove R515, R520, R527, R532, R615, R620, R627, and
R632 on the AD8334 analog outputs.
• Remove R512, R524, R612, and R624 to set the AD8334
mode and AD8334 HILO pin low. Some applications may
require this to be different. Consult the AD8334 data sheet
for more information on these functions.
In this configuration, L505 to L520 and L605 to L620 are
populated with 0 Ω resistors to allow signal connection and use
of a filter if additional requirements are necessary.
AD9222
Rev. C | Page 43 of 60
DNP
DNP
DNP
VGA Input
Ain
Ain
Ain
VGA Input
VGA Input
Connection
Connection
Connection
Connection
VGA Input
Channel C
Ain
DNP
Ain
Channel A
Ain
Ain
Channel B
Ain
Channel D
R134
33Ω
P105
P102
R148
1kΩ
R160
0Ω−DNP
R151
0Ω−DNP
R137
0Ω−DNP
R131
0Ω−DNP
R124
0Ω−DNP
R118
0Ω−DNP
R113
0Ω−DNP
R105
0Ω−DNP
R101
0Ω−DNP
R140
0Ω−DNP
R127
0Ω−DNP
R114
0Ω−DNP
R107
DNP
1
25
6
T104
1
2
34
34
5
6
T103
CM3
1
25
6
T101
1
2
34
34
5
6
T102
1
E102
1
E101
DNP
C127
10Ω
FB112
10Ω
FB111
10Ω
FB110
10Ω
FB109
10Ω
FB10 8
10Ω
FB107
10Ω
FB106
10Ω
FB105
10Ω
FB104
DNP
C113
10Ω
FB103
10Ω
FB102
10Ω
FB101
DNP
C106
2.2pF
C118
DNP
C124
VIN_D
0.1µF
C114
0.1µF
C107
VIN_D
VIN_C
VIN_B
VIN_B
AVDD_DUT
AVDD_DUT
CM2
CM1
CH_D
CH_D
CM3
CM1
INH 4
INH 3
INH 1
CH_A
CH_A CH_C
CM4
AVDD_DUT
AVDD_ DUT
AVDD_ DUT
CM4
AVDD_ DUT
INH 2
CH_B
CH_B
CM2
CH_C
R104
0Ω
R116
0Ω
R130
0Ω
R143
0Ω
AVDD_DUT
AVDD_DUT
AVDD_DUT
AVDD_DUT
AVDD_DUT
AVDD_DUT
DNP
C120
0.1µF
C128
0.1µF
C121
0.1µF
C101
2.2pF
C125
DNP
C117
DNP
C126
DNP
C119
DNP
C112
0.1µF
C108
0.1µF
C109
0.1µF
C116
0.1µF
C115
0.1µF
C122
0.1µF
C123
DNP
C110
2.2pF
C111
DNP
C103 2.2pF
C104
DNP
C105
0.1µF
C102
VIN_A
VIN_A
CM1
CM2
1
E103
1
E104
CM3
CM4
R135
1kΩ
R123
1kΩ
R109
1kΩ
499Ω
R164
R163
499Ω
R162
499Ω
499Ω
R161
DNP
R159
DNP
R158
DNP
R157
R156
DNP
R108
33Ω
DNP
R152
DNP
R155
DNP
R154
DNP
R153
R102
64.9Ω
R147
33Ω
R146
33Ω
R145
DNP
R149
1kΩ
R136
33Ω
R133
DNP
R132
DNP
R125
1KΩ
R122
33Ω
R121
33Ω
R111
1kΩ
R106
DNP
R112
1kΩ
R150
1kΩ
R139
1kΩ
R138
1kΩ
R126
1kΩ
R110
33Ω
R141
64.9Ω
R142
0Ω
R128
64.9Ω
R129
0Ω
R115
64.9Ω
R117
0Ω
R103
0Ω
R144
DNP
R120
DNP
R119
DNP
P101
P106
P108
P107
P104
P103
VIN_C
05967-072
DNP: DO NOT POPULATE.
Figure 90. Evaluation Board Schematic, DUT Analog Inputs
AD9222
Rev. C | Page 44 of 60
DNP
DNP
DNP
DNP
VGA Input
Ain
Ain
Ain
Ain
VGA Input
VGA Input VGA Input
Ain
Connection
Connection
Connection
Connection
Channel E
DNP
Ain
Channel G
Ain
Channel H
Channel F
Ain 1
25
6
T20 4
R266
1kΩ
10Ω
FB212
R265
1kΩ
10Ω
FB209
10Ω
FB207
R245
33Ω
R240
DNP
1
25
34
34
6
T203
2.2pF
C211
R231
1kΩ
10Ω
FB206
10Ω
FB20 3
1
25
6
T202
R220
0Ω
R257
DNP
R258
DNP
R224
DNP
R223
DNP
2.2pF
C204
R207
DNP
R206
DNP
1
25
34
34
6
T20 1
10Ω
FB201
R262
1kΩ
R256
0Ω−DNP
R255
0Ω−DNP
R238
0Ω−DNP
R237
0Ω−DNP
R222
0Ω−DNP
R221
0Ω−DNP
R213
0Ω−DNP
R205
0Ω−DNP
R201
0Ω−DNP
R251
0Ω−DNP
R233
0Ω−DNP
R217
0Ω−DNP
CM7
1
E202
1
E201
DNP
C227
10Ω
FB211
10Ω
FB210
10Ω
FB208
10Ω
FB205
10Ω
FB204
DNP
C213
10Ω
FB20 2
DNP
C206
2.2pF
C218
DNP
C224
VIN_H
0.1µF
C214
0.1µF
C207
VIN_H
VIN_G
VIN_G
VIN_F
VIN_F
AVDD_DUT
AVDD_DUT
CM6
CM5
CH_H
CH_H
CM7
CM5
INH 8
INH7
INH 5
CH_E
CH_E CH_G
CM8
AVDD_DUT
AVDD_DUT
AVDD_DUT
CM8
AVDD_DUT
INH 6
CH_F
CH_F
CM6
CH_G
R204
0ΩR236
0Ω
R254
0Ω
AVDD_DUT
AVDD_DUT
AVDD_DUT
AVDD_DUT
AVDD_DUT
AVDD_DUT
DNP
C220
0.1µF
C228
0.1µF
C221
0.1µF
C201
2.2pF
C225
DNP
C217
DNP
C226
DNP
C219
DNP
C212
0.1µF
C208
0.1µF
C209
0.1µF
C216
0.1µF
C215
0.1µF
C222
0.1µF
C223
DNP
C210
DNP
C203
DNP
C205
0.1µF
C202
VIN_E
VIN_E
CM5
CM6
1
E203
1
E204
CM7
CM8
R246
1kΩ
R228
1kΩ
R214
1kΩ
499Ω
R259
R241
499Ω
R225
499Ω
499Ω
R208
DNP
R263
DNP
R247
DNP
R229
R215
DNP
R209
33Ω
DNP
R216
DNP
R264
DNP
R248
DNP
R230
R202
64.9Ω
R261
33Ω
R260
33Ω
R239
DNP
R227
33Ω
R226
33Ω
R211
1kΩ
R212
1kΩ
R250
1kΩ
R249
1kΩ
R232
1kΩ
R210
33Ω
R242
33Ω
R252
64.9Ω
R253
0Ω
R234
64.9kΩR235
0Ω
R218
64.9Ω
R219
0Ω
R203
0Ω
P201
P202
P205
P206
P208
P207
P203
P204
05967-073
DNP: DO NOT POPULATE.
Figure 91. Evaluation Board Schematic, DUT Analog Inputs (Continued)
AD9222
Rev. C | Page 45 of 60
4.7µF
CW
GND
VOUT
TRIM/NC
AD9222BCPZ-65
AVDD
CLK+
CLK−
D+B
D+C
D+D
D+E
D+F
D+G
D+H
D−B
D−C
D−D
D−E
D−F
D−G
D−H
DCO+
DCO−
DRGND
DRVDD
FCO+
FCO−
PDWN
AVDD
RBIAS
REFB
REFT
SCLK/DTP
SDIO/ODM
VIN+A
VIN+C
VIN+D
VIN+E
VIN+G
VIN−A
VIN−B
VIN−C
VIN−D
VIN−F
VIN−G
VREF
VIN+F
SLUG
AVDD
AVDD
AVDD
DRGND
VIN−H
D+A
D−A
VIN+B
CSB
SENSE
VIN−E
VIN+H
DRVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
A1
A10
A2
A3
A4
A5
A6
A7
A8
A9
B1
B10
B2
B3
B4
B5
B6
B7
B8
B9
C1
C10
C2
C3
C4
C5
C6
C7
C8
C9
D1
D10
D2
D3
D4
D5
D6
D7
D8
D9
GNDAB1
GNDAB10
GNDAB2
GNDAB3
GNDAB4
GNDAB5
GNDAB6
GNDAB7
GNDAB8
GNDAB9
GNDCD1
GNDCD10
GNDCD2
GNDCD3
GNDCD4
GNDCD5
GNDCD6
GNDCD7
GNDCD8
GNDCD9
Optional Output
Terminations
Digital Outputs
using external Vref
VREF = 1V
VREF = External
VREF = 0.5V
Remove C214 when
ALWAYS ENABLE SPI
ODM Enable
DTP Enable
VREF = 0.5V(1 + R219/R220)
Vref Select
1.0V
Reference
Decoupling
OPTIONAL
EXT REF
PWDN ENABLE
NC
Reference Circuitry
R318,R320−R328
DNP
R322
CHB
1
10
2
3
4
5
6
7
8
9
11
20
12
13
14
15
16
17
18
19
31
40
32
33
34
35
36
37
38
39
41
50
42
43
44
45
46
47
48
49
21
30
22
23
24
25
26
27
28
29
51
60
52
53
54
55
56
57
58
59
P301
CHB
DNP
R318
DNP
R320
DNP
R321
DNP
R323
DNP
R324
DNP
R325
DNP
R328
DNP
R326
3
2
1J304
1
2
3
J303
1
2
3
J302
3
2
1J301
R319
1kΩ
AVDD_DUT
AVDD_DUT
AVDD_DUT
VIN_E
VIN_E
VIN_F
VIN_F
1
59
4
42
45
48
51
62
7
10
9
11
8
32
30
28
22
20
18
16
31
29
27
21
19
17
15
24
23
13 36
14 35
37
26
25
33
34
40
47
55
61
5
6
41
12
54
57
58
38
39
43
49
53
60
2
44
46
50
52
63
3
56
64
0
U301
R306
100kΩ
R305
100kΩ
R303
100kΩDNP
R304
DNP
R302
SCLK_DTP
SDIO_ODM
CSB_DUT
0.1µF
C305
4.99kΩ
R309
1µF
C307
C301
0.1µF
C304
0.1µF
C302
0.1µF
ADR510ARTZ
U302
10kΩ
R310
DNP
R311
R307
10kΩ
VSENSE_DUT
470kΩ
R308
DNP
R313
DNP
R312
0Ω
R317
DNP
R31
DNP
R315
DNP
R314
R301
10kΩ
0.1µF
C306
AVDD_DUT
VREF_DUT
AVDD_DUT
AVDD_DUT
DRVDD_DUT
AVDD_DUT
AVDD_DUT
AVDD_DUT
CLK
CLK
CHB
CHC
CHD
CHH
CHB
CHC
CHD
CHH
DCO
DCO
GND
DRVDD_DUT
FCO
FCO
VSENSE_DUT
VIN_H
VIN_H
VIN_C
VIN_D
VIN_G
VIN_C
VIN_D
VIN_G
VREF_DUT
CHG
CHG
CHF
CHF
CHE
CHE
AVDD_DUT
AVDD_DUT
GND
AVDD_DUT
VIN_A
VIN_A
CHA
CHA
AVDD_DUT
VIN_B
VIN_B
AVDD_DUT
AVDD_DUT
AVDD_DUT
DNP
R327
SCLK_CHA
SDI_CHA
CSB1_CHA
CSB2_CHA
SDO_CHA
SCLK_CHB
SDI_CHB
CSB3_CHB
CSB4_CHB
SDO_CHB
DCO
FCO
CHA
CHC
CHD
CHE
CHF
CHG
CHHCHH
CHG
CHF
CHE
CHD
CHC
CHA
FCO
DCO
C303
05967-074
DNP: DO NOT POPULATE.
Figure 92. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface
AD9222
Rev. C | Page 46 of 60
CRYSTAL_3
GND
OE
OUT
VCC
OE
GNDOU T
VCC
CLK
CLKB
GND
GND_PAD
OUT0
OUT0B
OUT1
OUT1B
RSET
S0
S1
S10
S2
S3
S4
S5
S6
S7
S8
S9
SYNCB
VREF
VS
SIGNAL=DNC;27,28
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
Input
Encode
Enc
Enc
Clock Circuit
DNP
DNP
DNP
DNP
DISABLE OSC401
ENABLE OSC401
Optional Clock
Oscillator
AD9515 Pin−strap settings
OPTIONAL CLOCK DRIVE CIRCUIT
LVPECL OUTPUT
DNP: DO NOT POPULATE.
DNP
DNP
DNP
LVDS OUTPUT
CLIP SINE OUT (DEFAULT)
DNP
12
6
7
25
8
16
9
15
10
14
11
13
3
2
5
18
19
23
22
32
1
31
33
U401
SIGNAL=AVDD_3.3V;4,17,20,21,24,26,29,30
AD9515BCPZ
0Ω
R430
R446
0Ω
R424
R428
0Ω
R425
0Ω
R427
0Ω
1
2
3
J401
10
12 3
5
7
1
8
14
OSC40 1
0Ω
R426
S0
0Ω
R436 R437
0Ω
10kΩ
R413
C401
0.1µF
R401
10kΩ
R403
0Ω
DNP
0.1µF
514C214C
0.1µF
C416
C411
0.1µF
0Ω
R406
0Ω
R415
10kΩ
R402
49.9Ω
R411
R407
0Ω
0Ω
R434
C405
0.1µF
DNP
0.1µF
C406
DNP
0.1µF
C407
DNP
C408
0.1µF
DNP
R444
0Ω
0Ω
R442
R440
0Ω
0Ω
R438
R432
0Ω
0Ω
R445
R443
0Ω
0Ω
R441
R439
0Ω
R435
0Ω
0Ω
R433
R431
0Ω
0Ω
R429
S4
1
E401
AVDD_ 3.3V
0Ω
R416
3
2
1
CR401
HSMS-2812-TR1G
R414
4.12kΩ
S5
S3
S2
S1
AVDD_3.3V
R421
240Ω
C409
0.1µF
R409
DNP
240Ω
R420
6
5
43
2
1
T401
0.1µF
C402
C410
0.1µF
49.9Ω
R404
R410
10kΩ
R412
DNP
DNP
R408
R405
0Ω
C403
0.1µF
100Ω
R423
R422
100Ω
R418
0Ω
R417
0Ω
S0S1S2S3S4S5S6S7S8S9S10
OPT_ CLK
OPT_ CL K
CLK
AVDD_3.3V
OPT_ CL K
OPT_CLK
CLK
CLK
CLK
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
S6
S7
S8
S9
S10
C413
0.1µF0.1µF
814C414C
0.1µF0.1µF
C417
AVDD_3.3V
AVDD_3.3V
P401
P402
05967-075
0.1µF
Figure 93. Evaluation Board Schematic, Clock Circuitry
AD9222
Rev. C | Page 47 of 60
CW
CW
AD8334ACPZ-REEL
INH 2
LMD2
COM2X
LON2
LOP2
VIP2
VIN2
VPS2
VPS3
VIN3
VIP3
LOP3
LON3
COM3X
LMD3
INH 3
COM4
INH4
LMD4
COM4X
LON4
LOP4
VIP4
VIN4
VPS4
HILO
MODE
VPS1
VIN1
VIP1
LOP1
LON1
COM1X
LMD1
INH1
COM1
NC
NC
VOL2
VOH2
COM2
VCM2
COM3
VCM3
VOL3
VOH3
VCM4
VOH4
VOL4
VOL1
VOH1
VCM1
GAIN12
CLMP12
EN12
COM12
VPS12
COM12
EN34
COM34
VPS34
COM34
CLMP34
GAIN34
EXT VG
External
Variable Gain Drive
Variable Gain Circuit
(0−1.0V DC)
HILO Pin=H=+/− 75mV
HILO Pin=LO=+/− 50mV
Rclamp Pin
EXT VG
HILO Pin=H=+/− 75mV
HILO Pin=LO=+/− 50mV
Rclamp Pin
External
Variable Gain Drive
Variable Gain Circuit
(0−1.0V DC)
resistors or design your own filter.
Power Down Enable
(0−1V=Disable Power)
DNP: DO NOT POPULATE.
MODE Pin
Positive Gain Slope = 0−1.0V
Negitive Gain Slope = 2.25−5.0V
Populate L505−L520 with 0Ω
0.1µF
C537
0Ω
L519
0Ω
L515
374Ω
R532
374Ω
R527
DNP
R522
DNP
R517
0.1µF
C530
0.1µF
C529
0.1µF
C528
120nH
L503
0.1µF
C524
0.1µF
C523
0.1µF
C518
374Ω
R515
10kΩ
R504
0.1µF
C504
62
61
60
59
58
57
56
55
54
53
52
51
50
49
33
34
35
36
37
38
39
41
42
43
44
45
46
47
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
63
64
48
40
U501
0.1µF
C506
AVDD_ 5V
10kΩ
R511
10kΩ
R512
10kΩ
R505 AVDD_5V
AVDD_ 5V
AVDD_5V
AVDD_5V
VG34
0.1µF
C538
AVDD_ 5V
AVDD_5V
0.1µF
C505
22pF
C503
VG12
C512
10µF
AVDD_ 5V
AVDD_5V
0.1µF
C501
187Ω
R513
10kΩ
DNP
R506
10kΩ
R501
274Ω
R503
0.018µF
C502
12
JP501
120nH
L501
0.1µF
C508
0.1µF
C509
1000pF
C507
39kΩ
R502
C510
10µF
AVDD_5V
VG12
VG12
GND
R521
DNP
0Ω
L510
R516
DNP
C542
DNP
187Ω
R518
187Ω
R514
0.1µF
C545
0.1µF
C541
0.1µF
C540
0Ω
L505
0Ω
L511
0Ω
L508
0Ω
L507
0Ω
L509
0Ω
L506
0Ω
L512
374Ω
R520
187Ω
R519
0.1µF
C544
C546
DNP
C543
DNP C547
DNP
CH_CCH_D CH_D CH_C
DNP
R534
R533
DNP
0Ω
L518
R528
DNP
C550
DNP
187Ω
R530
187Ω
R526
0.1µF
C553
0.1µF
C549
0.1µF
C548
0Ω
L513
0Ω
L516
0Ω
L517
0Ω
L514
0Ω
L520
187Ω
R531
187Ω
R525
0.1µF
C552
C554
DNP
C551
DNP C555
DNP
DNP
R529
CH_ACH_B CH_B CH_A
INH 4
0.1µF
C511
22pF
C514
0.1µF
C513
120nH
L502
INH3
274Ω
R507
0.018µF
C515
0.1µF
C522
22pF
C520
0.1µF
C519
274Ω
R508
0.018µF
C521
INH 2
C526
22pF
C525
0.1µF
L504
120nH
R509
274Ω
C527
0.018µF
INH 1
0.1µF0.1µF
C536C535C534C533
10µF10µF
10kΩ
DNP
R510
0.1µF
C532
1000pF
C531
10kΩ
R535
1
JP502
39kΩ
R536
AVDD_5V
VG34
VG34
GND
10kΩ
R523
10kΩ
R524
AVDD_5V
0
5967-076
2
Figure 94. Evaluation Board Schematic, Optional DUT Analog Input Drive
AD9222
Rev. C | Page 48 of 60
CW
CW
AD8334ACPZ-REEL
INH 2
LMD2
COM2X
LON2
LOP2
VIP2
VIN2
VPS2
VPS3
VIN3
VIP3
LOP3
LON3
COM3X
LMD3
INH 3
COM4
INH4
LMD4
COM4X
LON4
LOP4
VIP4
VIN4
VPS4
HILO
MODE
VPS1
VIN1
VIP1
LOP1
LON1
COM1X
LMD1
INH1
COM1
NC
NC
VOL2
VOH2
COM2
VCM2
COM3
VCM3
VOL3
VOH3
VCM4
VOH4
VOL4
VOL1
VOH1
VCM1
GAIN12
CLMP12
EN12
COM12
VPS12
COM12
EN34
COM34
VPS34
COM34
CLMP34
GAIN 34
MODE Pin
Positive Gain Slope = 0−1.0V
Negative Gain Slope = 2.25−5.0V
EXT VG
External
Variable Gain Drive
Variable Gain Circuit
(0−1.0V DC)
HILO Pin=H=+/− 75mV
HILO Pin=LO=+/− 50mV
Rclamp Pin
EXT VG
HILO Pin=H=+/− 75mV
HILO Pin=LO=+/− 50mV
Rclamp Pin
External
Variable Gain Drive
Variable Gain Circuit
(0−1.0V DC)
Populate L605−L620 with 0Ω
resistors or design your own filter.
Power Down Enable
(0−1V=Disable Power)
DNP: DO NOT POPULATE.
62
61
60
59
58
57
56
55
54
53
52
51
50
49
33
34
35
36
37
38
39
41
42
43
44
45
46
47
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
63
64
48
40
U601
374Ω
R620
DNP
R636
374Ω
R632
374Ω
R627
DNP
R622
0Ω
L619
0Ω
L611
0.1µF
C630
0.1µF
C629
0.1µF
C628
0.1µF
C624
0.1µF
C623
0.1µF
C618
0.1µF
C616
10kΩ
R604
0.1µF
C604
10kΩ
R612
10kΩ
R624
AVDD_5V
AVDD_5V
AVDD_ 5V
AVDD_5V
VG78
0.1µF
C617
AVDD_5V
AVDD_5V
0.1µF
C605
22pF
C603
0.1µF
C606
VG56
C612
10µF
AVDD_5V
AVDD_5V
0.1µF
C601
187Ω
R613
10kΩ
DNP
R606
10kΩ
R601
274Ω
R603
0.018µF
C602
12
JP601
L601
120nH
0.1µF
C608
0.1µF
C609
10kΩ
R605
1000pF
C607
39kΩ
R602
C610
10µF
AVDD_5V
VG56
VG56
GND
R621
DNP
0Ω
L610
R616
DNP
C642
DNP
374Ω
R615
187Ω
R618
187Ω
R614
0.1µF
C645
0.1µF
C641
0.1µF
C640
0Ω
L605
0Ω
L608
0Ω
L607
0Ω
L609
0Ω
L606
0Ω
L612
187Ω
R619
0.1µF
C644
C646
DNP
C643
DNP C647
DNP
DNP
R617
CH_GCH_H CH_H CH_G
R633
DNP
0Ω
L618
R628
DNP
C650
DNP
187Ω
R630
187Ω
R626
0.1µF
C653
0.1µF
C649
0.1µF
C648
0Ω
L613
0Ω
L616
0Ω
L615
0Ω
L617
0Ω
L614
0Ω
L620
187Ω
R631
187Ω
R625
0.1µF
C652
C654
DNP
C651
DNP C655
DNP
DNP
R629
CH_E
CH_F CH_F CH_E
INH8
0.1µF
C611
22pF
C614
0.1µF
C613
L602
120nH
INH7
274Ω
R607
0.018µF
C615
0.1µF
C622
22pF
C620
0.1µF
C619
L603
120nH
274Ω
R608
C621
INH 6
C626
22pF
C625
0.1µF
L604
120nH
R609
274Ω
C627
0.018µF
INH 5
0.1µF0.1µF
C636
10µF
C634C633
10µF
10kΩ
DNP
R610
0.1µF
C632
1000pF
C631
10kΩ
R634
12
JP602
39kΩ
R635
AVDD_5V
VG78
VG78
GND
10kΩ
R611
AVDD_5V
10kΩ
R623
AVDD_5V
C635
05967-077
0.018µF
Figure 95. Evaluation Board Schematic, Optional DUT Analog Input Drive (Continued)
AD9222
Rev. C | Page 49 of 60
NANOSMDC110F-2
S2A-TP
GP0
GP1
GP2
GP4
GP5
VDD VSS
MCLR/GP3
PIC12F629-I/SNG
4
Y1
VCC
Y2A2
GND
A1
CON005
7.5V POWER
2.5MM JACK
P1
P2
P3
P4
P5
P6
P7
P8
GND
GND
GND
GND
OUT
Y1
VCC
Y2A2
GND
A1
OPTIONAL
+3.3V = NORMAL OPERATION = AVDD_3.3V
+5V = PROGRAMMING = AVDD_5V
RESET/ REPROGRAM
ISPPIC PROGRAMMING HEADER
REMOVE WHEN USING OR PROGRAMMING PIC (U402)
SPI CIRCUITRY FROM FIFO
Power Supply Input
Input
6V, 2A max
+5.0V
DNP: DO NOT POPULATE.
+1.8V
+1.8V
+3.3V
Decoupling Capacitors
Optional Power
D702
6
5
4
3
2
1
U703
NC7WZ16P6X_NL
3.3V_AVDD
5V_AVDD
DUT_AVDD
DUT_DRVDD
L701
10µH
AVDD_5V
1
2
3
4
U707
ADP33 39ZAKC−1.8-RL
AVDD_5V
AVDD_DUT
CR702
GREEN
MCLR/GP3
CR701
GREEN
4
2
3
1
ADP3339ZAKC−5-RL7
U706
1
2
3
4
U704
ADP3339ZAKC−1.8-RL
4
2
3
1
ADP3339ZAKC−3.3-RL
U705
2
43
1
FER701
1
2
3
4
5
6
7
8
P702
DNP
1
3
2
P701
1
2
34
5
6
NC7W207P6X_NL
U702
1kΩ
R713
0Ω
R709
R708 0Ω
0Ω
0ΩR706
2
4
6
8
10
9
7
5
3
1
J702
1
2
3
S701
4
3
7
6
5
2
8
1
U701
0.1µF
C726
0.1µF
C742
AVDD_DUT
0.1µF
C730
D701
F70 1
AVDD_3.3V
0.1µF
C740
0.1µF
C741
L702
10µH
C710
0.1µF
C709
10µF
10µH
L705
R716
261Ω
10µH
L706
L704
10µH
C715
1µF
0.1µF
C708
0.1µF
C712
C706
0.1µF
C717
1µF
C716
1µF
C714
1µF
PWR_IN
PWR_IN
10µF
C707
C705
10µF
10µF
C711
DUT_AVDD
DUT_DRVDD
0.1µF
C735
0.1µF
C734
0.1µF
C733
0.1µF
C727
0.1µF
C732
0.1µF
C731
0.1µF
C743
0.1µF
C723 0.1µF
C725
0.1µF
C724
10µH
L703
5V_AVDD
3.3V_AVDD
PWR_IN
PWR_IN
1µF
C719
1µF
C721 1µF
C722
1µF
C720
L708
10µH
L707
10µH
DRVDD_DUT
1kΩ
R712
1kΩ
R710
R707
C701
0.1µF
R715
10kΩ
10kΩ
R711
0.1µF
C703
R704
0Ω−DNP
0Ω−DNP
R703
0Ω−DNP
R705
261Ω
R702
3
2
1
J701
R701
4.7kΩ
1
E701
C702
0.1µF
10kΩ
R714
PICVCC
GP1
GP0
MCLR/GP3
PICVCC
AVDD_DUT
AVDD_ 3.3V AVDD_5V
AVDD_DUT
SCLK_DTP
CSB_DUT
AVDD_3.3V
GP0
CSB1_CHA
SCLK_CHA
SDI_CHA
GP1
SDO_CHA
AVDD_DUT
SDIO_ODM
PWR_IN
AVDD_3.3V
AVDD_5V
AVDD_DUT
DRVDD_DUT
0.1µF
C744 0.1µF
C748
0.1µF
C747
0.1µF
C746
0.1µF
C745
0.1µF
C752
0.1µF
C753
0.1µF
C749 0.1µF
C751
0.1µF
C750
C704
10µF
0
5967-078
IN
IN OUT
OUT
OUT
SK33-TP
OUT
IN
IN OUT
OUT
OUT
Figure 96. Evaluation Board Schematic, Power Supply Inputs and SPI Interface Circuitry
AD9222
Rev. C | Page 50 of 60
05967-079
Figure 97. Evaluation Board Layout, Primary Side
AD9222
Rev. C | Page 51 of 60
05967-080
Figure 98. Evaluation Board Layout, Ground Plane
AD9222
Rev. C | Page 52 of 60
05967-081
Figure 99. Evaluation Board Layout, Power Plane
AD9222
Rev. C | Page 53 of 60
05967-082
Figure 100. Evaluation Board Layout, Secondary Side (Mirrored Image)
AD9222
Rev. C | Page 54 of 60
Table 17. Evaluation Board Bill of Materials (BOM)1
Item
Qnty.
per
Board
Reference
Designator Device Pkg. Value Mfg. Mfg. Part Number
1 1 AD9222-65EBZ PCB PCB PCB
2 118
C101, C102, C107,
C108, C109, C114,
C115, C116, C121,
C122, C123, C128,
C201, C202, C207,
C208, C209, C214,
C215, C216, C221,
C222, C223, C228,
C301, C302, C304,
C305, C306, C401,
C402, C403, C409,
C410, C411, C412,
C413, C414, C415,
C416, C417, C418,
C501, C504, C505,
C506, C508, C509,
C511, C513, C518,
C519, C522, C523,
C524, C525, C528,
C529, C530, C532,
C534, C536, C537,
C538, C601, C604,
C605, C606, C608,
C609, C611, C613,
C616, C617, C618,
C619, C622, C623,
C624, C625, C628,
C629, C630, C632,
C634, C636, C701,
C702, C703, C706,
C708, C710, C712,
C723, C724, C725,
C726, C727, C730,
C731, C732, C733,
C734, C735, C740,
C741, C742, C743,
C744, C745, C746,
C747, C748, C749,
C750, C751, C752,
C753
Capacitor 402 0.1 μF, ceramic, X5R,
10 V, 10% tol
Murata GRM155R71C104KA88D
3 8 C104, C111, C118,
C125, C204, C211,
C218, C225
Capacitor 402 2.2 pF, ceramic, COG,
0.25 pF tol, 50 V
Murata GRM1555C1H2R20CZ01D
4 8 C510, C512, C533,
C535, C610, C612,
C633, C635
Capacitor 805 10 μF, 6.3 V ±10%
ceramic, X5R
Murata GRM219R60J106KE19D
5 1 C303 Capacitor 603 4.7 μF, ceramic, X5R,
6.3 V, 10% tol
Murata GRM188R60J475KE19D
6 4 C507, C531, C607,
C631
Capacitor 402 1000 pF, ceramic, X7R,
25 V, 10% tol
Murata GRM155R71H102KA01D
7 8 C502, C515, C521,
C527, C602, C615,
C621, C627
Capacitor 402 0.018 μF, ceramic, X7R,
16 V, 10% tol
AVX 0402YC183KAT2A
AD9222
Rev. C | Page 55 of 60
Item
Qnty.
per
Board
Reference
Designator Device Pkg. Value Mfg. Mfg. Part Number
8 8 C503, C514, C520,
C526, C603, C614,
C620, C626
Capacitor 402 22 pF, ceramic, NPO,
5% tol, 50 V
Murata GRM1555C1H220JZ01D
9 1 C704 Capacitor 1206 10 μF, tantalum,
16 V, 20% tol
Rohm TCA1C106M8R
10 9 C307, C714, C715,
C716, C717, C719,
C720, C721, C722
Capacitor 603 1 μF, ceramic, X5R,
6.3 V, 10% tol
Murata GRM188R61C105KA93D
11 16 C540, C541, C544,
C545, C548, C549,
C552, C553, C640,
C641, C644, C645,
C648, C649, C652,
C653
Capacitor 805 0.1 μF, ceramic, X7R,
50 V, 10% tol
Murata GRM21BR71H104KA01L
12 4 C705, C707, C709,
C711
Capacitor 603 10 μF, ceramic, X5R,
6.3 V, 20% tol
Murata GRM188R60J106ME47D
13 1 CR401 Diode SOT-23 30 V, 20 mA, dual
Schottky
Avago
Technologies
HSMS-2812-TR1G
14 2 CR701, CR702 LED 603 Green, 4 V, 5 m candela Panasonic LNJ314G8TRA
15 1 D702 Diode DO-214AB 3 A, 30 V, SMC Micro
Commercial Co.
SK33-TP
16 1 D701 Diode DO-214AA 5 A, 50 V, SMC Micro
Commercial Co.
S2A-TP
17 1 F701 Fuse 1210 6.0 V, 2.2 A trip-current
resettable fuse
Tyco/Raychem NANOSMDC110F-2
18 1 FER701 Choke coil 2020 10 μH, 5 A, 50 V, 190 Ω
@ 100 MHz
Murata DLW5BSN191SQ2L
19 24 FB101, FB102,
FB103, FB104,
FB105, FB106,
FB107, FB108,
FB109, FB110,
FB111, FB112,
FB201, FB202,
FB203, FB204,
FB205, FB206,
FB207, FB208,
FB209, FB210,
FB211, FB212
Ferrite bead 603 10 Ω, test frequency
100 MHz, 25% tol,
500 mA
Murata BLM18BA100SN1D
20 4 JP501, JP502,
JP601, JP602
Connector 2-pin 100 mil header jumper,
2-pin
Samtec TSW-102-07-G-S
21 6 J301, J302, J303,
J304, J401, J701
Connector 3-pin 100 mil header jumper,
3-pin
Samtec TSW-103-07-G-S
23 1 J702 Connector 10-pin 100 mil header, male,
2 × 5 double row
straight
Samtec TSW-105-08-G-D
24 8 L701, L702, L703,
L704, L705, L706,
L707, L708
Ferrite bead 1210 10 μH, bead core 3.2 ×
2.5 × 1.6 SMD, 2 A
Murata BLM31PG500SN1L
25 8 L501, L502, L503,
L504, L601, L602,
L603, L604
Inductor 402 120 nH, test freq
100 MHz, 5% tol,
150 mA
Murata LQG15HNR12J02D
AD9222
Rev. C | Page 56 of 60
Item
Qnty.
per
Board
Reference
Designator Device Pkg. Value Mfg. Mfg. Part Number
26 32 L505, L506, L507,
L508, L509, L510,
L511, L512, L513,
L514, L515, L516,
L517, L518, L519,
L520, L605, L606,
L607, L608, L609,
L610, L611, L612,
L613, L614, L615,
L616, L617, L618,
L619, L620
Resistor 805 0 Ω, 1/8 W, 5% tol NIC
Components
Corp.
NRC04Z0TRF
27 1 OSC401 Oscillator SMT Clock oscillator,
50.00 MHz, 3.3 V,
±5% duty cycle
Valphey Fisher VFAC3H-L-50MHz
28 9 P101, P103, P105,
P107, P201, P203,
P205, P207, P401
Connector SMA Side-mount SMA for
0.063" board thickness
Johnson
Components
142-0701-851
29 1 P301 Connector HEADER 1469169-1, right angle
2-pair, 25 mm, header
assembly
Tyco 6469169-1
30 1 P701 Connector 0.1", PCMT
RAPC722, power
supply connector
Switchcraft RAPC722X
31 21 R301, R307, R401,
R402, R410, R413,
R504, R505, R511,
R512, R523, R524,
R604, R605, R611,
R612, R623, R624,
R711, R714, R715
Resistor 402 10 kΩ, 1/16 W,
5% tol
NIC
Components
Corp.
NRC04J103TRF
32 18 R103, R117, R129,
R142, R203, R219,
R235, R253, R317,
R405, R415, R416,
R417, R418, R706,
R707, R708, R709
Resistor 402 0 Ω, 1/16 W,
5% tol
NIC
Components
Corp.
NRC04Z0TRF
33 8 R102, R115, R128,
R141, R202, R218,
R234, R252
Resistor 402 64.9 Ω, 1/16 W,
1% tol
NIC
Components
Corp.
NRC04F64R9TRF
34 8 R104, R116, R130,
R143, R204, R220,
R236, R254
Resistor 603 0 Ω, 1/10 W,
5% tol
NIC
Components
Corp.
NRC06Z0TRF
35 28 R109, R111, R112,
R123, R125, R126,
R135, R138, R139,
R148, R149, R150,
R211, R212, R214,
R228, R231, R232,
R246, R249, R250,
R262, R265, R266,
R319, R710, R712,
R713
Resistor 402 1 kΩ, 1/16 W,
1% tol
NIC
Components
Corp.
NRC04F1001TRF
36 16 R108, R110, R121,
R122, R134, R136,
R146, R147, R209,
R210, R226, R227,
R242, R245, R260,
R261
Resistor 402 33 Ω, 1/16 W,
5% tol
NIC
Components
Corp.
NRC04J330TRF
AD9222
Rev. C | Page 57 of 60
Item
Qnty.
per
Board
Reference
Designator Device Pkg. Value Mfg. Mfg. Part Number
37 8 R161, R162, R163,
R164, R208, R225,
R241, R259
Resistor 402 499 Ω, 1/16 W,
1% tol
NIC
Components
Corp.
NRC04F4990TRF
38 3 R303, R305, R306 Resistor 402 100 kΩ, 1/16 W,
1% tol
NIC
Components
Corp.
NRC04F1003TRF
39 1 R414 Resistor 402 4.12 kΩ, 1/16W,
1% tol
NIC
Components
Corp.
NRC04F4121TRF
40 1 R404 Resistor 402 49.9 Ω, 1/16 W,
0.5% tol
Susumu RR0510R-49R9-D
41 1 R309 Resistor 402 4.99 kΩ, 1/16 W,
5% tol
NIC
Components
Corp.
NRC04F4991TRF
42 5 R310, R501, R535,
R601, R634
Potentiometer 3-lead 10 kΩ, Cermet trimmer
potentiometer, 18 turn
top adjust, 10%, 1/2 W
COPAL
ELECTRONICS
CT94EW103
43 1 R308 Resistor 402 470 kΩ, 1/16 W,
5% tol
NIC
Components
Corp.
NRC04J474TRF
44 4 R502, R536, R602,
R635
Resistor 402 39 kΩ, 1/16 W,
5% tol
NIC
Components
Corp.
NRC04J393TRF
45 16 R513, R514, R518,
R519, R525, R526,
R530, R531, R613,
R614, R618, R619,
R625, R626, R630,
R631
Resistor 402 187 Ω, 1/16 W,
1% tol
NIC
Components
Corp.
NRC04F1870TRF
46 8 R515, R520, R527,
R532, R615, R620,
R627, R632
Resistor 402 374 Ω, 1/16 W,
1% tol
NIC
Components
Corp.
NRC04F3740TRF
47 8 R503, R507, R508,
R509, R603, R607,
R608, R609
Resistor 402 274 Ω, 1/16 W,
1% tol
NIC
Components
Corp.
NRC04F2740TRF
48 11 R425,R427, R429,
R431, R433, R435,
R436, R439, R441,
R443, R445
Resistor 201 0 Ω, 1/20 W,
5% tol
NIC
Components
Corp.
NRC02Z0TRF
49 1 R701 Resistor 402 4.7 kΩ, 1/16 W,
1% tol
NIC
Components
Corp.
NRC04J472TRF
50 1 R702 Resistor 402 261 Ω, 1/16 W,
1% tol
NIC
Components
Corp.
NRC04F2610TRF
51 1 R716 Resistor 603 261 Ω, 1/16 W,
1% tol
NIC
Components
Corp.
NRC06F261OTRF
52 2 R420, R421 Resistor 402 240 Ω, 1/16 W,
5% tol
NIC
Components
Corp.
NRC04J241TRF
53 2 R422, R423 Resistor 402 100 Ω, 1/16 W,
1% tol
NIC
Components
Corp.
NRC04F1000TRF
54 1 S701 Switch SMD LIGHT TOUCH,
100GE, 5 mm
Panasonic EVQ-PLDA15
AD9222
Rev. C | Page 58 of 60
Item
Qnty.
per
Board
Reference
Designator Device Pkg. Value Mfg. Mfg. Part Number
55 9 T101, T102, T103,
T104, T201, T202,
T203, T204, T401
Transformer CD542 ADT1-1WT+,
1:1 impedance ratio
transformer
Mini-Circuits ADT1-1WT+
56 2 U704, U707 IC SOT-223 ADP33339AKC-1.8-RL,
1.5 A, 1.8 V LDO
regulator
Analog Devices ADP3339AKCZ-1.8-RL
57 2 U501, U601 IC CP-64-3 AD8334ACPZ-REEL,
ultralow noise
precision dual VGA
Analog Devices AD8334ACPZ-REEL
58 1 U706 IC SOT-223 ADP3339AKC-5-RL7 Analog Devices ADP3339AKCZ-5-RL
59 1 U705 IC SOT-223 ADP3339AKC-3.3-RL Analog Devices ADP3339AKCZ-3.3-RL
60 1 U301 IC CP-64-3 AD9222BCPZ-65, octal,
12-bit, 50 MSPS serial
LVDS 1.8 V ADC
Analog Devices AD9222BCPZ-65
61 1 U302 IC SOT-23 ADR510ARTZ, 1.0 V,
precision low noise
shunt voltage
reference
Analog Devices ADR510ARTZ
62 1 U401 IC LFCSP
CP-32-2
AD9515BCPZ, 1.6 GHz
clock distribution IC
Analog Devices AD9515BCPZ
63 1 U702 IC SC70,
MAA06A
NC7WZ07P6X_NL,
UHS dual buffer
Fairchild NC7WZ07P6X_NL
64 1 U703 IC SC70,
MAA06A
NC7WZ16P6X_NL,
UHS dual buffer
Fairchild NC7WZ16P6X_NL
65 1 U701 IC 8-SOIC Flash prog
mem 1kx14,
RAM size 64 × 8,
20 MHz speed, PIC12F
controller series
Microchip PIC12F629-I/SNG
1 This BOM is RoHS compliant.
AD9222
Rev. C | Page 59 of 60
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
080108-C
0.25 MIN
TOP VIEW 8.75
BSC SQ
9.00
BSC SQ
1
64
16
17
49
48
32
33
0.50
0.40
0.30
0.50
BSC
0.20 REF
12° MAX 0.80 MAX
0.65 TYP
1.00
0.85
0.80
7.50
REF
0.05 MAX
0.02 NOM
0.60 MAX
0.60
MAX
EXPOSED PAD
(BOTTOM VIEW)
SEATING
PLANE
PIN 1
INDICATOR
7.25
7.10 SQ
6.95
PIN 1
INDICATOR
0.30
0.23
0.18
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 101. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-3)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
041509-A
0.25 MIN
TOP VIEW 8.75
BSC SQ
9.00
BSC SQ
1
64
16
17
49
48
32
33
0.50
0.40
0.30
0.50
BSC
0.20 REF
12° MAX 0.80 MAX
0.65 TYP
1.00
0.85
0.80
7.50
REF
0.05 MAX
0.02 NOM
0.60 MAX
0.60
MAX
EXPOSED PAD
(BOTTOM VIEW)
SEATING
PLANE
PIN 1
INDICATOR
7.65
7.50 SQ
7.35
PIN 1
INDICATOR
0.30
0.23
0.18
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 102. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-6)
Dimensions shown in millimeters
AD9222
Rev. C | Page 60 of 60
ORDERING GUIDE
Model1Temperature Range Package Description Package Option
AD9222ABCPZ-402
−40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6
AD9222ABCPZRL7-402
−40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel CP-64-6
AD9222ABCPZ-502
−40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6
AD9222ABCPZRL7-502
−40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel CP-64-6
AD9222ABCPZ-652
−40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6
AD9222ABCPZRL7-652
−40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel CP-64-6
AD9222BCPZ-40 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-3
AD9222BCPZRL7-40 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel CP-64-3
AD9222BCPZ-50 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-3
AD9222BCPZRL7-50 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel CP-64-3
AD9222BCPZ-65 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-3
AD9222BCPZRL7-65 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel CP-64-3
AD9222-65EBZ Evaluation Board
1 Z = RoHS Compliant Part.
2 Recommended for use in new designs; reference PCN 09_0156.
©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05967-0-1/10(C)
