Octal, 12-Bit, 40/50/65 MSPS Serial LVDS 1.8 V A/D Converter AD9222 8 ADCs integrated into 1 package 114 mW ADC power per channel at 65 MSPS SNR = 70 dB (to Nyquist) ENOB = 11.3 bits SFDR = 80 dBc Excellent linearity: DNL = 0.3 LSB (typical), INL = 0.4 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar IEEE 1596.3) Data and frame clock outputs 325 MHz full-power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment FUNCTIONAL BLOCK DIAGRAM AVDD AD9222 The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable DRGND 12 VIN + A VIN - A ADC VIN + B VIN - B ADC VIN + C VIN - C ADC VIN + D VIN - D ADC VIN + E VIN - E ADC VIN + F VIN - F ADC VIN + G VIN - G ADC VIN + H VIN - H ADC SERIAL LVDS D+A D-A SERIAL LVDS D+B D-B SERIAL LVDS D+C D-C SERIAL LVDS D+D D-D SERIAL LVDS D+E D-E SERIAL LVDS D+F D-F SERIAL LVDS D+G D-G SERIAL LVDS D+H D-H 12 12 12 12 12 12 12 VREF SENSE FCO + 0.5V REFT REFB REF SELECT RBIAS GENERAL DESCRIPTION The AD9222 is an octal, 12-bit, 40/50/65 MSPS analog-todigital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. DRVDD PDWN SERIAL PORT INTERFACE AGND CSB SDIO/ ODM SCLK/ DTP DATA RATE MULTIPLIER CLK+ CLK- FCO - DCO + DCO - 05967-001 FEATURES Figure 1. clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom userdefined test patterns entered via the serial port interface (SPI). The AD9222 is available in an RoHS compliant, 64-lead LFCSP. It is specified over the industrial temperature range of -40C to +85C. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. Small Footprint. Eight ADCs are contained in a small, space-saving package. Low power of 114 mW/channel at 65 MSPS. Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 390 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. Pin-Compatible Family. This includes the AD9212 (10-bit) and AD9252 (14-bit). Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006-2010 Analog Devices, Inc. All rights reserved. AD9222 TABLE OF CONTENTS Features .............................................................................................. 1 Analog Input Considerations ................................................... 21 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 24 General Description ......................................................................... 1 Serial Port Interface (SPI) .............................................................. 33 Functional Block Diagram .............................................................. 1 Hardware Interface..................................................................... 34 Product Highlights ........................................................................... 1 Memory Map .................................................................................. 36 Revision History ............................................................................... 2 Reading the Memory Map Table .............................................. 36 Specifications..................................................................................... 3 Reserved Locations .................................................................... 36 AC Specifications.......................................................................... 4 Default Values ............................................................................. 36 Digital Specifications ................................................................... 5 Logic Levels ................................................................................. 36 Switching Specifications .............................................................. 6 Evaluation Board ............................................................................ 40 Timing Diagrams .............................................................................. 7 Power Supplies ............................................................................ 40 Absolute Maximum Ratings............................................................ 9 Input Signals................................................................................ 40 Thermal Impedance ..................................................................... 9 Output Signals ............................................................................ 40 ESD Caution .................................................................................. 9 Default Operation and Jumper Selection Settings ................. 41 Pin Configuration and Function Descriptions ........................... 10 Alternative Analog Input Drive Configuration...................... 42 Equivalent Circuits ......................................................................... 12 Outline Dimensions ....................................................................... 59 Typical Performance Characteristics ........................................... 14 Ordering Guide .......................................................................... 60 Theory of Operation ...................................................................... 21 REVISION HISTORY 1/10--Rev. B to Rev. C Updated Outline Dimensions ....................................................... 59 Changes to Ordering Guide .......................................................... 60 7/09--Rev. A to Rev. B Changes to Figure 5 ........................................................................ 10 Changes to Figure 61 and Figure 62 ............................................. 23 Changes to Figure 79 and Figure 80 ............................................. 31 Updated Outline Dimensions ....................................................... 59 Changes to Ordering Guide .......................................................... 59 8/07--Rev. 0 to Rev. A Added 65 MSPS Models .................................................... Universal Changes to Features.......................................................................... 1 Changes to Product Highlights....................................................... 1 Changes to Figure 2 to Figure 4 ...................................................... 7 Added Figure 21 to Figure 24, Figure 27, Figure 28, Figure 30, Figure 32, Figure 37, Figure 38, Figure 40, Figure 42, Figure 44, Figure 46, Figure 48, and Figure 51 ............................................. 15 Added Figure 56 and Figure 58..................................................... 22 Added Figure 70.............................................................................. 25 Added Figure 72.............................................................................. 26 Added Figure 74 ............................................................................. 27 Added Figure 76 and Figure 78 .................................................... 28 Changes to Digital Outputs and Timing Section ....................... 28 Changes to Table 9 Endnote.......................................................... 29 Added Table 10 ............................................................................... 30 Changes to RBIAS Pin Section ..................................................... 31 Deleted Figure 56 and Figure 57 .................................................. 27 Changes to Table 15 ....................................................................... 35 Change to Input Signals Section................................................... 40 Change to Output Signals Section ............................................... 40 Changes to Figure 86...................................................................... 40 Changes to Default Operation and Jumper Selection Settings Section ............................................................................... 41 Changes to Alternative Analog Input Configuration Section ......... 42 Added Figure 88 and Figure 89 .................................................... 42 Change to Figure 92 ....................................................................... 45 Changes to Table 17 ....................................................................... 54 Updated Outline Dimensions ....................................................... 59 Changes to Ordering Guide .......................................................... 60 9/06--Revision 0: Initial Version Rev. C | Page 2 of 60 AD9222 SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, unless otherwise noted. Table 1. Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Voltage (1 V Mode) REFERENCE Output Voltage Error (VREF = 1 V) Load Regulation @ 1.0 mA (VREF = 1 V) Input Resistance ANALOG INPUTS Differential Input Voltage Range (VREF = 1 V) Common-Mode Voltage Differential Input Capacitance Analog Bandwidth, Full Power POWER SUPPLY AVDD DRVDD IAVDD IDRVDD Total Power Dissipation (Including Output Drivers) Power-Down Dissipation Standby Dissipation 2 CROSSTALK CROSSTALK (Overrange Condition) 3 Temp Min 12 Full Full Full Full Full Full Full AD9222-40 Typ Max Min 12 Guaranteed 1 8 3 8 0.4 1.2 0.3 0.7 0.25 0.5 0.4 1 AD9222-50 Typ Max Min 12 Guaranteed 1 8 3 8 1.5 2.5 0.3 0.7 0.3 0.65 0.4 1 AD9222-65 Typ Max Guaranteed 1 8 3 8 3.5 5 0.4 0.8 0.25 0.6 0.4 1 2 17 21 Full Full Full 2 3 6 Full 2 2 2 V p-p Full Full Full AVDD/2 7 325 AVDD/2 7 325 AVDD/2 7 325 V pF MHz Full Full Full Full 1.7 1.7 30 1.8 1.8 338 51 700 1.9 1.9 348.5 53.6 722 2 83 -90 -90 11 2 3 6 1.7 1.7 1 2 17 21 mV mV % FS % FS LSB LSB Full Full Full Full Full Full Full Full 2 17 21 Unit Bits 30 1.8 1.8 357.5 53.5 740 1.9 1.9 367.5 56.2 760 2 89 -90 -90 11 2 3 6 1.7 1.7 ppm/C ppm/C ppm/C 30 mV mV k 1.8 1.8 450 56.6 910 1.9 1.9 470 60.5 950.5 V V mA mA mW 2 100 -90 -90 11 mW mW dB dB See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. This can be controlled via SPI. 3 Overrange condition is specific with 6 dB of the full-scale input range. 2 Rev. C | Page 3 of 60 AD9222 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz WORST HARMONIC (Second or Third) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz WORST OTHER (Excluding Second or Third) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz TWO-TONE INTERMODULATION DISTORTION (IMD)-- AIN1 AND AIN2 = -7.0 dBFS fIN1 = 15 MHz, fIN2 = 16 MHz fIN1 = 70 MHz, fIN2 = 71 MHz 1 Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Min AD9222-40 Typ Max 69.5 68.7 11.25 73 70.3 70.3 69.9 68.8 68.5 11.38 11.38 11.32 11.14 11.25 85 85 80 76 -85 -85 -80 -76 Full Full Full Full -92 -92 -92 -90 25C 25C 80.0 77.0 AD9222-50 Typ Max 69.5 70.0 70.0 69.5 68.0 Full Full Full Full Min 73 -74 -80 70.4 70.3 70.0 69.0 68.5 70.0 70.0 69.8 68.5 66.8 11.4 11.38 11.33 11.17 11.1 85 84 83 77 -85 -84 -83 -77 -92 -92 -92 -90 80.0 77.0 Min 70.5 -73 -80 AD9222-65 Typ Max 70.3 70.0 69.8 69.5 dB dB dB dB 69.5 69.4 69.3 69 dB dB dB dB 11.4 11.34 11.30 11.25 Bits Bits Bits Bits 83 80 80 75 dBc dBc dBc dBc -83 -80 -80 -75 -90 -90 -90 -85 -70.5 -80 80.0 75.0 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Rev. C | Page 4 of 60 Unit dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc AD9222 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, unless otherwise noted. Table 3. Parameter 1 CLOCK INPUTS (CLK+, CLK-) Logic Compliance Differential Input Voltage 2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, SCLK/DTP) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO/ODM) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO/ODM) 3 Logic 1 Voltage (IOH = 800 A) Logic 0 Voltage (IOL = 50 A) DIGITAL OUTPUTS (D + x, D - x), (ANSI-644)1 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (D + x, D - x), (Low Power, Reduced Signal Option)1 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) 1 2 3 Temp Min Full Full 25C 25C 250 Full Full 25C 25C 1.2 0 Full Full 25C 25C 1.2 0 Full Full 25C 25C 1.2 0 AD9222-40 Typ Max Min CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL 250 1.2 20 1.5 1.2 20 1.5 3.6 0.3 1.2 30 0.5 3.6 0.3 3.6 0.3 1.2 DRVDD + 0.3 0.3 247 1.125 LVDS 454 1.375 Offset binary 150 1.10 DRVDD + 0.3 0.3 V V k pF 250 1.30 Offset binary V V LVDS 247 1.125 LVDS 250 1.30 Offset binary V V k pF 0.05 LVDS 454 1.375 Offset binary 3.6 0.3 1.79 0.05 mV p-p V k pF V V k pF 30 2 1.79 LVDS 150 1.10 1.2 0 Unit 3.6 0.3 70 0.5 DRVDD + 0.3 0.3 0.05 Full Full 1.2 30 2 1.79 247 1.125 1.2 30 0.5 3.6 0.3 1.2 0 AD9222-65 Typ Max CMOS/LVDS/LVPECL 250 1.2 20 1.5 70 0.5 30 2 Full Full Min 30 0.5 70 0.5 Full Full AD9222-50 Typ Max 454 1.375 Offset binary mV V LVDS 150 1.10 250 1.30 Offset binary mV V See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. This is specified for LVDS and LVPECL only. This is specified for 13 SDIO pins sharing the same connection. Rev. C | Page 5 of 60 AD9222 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, unless otherwise noted. Table 4. AD9222-40 Typ Max AD9222-50 Typ Max AD9222-65 Typ Max Parameter 1 CLOCK 2 Maximum Clock Rate Minimum Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) Temp Min Full Full Full Full 40 OUTPUT PARAMETERS2, 3 Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) FCO Propagation Delay (tFCO) DCO Propagation Delay (tCPD)4 Full Full Full Full Full 1.5 DCO to Data Delay (tDATA)4 Full DCO to FCO Delay (tFRAME)4 Full (tSAMPLE/24) - 300 (tSAMPLE/24) - 300 Data to Data Skew (tDATA-MAX - tDATA-MIN) Wake-Up Time (Standby) Wake-Up Time (Power-Down) Pipeline Latency Full 50 25C 25C Full 600 375 8 600 375 8 600 375 8 ns s CLK cycles APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) 25C 25C 750 <1 750 <1 750 <1 25C 1 1 1 ps ps rms CLK cycles Out-of-Range Recovery Time Min 50 65 10 10 12.5 12.5 1.5 2.3 300 300 2.3 tFCO + (tSAMPLE/24) (tSAMPLE/24) (tSAMPLE/24) Min 10 10.0 10.0 3.1 1.5 3.1 1.5 (tSAMPLE/24) + 300 (tSAMPLE/24) + 300 200 (tSAMPLE/24) - 300 (tSAMPLE/24) - 300 1 2.3 300 300 2.3 tFCO + (tSAMPLE/24) (tSAMPLE/24) (tSAMPLE/24) 50 7.5 7.5 3.1 1.5 3.1 1.5 (tSAMPLE/24) + 300 (tSAMPLE/24) + 300 200 (tSAMPLE/24) - 300 (tSAMPLE/24) - 300 2.3 300 300 2.3 tFCO + (tSAMPLE/24) (tSAMPLE/24) (tSAMPLE/24) 50 3.1 3.1 (tSAMPLE/24) + 300 (tSAMPLE/24) + 300 200 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. This can be adjusted via the SPI interface. 3 Measurements were made using a part soldered to FR4 material. 4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles. 2 Rev. C | Page 6 of 60 Unit MSPS MSPS ns ns ns ps ps ns ns ps ps ps AD9222 TIMING DIAGRAMS N-1 tA VIN x N tEH CLK- tEL CLK+ tCPD DCO- DCO+ tFRAME tFCO FCO- FCO+ tPD MSB N-9 D10 N-9 D9 N-9 D8 N-9 D7 N-9 D6 N-9 D5 N-9 D4 N-9 D3 N-9 D2 N-9 D1 N-9 D0 N-9 MSB N-8 D10 N-8 D+x 05967-002 tDATA D-x Figure 2. 12-Bit Data Serial Stream, MSB First (Default) N-1 VIN x tA N tEL tEH CLK- CLK+ tCPD DCO- DCO+ tFRAME tFCO FCO- FCO+ tPD tDATA D-x MSB N-9 D8 N-9 D7 N-9 D6 N-9 D5 N-9 D4 N-9 D3 N-9 D2 N-9 D0 N-9 MSB N-8 D8 N-8 D7 N-8 D6 N-8 D5 N-8 05967-003 D+x D1 N-9 Figure 3. 10-Bit Data Serial Stream, MSB First Rev. C | Page 7 of 60 AD9222 N-1 VIN x tA N tEL tEH CLK- CLK+ tCPD DCO- DCO+ tFRAME tFCO FCO- FCO+ tPD tDATA D-x D0 N-9 D1 N-9 D2 N-9 D3 N-9 D4 N-9 D5 N-9 D6 N-9 D7 N-9 D8 N-9 D9 N-9 D10 N-9 LSB N-8 D0 N-8 05967-004 LSB N-9 D+x Figure 4. 12-Bit Data Serial Stream, LSB First Rev. C | Page 8 of 60 AD9222 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs (D + x, D - x, DCO+, DCO-, FCO+, FCO-) CLK+, CLK- VIN + x, VIN - x SDIO/ODM PDWN, SCLK/DTP, CSB REFT, REFB, RBIAS VREF, SENSE ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) With Respect To Rating AGND DRGND DRGND DRVDD DRGND -0.3 V to +2.0 V -0.3 V to +2.0 V -0.3 V to +0.3 V -2.0 V to +2.0 V -0.3 V to +2.0 V AGND AGND AGND AGND AGND AGND -0.3 V to +3.9 V -0.3 V to +2.0 V -0.3 V to +2.0 V -0.3 V to +3.9 V -0.3 V to +2.0 V -0.3 V to +2.0 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL IMPEDANCE Table 6. Air Flow Velocity (m/s) 0.0 1.0 2.5 1 JB JC 8.7C/W 0.6C/W JA for a 4-layer PCB with solid ground plane (simulated). Exposed pad soldered to PCB. -40C to +85C ESD CAUTION 150C JA1 17.7C/W 15.5C/W 13.9C/W 300C -65C to +150C Rev. C | Page 9 of 60 AD9222 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VIN + F VIN - F AVDD VIN - E VIN + E AVDD REFT REFB VREF SENSE RBIAS VIN + D VIN - D AVDD VIN - C VIN + C PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) AD9222 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AVDD VIN + B VIN - B AVDD VIN - A VIN + A AVDD PDWN CSB SDIO/ODM SCLK/DTP AVDD DRGND DRVDD D+A D-A NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND Figure 5. 64-Lead LFCSP Pin Configuration, Top View Table 7. Pin Function Descriptions Pin No. 0 1, 4, 7, 8, 11, 12, 37, 42, 45, 48, 51, 59, 62 13, 36 14, 35 2 3 5 6 9 10 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Mnemonic AGND AVDD Description Analog Ground (Exposed Paddle) 1.8 V Analog Supply DRGND DRVDD VIN + G VIN - G VIN - H VIN + H CLK- CLK+ D-H D+H D-G D+G D-F D+F D-E D+E DCO- DCO+ FCO- FCO+ D-D D+D D-C D+C D-B D+B Digital Output Driver Ground 1.8 V Digital Output Driver Supply ADC G Analog Input True ADC G Analog Input Complement ADC H Analog Input Complement ADC H Analog Input True Input Clock Complement Input Clock True ADC H Digital Output Complement ADC H Digital Output True ADC G Digital Output Complement ADC G Digital Output True ADC F Digital Output Complement ADC F Digital Output True ADC E Digital Output Complement ADC E Digital Output True Data Clock Digital Output Complement Data Clock Digital Output True Frame Clock Digital Output Complement Frame Clock Digital Output True ADC D Digital Output Complement ADC D Digital Output True ADC C Digital Output Complement ADC C Digital Output True ADC B Digital Output Complement ADC B Digital Output True Rev. C | Page 10 of 60 05967-005 D-G D+G D-F D+F D-E D+E DCO- DCO+ FCO- FCO+ D-D D+D D-C D+C D-B D+B 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVDD VIN + G VIN - G AVDD VIN - H VIN + H AVDD AVDD CLK- CLK+ AVDD AVDD DRGND DRVDD D-H D+H AD9222 Pin No. 33 34 38 39 40 41 43 44 46 47 49 50 52 53 54 55 56 57 58 60 61 63 64 Mnemonic D-A D+A SCLK/DTP SDIO/ODM CSB PDWN VIN + A VIN - A VIN - B VIN + B VIN + C VIN - C VIN - D VIN + D RBIAS SENSE VREF REFB REFT VIN + E VIN - E VIN - F VIN + F Description ADC A Digital Output Complement ADC A Digital Output True Serial Clock/Digital Test Pattern Serial Data Input-Output/Output Driver Mode Chip Select Bar Power Down ADC A Analog Input True ADC A Analog Input Complement ADC B Analog Input Complement ADC B Analog Input True ADC C Analog Input True ADC C Analog Input Complement ADC D Analog Input Complement ADC D Analog Input True External Resistor to Set the Internal ADC Core Bias Current Reference Mode Selection Voltage Reference Input/Output Differential Reference (Negative) Differential Reference (Positive) ADC E Analog Input True ADC E Analog Input Complement ADC F Analog Input Complement ADC F Analog Input True Rev. C | Page 11 of 60 AD9222 EQUIVALENT CIRCUITS DRVDD V V D- VIN x D+ V 05967-009 05967-006 V DRGND Figure 9. Equivalent Digital Output Circuit Figure 6. Equivalent Analog Input Circuit 10 CLK+ 10k 1.25V 10k SCLK/DTP AND PDWN 10 1k CLK- 05967-010 05967-007 30k Figure 7. Equivalent Clock Input Circuit Figure 10. Equivalent SCLK/DTP and PDWN Input Circuit RBIAS 30k 05967-011 350 05967-008 SDIO/ODM 100 Figure 11. Equivalent RBIAS Circuit Figure 8. Equivalent SDIO/ODM Input Circuit Rev. C | Page 12 of 60 AD9222 AVDD 70k CSB 1k 6k Figure 12. Equivalent CSB Input Circuit Figure 14. Equivalent VREF Circuit 1k 05967-013 SENSE 05967-014 05967-012 VREF Figure 13. Equivalent SENSE Circuit Rev. C | Page 13 of 60 AD9222 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 AIN = -0.5dBFS SNR = 70.79dB ENOB = 11.47 BITS SFDR = 84.71dBc -20 AMPLITUDE (dBFS) -40 -60 -80 4 6 8 10 12 14 16 18 20 -120 0 AIN = -0.5dBFS SNR = 70.32dB ENOB = 11.39 BITS SFDR = 84.28dBc 10 15 20 25 AIN = -0.5dBFS SNR = 70.02dB ENOB = 11.45 BITS SFDR = 86.3dBc -20 AMPLITUDE (dBFS) -40 -60 -80 -40 -60 -80 -100 -100 2 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz) -120 05967-016 0 0 15 20 25 Figure 19. Single-Tone 32k FFT with fIN = 70 MHz, AD9222-50 0 AIN = -0.5dBFS SNR = 70.72dB ENOB = 11.45 BITS SFDR = 85.79dBc AIN = -0.5dBFS SNR = 69.25dB ENOB = 11.21 BITS SFDR = 72.85dBc -20 AMPLITUDE (dBFS) -20 10 FREQUENCY (MHz) Figure 16. Single-Tone 32k FFT with fIN = 19.7 MHz, AD9222-40 0 5 05967-019 AMPLITUDE (dBFS) -20 5 Figure 18. Single-Tone 32k FFT with fIN = 35 MHz, AD9222-50 0 -40 -60 -80 -40 -60 -80 -100 -100 0 5 10 15 20 25 FREQUENCY (MHz) 05967-017 AMPLITUDE (dBFS) 0 FREQUENCY (MHz) Figure 15. Single-Tone 32k FFT with fIN = 2.3 MHz, AD9222-40 -120 -80 05967-018 2 05967-015 0 FREQUENCY (MHz) -120 -60 -100 -100 -120 -40 -120 0 5 10 15 20 25 FREQUENCY (MHz) Figure 20. Single-Tone 32k FFT with fIN = 120 MHz, AD9222-50 Figure 17. Single-Tone 32k FFT with fIN = 2.3 MHz, AD9222-50 Rev. C | Page 14 of 60 05967-020 AMPLITUDE (dBFS) -20 AIN = -0.5dBFS SNR = 70.35dB ENOB = 11.40 BITS SFDR = 83.86dBc AD9222 0 0 AIN = -0.5dBFS SNR = 70.21dB ENOB = 11.31 BITS SFDR = 82.37dBc -40 -60 -80 -60 -80 10 15 20 25 30 -120 0 5 10 15 20 25 05967-088 5 05967-085 0 FREQUENCY (MHz) 30 FREQUENCY (MHz) Figure 21. Single-Tone 32k FFT with fIN = 2.3 MHz, AD9222-65 Figure 24. Single-Tone 32k FFT with fIN = 120 MHz, AD9222-65 0 100 AIN = -0.5dBFS SNR = 69.8dB ENOB = 11.22 BITS SFDR = 80.61dBc -20 95 2V p-p, SFDR 90 -40 SNR/SFDR (dB) AMPLITUDE (dBFS) -40 -100 -100 -120 AIN = -0.5dBFS SNR = 68.67dB ENOB = 10.79 BITS SFDR = 71.49dBc -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -20 -60 -80 85 80 75 2V p-p, SNR 70 -100 5 10 15 20 25 30 FREQUENCY (MHz) 60 10 15 20 25 30 35 40 45 50 ENCODE (MSPS) 05967-021 0 05967-086 -120 65 Figure 25. SNR/SFDR vs. fSAMPLE, fIN = 2.61 MHz, AD9222-50 Figure 22. Single-Tone 32k FFT with fIN = 35 MHz, AD9222-65 0 90 AIN = -0.5dBFS SNR = 69.65dB ENOB = 11.07 BITS SFDR = 74.79dBc -20 85 SNR/SFDR (dB) -60 -80 -100 75 70 2V p-p, SNR 0 5 10 15 20 25 30 FREQUENCY (MHz) Figure 23. Single-Tone 32k FFT with fIN = 70 MHz, AD9222-65 60 10 15 20 25 30 35 40 45 ENCODE (MSPS) Figure 26. SNR/SFDR vs. fSAMPLE, fIN = 20.1 MHz, AD9222-50 Rev. C | Page 15 of 60 50 05967-022 -120 80 65 05967-087 AMPLITUDE (dBFS) 2V p-p, SFDR -40 AD9222 100 90 95 80 70 2V p-p, SFDR SNR/SFDR (dB) 85 80 75 70 80dB REFERENCE LINE 50 2V p-p, SFDR 40 2V p-p, SNR 30 20 2V p-p, SNR 65 10 15 20 25 30 35 40 45 50 55 60 65 ENCODE (MSPS) 0 -60 05967-089 60 10 -50 -40 -30 -20 -10 0 INPUT AMPLITUDE (dBFS) Figure 30. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, AD9222-65 Figure 27. SNR/SFDR vs. fSAMPLE, fIN = 2.3 MHz, AD9222-65 100 90 2V p-p, SFDR 90 85 80 2V p-p, SFDR 70 80 SNR/SFDR (dB) SNR/SFDR (dB) 60 05967-091 SNR/SFDR (dB) 90 75 2V p-p, SNR 70 60 80dB REFERENCE 50 40 30 2V p-p, SNR 20 65 20 25 30 35 40 45 50 55 60 65 ENCODE (MSPS) 0 -60 100 90 90 80 80 50 80dB REFERENCE 40 30 2V p-p, SNR -20 -10 0 60 50 80dB REFERENCE LINE 2V p-p, SFDR 40 2V p-p, SNR 30 20 20 10 10 -50 -40 -30 -20 INPUT AMPLITUDE (dBFS) -10 0 0 -60 05967-023 0 -60 -30 70 2V p-p, SFDR SNR/SFDR (dB) SNR/SFDR (dB) 60 -40 INPUT AMPLITUDE (dBFS) Figure 31. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, AD9222-50 Figure 28. SNR/SFDR vs. fSAMPLE, fIN = 19.7 MHz, AD9222-65 70 -50 Figure 29. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, AD9222-50 -50 -40 -30 -20 INPUT AMPLITUDE (dBFS) -10 0 05967-092 15 05967-090 60 10 05967-024 10 Figure 32. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, AD9222-65 Rev. C | Page 16 of 60 AD9222 0 -40 -60 -80 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 Figure 36. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz, AD9222-50 0 AIN1 AND AIN2 = -7dBFS SFDR = 79.5dB IMD2 = 80.0dBc IMD3 = 84.1dBc -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -40 -60 -80 2 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz) Figure 34. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz, AD9222-40 0 -120 05967-026 0 5 10 15 20 25 30 FREQUENCY (MHz) Figure 37. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, AD9222-65 0 AIN1 AND AIN2 = -7dBFS SFDR = 84.49dB IMD2 = 85.83dBc IMD3 = 84.54dBc AIN1 AND AIN2 = -7dBFS SFDR = 75.2dB IMD2 = 79.3dBc IMD3 = 75.1dBc -20 AMPLITUDE (dBFS) -20 0 05967-093 -100 -40 -60 -80 -40 -60 -80 -100 -100 5 10 15 FREQUENCY (MHz) 20 25 -120 05967-027 0 Figure 35. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, AD9222-50 0 5 10 15 20 FREQUENCY (MHz) 25 30 05967-094 AMPLITUDE (dBFS) 0 FREQUENCY (MHz) AIN1 AND AIN2 = -7dBFS SFDR = 77.24dB IMD2 = 91.66dBc IMD3 = 77.72dBc -20 AMPLITUDE (dBFS) -80 -120 05967-025 0 Figure 33. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, AD9222-40 -120 -60 -100 FREQUENCY (MHz) -120 -40 05967-032 -100 -120 AIN1 AND AIN2 = -7dBFS SFDR = 80.42dB IMD2 = 83.92dBc IMD3 = 80.60dBc -20 AMPLITUDE (dBFS) -20 AMPLITUDE (dBFS) 0 AIN1 AND AIN2 = -7dBFS SFDR = 89.87dB IMD2 = 96.07dBc IMD3 = 90.16dBc Figure 38. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz, AD9222-65 Rev. C | Page 17 of 60 AD9222 90 90 85 85 2V p-p, SFDR SINAD/SFDR (dB) 75 SNR 70 65 1 10 100 1000 ANALOG INPUT FREQUENCY (MHz) 70 60 -40 2V p-p, SINAD -20 0 20 40 60 80 TEMPERATURE (C) Figure 39. SNR/SFDR vs. fIN, AD9222-50 Figure 42. SINAD/SFDR vs. Temperature, fIN = 2.3 MHz, AD9222-65 90 90 85 85 SINAD/SFDR (dB) 2V p-p, SFDR 80 SNR/SFDR (dB) 75 65 05967-029 60 80 05967-096 SNR/SFDR (dB) SFDR 80 75 70 2V p-p, SNR 65 2V p-p, SFDR 80 75 2V p-p, SINAD 70 60 1 10 100 60 -40 05967-095 50 1000 FREQUENCY (MHz) -20 0 20 40 60 80 TEMPERATURE (C) Figure 40. SNR/SFDR vs. fIN, AD9222-65 05967-031 65 55 Figure 43. SINAD/SFDR vs. Temperature, fIN = 20.1 MHz, AD9222-50 100 90 95 2V p-p, SFDR 85 2V p-p, SFDR 85 SINAD/SFDR (dB) 80 75 2V p-p, SINAD 80 75 70 2V p-p, SINAD 70 65 60 -40 -20 0 20 40 TEMPERATURE (C) 60 80 05967-030 65 Figure 41. SINAD/SFDR vs. Temperature, fIN = 2.61 MHz, AD9222-50 60 -40 -20 0 20 40 60 80 05967-097 SINAD/SFDR (dB) 90 TEMPERATURE (C) Figure 44. SINAD/SFDR vs. Temperature, fIN = 19.7 MHz, AD9222-65 Rev. C | Page 18 of 60 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 -0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 0 500 1000 1500 2000 2500 3000 3500 4000 CODE -1.0 0 500 1000 1500 2000 2500 3000 3500 4000 35 40 CODE 05967-099 DNL (LSB) 1.0 05967-036 INL (LSB) AD9222 Figure 48. DNL, fIN = 35 MHz, AD9222-65 Figure 45. INL, fIN = 2.3 MHz, AD9222-50 1.0 -30 0.8 -35 0.6 -40 0.2 CMRR (dB) INL (LSB) 0.4 0 -0.2 -0.4 -45 -50 -55 -60 -0.6 0 500 1000 1500 2000 2500 3000 3500 4000 CODE -70 05967-098 0 15 20 25 30 Figure 49. CMRR vs. Frequency, AD9222-50 1.0 1.8 0.8 1.6 0.6 1.4 NUMBER OF HITS (Millions) 0.27 LSB rms 0.4 0.2 0 -0.2 -0.4 -0.6 1.2 1.0 0.8 0.6 0.4 0.2 -0.8 0 500 1000 1500 2000 2500 3000 CODE 3500 4000 05967-099 DNL (LSB) 10 FREQUENCY (MHz) Figure 46. INL, fIN = 35 MHz, AD9222-65 -1.0 5 0 N-3 N-2 N-1 N N+1 N+2 N+3 CODE Figure 50. Input-Referred Noise Histogram, AD9222-50 Figure 47. DNL, fIN = 2.3 MHz, AD9222-50 Rev. C | Page 19 of 60 05967-038 -1.0 05967-056 -65 -0.8 AD9222 2.5 0 -1 -3dB BANDWIDTH = 325MHz -2 -3 AMPLITUDE (dBFS) NUMBER OF HITS (Millions) 0.3 LSB rms 2.0 1.5 1.0 -4 -5 -6 -7 -8 0.5 -9 N-3 N-2 N-1 N N+1 N+2 N+3 CODE Figure 51. Input-Referred Noise Histogram, AD9222-65 0 -60 -80 -100 0 5 10 15 20 FREQUENCY (MHz) 25 05967-041 AMPLITUDE (dBFS) -40 -120 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) Figure 53. Full-Power Bandwidth vs. Frequency, AD9222-50 NPR = 60.3dB NOTCH = 18.0MHz NOTCH WIDTH = 3.0MHz -20 -11 Figure 52. Noise Power Ratio (NPR), AD9222-50 Rev. C | Page 20 of 60 05967-040 0 05967-100 -10 AD9222 THEORY OF OPERATION The AD9222 architecture consists of a pipelined ADC divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The data is then serialized and aligned to the frame and data clocks. ANALOG INPUT CONSIDERATIONS The analog input to the AD9222 is a differential switched-capacitor circuit designed for processing differential input signals. This circuit can support a wide common-mode range while maintaining excellent performance. An input common-mode voltage of midsupply minimizes signal-dependent errors and provides optimum performance. The clock signal alternately switches the input circuit between sample mode and hold mode (see Figure 54). When the input circuit is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. In addition, low-Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and therefore achieve the maximum bandwidth of the ADC. Such use of lowQ inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Either a shunt capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article "Transformer-Coupled Front-End for Wideband A/D Converters" (Volume 39, April 2005) for more information. In general, the precise values depend on the application. The analog inputs of the AD9222 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 55 and Figure 57. H CPAR H VIN + x CSAMPLE S S S S CSAMPLE VIN - x H 05967-043 H CPAR Figure 54. Switched-Capacitor Input Circuit Rev. C | Page 21 of 60 AD9222 90 90 SFDR (dBc) 85 85 80 80 SNR/SFDR (dB) 75 SNR (dB) 70 75 SNR (dB) 70 65 65 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ANALOG INPUT COMMON-MODE VOLTAGE (V) 60 0.2 05967-044 60 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 55. SNR/SFDR vs. Common-Mode Voltage, fIN = 2.3 MHz, AD9222-50 05967-042 SNR/SFDR (dB) SFDR (dBc) Figure 57. SNR/SFDR vs. Common-Mode Voltage, fIN = 35 MHz, AD9222-50 90 90 SFDR (dBc) 85 85 SNR/SFDR (dB) 80 75 SNR (dB) 70 80 75 70 SNR (dB) 65 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ANALOG INPUT COMMON-MODE VOLTAGE (V) 1.6 Figure 56. SNR/SFDR vs. Common-Mode Voltage, fIN = 2.3 MHz, AD9222-65 60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 58. SNR/SFDR vs. Common-Mode Voltage, fIN = 35 MHz, AD9222-65 Rev. C | Page 22 of 60 1.6 05967-102 60 65 05967-101 SNR/SFDR (dB) SFDR (dBc) AD9222 ADT1-1WT 1:1 Z RATIO For best dynamic performance, the source impedances driving VIN + x and VIN - x should be matched such that commonmode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates the positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common-mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as 2V p-p C R 49.9 VIN + x ADC AD9222 CDIFF1 R AVDD VIN - x C 1k AGND 05967-046 1k 0.1F 1C DIFF REFT = 1/2 (AVDD + VREF) REFB = 1/2 (AVDD - VREF) Span = 2 x (REFT - REFB) = 2 x VREF IS OPTIONAL. Figure 59. Differential Transformer-Coupled Configuration for Baseband Applications 2V p-p It can be seen from these equations that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage. 16nH ADT1-1WT 0.1F 1:1 Z RATIO 16nH 65 499 16nH 33 VIN + x 2.2pF ADC AD9222 1k 33 VIN - x AVDD Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9222, the largest input span available is 2 V p-p. 1k 05967-047 0.1F 1k Figure 60. Differential Transformer-Coupled Configuration for IF Applications Differential Input Configurations Single-Ended Input Configuration There are several ways to drive the AD9222 either actively or passively; however, optimum performance is achieved by driving the analog input differentially. For example, using the AD8334 differential driver to drive the AD9222 provides excellent performance and a flexible interface to the ADC (see Figure 62) for baseband applications. This configuration is commonly used for medical ultrasound systems. A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input commonmode swing. If the application requires a single-ended input configuration, ensure that the source impedances on each input are well matched in order to achieve the best possible performance. A full-scale input of 2 V p-p can still be applied to the ADC's VIN + x pin while the VIN - x pin is terminated. Figure 61 details a typical single-ended input configuration. For applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration (see Figure 59 and Figure 60) because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9222. AVDD C 1k Regardless of the configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed. 2V p-p R VIN + x 0.1F 1k 49.9 1k 25 R VIN - x C 1k 05967-048 0.1F ADC AD9222 CDIFF1 AVDD 1C DIFF IS OPTIONAL. Figure 61. Single-Ended Input Configuration 0.1F LOP VOH INH 1V p-p 187 AD8334 22pF 0.1F LNA VGA 374 LMD VOL LON 18nF 274 VIN + x VIN 187 R VIN - x 0.1F 0.1F 0.1F Figure 62. Differential Input Configuration Using the AD8334 Rev. C | Page 23 of 60 ADC AD9222 C 1.0k 0.1F R 1.0k AVDD 10F 1k 1k 05967-049 0.1F 120nH VIP AD9222 For optimum performance, the AD9222 sample clock inputs (CLK+ and CLK-) should be clocked with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK- pins via a transformer or capacitors. These pins are biased internally and require no additional biasing. Figure 63 shows a preferred method for clocking the AD9222. The low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. The back-toback Schottky diodes across the secondary transformer limit clock excursions into the AD9222 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9222, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 0.1F CLK CLK+ 100 PECL DRIVER 0.1F CLK 150 RESISTORS ARE ADC AD9222 CLK- 240 05967-051 240 501 OPTIONAL. Figure 64. Differential PECL Sample Clock 0.1F CLK+ 0.1F CLK- 0.1F CLK+ LVDS DRIVER 100 0.1F CLK ADC AD9222 CLK- 501 150 RESISTORS ARE OPTIONAL. Figure 65. Differential LVDS Sample Clock 05967-052 501 AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 CLK CMOS DRIVER 0.1F 0.1F CLK CLK 501 05967-050 SCHOTTKY DIODES: HSM2812 AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 501 39k AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 0.1F CLK+ Another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure 64. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515 family of clock drivers offers excellent jitter performance. CLK- CLK- 0.1F Figure 63. Transformer-Coupled Differential Clock 0.1F CLK+ ADC AD9222 CLK 0.1F ADC AD9222 CLK- CLK+ OPTIONAL 0.1F 100 CMOS DRIVER CLK+ 0.1F 0.1F CLK 501 Figure 66. Single-Ended 1.8 V CMOS Sample Clock 100 50 0.1F CLK+ OPTIONAL 0.1F 100 0.1F CLK+ ADC AD9222 CLK- 150 RESISTOR IS OPTIONAL. 05967-054 CLK+ AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 150 RESISTOR IS OPTIONAL. MINI-CIRCUITS(R) ADT1-1WT, 1:1Z 0.1F XFMR 0.1F In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be directly driven from a CMOS gate, and the CLK- pin should be bypassed to ground with a 0.1 F capacitor in parallel with a 39 k resistor (see Figure 66). Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages of up to 3.3 V, making the selection of the drive logic voltage very flexible. 05967-053 CLOCK INPUT CONSIDERATIONS Figure 67. Single-Ended 3.3 V CMOS Sample Clock Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9222 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9222. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See the Memory Map section for more details on using this feature. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate. Rev. C | Page 24 of 60 AD9222 Clock Jitter Considerations Power Dissipation and Power-Down Mode High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by As shown in Figure 69, the power dissipated by the AD9222 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. 0.40 In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 68). 0.35 AVDD CURRENT 0.600 0.550 DRVDD CURRENT 15 20 25 30 35 40 45 50 0.500 ENCODE (MSPS) Figure 69. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, AD9222- 50 950 500 450 900 400 16 BITS 90 14 BITS CURRENT (mA) 350 100 12 BITS 70 AVDD CURRENT 850 300 TOTAL POWER 250 800 200 POWER (mW) RMS CLOCK JITTER REQUIREMENT 80 POWER (W) 0.650 TOTAL POWER 0.15 0 10 110 150 10 BITS 8 BITS 50 40 1 10 100 ANALOG INPUT FREQUENCY (MHz) 750 100 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps DRVDD CURRENT 50 0 10 1000 Figure 68. Ideal SNR vs. Input Frequency and Jitter Rev. C | Page 25 of 60 20 30 40 50 60 700 ENCODE (MSPS) Figure 70. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, AD9222- 65 05967-103 60 05967-055 SNR (dB) 0.20 0.05 120 30 0.700 0.25 0.10 Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs. 130 0.750 0.30 CURRENT (A) The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9222. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. 0.800 05967-057 SNR Degradation = 20 x log 10(1/2 x x fA x tJ) AD9222 In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode; shorter cycles result in proportionally shorter wake-up times. With the recommended 0.1 F and 4.7 F decoupling capacitors on REFT and REFB, approximately 1 sec is required to fully discharge the reference buffer decoupling capacitors, and approximately 375 s is required to restore full operation. There are several other power-down options available when using the SPI. The user can individually power down each channel or put the entire device into standby mode. The latter option allows the user to keep the internal PLL powered when fast wake-up times (~600 ns) are required. See the Memory Map section for more details on using these features. placed as close to the receiver as possible. If there is no far-end receiver termination or there is poor differential trace routing, timing errors may result. To avoid such timing errors, it is recommended that the trace length be no longer than 24 inches and that the differential output traces be kept close together and at equal lengths. An example of the FCO and data stream with proper trace length and position is shown in Figure 71. CH1 500mV/DIV = FCO CH2 500mV/DIV = DCO CH3 500mV/DIV = DATA 5.0ns/DIV 05967-058 By asserting the PDWN pin high, the AD9222 is placed into power-down mode. In this state, the ADC typically dissipates 11 mW. During power-down, the LVDS output drivers are placed in a high impedance state. The AD9222 returns to normal operating mode when the PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. Figure 71. LVDS Output Timing Example in ANSI-644 Mode (Default), AD9222-50 Digital Outputs and Timing The AD9222 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 termination resistor CH1 500mV/DIV = FCO CH2 500mV/DIV = DCO CH3 500mV/DIV = DATA 5.0ns/DIV 05967-084 The AD9222 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option (similar to the IEEE 1596.3 standard) via the SDIO/ODM pin or SPI. This LVDS standard can further reduce the overall power dissipation of the device by approximately 36 mW. See the SDIO/ODM Pin section or Table 16 in the Memory Map section for more information. The LVDS driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. Figure 72. LVDS Output Timing Example in ANSI-644 Mode (Default), AD9222-65 Rev. C | Page 26 of 60 AD9222 600 An example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on standard FR-4 material is shown in Figure 73 and Figure 74. Figure 75 and Figure 76 show examples of trace lengths exceeding 24 inches on standard FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. It is the user's responsibility to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. Additional SPI options allow the user to further increase the internal termination (increasing the current) of all eight outputs in order to drive longer trace lengths (see Figure 77 and Figure 78). Even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the DRVDD supply increases when this option is used. EYE: ALL BITS ULS: 9596/15596 EYE DIAGRAM VOLTAGE (mV) 400 200 0 -200 -400 -600 -1.5ns -1.0ns -0.5ns 0ns 0.5ns 1.0ns 1.5ns -100ps -50ps 0ps 50ps 100ps 150ps 140 120 TIE JITTER HISTOGRAM (Hits) In cases that require increased driver strength to the DCO and FCO outputs because of load mismatch, Register 0x15 allows the user to increase the drive strength by 2x. To do this, set the appropriate bit in Register 0x5. Note that this feature cannot be used with Bit 4 and Bit 5 in Register 0x15. Bit 4 and Bit 5 take precedence over this feature. See the Memory Map section for more details. 100 80 60 40 EYE: ALL BITS ULS: 12071/12071 0 -150ps 300 Figure 74. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Less than 24 Inches on Standard FR-4, AD9222-65 200 100 0 500 -100 400 EYE DIAGRAM VOLTAGE (mV) -200 -300 -400 -500 -1.5ns -1.0ns -0.5ns 0ns 0.5ns 1.0ns 1.5ns 90 ULS: 12067/12067 300 200 100 0 -100 -200 -300 -400 80 -500 70 -1.5ns -1.0ns -0.5ns 0ns 0.5ns 1.0ns 1.5ns 60 100 50 90 40 TIE JITTER HISTOGRAM (Hits) TIE JITTER HISTOGRAM (Hits) EYE: ALL BITS 30 20 0 -150ps -100ps -50ps 0ps 50ps 100ps 150ps 05967-061 10 Figure 73. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Less than 24 Inches on Standard FR-4, AD9222-50 80 70 60 50 40 30 20 10 0 -200ps -100ps 0ps 100ps 200ps 05967-059 EYE DIAGRAM VOLTAGE (mV) 400 05967-106 20 500 Figure 75. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Greater than 24 Inches on Standard FR-4, AD9222-50 Rev. C | Page 27 of 60 AD9222 500 500 ULS: 7591/15591 400 300 EYE DIAGRAM VOLTAGE (mV) 200 100 0 -100 -200 -300 -0.5ns 0ns 0.5ns 1.0ns 100 0 -100 -200 -300 140 120 120 100 80 60 40 400 -1.0ns -0.5ns 0ns 0.5ns 1.0ns 1.5ns 100 80 60 40 20 -100ps 0ps 100ps 200ps 300ps 05967-105 -200ps 0 -200ps Figure 76. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Greater than 24 Inches on Standard FR-4, AD9222-65 EYE DIAGRAM VOLTAGE (mV) 200 -500 -1.5ns 1.5ns TIE JITTER HISTOGRAM (Hits) TIE JITTER HISTOGRAM (Hits) -1.0ns 20 EYE: ALL BITS -100ps 0ps 100ps 200ps 300ps Figure 78. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Termination on and Trace Lengths Greater than 24 Inches on Standard FR-4, AD9222-65 The format of the output data is offset binary by default. An example of the output coding format can be found in Table 8. To change the output data format to twos complement, see the Memory Map section. ULS: 12072/12072 300 200 100 Table 8. Digital Output Coding 0 -100 Code 4095 2048 2047 0 -200 -300 -400 -1.5ns -1.0ns -0.5ns 0ns 0.5ns 1.0ns Digital Output Offset Binary (D11 ... D0) 1111 1111 1111 1000 0000 0000 0111 1111 1111 0000 0000 0000 Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 12 bits times the sample clock rate, with a maximum of 780 Mbps (12 bits x 65 MSPS = 780 Mbps). The lowest typical conversion rate is 10 MSPS. However, if lower sample rates are required for a specific application, the PLL can be set up via the SPI to allow encode rates as low as 5 MSPS. See the Memory Map section to enable this feature. 70 60 50 40 30 20 -100ps -50ps 0ps 50ps 100ps 150ps 05967-060 10 0 -150ps (VIN + x) - (VIN - x), Input Span = 2 V p-p (V) +1.00 0.00 -0.000488 -1.00 1.5ns 80 TIE JITTER HISTOGRAM (Hits) 300 140 0 -300ps ULS: 8000/15600 -400 -400 -500 -1.5ns EYE: ALL BITS 05967-104 EYE DIAGRAM VOLTAGE (mV) 400 EYE: ALL BITS Figure 77. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Termination on and Trace Lengths Greater than 24 Inches on Standard FR-4, AD9222-50 Rev. C | Page 28 of 60 AD9222 Two output clocks are provided to assist in capturing data from the AD9222. The DCO is used to clock the output data and is equal to six times the sample clock (CLK) rate. Data is clocked out of the AD9222 and must be captured on the rising and falling edges of the DCO that supports double data rate (DDR) capturing. The FCO is used to signal the start of a new output byte and is equal to the sample clock rate. See the timing diagram shown in Figure 2 for more information. Table 9. Flexible Output Test Modes Output Test Mode Bit Sequence 0000 0001 Pattern Name Off (default) Midscale short 0010 +Full-scale short 0011 -Full-scale short 0100 Checkerboard 0101 0110 0111 PN sequence long 1 PN sequence short1 One-/zero-word toggle 1000 1001 User input 1-/0-bit toggle 1010 1x sync 1011 One bit high 1100 Mixed frequency 1 Digital Output Word 1 N/A 1000 0000 (8-bit) 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit) 1111 1111 (8-bit) 11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit) 0000 0000 (8-bit) 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit) 1010 1010 (8-bit) 10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit) N/A N/A 1111 1111 (8-bit) 11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit) Register 0x19 to Register 0x1A 1010 1010 (8-bit) 10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit) 0000 1111 (8-bit) 00 0001 1111 (10-bit) 0000 0011 1111 (12-bit) 00 0000 0111 1111 (14-bit) 1000 0000 (8-bit) 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit) 1010 0011 (8-bit) 10 0110 0011 (10-bit) 1010 0011 0011 (12-bit) 10 1000 0110 0111 (14-bit) Digital Output Word 2 N/A Same Subject to Data Format Select N/A Yes Same Yes Same Yes 0101 0101 (8-bit) 01 0101 0101 (10-bit) 0101 0101 0101 (12-bit) 01 0101 0101 0101 (14-bit) N/A N/A 0000 0000 (8-bit) 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit) Register 0x1B to Register 0x1C N/A No Yes Yes No No No N/A No N/A No N/A No All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver. Rev. C | Page 29 of 60 AD9222 When the SPI is used, the DCO phase can be adjusted in 60 increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO+ and DCO- timing, as shown in Figure 2, is 90 relative to the output data edge. An 8-, 10-, and 14-bit serial stream can also be initiated from the SPI. This allows the user to implement and test compatibility with lower and higher resolution systems. When changing the resolution to an 8- or 10-bit serial stream, the data stream is shortened. See Figure 3 for the 10-bit example. However, when using the 14-bit option, the data stream stuffs two 0s at the end of the 14-bit serial data. When the SPI is used, all of the data outputs can also be inverted from their nominal state. This is not to be confused with inverting the serial stream to an LSB-first mode. In default mode, as shown in Figure 2, the MSB is first in the data output serial stream. However, this can be inverted so that the LSB is first in the data output serial stream (see Figure 4). There are 12 digital output test pattern options available that can be initiated through the SPI. This is a useful feature when validating receiver capture and timing. Refer to Table 9 for the output bit sequencing options available. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. Note that some patterns may not adhere to the data format select option. In addition, user-defined test patterns can be assigned in the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver. The PN sequence short pattern produces a pseudorandom bit sequence that repeats itself every 29 - 1 or 511 bits. A description of the PN sequence and how it is generated can be found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The only difference is that the starting value must be a specific value instead of all 1s (see Table 10 for the initial values). The PN sequence long pattern produces a pseudorandom bit sequence that repeats itself every 223 - 1 or 8,388,607 bits. A description of the PN sequence and how it is generated can be found in section 5.6 of the ITU-T 0.150 (05/96) standard. The only differences are that the starting value must be a specific value instead of all 1s (see Table 10 for the initial values) and the AD9222 inverts the bit stream with relation to the ITU standard. Table 10. PN Sequence Sequence PN Sequence Short PN Sequence Long Initial Value 0x0df 0x29b80a First Three Output Samples (MSB First) 0xdf9, 0x353, 0x301 0x591, 0xfd7, 0x0a3 Consult the Memory Map section for information on how to change these additional digital output timing features through the SPI. SDIO/ODM Pin The SDIO/ODM pin is for use in applications that do not require SPI mode operation. This pin can enable a low power, reduced signal option (similar to the IEEE 1596.3 reduced range link output standard) if it and the CSB pin are tied to AVDD during device power-up. This option should only be used when the digital output trace lengths are less than 2 inches from the LVDS receiver. When this option is used, the FCO, DCO, and outputs function normally, but the LVDS signal swing of all channels is reduced from 350 mV p-p to 200 mV p-p, allowing the user to further reduce the power on the DRVDD supply. For applications where this pin is not used, it should be tied low. In this case, the device pin can be left open, and the 30 k internal pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant. If applications require this pin to be driven from a 3.3 V logic level, insert a 1 k resistor in series with this pin to limit the current. Table 11. Output Driver Mode Pin Settings Selected ODM Normal Operation ODM ODM Voltage 10 k to AGND AVDD Resulting Output Standard ANSI-644 (default) Low power, reduced signal option Resulting FCO and DCO ANSI-644 (default) Low power, reduced signal option SCLK/DTP Pin The SCLK/DTP pin is for use in applications that do not require SPI mode operation. This pin can enable a single digital test pattern if it and the CSB pin are held high during device powerup. When the SCLK/DTP is tied to AVDD, the ADC channel outputs shift out the following pattern: 1000 0000 0000. The FCO and DCO function normally while all channels shift out the repeatable test pattern. This pattern allows the user to perform timing alignment adjustments among the FCO, DCO, and output data. For normal operation, this pin should be tied to AGND through a 10 k resistor. This pin is both 1.8 V and 3.3 V tolerant. Table 12. Digital Test Pattern Pin Settings Selected DTP Normal Operation DTP DTP Voltage 10 k to AGND AVDD Resulting D + x and D - x Normal operation 1000 0000 0000 Resulting FCO and DCO Normal operation Normal operation Additional and custom test patterns can also be observed when commanded from the SPI port. Consult the Memory Map section for information about the options available. Rev. C | Page 30 of 60 AD9222 CSB Pin The CSB pin should be tied to AVDD for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. This pin is both 1.8 V and 3.3 V tolerant. RBIAS Pin To set the internal core bias current of the ADC, place a resistor (nominally equal to 10.0 k) to ground at the RBIAS pin. The resistor current is derived on-chip and sets the AVDD current of the ADC to a nominal 450 mA at 65 MSPS. Therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance The REFT and REFB pins establish their input span of the ADC core from the reference configuration. The analog input fullscale range of the ADC equals twice the voltage at the reference pin for either an internal or an external reference configuration. If the reference of the AD9222 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 81 depicts how the internal reference voltage is affected by loading. VIN + x VIN - x REFT ADC CORE Voltage Reference 0.1F + 4.7F REFB A stable, accurate 0.5 V voltage reference is built into the AD9222. This is gained up internally by a factor of 2, setting VREF to 1.0 V, which results in a full-scale differential input span of 2 V p-p. The VREF is set internally by default; however, the VREF pin can be driven externally with a 1.0 V reference to improve accuracy. 0.1F VREF 1F 0.1F SELECT LOGIC 05967-064 Figure 79. Internal Reference Configuration VIN + x VIN - x REFT Table 13. Reference Settings SENSE Voltage AVDD Resulting VREF (V) N/A AGND to 0.2 V 1.0 Resulting Differential Span (V p-p) 2 x external reference 2.0 0.5V SENSE When applying the decoupling capacitors to the VREF, REFT, and REFB pins, use ceramic low-ESR capacitors. These capacitors should be close to the ADC pins and on the same layer of the PCB as the AD9222. The recommended capacitor values and configurations for the AD9222 reference pin are shown in Figure 79. Selected Mode External Reference Internal, 2 V p-p FSR 0.1F ADC CORE + 4.7F 0.1F VREF 0.1F1 AVDD 0.1F REFB EXTERNAL REFERENCE 1F1 0.1F SELECT LOGIC 0.5V SENSE A comparator within the AD9222 detects the potential at the SENSE pin and configures the reference. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 79), setting VREF to 1 V. 05967-065 Internal Reference Operation 1OPTIONAL. Rev. C | Page 31 of 60 Figure 80. External Reference Operation AD9222 0.02 External Reference Operation -0.02 -0.04 -0.10 -0.12 -0.14 -0.16 -20 0 20 40 60 TEMPERATURE (C) 0 Figure 82. Typical VREF Drift, AD9222-50 -5 -10 -15 -20 -25 05727-083 VREF ERROR (%) -0.08 -0.18 -40 5 -30 -0.06 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 CURRENT LOAD (mA) Figure 81. VREF Accuracy vs. Load, AD9222-50 Rev. C | Page 32 of 60 80 05967-028 When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. The external reference is loaded with an equivalent 6 k load. An internal reference buffer generates the positive and negative full-scale references, REFT and REFB, for the ADC core. Therefore, the external reference must be limited to a nominal of 1.0 V. 0 VREF ERROR (%) The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 82 shows the typical drift characteristics of the internal reference in 1 V mode. AD9222 SERIAL PORT INTERFACE (SPI) The AD9222 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided down into fields, as documented in the Memory Map section. Detailed operational information can be found in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. There are three pins that define the SPI: SCLK, SDIO, and CSB (see Table 14). The SCLK pin is used to synchronize the read and write data presented to the ADC. The SDIO pin is a dualpurpose pin that allows data to be sent to and read from the internal ADC memory map registers. The CSB pin is an active low control that enables or disables the read and write cycles. Table 14. Serial Port Pins Pin SCLK SDIO CSB Function Serial Clock. The serial shift clock input. SCLK is used to synchronize serial interface reads and writes. Serial Data Input/Output. A dual-purpose pin. The typical role for this pin is an input or output, depending on the instruction sent and the relative position in the timing frame. Chip Select Bar (Active Low). This control gates the read and write cycles. The falling edge of the CSB in conjunction with the rising edge of the SCLK determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted followed by one or more data bytes, which is determined by Bit Field W0 and Bit Field W1. An example of the serial timing and its definitions can be found in Figure 84 and Table 15. During normal operation, CSB is used to signal to the device that SPI commands are to be received and processed. When CSB is brought low, the device processes SCLK and SDIO to process instructions. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until CSB is taken high to end the communication cycle. This allows complete memory transfers without requiring additional instructions. Regardless of the mode, if CSB is taken high in the middle of a byte transfer, the SPI state machine is reset and the device waits for a new instruction. In addition to the operation modes, the SPI port configuration influences how the AD9222 operates. For applications that do not require a control port, the CSB line can be tied and held high. This places the remainder of the SPI pins into their secondary modes, as defined in the SDIO/ODM Pin and SCLK/DTP Pin sections. CSB can also be tied low to enable 2-wire mode. When CSB is tied low, SCLK and SDIO are the only pins required for communication. Although the device is synchronized during power-up, the user should ensure that the serial port remains synchronized with the CSB line when using this mode. When operating in 2-wire mode, it is recommended to use a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB line, streaming mode can be entered but not exited. In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the SDIO pin to change from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB- or LSB-first mode. MSB-first mode is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. C | Page 33 of 60 AD9222 HARDWARE INTERFACE The pins described in Table 14 compose the physical interface between the user's programming device and the serial port of the AD9222. The SCLK and CSB pins function as inputs when using the SPI. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. If multiple SDIO pins share a common connection, care should be taken to ensure that proper VOH levels are met. Assuming the same load for each AD9222, Figure 83 shows the number of SDIO pins that can be connected together and the resulting VOH level. If the user chooses not to use the SPI, these dual-function pins serve their secondary functions when the CSB is strapped to AVDD during device power-up. See the Theory of Operation section for details on which pin-strappable functions are supported on the SPI pins. 0 10 20 30 40 50 60 70 80 90 NUMBER OF SDIO PINS CONNECTED TOGETHER 100 05967-037 VOH (V) 1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 This interface is flexible enough to be controlled by either serial PROMS or PIC mirocontrollers, providing the user with an alternative method, other than a full SPI controller, to program the ADC (see the AN-812 Application Note). Figure 83. SDIO Pin Loading Rev. C | Page 34 of 60 AD9222 tDS tS tHI tCLK tDH tH tLO CSB SCLK DON'T CARE DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON'T CARE 05967-068 SDIO DON'T CARE Figure 84. Serial Timing Details Table 15. Serial Timing Definitions Parameter tDS tDH tCLK tS tH tHI tLO tEN_SDIO Timing (Minimum, ns) 5 2 40 5 2 16 16 10 tDIS_SDIO 10 Description Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the clock Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 84) Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 84) Rev. C | Page 35 of 60 AD9222 MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS Each row in the memory map register table (Table 16) has eight address locations. The memory map is divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device index and transfer register map (Address 0x05 and Address 0xFF), and the ADC functions register map (Address 0x08 to Address 0x22). Undefined memory locations should not be written to except when writing the default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. The leftmost column of the memory map indicates the register address number, and the default value is shown in the second rightmost column. The (MSB) Bit 7 column is the start of the default hexadecimal value given. For example, Address 0x09, the clock register, has a default value of 0x01, meaning Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. By writing a 0 to Bit 6 of this address, the duty cycle stabilizer turns off. For more information on this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. DEFAULT VALUES When the AD9222 comes out of a reset, critical registers are preloaded with default values. These values are indicated in Table 16, where an X refers to an undefined feature. LOGIC LEVELS An explanation of various registers follows: "Bit is set" is synonymous with "bit is set to Logic 1" or "writing Logic 1 for the bit." Similarly, "clear a bit" is synonymous with "bit is set to Logic 0" or "writing Logic 0 for the bit." Rev. C | Page 36 of 60 AD9222 Table 16. Memory Map Register Addr. (MSB) (Hex) Parameter Name Bit 7 Chip Configuration Registers 00 chip_port_config 0 01 chip_id 02 chip_grade Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB first 1 = on 0 = off (default) Soft reset 1 = on 0 = off (default) 1 1 Soft reset 1 = on 0 = off (default) LSB first 1 = on 0 = off (default) (LSB) Bit 0 Default Value (Hex) 0 0x18 8-bit Chip ID Bits 7:0 (AD9222 = 0x07), (default) X Read only Default Notes/ Comments The nibbles should be mirrored so that LSB- or MSB-first mode is set correctly regardless of shift mode. Default is unique chip ID, different for each device. This is a readonly register. Child ID used to differentiate graded devices. Child ID [6:4] (identify device variants of Chip ID) 000 = 65 MSPS 011 = 50 MSPS 001 = 40 MSPS X X X X Read only Device Index and Transfer Registers 04 device_index_2 X X X X Data Channel G 1 = on (default) 0 = off Data Channel F 1 = on (default) 0 = off Data Channel E 1 = on (default) 0 = off 0x0F Bits are set to determine which on-chip device receives the next write command. 05 device_index_1 X X X X Data Channel C 1 = on (default) 0 = off X Data Channel B 1 = on (default) 0 = off X Data Channel A 1 = on (default) 0 = off SW transfer 1 = on 0 = off (default) Bits are set to determine which on-chip device receives the next write command. device_update Clock Channel FCO 1 = on 0 = off (default) X 0x0F FF Clock Channel DCO 1 = on 0 = off (default) X Data Channel H 1 = on (default) 0 = off Data Channel D 1 = on (default) 0 = off X 0x00 Synchronously transfers data from the master shift register to the slave. ADC Functions 08 modes X X X X X 0x00 Determines various generic modes of chip operation. 09 clock X X X X X Internal power-down mode 000 = chip run (default) 001 = full power-down 010 = standby 011 = reset X X Duty cycle stabilizer 1 = on (default) 0 = off 0x01 Turns the internal duty cycle stabilizer on and off. 0D test_io User test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once Reset PN long gen 1 = on 0 = off (default) Reset PN short gen 1 = on 0 = off (default) Output test mode--see Table 9 in the Digital Outputs and Timing section 0x00 When this register is set, the test data is placed on the output pins in place of normal data. 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = -FS short 0100 = checkerboard output 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1x sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode) Rev. C | Page 37 of 60 AD9222 Addr. (Hex) 14 Parameter Name output_mode (MSB) Bit 7 X 15 output_adjust X Bit 6 0 = LVDS ANSI-644 (default) 1 = LVDS low power, (IEEE 1596.3 similar) X 16 output_phase X 19 user_patt1_lsb 1A Bit 5 X Bit 4 X (LSB) Bit 1 Bit 0 00 = offset binary (default) 01 = twos complement Default Value (Hex) 0x00 Bit 3 X Bit 2 Output invert 1 = on 0 = off (default) Output driver termination 00 = none (default) 01 = 200 10 = 100 11 = 100 X X X X X 0x03 B7 B6 B5 B4 0011 = output clock phase adjust (0000 through 1010) 0000 = 0 relative to data edge 0001 = 60 relative to data edge 0010 = 120 relative to data edge 0011 = 180 relative to data edge (default) 0100 = 240 relative to data edge 0101 = 300 relative to data edge 0110 = 360 relative to data edge 0111 = 420 relative to data edge 1000 = 480 relative to data edge 1001 = 540 relative to data edge 1010 = 600 relative to data edge 1011 to 1111 = 660 relative to data edge B3 B2 B1 B0 user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 1B user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 1C user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 21 serial_control LSB first 1 = on 0 = off (default) X X X 000 = 12 bits (default, normal bit stream) 001 = 8 bits 010 = 10 bits 011 = 12 bits 100 = 14 bits 0x00 22 serial_ch_stat X X X X <10 MSPS, low encode rate mode 1 = on 0 = off (default) X Channel powerdown 1 = on 0 = off (default) 0x00 Rev. C | Page 38 of 60 X X Channel output reset 1 = on 0 = off (default) DCO and FCO 2x Drive Strength 1 = on 0 = off (default) 0x00 0x00 Default Notes/ Comments Configures the outputs and the format of the data. Determines LVDS or other output properties. Primarily functions to set the LVDS span and common-mode levels in place of an external resistor. On devices that utilize global clock divide, determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected. User-defined pattern, 1 LSB. User-defined pattern, 1 MSB. User-defined pattern, 2 LSB. User-defined pattern, 2 MSB. Serial stream control. Default causes MSB first and the native bit stream (global). Used to power down individual sections of a converter (local). AD9222 Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations When connecting power to the AD9222, it is recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one supply is available, it should be routed to the AVDD first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD. The user can employ several different decoupling capacitors to cover both high and low frequencies. These should be located close to the point of entry at the PC board level and close to the parts, with minimal trace lengths. It is required that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9222. An exposed continuous copper plane on the PCB should mate to the AD9222 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder-filled or plugged. A single PC board ground plane should be sufficient when using the AD9222. With proper decoupling and smart partitioning of the PC board's analog, digital, and clock sections, optimum performance can be easily achieved. To maximize the coverage and adhesion between the ADC and PCB, partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections. This provides several tie points between the ADC and PCB during the reflow process, whereas using one continuous plane with no partitions only guarantees one tie point. See Figure 85 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). 05967-069 SILKSCREEN PARTITION PIN 1 INDICATOR Figure 85. Typical PCB Layout Rev. C | Page 39 of 60 AD9222 EVALUATION BOARD section. At least one 1.8 V supply is needed for AVDD_DUT and DRVDD_DUT; however, it is recommended that separate supplies be used for both analog and digital signals and that each supply have a current capability of 1 A. To operate the evaluation board using the VGA option, a separate 5.0 V analog supply (AVDD_5 V) is needed. To operate the evaluation board using the SPI and alternate clock options, a separate 3.3 V analog supply (AVDD_3.3 V) is needed in addition to the other supplies. The AD9222 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially using a transformer (default) or an AD8334 driver. The ADC can also be driven in a single-ended fashion. Separate power pins are provided to isolate the DUT from the drive circuitry of the AD8334. Each input configuration can be selected by changing the connection of various jumpers (see Figure 90 to Figure 94). Figure 86 shows the typical bench characterization setup used to evaluate the ac performance of the AD9222. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. INPUT SIGNALS When connecting the clock and analog sources to the evaluation board, use clean signal generators with low phase noise, such as Rohde & Schwarz SMA or HP8644 signal generators or the equivalent, as well as a 1 m, shielded, RG-58, 50 coaxial cable. Enter the desired frequency and amplitude from the ADC specifications tables. Typically, most Analog Devices, Inc., evaluation boards can accept approximately 2.8 V p-p or 13 dBm sine wave input for the clock. When connecting the analog input source, it is recommended to use a multipole, narrow-band, band-pass filter with 50 terminations. Good choices of such band-pass filters are available from TTE, Allen Avionics, and K&L Microwave, Inc. The filter should be connected directly to the evaluation board if possible. See Figure 90 to Figure 100 for the complete schematics and layout diagrams demonstrating the routing and grounding techniques that should be applied at the system level. POWER SUPPLIES This evaluation board has a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The other end of the supply is a 2.1 mm inner diameter jack that connects to the PCB at P701. Once on the PC board, the 6 V supply is fused and conditioned before connecting to three low dropout linear regulators that supply the proper bias to each of the various sections on the board. OUTPUT SIGNALS The default setup uses the Analog Devices HSC-ADC-FPGA-8Z high speed deserialization board to deserialize the digital output data and convert it to parallel CMOS. These two channels interface directly with the Analog Devices standard dual-channel FIFO data capture board (HSC-ADC-EVALB-DCZ). Two of the eight channels can then be evaluated at the same time. For more information on the channel settings and optional settings of these boards, visit www.analog.com/FIFO. When operating the evaluation board in a nondefault condition, L701 to L704 can be removed to disconnect the switching power supply. This enables the user to bias each section of the board individually. Use P702 to connect a different supply for each WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz CLK - + - + - + AVDD_3.3V GND 3.3V_D GND 1.5V_FPGA GND VCC GND 3.3V + AD9222 EVALUATION BOARD ROHDE & SCHWARZ, SMA, 2V p-p SIGNAL SYNTHESIZER 1.5V - GND AVDD_5V XFMR INPUT 3.3V 3.3V + CH A TO CH H 12-BIT SERIAL LVDS HSC-ADC-FPGA-8Z HIGH SPEED DESERIALIZATION BOARD 2-CH SPI Figure 86. Evaluation Board Connection Rev. C | Page 40 of 60 12-BIT PARALLEL CMOS SPI HSC-ADC-EVALB-DCZ FIFO DATA CAPTURE BOARD USB CONNECTION SPI PC RUNNING ADC ANALYZER AND SPI USER SOFTWARE SPI 05967-070 BAND-PASS FILTER 1.8V - DRVDD_DUT - GND ROHDE & SCHWARZ, SMA, 2V p-p SIGNAL SYNTHESIZER 1.8V + + GND 5.0V - SWITCHING POWER SUPPLY AVDD_DUT 6V DC 2A MAX AD9222 50 terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9222 Rev. A evaluation board. * POWER: Connect the switching power supply that is provided with the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P701. * AIN: The evaluation board is set up for a transformercoupled analog input with an optimum 50 impedance match of 150 MHz of bandwidth (see Figure 87). For more bandwidth response, the differential capacitor across the analog inputs can be changed or removed. The common mode of the analog inputs is developed from the center tap of the transformer or AVDD_DUT/2. A differential LVPECL clock can also be used to clock the ADC input using the AD9515 (U401). Populate R406 and R407 with 0 resistors and remove R215 and R216 to disconnect the default clock path inputs. In addition, populate C205 and C206 with a 0.1 F capacitor and remove C409 and C410 to disconnect the default clock path outputs. The AD9515 has many pin-strappable options that are set to a default mode of operation. Consult the AD9515 data sheet for more information about these and other options. In addition, an on-board oscillator is available on the OSC401 and can act as the primary clock source. The setup is quick and involves installing R403 with a 0 resistor and setting the enable jumper (J401) to the on position. If the user wishes to employ a different oscillator, two oscillator footprint options are available (OSC401) to check the ADC performance. 0 -2 -3dB CUTOFF = 150MHz AMPLITUDE (dBFS) -4 -6 -8 -10 * PDWN: To enable the power-down feature, short J301 to the on position (AVDD) on the PDWN pin. * SCLK/DTP: To enable the digital test pattern on the digital outputs of the ADC, use J304. If J304 is tied to AVDD during device power-up, Test Pattern 1000 0000 0000 is enabled. See the SCLK/DTP Pin section for details. * SDIO/ODM: To enable the low power, reduced signal option (similar to the IEEE 1595.3 reduced range link LVDS output standard), use J303. If J303 is tied to AVDD during device power-up, it enables the LVDS outputs in a low power, reduced signal option from the default ANSI-644 standard. This option changes the signal swing from 350 mV p-p to 200 mV p-p, reducing the power of the DRVDD supply. See the SDIO/ODM Pin section for more details. * CSB: To enable processing of the SPI information on the SDIO and SCLK pins, tie J302 low in the always enable mode. To ignore the SDIO and SCLK information, tie J302 to AVDD. * Non-SPI Mode: For users who wish to operate the DUT without using SPI, remove Jumpers J302, J303, and J304. This disconnects the CSB, SCLK/DTP, and SDIO/ODM pins from the control bus, allowing the DUT to operate in its simplest mode. Each of these pins has internal termination and will float to its respective level. * D + x, D - x: If an alternative data capture method to the setup shown in Figure 90 is used, optional receiver terminations, R318 and R320 to R328, can be installed next to the high speed backplane connector. -12 -14 -18 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) 05967-071 -16 Figure 87. Evaluation Board Full-Power Bandwidth, AD9222-50 * VREF: VREF is set to 1.0 V by tying the SENSE pin to ground, R317. This causes the ADC to operate in 2.0 V p-p full-scale range. A separate external reference option using the ADR510 or ADR520 is also included on the evaluation board. Populate R312 and R313 and remove C307. Proper use of the VREF options is noted in the Voltage Reference section. * RBIAS: RBIAS has a default setting of 10 k (R301) to ground and is used to set the ADC core bias current. * CLOCK: The default clock input circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T401) that adds a very low amount of jitter to the clock path. The clock input is Rev. C | Page 41 of 60 AD9222 * Remove R102, R115, R128, R141, R161, R162, R163, R164, R202, R208, R218, R225, R234, R241, R252, R259, T101, T102, T103, T104, T201, T202, T203, and T204 in the default analog input path. * Populate R101, R114, R127, R140, R201, R217, R233, and R251 with 0 resistors in the analog input path. * Populate R152, R153, R154, R155, R156, R157, R158, R159, R215, R216, R229, R230, R247, R248, R263, R264, C103, C105, C110, C112, C117, C119, C124, C126, C203, C205, C210, C212, C217, C219, C224, and C226 with 10 k resistors to provide an input common-mode level to the ADC analog inputs. * Remove L507, L508, L511, L512, L515, L516, L519, L520, L607, L608, L611, L612, L615, L616, L619, and L620 on the AD8334 analog outputs. * Populate L507, L508, L511, L512, L515, L516, L519, L520, L607, L608, L611, L612, L615, L616, L619, and L620 with 680 nH inductors. * Populate C543, C547, C551, C555, C643, C647, C651, and C655 with a 68 pF capacitor. 680nH Figure 88. Example Filter Configured for16 MHz, Two-Pole Low-Pass Filter 0 fSAMPLE = 50MSPS Remove R515, R520, R527, R532, R615, R620, R627, and R632 on the AD8334 analog outputs. * Remove R512, R524, R612, and R624 to set the AD8334 mode and AD8334 HILO pin low. Some applications may require this to be different. Consult the AD8334 data sheet for more information on these functions. AIN = 3.5MHz AD8334 = MAX GAIN SETTING -20 -40 -60 -80 -100 Populate R105, R113, R118, R124, R131, R137, R151, R160, R205, R213, R221, R222, R237, R238, R255, and R256 with 0 resistors in the ADC analog input path to connect the VGA outputs. * 68pF 680nH -120 05967-108 To configure the analog input to drive the VGA instead of the default transformer option, the following components need to be removed and/or changed. * 05967-107 The following is a brief description of the alternative analog input drive configuration using the AD8334 dual VGA. If this drive option is in use, some components may need to be populated, in which case all the necessary components are listed in Table 17. For more details on the AD8334 dual VGA, including how it works and its optional pin settings, consult the AD8334 data sheet. In this example, a 16 MHz, two-pole low-pass filter was applied to the AD8334 outputs. The following components need to be removed and/or changed: AMPLITUDE (dBFS) ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 FREQUENCY (MHz) Figure 89. AD9222 FFT Example Results Using 16 MHz, Two-Pole Low-Pass Filter Applied to the AD8334 Outputs (fSAMPLE = 50 MSPS, AIN = 3.5 MHz, AD8334 = Maximum Gain Setting, Analog Input Signal = -1.03 dBFS, SNR = 60.8 dBc, SFDR = 67.02 dBc) In this configuration, L505 to L520 and L605 to L620 are populated with 0 resistors to allow signal connection and use of a filter if additional requirements are necessary. Rev. C | Page 42 of 60 Rev. C | Page 43 of 60 Channel A P101 Figure 90. Evaluation Board Schematic, DUT Analog Inputs VGA Input Connection R115 64.9 R114 0-DNP INH2 R102 64.9 R101 0-DNP DNP: DO NOT POPULATE. Ain P103 Channel B Ain INH1 Ain DNP P104 Ain 0 R117 R103 0 DNP P102 C109 0.1F C108 0.1F AVDD_DUT R116 0 FB104 10 E102 R125 1K R126 1k 1 R113 3 2 C114 0.1F 0-DNP R124 4 5 6 R118 0-DNP C107 0.1F 0-DNP 4 5 6 R105 0-DNP T101 1 T102 3 2 1 CM2 CH_B CM2 CH_B CM1 CH_A CM1 CH_A R112 1k 1 R111 1k E101 C102 0.1F C101 0.1F AVDD_DUT FB101 10 R104 0 C113 DNP R120 DNP CM2 C106 DNP R107 DNP CM1 R119 DNP R106 DNP R162 499 FB106 10 FB105 10 FB103 10 R161 499 FB102 10 R122 33 R121 33 R110 33 R108 33 C110 DNP C103 DNP R156 DNP R109 1k R157 DNP R123 1k AVDD_DUT C112 DNP C111 2.2pF R153 DNP AVDD_DUT AVDD_DUT C105 DNP C104 2.2pF R152 DNP AVDD_DUT VIN_B VIN_B VIN_A VIN_A Ain INH4 Channel C P105 Channel D P107 Ain R141 64.9 R140 0-DNP VGA Input Connection R128 64.9 R127 0-DNP VGA Input Connection INH3 Ain DNP P108 Ain P106 DNP R142 0 R129 0 1 CM3 CH_C CM3 CH_C E104 C123 0.1F C122 0.1F R149 1k R150 1k 1 3 2 1 3 2 1 4 5 6 T104 4 5 6 R151 0-DNP C121 0.1F 0-DNP R137 T103 R131 0-DNP C128 0.1F R160 CH_D CM4 0-DNP CM4 CH_D R138 1k R139 1k E103 C116 0.1F C115 0.1F AVDD_DUT R143 0 FB110 10 AVDD_DUT FB107 10 R130 0 C127 DNP R145 DNP CM4 C120 DNP R133 DNP CM3 R144 DNP R132 DNP FB109 10 FB111 10 FB112 10 R164 499 R163 499 FB108 10 R147 33 C124 DNP R146 33 R136 33 C117 DNP R134 33 R159 DNP VIN_D R148 1k VIN_D R155 DNP AVDD_DUT C126 DNP VIN_C R158 DNP AVDD_DUT C125 2.2pF VIN_C R135 1k AVDD_DUT C119 DNP C118 2.2pF R154 DNP AVDD_DUT 05967-072 VGA Input Connection AD9222 Rev. C | Page 44 of 60 Ain Figure 91. Evaluation Board Schematic, DUT Analog Inputs (Continued) P203 Channel F VGA Input Connection R218 64.9 R217 0-DNP INH6 R202 64.9 R201 0-DNP DNP: DO NOT POPULATE. Ain P201 Channel E INH5 Ain DNP P204 Ain DNP P202 R219 0 R203 0 C209 0.1F C208 0.1F AVDD_DUT R220 0 FB204 10 1 R231 1k 2 3 CM6 R232 1k 1 CH_F CM6 CH_F 4 4 5 6 C214 0.1F 0-DNP R222 T202 R221 0-DNP C207 0.1F 0-DNP 5 6 3 R213 T201 R205 0-DNP 2 1 1 CM5 CH_E CM5 CH_E R211 1k R212 1k E202 E201 C202 0.1F C201 0.1F AVDD_DUT FB201 10 R204 0 C213 DNP R224 DNP CM6 C206 DNP R207 DNP CM5 R223 DNP R206 DNP R225 499 FB206 10 FB205 10 FB203 10 R208 499 FB202 10 R227 33 R226 33 R210 33 R209 33 C210 DNP C203 DNP R215 DNP R229 DNP R228 1k AVDD_DUT C212 DNP C211 2.2pF R230 DNP AVDD_DUT VIN_E VIN_E VIN_F VIN_F R214 1k AVDD_DUT C205 DNP C204 2.2pF R216 DNP AVDD_DUT Ain DNP P207 Channel H Ain P205 Channel G R252 64.9 R251 0-DNP INH8 VGA Input Connection R234 64.9k R233 0-DNP INH7 VGA Input Connection Ain DNP P208 Ain DNP P206 R253 0 R235 0 1 E204 C223 0.1F C222 0.1F R265 1k R266 1k 1 CH_H CM8 CH_H 3 2 1 3 2 1 CM8 CM7 CH_G CM7 CH_G R249 1k R250 1k E203 C216 0.1F C215 0.1F AVDD_DUT R254 0 FB210 10 AVDD_DUT FB207 10 R236 0 4 5 6 R256 C228 0.1F 0-DNP 4 5 T204 6 R255 0-DNP C221 0.1F 0-DNP R238 T203 R237 0-DNP C227 DNP R258 DNP CM8 C220 DNP R240 DNP CM7 R257 DNP R239 DNP FB211 10 FB209 10 FB212 10 R259 499 R241 499 FB208 10 R261 33 C224 DNP R260 33 R245 33 C217 DNP R242 33 R263 DNP VIN_H R262 1k VIN_H R264 DNP AVDD_DUT C226 DNP VIN_G R247 DNP AVDD_DUT C225 2.2pF VIN_G R246 1k AVDD_DUT C219 DNP C218 2.2pF R248 DNP AVDD_DUT 05967-073 VGA Input Connection AD9222 Rev. C | Page 45 of 60 16 D+H D-H DRVDD DRGND D+C VIN-D D-C VIN+D D+D RBIAS FCO+ D-D FCO- DCO+ DCO- AVDD D+E VIN+E VIN-E D-E D+F AVDD D-F VIN+F VIN-F D+G D-G 30 29 28 27 26 25 24 23 22 21 20 19 18 17 CHB CHD CHD FCO FCO Figure 92. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface CHC CHC C305 0.1F VOUT CHB R308 470k AVDD 32 ADR510ARTZ 1.0V D-B 31 R310 10k R311 DNP R313 DNP C307 1F R312 DNP VREF_DUT Remove C214 when using external Vref C306 0.1F Reference Circuitry R306 100k TRIM/NC D+B R309 4.99k CHA CHA DRVDD_DUT GND AVDD_DUT 1k 1 J301 J302 J303 J304 R317 0 R31 DNP R315 DNP R314 DNP Vref Select SCLK_DTP 1 1 SDIO_ODM CSB_DUT 1 R304 DNP R307 10k U302 33 34 35 36 37 38 39 R305 100k OPTIONAL EXT REF VIN-C AVDD_DUT D-A D+A DRVDD DRGND AVDD SCLK/DTP SDIO/ODM R319 R303 100k 3 3 3 3 VREF = 1V CHH CHG CHF CHE CHD CHC CHB CHA FCO DCO SDO_CHB CSB4_CHB CSB3_CHB SDI_CHB SCLK_CHB VSENSE_DUT NC DTP Enable ODM Enable ALWAYS ENABLE SPI PWDN ENABLE VREF = 0.5V(1 + R219/R220) VREF = External VREF = 0.5V 2 DNP: DO NOT POPULATE. CHH 15 14 13 AVDD AVDD U301 40 AVDD_DUT R302 DNP CHH DRVDD_DUT GND 12 CLK+ CSB 41 42 VIN_A VIN_A AVDD_DUT VIN_B VIN_B AVDD_DUT 2 AVDD_DUT AVDD_DUT 11 VIN+C 10 CLK- PDWN AVDD 43 44 45 46 47 48 2 CLK 9 REFB CLK REFT AD9222BCPZ-65 VREF AVDD SENSE 8 AVDD VIN+A VIN-A AVDD VIN-B VIN+B AVDD AVDD_DUT 2 AVDD_DUT SLUG 7 0 AVDD_DUT 64 VIN+H VIN_F 63 6 VIN_F 62 VIN_H AVDD_DUT 61 VIN-H VIN_E 60 5 VIN_E 59 VIN_H 58 AVDD 57 VIN-G AVDD_DUT 56 4 VREF_DUT 55 3 54 VIN_G VSENSE_DUT 53 AVDD_DUT VIN_D 52 VIN+G R301 10k 51 VIN_G VIN_D 50 AVDD AVDD_DUT 49 2 C304 0.1F VIN_C 1 C303 4.7F Reference Decoupling VIN_C AVDD_DUT C302 0.1F C301 0.1F 1 21 2 22 3 23 4 24 5 25 6 26 7 27 8 28 9 29 10 30 31 51 32 52 33 53 34 54 35 55 36 56 37 57 38 58 39 59 40 60 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 P301 Digital Outputs GNDAB1 GNDAB2 GNDAB3 GNDAB4 GNDAB5 GNDAB6 GNDAB7 GNDAB8 GNDAB9 GNDAB10 GNDCD1 GNDCD2 GNDCD3 GNDCD4 GNDCD5 GNDCD6 GNDCD7 GNDCD8 GNDCD9 GNDCD10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 11 12 13 14 15 16 17 18 19 20 41 42 43 44 45 46 47 48 49 50 DNP DNP R328 SDO_CHA CSB2_CHA CSB1_CHA SDI_CHA SCLK_CHA CHH DNP R327 DNP R326 CHG DNP R325 CHF DNP R324 DNP R323 DNP R322 DNP R321 DNP R320 R318 CHE CHD CHC CHB CHA FCO DCO R318,R320-R328 Optional Output Terminations AD9222 AVDD_DUT CW GND DCO DCO CHE CHE CHF CHF CHG CHG 05967-074 Figure 93. Evaluation Board Schematic, Clock Circuitry Rev. C | Page 46 of 60 DNP: DO NOT POPULATE. R405 0 0 1 6 C411 0.1F R418 0 7 5 S7 S6 HSMS-2812-TR1G CR401 S8 9 4 8 S9 10 2 VREF 11 3 S10 S5 12 0 S9 S10 SIGNAL=DNC;27,28 S4 S3 S2 SIGNAL=AVDD_3.3V;4,17,20,21,24,26,29,30 S8 13 R416 E401 GND_PAD AD9515BCPZ S7 T401 R417 0 1 SYNCB CLKB S6 14 C403 0.1F R415 R413 10k 5 3 CLK AVDD_3.3V S5 15 Enc OPT_CLK R407 0 R412 DNP DNP R411 49.9 DNP 2 U401 R414 4.12k S4 DNP P402 R404 49.9 C402 0.1F OPT_CLK OPT_CLK R406 0 DNP R410 10k S3 S1 OUT0 OUT1B OUT1 OUT0B 16 Clock Circuit Enc P401 CRYSTAL_3 7 OPT_CLK DISABLE OSC401 R409 DNP RSET R403 0 DNP GND R402 10k 1 R408 DNP VS OUT 5 3 1 ENABLE OSC401 J401 S0 C410 0.1F 0.1F C409 18 19 22 23 R420 240 CLK R423 100 R421 240 R422 100 C408 0.1F DNP DNP C407 0.1F DNP 0.1F C406 DNP 0.1F C405 CLK CLIP SINE OUT (DEFAULT) OPTIONAL CLOCK DRIVE CIRCUIT GND 8 OE OE 3 32 OUT GND VCC VCC 2 1 10 12 14 Optional Clock Oscillator OSC401 AVDD_3.3V 31 Input Encode AVDD_3.3V R401 10k S2 25 3 S1 2 C401 0.1F 33 S0 1 AVDD_3.3V CLK R446 DNP LVDS OUTPUT CLK LVPECL OUTPUT C 41 2 0.1F C413 0.1F0.1F AVDD_3.3V S5 AVDD_3.3V S4 AVDD_3.3V S3 AVDD_3.3V S2 AVDD_3.3V S1 AVDD_3.3V S0 AVDD_3.3V C 4 14 DNP 0 0 0 0 0 0 C 415 0.1F R434 DNP R432 DNP R430 DNP R428 DNP R426 DNP R424 C416 0.1F R435 R433 R431 R429 R427 R425 0 0 0 0 0 0 C417 0.1F C 4 18 0.1F S10 AVDD_3.3V S9 AVDD_3.3V S8 AVDD_3.3V S7 AVDD_3.3V S6 AVDD_3.3V DNP R444 DNP R442 DNP R440 DNP R438 R436 0 0 0 0 0 AD9515 Pin-strap settings R445 R443 R441 R439 DNP R437 0 0 0 0 0 AD9222 6 05967-075 1 2 EXT VG CW GND VG12 EXT VG C515 0.018F L502 120nH Variable Gain Circuit (0-1.0V DC) VG12 External Variable Gain Drive Rev. C | Page 47 of 60 C524 0.1F 16 15 14 13 12 INH3 LMD3 VIN4 VIP4 LON4 LOP4 COM4X LMD1 LMD4 INH1 INH4 COM1 COM4 COM3 L501 120nH 0.1F C513 26 25 24 23 19 18 GND VG34 External Variable Gain Drive Figure 94. Evaluation Board Schematic, Optional DUT Analog Input Drive Rclamp Pin 27 VG34 AVDD_5V 22 20 R509 274 17 C527 0.018F HILO Pin=LO=+/- 50mV HILO Pin=H=+/- 75mV DNP 10k R510 COM34 VOH4 VOL4 VPS34 VOL3 VOH3 AVDD_5V 31 C532 0.1F VPS4 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 C540 0.1F CH_D AVDD_5V C542 DNP R514 187 R515 374 R516 DNP L505 0 AVDD_5V C541 0.1F L506 0 187 C550 DNP R526 187 R525 187 R527 374 R528 DNP L513 0 C549 0.1F L514 0 187 R530 C552 0.1F L517 0 R532 374 R533 DNP L518 0 C554 DNP 187 R531 C553 0.1F CH_A L520 0 C555 DNP C551 DNP L519 0 CH_A R534 DNP L516 0 CH_B R529 DNP L515 0 CH_B C548 0.1F AVDD_5V R519 C545 0.1F R518 R520 374 R521 DNP L510 0 C546 DNP 187 C544 0.1F L509 0 CH_C L512 0 C547 DNP L507 0 C543 DNP L511 0 CH_C Populate L505-L520 with 0 resistors or design your own filter. R522 DNP L508 0 CH_D R517 DNP MODE Pin Positive Gain Slope = 0-1.0V Negitive Gain Slope = 2.25-5.0V C535 10F C531 1000pF GAIN34 C530 0.1F CLMP34 0.1F HILO C529 VCM4 EN12 C528 0.1F COM3X LON3 LOP3 VIP3 EN34 C534 0.1F R512 10k VG34 Variable Gain Circuit (0-1.0V DC) DNP: DO NOT POPULATE. R508 274 INH1 C523 0.1F COM34 NC MODE COM12 VOH2 VOL2 VPS12 VOL1 VOH1 COM12 C533 10F R536 39k R535 10k R507 274 NC 2 0.1F C501 VIN3 CLMP12 VCM3 1 C503 22pF 11 COM2 VPS3 COM1X 10 LOP1 AVDD_5V LON1 AD8334ACPZ-REEL VIP1 VPS2 VIN1 9 64 VPS1 8 63 GAIN12 AVDD_5V 62 VIN2 C505 0.1F VIP2 61 7 60 6 59 LOP2 58 LON2 57 5 56 4 55 INH2 C518 AVDD_5V C511 0.1F JP502 AVDD_5V 54 R513 187 0.1F VG12 COM2X 53 3 52 LMD2 51 VCM2 2 R504 10k VCM1 INH2 50 1 U501 AVDD_5V 0.1F C506 HILO Pin=LO=+/- 50mV HILO Pin=H=+/- 75mV Rclamp Pin AVDD_5V 49 R524 10k 0.1F C522 C538 0.1F C537 0.1F C504 0.1F DNP 10k R506 R505 10k C509 0.1F INH3 INH4 C508 0.1F C510 10F R502 39k R501 10k C507 1000pF Power Down Enable (0-1V=Disable Power) C512 10F 05967-076 JP501 AD9222 R523 10k C536 0.1F R511 10k 30 29 28 21 C526 22pF L504 120nH 0.1F C525 R503 274 C502 0.018F C521 0.018F C514 22pF C520 22pF L503 120nH 0.1F C519 CW AVDD_5V 1 CW C615 0.018F L602 120nH GND VG56 Variable Gain Circuit (0-1.0V DC) VG56 External Variable Gain Drive Rev. C | Page 48 of 60 R608 274 INH5 C624 0.1F 16 15 INH3 LMD3 COM3X LON3 LOP3 GAIN34 VPS4 VIN4 LOP4 VIP4 COM4X LMD4 INH1 INH4 COM1 COM4 COM3 L601 120nH 0.1F C613 AVDD_5V 30 27 26 VG78 25 AVDD_5V 24 23 20 19 18 17 VG78 External Variable Gain Drive Figure 95. Evaluation Board Schematic, Optional DUT Analog Input Drive (Continued) Rclamp Pin HILO Pin=LO=+/- 50mV HILO Pin=H=+/- 75mV DNP 10k R610 LON4 31 R609 274 C632 0.1F CLMP34 32 C627 0.018F C631 1000pF HILO C630 0.1F EN12 0.1F VCM4 C629 EN34 C628 0.1F COM34 VOH4 VOL4 VPS34 VOL3 NC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 C634 0.1F C635 10F R612 10k VG78 Variable Gain Circuit (0-1.0V DC) DNP: DO NOT POPULATE. R607 274 14 13 12 VOH3 COM34 NC MODE COM12 VOH2 VOL2 VPS12 VOL1 VOH1 COM12 C633 10F R635 39k R634 10k C623 0.1F VIP3 VIN3 CLMP12 VCM3 2 0.1F C601 EXT VG C603 22pF 11 LMD1 VPS3 COM1X AD8334ACPZ-REEL LON1 VPS2 VIP1 10 COM2 VIN2 LOP1 9 64 VIN1 AVDD_5V 63 VPS1 8 62 7 C605 0.1F GAIN12 AVDD_5V 61 VIP2 60 LOP2 59 6 58 INH6 C618 57 0.1F 56 LON2 55 COM2X AVDD_5V 5 54 4 53 3 52 VCM2 LMD2 51 VCM1 2 VG56 50 INH2 49 1 U601 C606 10k JP602 AVDD_5V 0.1F Rclamp Pin HILO Pin=LO=+/- 50mV HILO Pin=H=+/- 75mV AVDD_5V R604 0.1F C622 C617 0.1F C616 0.1F C604 0.1F DNP 10k R606 R605 10k C609 0.1F INH7 INH8 C608 0.1F C610 10F R602 39k R601 10k C607 1000pF AVDD_5V Power Down Enable (0-1V=Disable Power) AVDD_5V AVDD_5V CH_H C642 DNP R614 187 R615 374 187 R618 R620 374 C645 0.1F L610 0 C646 DNP C640 0.1F C644 0.1F L609 0 R621 DNP C641 0.1F L606 0 R616 DNP L605 0 L612 0 C647 DNP C643 DNP L607 0 CH_G R625 187 AVDD_5V R623 10k R624 10k R619 187 C648 0.1F CH_F C651 DNP R629 DNP C649 0.1F L614 0 L616 0 CH_F R626 187 R627 374 R628 DNP L613 0 C650 DNP L615 0 Populate L605-L620 with 0 resistors or design your own filter. R622 DNP L611 0 CH_G R617 DNP L608 0 CH_H Positive Gain Slope = 0-1.0V Negative Gain Slope = 2.25-5.0V MODE Pin R613 187 1 2 EXT VG C612 10F R630 187 C652 0.1F L617 0 L619 0 CH_E R631 187 R632 374 R633 DNP L618 0 C654 DNP C653 0.1F CH_E L620 0 C655 DNP R636 DNP 05967-077 JP601 AD9222 C611 0.1F C636 0.1F 29 R611 10k 28 22 21 C626 22pF L604 120nH R603 274 0.1F C625 C602 0.018F C621 0.018F C614 22pF C620 22pF L603 120nH 0.1F C619 GND CW AVDD_5V 4 OPTIONAL GREEN Rev. C | Page 49 of 60 Figure 96. Evaluation Board Schematic, Power Supply Inputs and SPI Interface Circuitry ADP3339ZAKC-1.8-RL GND 1 2 OUT 4 OUT 4 J702 1 E701 C717 1F L706 10H C715 1F L705 10H 0-DNP R704 DUT_DRVDD DUT_AVDD 0-DNP R705 R711 10k C721 1F PWR_IN C719 1F PWR_IN R714 10k R715 10k 3 IN IN U706 3 ADP3339ZAKC-3.3-RL U703 3 A2 GND 1 A1 2 Y1 Y2 R712 1k SDIO_ODM 2 OUT 4 OUT 2 OUT 4 OUT 4 VCC 5 6 Y2 4 VCC 5 Y1 6 NC7WZ16P6X_NL U702 ADP3339ZAKC-5-RL7 U705 GND 3 A2 2 1 A1 NC7W207P6X_NL GND DNP: DO NOT POPULATE. GND C716 1F 2 IN 10 U704 MCLR/GP3 9 3 CR701 1 PWR_IN 8 2 GP0 7 OUT OUT GP1 6 GND 1 5 ADP3339ZAKC-1.8-RL PICVCC 4 ISP 2 3 C714 1F MCLR/GP3 1 IN 5 PICVCC 3 PIC12F629-I/SNG GP0 C703 0.1F PWR_IN GP1 MCLR/GP3 GP2 GP4 GP1 C702 0.1F U707 R702 261 4 0-DNP AVDD_DUT C722 1F L708 10H C720 1F L707 10H CSB_DUT AVDD_DUT SCLK_DTP AVDD_DUT R713 1k 5V_AVDD 3.3V_AVDD R710 1k AVDD_3.3V AVDD_DUT AVDD_DUT AVDD_5V AVDD_3.3V C744 0.1F C730 0.1F C723 0.1F Input Optional Power 3 2 C741 0.1F C746 0.1F C732 0.1F C725 0.1F P8 P7 P6 P5 P4 P3 P2 P1 P702 DNP 8 7 6 5 4 3 2 1 DRVDD_DUT C747 0.1F C733 0.1F C726 0.1F Decoupling Capacitors C740 0.1F C745 0.1F C731 0.1F C724 0.1F 1 7.5V POWER CON005 2.5MM JACK P701 6V, 2A max Power Supply Input C748 0.1F C734 0.1F C742 0.1F C743 0.1F AVDD_5V C735 0.1F DUT_DRVDD DUT_AVDD 5V_AVDD 3.3V_AVDD 10F C704 C727 0.1F F701 NANOSMDC110F-2 D701 C749 0.1F S2A-TP C750 0.1F L704 10H L702 10H L701 10H L703 10H C711 10F C707 10F C705 10F C709 10F FER701 C751 0.1F 4 1 3 2 C752 0.1F D702 C712 0.1F C753 0.1F DRVDD_DUT C708 0.1F AVDD_DUT C706 0.1F AVDD_5V C710 0.1F AVDD_3.3V SK33-TP +1.8V +1.8V +5.0V +3.3V GREEN PIC PROGRAMMING HEADER RESET/ REPROGRAM 3 2 6 7 0 GP0 0 R706 GP5 R707 3 0 2 R703 0 R708 R701 4.7k 8 REMOVE WHEN USING OR PROGRAMMING PIC (U402) PWR_IN R716 261 CR702 1 S701 VSS SDI_CHA R709 VDD U701 CSB1_CHA 1 3 SCLK_CHA 0.1F J701 AVDD_5V SDO_CHA C701 1 AVDD_3.3V SPI CIRCUITRY FROM FIFO 05967-078 +5V = PROGRAMMING = AVDD_5V +3.3V = NORMAL OPERATION = AVDD_3.3V AD9222 1 05967-079 AD9222 Figure 97. Evaluation Board Layout, Primary Side Rev. C | Page 50 of 60 05967-080 AD9222 Figure 98. Evaluation Board Layout, Ground Plane Rev. C | Page 51 of 60 05967-081 AD9222 Figure 99. Evaluation Board Layout, Power Plane Rev. C | Page 52 of 60 05967-082 AD9222 Figure 100. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev. C | Page 53 of 60 AD9222 Table 17. Evaluation Board Bill of Materials (BOM) 1 Item 1 2 Qnty. per Board 1 118 3 8 4 8 5 1 6 4 7 8 Reference Designator AD9222-65EBZ C101, C102, C107, C108, C109, C114, C115, C116, C121, C122, C123, C128, C201, C202, C207, C208, C209, C214, C215, C216, C221, C222, C223, C228, C301, C302, C304, C305, C306, C401, C402, C403, C409, C410, C411, C412, C413, C414, C415, C416, C417, C418, C501, C504, C505, C506, C508, C509, C511, C513, C518, C519, C522, C523, C524, C525, C528, C529, C530, C532, C534, C536, C537, C538, C601, C604, C605, C606, C608, C609, C611, C613, C616, C617, C618, C619, C622, C623, C624, C625, C628, C629, C630, C632, C634, C636, C701, C702, C703, C706, C708, C710, C712, C723, C724, C725, C726, C727, C730, C731, C732, C733, C734, C735, C740, C741, C742, C743, C744, C745, C746, C747, C748, C749, C750, C751, C752, C753 C104, C111, C118, C125, C204, C211, C218, C225 C510, C512, C533, C535, C610, C612, C633, C635 C303 C507, C531, C607, C631 C502, C515, C521, C527, C602, C615, C621, C627 Device PCB Capacitor Pkg. PCB 402 Value PCB 0.1 F, ceramic, X5R, 10 V, 10% tol Mfg. Mfg. Part Number Murata GRM155R71C104KA88D Capacitor 402 2.2 pF, ceramic, COG, 0.25 pF tol, 50 V Murata GRM1555C1H2R20CZ01D Capacitor 805 10 F, 6.3 V 10% ceramic, X5R Murata GRM219R60J106KE19D Capacitor 603 Murata GRM188R60J475KE19D Capacitor 402 Murata GRM155R71H102KA01D Capacitor 402 4.7 F, ceramic, X5R, 6.3 V, 10% tol 1000 pF, ceramic, X7R, 25 V, 10% tol 0.018 F, ceramic, X7R, 16 V, 10% tol AVX 0402YC183KAT2A Rev. C | Page 54 of 60 AD9222 Item 8 Qnty. per Board 8 9 1 10 9 11 16 12 4 13 Reference Designator C503, C514, C520, C526, C603, C614, C620, C626 C704 Device Capacitor Pkg. 402 Value 22 pF, ceramic, NPO, 5% tol, 50 V Mfg. Murata Mfg. Part Number GRM1555C1H220JZ01D Capacitor 1206 Rohm TCA1C106M8R Capacitor 603 10 F, tantalum, 16 V, 20% tol 1 F, ceramic, X5R, 6.3 V, 10% tol Murata GRM188R61C105KA93D Capacitor 805 0.1 F, ceramic, X7R, 50 V, 10% tol Murata GRM21BR71H104KA01L Murata GRM188R60J106ME47D Avago Technologies Panasonic Micro Commercial Co. Micro Commercial Co. Tyco/Raychem HSMS-2812-TR1G Murata DLW5BSN191SQ2L Murata BLM18BA100SN1D Samtec TSW-102-07-G-S Samtec TSW-103-07-G-S Samtec TSW-105-08-G-D Murata BLM31PG500SN1L Murata LQG15HNR12J02D Capacitor 603 1 C307, C714, C715, C716, C717, C719, C720, C721, C722 C540, C541, C544, C545, C548, C549, C552, C553, C640, C641, C644, C645, C648, C649, C652, C653 C705, C707, C709, C711 CR401 Diode SOT-23 14 15 2 1 CR701, CR702 D702 LED Diode 603 DO-214AB 10 F, ceramic, X5R, 6.3 V, 20% tol 30 V, 20 mA, dual Schottky Green, 4 V, 5 m candela 3 A, 30 V, SMC 16 1 D701 Diode DO-214AA 5 A, 50 V, SMC 17 1 F701 Fuse 1210 18 1 FER701 Choke coil 2020 19 24 Ferrite bead 603 20 4 Connector 2-pin 21 6 Connector 3-pin 23 1 FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112, FB201, FB202, FB203, FB204, FB205, FB206, FB207, FB208, FB209, FB210, FB211, FB212 JP501, JP502, JP601, JP602 J301, J302, J303, J304, J401, J701 J702 6.0 V, 2.2 A trip-current resettable fuse 10 H, 5 A, 50 V, 190 @ 100 MHz 10 , test frequency 100 MHz, 25% tol, 500 mA Connector 10-pin 24 8 Ferrite bead 1210 25 8 L701, L702, L703, L704, L705, L706, L707, L708 L501, L502, L503, L504, L601, L602, L603, L604 Inductor 402 100 mil header jumper, 2-pin 100 mil header jumper, 3-pin 100 mil header, male, 2 x 5 double row straight 10 H, bead core 3.2 x 2.5 x 1.6 SMD, 2 A 120 nH, test freq 100 MHz, 5% tol, 150 mA Rev. C | Page 55 of 60 LNJ314G8TRA SK33-TP S2A-TP NANOSMDC110F-2 AD9222 Item 26 Qnty. per Board 32 27 1 28 9 29 Reference Designator L505, L506, L507, L508, L509, L510, L511, L512, L513, L514, L515, L516, L517, L518, L519, L520, L605, L606, L607, L608, L609, L610, L611, L612, L613, L614, L615, L616, L617, L618, L619, L620 OSC401 Device Resistor Pkg. 805 Value 0 , 1/8 W, 5% tol Mfg. NIC Components Corp. Mfg. Part Number NRC04Z0TRF Oscillator SMT Clock oscillator, 50.00 MHz, 3.3 V, 5% duty cycle Side-mount SMA for 0.063" board thickness Valphey Fisher VFAC3H-L-50MHz Johnson Components 142-0701-851 1469169-1, right angle 2-pair, 25 mm, header assembly RAPC722, power supply connector 10 k, 1/16 W, 5% tol Tyco 6469169-1 Switchcraft RAPC722X NIC Components Corp. NRC04J103TRF Connector SMA 1 P101, P103, P105, P107, P201, P203, P205, P207, P401 P301 Connector HEADER 30 1 P701 Connector 0.1", PCMT 31 21 Resistor 402 32 18 Resistor 402 0 , 1/16 W, 5% tol NIC Components Corp. NRC04Z0TRF 33 8 Resistor 402 64.9 , 1/16 W, 1% tol 8 Resistor 603 0 , 1/10 W, 5% tol 35 28 Resistor 402 1 k, 1/16 W, 1% tol NIC Components Corp. NIC Components Corp. NIC Components Corp. NRC04F64R9TRF 34 36 16 R301, R307, R401, R402, R410, R413, R504, R505, R511, R512, R523, R524, R604, R605, R611, R612, R623, R624, R711, R714, R715 R103, R117, R129, R142, R203, R219, R235, R253, R317, R405, R415, R416, R417, R418, R706, R707, R708, R709 R102, R115, R128, R141, R202, R218, R234, R252 R104, R116, R130, R143, R204, R220, R236, R254 R109, R111, R112, R123, R125, R126, R135, R138, R139, R148, R149, R150, R211, R212, R214, R228, R231, R232, R246, R249, R250, R262, R265, R266, R319, R710, R712, R713 R108, R110, R121, R122, R134, R136, R146, R147, R209, R210, R226, R227, R242, R245, R260, R261 Resistor 402 33 , 1/16 W, 5% tol NIC Components Corp. NRC04J330TRF Rev. C | Page 56 of 60 NRC06Z0TRF NRC04F1001TRF AD9222 Item 37 Qnty. per Board 8 38 Device Resistor Pkg. 402 Value 499 , 1/16 W, 1% tol 3 Reference Designator R161, R162, R163, R164, R208, R225, R241, R259 R303, R305, R306 Resistor 402 100 k, 1/16 W, 1% tol 39 1 R414 Resistor 402 4.12 k, 1/16W, 1% tol 40 1 R404 Resistor 402 41 1 R309 Resistor 402 49.9 , 1/16 W, 0.5% tol 4.99 k, 1/16 W, 5% tol 42 5 R310, R501, R535, R601, R634 Potentiometer 3-lead 43 1 R308 Resistor 402 44 4 R502, R536, R602, R635 Resistor 402 39 k, 1/16 W, 5% tol 45 16 Resistor 402 187 , 1/16 W, 1% tol 46 8 Resistor 402 374 , 1/16 W, 1% tol 47 8 Resistor 402 274 , 1/16 W, 1% tol 48 11 Resistor 201 0 , 1/20 W, 5% tol 49 1 R513, R514, R518, R519, R525, R526, R530, R531, R613, R614, R618, R619, R625, R626, R630, R631 R515, R520, R527, R532, R615, R620, R627, R632 R503, R507, R508, R509, R603, R607, R608, R609 R425,R427, R429, R431, R433, R435, R436, R439, R441, R443, R445 R701 Resistor 402 4.7 k, 1/16 W, 1% tol 50 1 R702 Resistor 402 261 , 1/16 W, 1% tol 51 1 R716 Resistor 603 261 , 1/16 W, 1% tol 52 2 R420, R421 Resistor 402 240 , 1/16 W, 5% tol 53 2 R422, R423 Resistor 402 100 , 1/16 W, 1% tol 54 1 S701 Switch SMD LIGHT TOUCH, 100GE, 5 mm 10 k, Cermet trimmer potentiometer, 18 turn top adjust, 10%, 1/2 W 470 k, 1/16 W, 5% tol Rev. C | Page 57 of 60 Mfg. NIC Components Corp. NIC Components Corp. NIC Components Corp. Susumu NIC Components Corp. COPAL ELECTRONICS NIC Components Corp. NIC Components Corp. NIC Components Corp. Mfg. Part Number NRC04F4990TRF NRC04F1003TRF NRC04F4121TRF RR0510R-49R9-D NRC04F4991TRF CT94EW103 NRC04J474TRF NRC04J393TRF NRC04F1870TRF NIC Components Corp. NIC Components Corp. NIC Components Corp. NRC04F3740TRF NIC Components Corp. NIC Components Corp. NIC Components Corp. NIC Components Corp. NIC Components Corp. Panasonic NRC04J472TRF NRC04F2740TRF NRC02Z0TRF NRC04F2610TRF NRC06F261OTRF NRC04J241TRF NRC04F1000TRF EVQ-PLDA15 AD9222 Item 55 Qnty. per Board 9 56 2 Reference Designator T101, T102, T103, T104, T201, T202, T203, T204, T401 U704, U707 57 2 58 59 60 Device Transformer Pkg. CD542 IC SOT-223 U501, U601 IC CP-64-3 1 1 1 U706 U705 U301 IC IC IC SOT-223 SOT-223 CP-64-3 61 1 U302 IC SOT-23 62 1 U401 IC 63 1 U702 IC 64 1 U703 IC 65 1 U701 IC LFCSP CP-32-2 SC70, MAA06A SC70, MAA06A 8-SOIC 1 Value ADT1-1WT+, 1:1 impedance ratio transformer ADP33339AKC-1.8-RL, 1.5 A, 1.8 V LDO regulator AD8334ACPZ-REEL, ultralow noise precision dual VGA ADP3339AKC-5-RL7 ADP3339AKC-3.3-RL AD9222BCPZ-65, octal, 12-bit, 50 MSPS serial LVDS 1.8 V ADC ADR510ARTZ, 1.0 V, precision low noise shunt voltage reference AD9515BCPZ, 1.6 GHz clock distribution IC NC7WZ07P6X_NL, UHS dual buffer NC7WZ16P6X_NL, UHS dual buffer Flash prog mem 1kx14, RAM size 64 x 8, 20 MHz speed, PIC12F controller series This BOM is RoHS compliant. Rev. C | Page 58 of 60 Mfg. Mini-Circuits Mfg. Part Number ADT1-1WT+ Analog Devices ADP3339AKCZ-1.8-RL Analog Devices AD8334ACPZ-REEL Analog Devices Analog Devices Analog Devices ADP3339AKCZ-5-RL ADP3339AKCZ-3.3-RL AD9222BCPZ-65 Analog Devices ADR510ARTZ Analog Devices AD9515BCPZ Fairchild NC7WZ07P6X_NL Fairchild NC7WZ16P6X_NL Microchip PIC12F629-I/SNG AD9222 OUTLINE DIMENSIONS 0.60 MAX 9.00 BSC SQ 0.60 MAX 64 1 49 48 PIN 1 INDICATOR PIN 1 INDICATOR 8.75 BSC SQ 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 16 17 33 32 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 12 MAX 7.25 7.10 SQ 6.95 EXPOSED PAD (BOTTOM VIEW) 0.20 REF 080108-C TOP VIEW COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 101. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm x 9 mm Body, Very Thin Quad (CP-64-3) Dimensions shown in millimeters 0.60 MAX 9.00 BSC SQ 0.60 MAX 48 64 1 49 PIN 1 INDICATOR PIN 1 INDICATOR 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 SEATING PLANE 16 17 33 32 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 12 MAX 7.65 7.50 SQ 7.35 EXPOSED PAD (BOTTOM VIEW) 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 102. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm x 9 mm Body, Very Thin Quad (CP-64-6) Dimensions shown in millimeters Rev. C | Page 59 of 60 041509-A 8.75 BSC SQ TOP VIEW AD9222 ORDERING GUIDE Model 1 AD9222ABCPZ-40 2 AD9222ABCPZRL7-402 AD9222ABCPZ-502 AD9222ABCPZRL7-502 AD9222ABCPZ-652 AD9222ABCPZRL7-652 AD9222BCPZ-40 AD9222BCPZRL7-40 AD9222BCPZ-50 AD9222BCPZRL7-50 AD9222BCPZ-65 AD9222BCPZRL7-65 AD9222-65EBZ 1 2 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel Evaluation Board Z = RoHS Compliant Part. Recommended for use in new designs; reference PCN 09_0156. (c)2006-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05967-0-1/10(C) Rev. C | Page 60 of 60 Package Option CP-64-6 CP-64-6 CP-64-6 CP-64-6 CP-64-6 CP-64-6 CP-64-3 CP-64-3 CP-64-3 CP-64-3 CP-64-3 CP-64-3