DGN−8
DDA−8D−8
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FEATURES DESCRIPTION
APPLICATIONS
_
+
RF
CF
λ
−V(Bias)
RL
Photodiode Circuit
THS4631
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
HIGH-VOLTAGE, HIGH SLEW RATE, WIDEBANDFET-INPUT OPERATIONAL AMPLIFIER
•High Bandwidth:
The THS4631 is a high-speed, FET-input operationalamplifier designed for applications requiring wideband– 325 MHz in Unity Gain
operation, high-input impedance, and high-power– 210 MHz Gain Bandwidth Product
supply voltages. By providing a 210-MHz gain•High Slew Rate:
bandwidth product, ±15-V supply operation, and– 900 V/µs (G = 2) 100-pA input bias current, the THS4631 is capable ofsimultaneous wideband transimpedance gain and– 1000 V/µs (G = 5)
large output signal swing. The fast 1000 V/µs slew•Low Distortion of –76 dB, SFDR at 5 MHz
rate allows for fast settling times and good harmonic•Maximum Input Bias Current: 100 pA
distortion at high frequencies. Low current and volt-age noise allow amplification of extremely low-level•Input Voltage Noise: 7 nV/ √Hz
input signals while still maintaining a large sig-•Maximum Input Offset Voltage: 500 µV at 25°C
nal-to-noise ratio.•Low Offset Drift: 2.5 µV/°C
The characteristics of the THS4631 make it ideally•Input Impedance: 10
9
|| 3.9 pF
suited for use as a wideband photodiode amplifier.Photodiode output current is a prime candidate for•Wide Supply Range: ± 5 V to ± 15 V
transimpedance amplification as shown below. Other•High Output Current: 95 mA
potential applications include test and measurementsystems requiring high-input impedance, ADC andDAC buffering, high-speed integration, and active•Wideband Photodiode Amplifier
filtering.•High-Speed Transimpedance Gain Stage
The THS4631 is offered in an 8-pin SOIC (D), and•Test and Measurement Systems
the 8-pin SOIC (DDA) and MSOP (DGN) with•Current-DAC Output Buffer
PowerPAD™ package.•Active Filtering
Related FET Input Amplifier Products•High-Speed Signal Integrator
SLEW VOLTAGE•High-Impedance Buffer
V
S
GBWP MINIMUMDEVICE RATE NOISE(V) (MHz) GAIN(V/µS) (nV/ √Hz)
OPA656 ±5 230 290 7 1
OPA657 ±5 1600 700 4.8 7
OPA627 ±15 16 55 4.5 1
THS4601 ±15 180 100 5.4 1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPad is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
PACKAGE DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
THS4631
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integratedcircuits be handled with appropriate precautions. Failure to observe proper handling and installationprocedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precisionintegrated circuits may be more susceptible to damage because very small parametric changes couldcause the device not to meet its published specifications.
over operating free-air temperature range (unless otherwise noted)
(1)
UNITS
V
S
Supply voltage, V
S–
to V
S+
33 VV
I
Input voltage ±V
S
I
O
(2)
Output current 150 mAContinuous power dissipation See Dissipation Rating TableT
J
Maximum junction temperature
(2)
150°CT
A
Operating free-air temperature, continues operation, long-term reliability
(2)
125°CT
stg
Storage temperature range 65°C to 150°CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300°CHBM 1000 VESD ratings: CDM 1500 VMM 100 V
(1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings maycause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These arestress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature mayresult in reduced reliability and/or lifetime of the device.
POWER RATING
(1)
(T
J
=125°C)PACKAGE θ
JC
(°C/W) θ
JA
(°C/W)
T
A
≤25°C T
A
= 85°C
D (8)
(2)
38.3 95 1.1 W 0.47 WDDA (8) 9.2 45.8 2.3 W 0.98 WDGN (8) 4.7 58.4 2.14 W 1.11 W
(1) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase.Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance.(2) This data was taken using the JEDEC standard High-K test PCB.
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNITS
Dual Supply ±5 ±15V
S
Supply Voltage VSingle Supply 10 30T
A
Operating free-air temperature -40 85 °C
2
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PIN ASSIGNMENTS
1
2
3
4
8
7
6
5
NC
VIN−
VIN+
VS−
NC
VS+
VOUT−
NC
NC = No Internal Connection
TOP VIEW D, DDA, AND DGN
THS4631
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
PACKAGE / ORDERING INFORMATION
PACKAGE DEVICES
(1)
PACKAGE TYPE SOIC – 8 TRANSPORT MEDIA, QUANTITY
THS4631D Rails, 75SOIC – 8THS4631DR Tape and Reel, 2500THS4631DDA Rails, 75SOIC-PP – 8
(2)THS4631DDAR Tape and Reel, 2500THS4631DGN Rails, 100MSOP-PP – 8
(2)THS4631DGNR Tape and Reel, 2500
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) PowerPad™ is electrically isolated from all other pins. Connection of the PowerPAD to the PCB ground plane is recommended becausethe ground plane is typically the largest copper area on a PCB. However, connection of the PowerPAD to V
S-
up to V
S+
is allowed ifdesired.
THS4631
3
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ELECTRICAL CHARACTERISTICS
THS4631
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
V
S
= ±15 V, R
F
= 499 Ω, R
L
= 1 k Ω, and G = 2 (unless otherwise noted)
TYP OVER TEMPERATUREPARAMETER TEST CONDITIONS
0°C to –40°C to MIN/25°C 25°C UNITS70°C 85°C MAX
AC PERFORMANCE
G = 1, R
F
= 0 Ω, V
O
= 200 mV
PP
325
G = 2, R
F
= 499 Ω, V
O
= 200 mV
PP
105Small signal bandwidth, -3 dB MHzG = 5, R
F
= 499 Ω, V
O
= 200 mV
PP
55
G = 10, R
F
= 499 Ω, V
O
= 200 mV
PP
25
Gain bandwidth product G > 20 210 MHz
0.1 dB bandwidth flatness G = 2, R
F
= 499 Ω, C
F
= 8.2 pF 38 MHz
Large-signal bandwidth G = 2, R
F
= 499 Ω, V
O
= 2 V
PP
105 MHz
G = 2, R
F
= 499 Ω, V
O
= 2-V step 550
Slew rate G = 2, R
F
= 499 Ω, V
O
= 10-V step 900 V/µs
G = 5, R
F
= 499 Ω, V
O
= 10-V step 1000
Rise and fall time 2-V step 5 ns
0.1%, G = -1, V
O
= 2-V step, C
F
= 4.7 pF 40Settling time ns0.01%, G = -1, V
O
= 2-V step, C
F
= 4.7 pF 190
HARMONIC DISTORTION
R
L
= 100 Ω-65Second harmonic distortion dBcG = 2,
R
L
= 1 k Ω-76V
O
= 2 V
PP
,
R
L
= 100 Ω-62f = 5 MHzThird harmonic distortion dBcR
L
= 1 k Ω-94
Input voltage noise f > 10 kHz 7 nV/ √Hz
Input current noise f > 10 kHz 20 fA/ √Hz
DC PERFORMANCE
Open-loop gain R
L
= 1 k Ω80 70 65 65 dB Min
Input offset voltage
(1)
260 500 1600 2000 µV MaxV
CM
= 0 VAverage offset voltage drift
(1)
25°C to 85°C ±2.5 ±10 ±12 ±12 µV/°C Max
Input bias current 50 100 1500 2000 pA MaxV
CM
= 0 VInput offset current 25 100 700 1000 pA Max
INPUT CHARACTERISTICS
-12.5 toCommon-mode input range -13 to 12 -12 to 11 -9 to 11 V Min11.5
Common-mode rejection ratio V
CM
= 10 V 95 86 80 80 dB Min
Differential input resistance 10
9
|| 3.9 Ω|| pF
Common-mode input resistance 10
9
|| 3.9 Ω|| pF
OUTPUT CHARACTERISTICS
R
L
= 100 Ω±11 ±10 ±9.5 ±9.5Output voltage swing V MinR
L
= 1 k Ω±13.5 ±13 ±12.8 ±12.8
Static output current (sourcing) R
L
= 20 Ω98 90 85 80 mA Min
Static output current (sinking) R
L
= 20 Ω95 85 80 80 mA Min
Closed loop output impedance G = 1, f = 1 MHz 0.1 Ω
POWER SUPPLY
±15 ±16.5 ±16.5 ±16.5 V MaxSpecified operating voltage
±5 ±4 ±4 ±4 V Min
Maximum quiescent current 11.5 13 14 14 mA Max
Minimum quiescent current 11.5 10 9 9 mA Min
Power supply rejection (PSRR +) V
S+
= 15.5 V to 14.5 V, V
S–
= 15 V 95 85 80 80 dB Min
Power supply rejection (PSRR –) V
S+
= 15 V, V
S–
= -15.5 V to -14..5 V 95 85 80 80 dB Min
(1) Input offset voltage is 100% tested at 25°C. It is specified by characterization and simulation over the listed temperature range.
4
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TYPICAL CHARACTERISTICS (±15 V GRAPHS)
_
+
THS4631
49.9 Ω
50 Ω Source
+15 V
953 Ω
499 Ω499 Ω
−15 V
49.9 Ω
Test Data
Mesurement Point
50 Ω Test
Equipment
CF
RF
RG
0
1
2
3
4
5
6
7
8
9
10
100 k 1 M 10 M 100 M 1 G
VO = 200 mVPP
G = 2, RF = 499 Ω,
RG = 499 Ω
105 MHz
f − Frequency − Hz
Signal Gain − dB
CF = 5.6 pF
CF = 0 pF
CF = 8.2 pF
5.6
5.7
5.8
5.9
6
6.1
6.2
6.3
100 k 1 M 10 M 100 M
f − Frequency − Hz
Signal Gain − dB
CF = 8.2 pF
38 MHz
−10
0
10
20
30
40
50
100 k 1 M 10 M 100 M 1 G
G = 100, RF = 11.3 kΩ, RG = 115 Ω
VO = 200 mVPP
G = 10, RF = 499 Ω,
RG = 54.9 Ω
G = 5, RF = 499 Ω,
RG = 124 Ω
G = 2, RF = 499 Ω,
RG = 499 Ω
G = 1, RF = 0 Ω
105 MHz
f − Frequency − Hz
Signal Gain − dB
−5
−4
−3
−2
−1
0
1
2
3
4
5
100 k 1 M 10 M 100 M 1 G
G = −1, RF = 499 Ω,
RG = 499 Ω
CF = 2.2 pF
CF = 0 pF
CF = 5.2 pF
VO = 200 mVPP
f − Frequency − Hz
Signal Gain − dB
102 MHz
0
1
2
3
4
5
6
7
8
100 k 1 M 10 M 100 M 1 G
VO = 0.5 VPP
VO = 2 VPP
f − Frequency − Hz
Signal Gain − dB
VO = 5 VPP
105 MHz
THS4631
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
T
A
= 25°C, G = 2, R
F
= 499 Ω, R
L
= 1 k Ω, Unless otherwise noted.
SMALL SIGNAL FREQUENCY SMALL SIGNAL FREQUENCYRESPONSE RESPONSE 0.1-dB FLATNESS
Figure 1. Figure 2. Figure 3.
FREQUENCY RESPONSESMALL SIGNAL FREQUENCY LARGE SIGNAL FREQUENCY vsRESPONSE RESPONSE CAPACiTIVE LOAD
Figure 4. Figure 5. Figure 6.
5
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-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
00.5 11.5 22.5 33.5 4
Harmonic Distortion - dB
VO- Output Voltage Swing - VPP
G = 2,
RF= 499 ,W
CF= 8.2 pF,
f = 4 MHz HD3, RL= 100 W
HD2, RL= 1 kW
HD3, RL= 1 kW
HD2, RL= 100 W
−90
−80
−70
−60
−50
−40
−30
1 M 10 M 100 M
2nd Order Harmonic Distortion − dB
f − Frequency − Hz
Gain = 2
RF = 499 Ω,
CF = 8.2 pF
VO = 2 VPP
RL = 100 Ω
RL = 1 kΩ
-1 10
-100
-90
-80
-70
-60
-50
-40
-30
1 M 10 M 100 M
f - Frequency - Hz
3rd Order Harmonic Distortion - dB
Gain = 2
RF= 499 W
CF= 8.2 pF
VO= 2 VPP
RL= 100 W
RL= 1 kW
−10
0
10
20
30
40
50
60
70
80
90
1 k 10 k 100 k 1 M 10 M 100 M 1 G
f − Frequency − Hz
Open−Loop Gain − dB
−200
−175
−150
−125
−100
−75
−50
−25
0
25
50
Phase −
0
200
400
600
800
1000
1200
0 2 4 6 8 10 12
VO − Output Voltage − VPP
G = 5,
RF = 499 Ω,
RG = 124 Ω
SR − Slew Rate − V/ µs
72
73
74
75
76
77
78
79
80
81
82
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
TC − Case Temperature − °C
Open-Loop Gain − dB
9
9.5
10
10.5
11
11.5
12
0 2 4 6 8 10 12 14 16
TA = 85°C
TA = 25°C
− Quiescent Current − mA
IQ
VS − Supply Voltage − V
TA = −40°C
nV/ HzInput Voltage Noise −
1
10
100
10 100 1 k 10 k 100 k
f − Frequency − Hz
0
100
200
300
400
500
600
700
800
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
IIB− Input Bias Current − pA
TA − Free-Air Temperature − °C
THS4631
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
TYPICAL CHARACTERISTICS (±15 V GRAPHS) (continued)T
A
= 25°C, G = 2, R
F
= 499 Ω, R
L
= 1 k Ω, Unless otherwise noted.
SECOND ORDER THIRD ORDERHARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTIONvs vs vsFREQUENCY FREQUENCY OUTPUT VOLTAGE SWING
Figure 7. Figure 8. Figure 9.
SLEW RATE OPEN-LOOP GAIN OPEN-LOOP GAIN AND PHASEvs vs vsOUTPUT VOLTAGE TEMPERATURE FREQUENCY
Figure 10. Figure 11. Figure 12.
INPUT VOLTAGE QUIESCENT CURRENT INPUT BIAS CURRENTvs vs vsFREQUENCY SUPPLY VOLTAGE TEMPERATURE
Figure 13. Figure 14. Figure 15.
6
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−300
−200
−100
0
100
200
300
25 35 45 55 65 75 85
Input Offset Voltage −
TA − Free-Air Temperature − °C
V
D Package
DDA Package
DGN Package
Referred to 25°C
0
25
50
75
100
125
150
175
200
225
250
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
IIO − Input Offset Current − pA
TA − Free-Air Temperature − °C
13.2
13.25
13.3
13.35
13.4
13.45
13.5
13.55
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
− Output Voltage − |V|
VO
TC − Case Temperature − °C
VO+
VO−
− Output Voltage − mVVO
−125
−100
−75
−50
−25
0
25
50
75
100
125
0 10 20 30 40 50 60 70 80
t − Time− ns
Gain = 2,
CF = 8.2 pF,
VI = 100 mVPP,
RL = 1 kΩ
−1.2
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
1.2
0 10 20 30 40 50 60 70 80
Gain = 2,
CF = 8.2 pF,
VI = 1 VPP,
RL = 1 kΩ
t − Time − ns
− Output Voltage − VVO
84
86
88
90
92
94
96
98
100
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Sink
Source
IO− Output Drive Current − |mA|
TC − Case Temperature − °C
-7
-5
-3
-1
1
3
5
7
020 40 60 80 100 120 140 180160
Gain = 5,
R = 499 ,
R = 1 k
F
L
W
W
10 VPP
t - Time - ns
- Output Voltage - VVO
-12
-8
-4
0
4
8
12
10
6
2
-2
-6
-10
020 40 60 80 100 120 140 180160
t - Time - ns
- Output Voltage - VVO
20 VPP
Gain = 5,
R= 499 ,W
R= 1 kW
F
L
Gain = 2,
CF = 8.2 pF,
VI = 2 VPP,
RL = 1 kΩ
− Output Voltage − VVO
−2.5
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
2.5
0 25 50 75 100 125 150
t − Time− ns
Gain = 2,
CF = 8.2 pF,
VI = 2 VPP,
RL = 1 kΩ
THS4631
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
TYPICAL CHARACTERISTICS (±15 V GRAPHS) (continued)T
A
= 25°C, G = 2, R
F
= 499 Ω, R
L
= 1 k Ω, Unless otherwise noted.
INPUT OFFSET CURRENT INPUT OFFSET VOLTAGE OUTPUT VOLTAGEvs vs vsTEMPERATURE TEMPERATURE TEMPERATURE
Figure 16. Figure 17. Figure 18.
STATIC OUTPUT DRIVE CURRENT
vs SMALL SIGNAL TRANSIENT LARGE SIGNAL TRANSIENTTEMPERATURE RESPONSE RESPONSE
Figure 19. Figure 20. Figure 21.
LARGE SIGNAL TRANSIENT LARGE SIGNAL TRANSIENT LARGE SIGNAL TRANSIENTRESPONSE RESPONSE RESPONSE
Figure 22. Figure 23. Figure 24.
7
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− Output Voltage − V
VO
t − Time − ns
−3
−2.5
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
2.5
3
0 5 10 15 20 25 30 35 40
Rising
Falling
G = −1,
CF = 4.7 pF
−20
−15
−10
−5
0
5
10
15
20
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1−4
−3
−2
−1
0
1
2
3
4
Gain = 5,
RF = 499 Ω,
RG = 124 Ω
t − Time − s
− Output Voltage − VVO
Input
Output
− Input Voltage − VVI
− Output Voltage − V
VO
t − Time − ns
−1.5
−1.25
−1
−0.75
−0.5
−0.25
0
0.25
0.5
0.75
1
1.25
1.5
0 5 10 15 20 25 30 35 40
Rising
Falling
G = −1,
CF = 4.7 pF
−20
−15
−10
−5
0
5
10
15
20
−0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35
−4
−3
−2
−1
0
1
2
3
4
Gain = 5,
RF = 499 Ω,
RG = 124 Ω
t − Time − s
− Output Voltage − VVO
Input
Output
− Input Voltage − VVI
0
10
20
30
40
50
60
70
80
90
100
−15 −10 −5 0 5 10 15
VICR − Input Common-Mode Range − V
CMRR − Common-Mode Rejection Ratio − dB
0.01
0.1
1
10
100
100 k 1 M 10 M 100 M 1 G
f − Frequency − Hz
− Output Impedance −ZoΩ
THS4631
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
TYPICAL CHARACTERISTICS (±15 V GRAPHS) (continued)T
A
= 25°C, G = 2, R
F
= 499 Ω, R
L
= 1 k Ω, Unless otherwise noted.
SETTLING TIME SETTLING TIME OVERDRIVE RECOVERY
Figure 25. Figure 26. Figure 27.
COMMON-MODE REJECTION RATIO REJECTION RATIOvs vsOVERDRIVE RECOVERY INPUT COMMON-MODE RANGE FREQUENCY
Figure 28. Figure 29. Figure 30.
OUTPUT IMPEDANCE
vsFREQUENCY
Figure 31.
8
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APPLICATION INFORMATION
INTRODUCTION
TRANSIMPEDANCE FUNDAMENTALS
_
+
RF
CF
λ
−V(Bias)
RL
Photodiode Circuit
DESIGNING THE TRANSIMPEDANCE
THS4631
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
The large gain-bandwidth product of the THS4631provides the capability for simultaneously achievingboth high-transimpedance gain, wide bandwidth, highThe THS4631 is a high-speed, FET-input operational
slw rate, and low noise. In addition, the high-poweramplifier. The combination of: high gain bandwidth
supply rails provide the potential for a very wideproduct of 210 MHz, high slew rate of 1000 V/µs, and
dynamic range at the output, allowing for the use oftrimmed dc precision makes the device an excellent
input sources which possess wide dynamic range.design option for a wide variety of applications,
The combination of these characteristics makes theincluding test and measurement, optical monitoring,
THS4631 a design option for systems that requiretransimpedance gain circuits, and high-impedance
transimpedance amplification of wideband, low-levelbuffers. The applications section of the data sheet
input signals. A standard transimpedance circuit isdiscusses these particular applications in addition to
shown in Figure 32 .general information about the device and its features
FET-input amplifiers are often used intransimpedance applications because of their ex-tremely high input impedance. A transimpedanceblock accepts a current as an input and converts thiscurrent to a voltage at the output. The high-inputimpedance associated with FET-input amplifiersminimizes errors in this process caused by the inputbias currents, IIB, of the amplifier.
Figure 32. Wideband Photodiode TransimpedanceCIRCUIT
AmplifierTypically, design of a transimpedance circuit is drivenby the characteristics of the current source that
As indicated, the current source typically sets theprovides the input to the gain block. A photodiode is
requirements for gain, speed, and dynamic range ofthe most common example of a capacitive current
the amplifier. For a given amplifier and source combi-source that interfaces with a transimpedance gain
nation, achievable performance is dictated by theblock. Continuing with the photodiode example, the
following parameters: the amplifier gain-bandwidthsystem designer traditionally chooses a photodiode
product, the amplifier input capacitance, the sourcebased on two opposing criteria: speed and sensitivity.
capacitance, the transimpedance gain, the amplifierFaster photodiodes cause a need for faster gain
slew rate, and the amplifier output swing. From thisstages, and more sensitive photodiodes require
information, the optimal performance of ahigher gains in order to develop appreciable signal
transimpedance circuit using a given amplifier islevels at the output of the gain stage.
determined. Optimal is defined here as providing therequired transimpedance gain with a maximized flatThese parameters affect the design of the
frequency response.transimpedance circuit in a few ways. First, the speedof the photodiode signal determines the required
For the circuit shown in Figure 32 , all but one of thebandwidth of the gain circuit. Second, the required
design parameters is known; the feedback capacitorgain, based on the sensitivity of the photodiode, limits
(C
F
) must be determined. Proper selection of thethe bandwidth of the circuit. Third, the larger capaci-
feedback capacitor prevents an unstable design,tance associated with a more sensitive signal source
controls pulse response characteristics, providesalso detracts from the achievable speed of the gain
maximized flat transimpedance bandwidth, and limitsblock. The dynamic range of the input signal also
broadband integrated noise. The maximized flat fre-places requirements on the amplifier dynamic range.
quency response results with CF calculated as shownKnowledge of the source output current levels,
in Equation 1 , where CF is the feedback capacitor, R
Fcoupled with a desired voltage swing on the output,
is the feedback resistor, CS is the total sourcedictates the value of the feedback resistor, RF. The
capacitance (including amplifier input capacitancetransfer function from input to output is VOUT = I
IN
R
F
.
and parasitic capacitance at the inverting node), andGBP is the gain-bandwidth product of the amplifier inhertz.
9
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CF
1
RFGBP 1
RFGBP2
4CS
RFGBP
2
(1)
F3dB GBP
2RFCSCF
(2)
Gain AOL
20 dB/Decade
Rate-of-Closure
GBP
20 dB/
Decade
Noise Gain
−20 dB/
Decade
f
PoleZero
0
_
+
CI(DIFF)
RF
CF
CP
CD
I(DIODE)
CI(CM)
CS = CI(CM) + CI(DIFF) + CP + CD
THS4631
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
Once the optimal feedback capacitor has been selec-ted, the transimpedance bandwidth can be calculatedwith Equation 2 .
Figure 34. Transimpedance Circuit Bode Plot
The performance of the THS4631 has beenmeasured for a variety of transimpedance gains witha variety of source capacitances. The achievablebandwidths of the various circuit configurations aresummarized numerically in Table 1 . The frequencyresponses are presented in Figure 35 , Figure 36 , andFigure 37 .A. The total source capacitance is the sum of
Note that the feedback capacitances do not corre-several distinct capacitances.
spond exactly with the values predicted by theFigure 33. Transimpedance Analysis Circuit
equation. They have been tuned to account for theparasitic capacitance of the feedback resistor(typically 0.2 pF for 0805 surface mount devices) asWhere:
well as the additional capacitance associated with theC
I(CM)
is the common-mode input capacitance.
PC board. The equation should be used as a startingC
I(DIFF)
is the differential input capacitance.
point for the design, with final values for CF optimizedC
D
is the diode capacitance.
in the laboratory.C
P
is the parasitic capacitance at the invertingnode.
Table 1. Transimpedance Performance Summaryfor Various ConfigurationsThe feedback capacitor provides a pole in the noisegain of the circuit, counteracting the zero in the noise
SOURCE TRANS- FEEDBACK -3 dBCAPACITANCE IMPEDANCE CAPACITANCE FREQUENCYgain caused by the source capacitance. The pole is
(PF) GAIN ( Ω) (PF) (MHZ)set such that the noise gain achieves a 20-dB per
18 10 k 2 15.8decade rate-of-closure with the open-loop gain re-
18 100 k 0.5 3sponse of the amplifier, resulting in a stable circuit.
18 1 M 0 1.2As indicated, the formula given provides the feedback
47 10 k 2.2 8.4capacitance for maximized flat bandwidth. Reductionin the value of the feedback capacitor can increase
47 100 k 0.7 2.1the signal bandwidth, but this occurs at the expense
47 1 M 0.2 0.52of peaking in the ac response.
100 10 k 3 5.5
100 100 k 1 1.4
100 1 M 0.2 0.37
10
www.ti.com
65
70
75
80
85
10 k 100 k 1 M 10 M 1 G
f − Frequency − Hz
Transimpedance Gain − dB
VS = ±15 V
RL = 1 k
RF = 10 k
CS = 100 PF
CF = 3 PF
CS = 18 PF
CF = 2 PF
CS = 47 PF
CF = 2.2 PF
50 50
RS
VS
C1
C2
IO
Network Analizer IO
VS(s) 1
2RS1C1
C2
(Above the Pole Frequency)
IO
VS(s)
s
2RS1C1
C2
s1
2 RSC1C2
(3)
85
90
95
100
105
10 k 100 k 1 M 10 M 1 G
f − Frequency − Hz
Transimpedance Gain − dB
VS = ±15 V
RL = 1 k
RF = 100 k
CS = 47 PF
CF = 0.7 PF
CS = 100 PF
CF = 1 PF
CS = 18 PF
CF = 0.5 PF
at:
1
2 RS(C1 C2)
. The transconductance is constant
at:
1
2 RS1C1
C2
, above the pole frequency, provid-
95
100
110
120
10 k 100 k 1 M 10 M
f − Frequency − Hz
Transimpedance Gain − dB
125
VS = ±15 V
RL = 1 k
RF = 1 M
115
105
CS = 18 PF
CF = 0 PF
CS = 47 PF
CF = 0.2 PF
CS = 100 PF
CF = 0.2 PF
ZO(s) C1 C2
C1 C2
s1
2RSC1C2
ss1
2 RSC1
(4)
MEASURING TRANSIMPEDANCE
ZO1
sC2
, giving the appearance of a capacitive
THS4631
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
10-k ΩTRANSIMPEDANCE RESPONSES
current as an input rather than a voltage. Also, thecapacitance of the current source has a direct effecton the frequency response. A simple interface circuitcan be used to emulate a capacitive current sourcewith a network analyzer. With this circuit,transimpedance bandwidth measurements are simpli-fied, making amplifier evaluation easier and faster.
Figure 35.
A. The interface network creates a capacitive,constant current source from a network100-k ΩTRANSIMPEDANCE RESPONSES
analyzer and properly terminates the net-work analyzer at high frequencies.
Figure 38. Emulating a Capacitive Current SourceWith a Network Analyzer
The transconductance transfer function of theinterface circuit is:
The transfer function contains a zero at dc and a poleFigure 36.
1-M ΩTRANSIMPEDANCE RESPONSES
ing a controllable ac-current source. This circuit alsoproperly terminates the network analyzer with 50 Ωathigh frequencies. The second requirement for thiscurrent source is to provide the desired output im-pedance, emulating the output impedance of aphotodiode or other current source. The output im-pedance of this circuit is given by:
Figure 37.
Assuming C1 >> C2, the equation reduces to:
BANDWIDTH
source at a higher frequency.While there is no substitute for measuring the per-formance of a particular circuit under the exact
Capacitor values should be chosen to satisfy twoconditions that are used in the application, the com-
requirements. First, C2 represents the anticipatedplete system environment often makes measure-
capacitance of the true source. Second C1 is chosenments harder. For transimpedance circuits, it is diffi-
such that the corner frequency of thecult to measure the frequency response with tradition-
transconductance network is much less than theal laboratory equipment because the circuit requires a
transimpedance bandwidth of the circuit. Choosing
11
www.ti.com
REQ RF1 1RF2
RF3
(5)
ALTERNATIVE TRANSIMPEDANCE
_
+
RF2
CF
λ
−V(Bias)
RL
RF1
RF3
1
CFEQ 1
CF1 1CF3
CF2
(6)
_
+
RF2
CF
λ
−V(Bias)
RL
RF1
_
+
RF
CF2
λ
−V(Bias)
RL
CF1
CF3
THS4631
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
this corner frequency properly leads to more accuratemeasurements of the transimpedance bandwidth. Ifthe interface circuit corner frequency is too close tothe bandwidth of the circuit, determining the powerlevel in the flatband is difficult. A decade or more offlat bandwidth provides a good basis for determiningthe proper transimpedance bandwidth.
CONFIGURATIONS
Other transimpedance configurations are possible.Three possibilities are shown below.
The first configuration is a slight modification of thebasic transimpedance circuit. By splitting thefeedback resistor, the feedback capacitor value be-
A. A resistive T-network enables hightransimpedance gain with reasonable re-comes more manageable and easier to control. This
sistor values.type of compensation scheme is useful when thefeedback capacitor required in the basic configuration
Figure 40. Alternative Transimpedancebecomes so small that the parasitic effects of the
Configuration 2board and components begin to dominate the totalfeedback capacitance. By reducing the resistance
The third configuration uses a capacitive T-network toacross the capacitor, the capacitor value can be
achieve fine control of the compensation capacitance.increased. This mitigates the dominance of the para-
The capacitor CF3 can be used to tune the totalsitic effects.
effective feedback capacitance to a fine degree. Thiscircuit behaves the same as the basictransimpedance configuration, with the effective CFgiven by Equation 6 .
A. Splitting the feedback resistor enables useof a larger, more manageable feedbackcapacitor.
Figure 39. Alternative Transimpedance
Configuration 1
The second configuration uses a resistive T-networkto achieve high transimpedance gains using relativelysmall resistor values. This topology can be usefulwhen the desired transimpedance gain exceeds the
A. A capacitive T-network enables fine controlvalue of available resistors. The transimpedance gain
of the effective feedback capacitance usingis given by Equation 5 .
relatively large capacitor values.
Figure 41. Alternative Transimpedance
Configuration 3
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SUMMARY OF KEY DECISIONS IN
NOISE ANALYSIS
_
+
Rf
4kT = 1.6E−20J
at 290K
IBN EO
ERF
RS
ERS
IBI
Rg
ENI
4kTRS
4kT
Rg4kTRf
SELECTION OF FEEDBACK RESISTORS
EOE2
NI IBNRS24kTRSNG2IBIRf24kTRfNG
ENE2
NI IBNRS24kTRSIBIRf
NG2
4kTRf
NG
THS4631
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
feedback resistors this large or anticipate using anTRANSIMPEDANCE DESIGN external compensation scheme to stabilize the circuit.Using a simple capacitor in parallel with the feedbackThe following is a simplified process for basic
resistor makes the amplifier more stable as shown intransimpedance circuit design. This process gives a
the Typical Characteristics graphs.start to the design process, though it does ignoresome aspects that may be critical to the circuit.
STEP 1: Determine the capacitance of the
High slew rate, unity gain stable, voltage-feedbacksource.
operational amplifiers usually achieve their slew rateSTEP 2: Calculate the total source capacitance, at the expense of a higher input noise voltage. Theincluding the amplifier input capaci- 7 nV/ √Hz input voltage noise for the THS4631 is,tance, C
I(CM)
and C
I(DIFF)
. however, much lower than comparable amplifierswhile achieving high slew rates. The input-referredSTEP 3: Determine the magnitude of the poss-
voltage noise, and the input-referred current noiseible current output from the source,
term, combine to give low output noise under a wideincluding the minimum signal current
variety of operating conditions. Figure 42 shows theanticipated and maximum signal current
amplifier noise analysis model with all the noise termsanticipated.
included. In this model, all noise terms are taken tobe noise voltage or current density terms in eitherSTEP 4: Choose a feedback resistor value such
nV/ √Hz or fA/ √Hz.that the input current levels create thedesired output signal voltages, andensure that the output voltages canaccommodate the dynamic range of theinput signal.
STEP 5: Calculate the optimum feedback capaci-tance using Equation 1 .
STEP 6: Calculate the bandwidth given theresulting component values.
STEP 7: Evaluate the circuit to determine if alldesign goals are satisfied.
Figure 42. Noise Analysis ModelFeedback resistor selection can have a significanteffect on the performance of the THS4631 in a given
The total output noise voltage can be computed asapplication, especially in configurations with low
the square root of all square output noise voltageclosed-loop gain. If the amplifier is configured for
contributors. Equation 7 shows the general form forunity gain, the output should be directly connected to
the output noise voltage using the terms shown inthe inverting input. Any resistance between these two
Figure 42 .points interacts with the input capacitance of theamplifier and causes an additional pole in the fre-quency response. For nonunity gain configurations,
(7)low resistances are desirable for flat frequency re-sponse. However, care must be taken not to load the
Dividing this expression by the noise gain [NG = (1+amplifier too heavily with the feedback network if
R
f
/R
g
)] gives the equivalent input-referred spot noiselarge output signals are expected. In most cases, a
voltage at the noninverting input, as shown intrade off is made between the frequency response
Equation 8 :characteristics and the loading of the amplifier. For again of 2, a 499- Ωfeedback resistor is a suitableoperating point from both perspectives. If resistorvalues are chosen too large, the THS4631 is subject
(8)to oscillation problems. For example, an invertingamplifier configuration with a 5-k Ωgain resistor and a
Using high resistor values can dominate the total5-k Ωfeedback resistor develops an oscillation due to
equivalent input-referred noise. Using a 3-k Ωthe interaction of the large resistors with the input
source-resistance (R
S
) value adds a voltage noisecapacitance. In low gain configurations, avoid
term of approximately 7 nV/ √Hz. This is equivalent tothe amplifier voltage noise term. Using higher resistor
13
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SLEW RATE PERFORMANCE WITH VARYING
PRINTED-CIRCUIT BOARD LAYOUT
THS4631
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
values dominate the noise of the system. Although formance of the THS4631. Resistors should be athe THS4631 JFET input stage is ideal for very low reactance type. Surface-mount resistorshigh-source impedance because of the low-bias cur- work best and allow a tighter overall layout.rents, the system noise and bandwidth is limited by a Again, keep their leads and PC board tracehigh-source (R
S
) impedance. length as short as possible. Never use wireboundtype resistors in a high frequency application.Since the output pin and inverting input pins arethe most sensitive to parasitic capacitance,INPUT STEP AMPLITUDE AND RISE/FALL
always position the feedback and series outputTIME
resistors, if any, as close as possible to theSome FET input amplifiers exhibit the peculiar
inverting input pins and output pins. Other net-behavior of having a larger slew rate when presented
work components, such as input termination re-with smaller input voltage steps and slower edge
sistors, should be placed close to the gain-settingrates due to a change in bias conditions in the input
resistors. Even with a low parasitic capacitancestage of the amplifier under these circumstances.
shunting the external resistors, excessively highThis phenomena is most commonly seen when FET
resistor values can create significant time con-input amplifiers are used as voltage followers. As this
stants that can degrade performance. Good axialbehavior is typically undesirable, the THS4631 has
metal-film or surface-mount resistors have ap-been designed to avoid these issues. Larger ampli-
proximately 0.2 pF in shunt with the resistor. Fortudes lead to higher slew rates, as would be antici-
resistor values > 2.0 k Ω, this parasitic capaci-pated, and fast edges do not degrade the slew rate of
tance can add a pole and/or a zero that canthe device. The high slew rate of the THS4631 allows
effect circuit operation. Keep resistor values asimproved SFDR and THD performance, especially
low as possible, consistent with load drivingnoticeable above 5 MHz.
considerations.
•Connections to other wideband devices on theboard may be made with short direct traces orTECHNIQUES FOR OPTIMAL
through onboard transmission lines. For shortPERFORMANCE
connections, consider the trace and the input tothe next device as a lumped capacitive load.Achieving optimum performance with high frequency
Relatively wide traces (50 mils to 100 mils)amplifier-like devices in the THS4631 requires careful
should be used, preferably with ground andattention to board layout parasitic and external
power planes opened up around them. Estimatecomponent types.
the total capacitive load and determine if isolationRecommendations that optimize performance include:
resistors on the outputs are necessary. Low•Minimize parasitic capacitance to any ac ground
parasitic capacitive loads (< 4 pF) may not needfor all of the signal I/O pins. Parasitic capacitance
an RS since the THS4631 is nominally compen-on the output and input pins can cause instability.
sated to operate with a 2-pF parasitic load.To reduce unwanted capacitance, a window
Higher parasitic capacitive loads without an RSaround the signal I/O pins should be opened in all
are allowed as the signal gain increasesof the ground and power planes around those
(increasing the unloaded phase margin). If a longpins. Otherwise, ground and power planes should
trace is required, and the 6-dB signal loss intrin-be unbroken elsewhere on the board.
sic to a doubly-terminated transmission line isacceptable, implement a matched impedance•Minimize the distance (< 0.25”) from the power
transmission line using microstrip or striplinesupply pins to high frequency 0.1-µF and 100-pF
techniques (consult an ECL design handbook forde-coupling capacitors. At the device pins, the
microstrip and stripline layout techniques). Aground and power plane layout should not be in
50- Ωenvironment is not necessary onboard, andclose proximity to the signal I/O pins. Avoid
in fact, a higher impedance environment im-narrow power and ground traces to minimize
proves distortion as shown in the distortion ver-inductance between the pins and the de-coupling
sus load plots. With a characteristic board tracecapacitors. The power supply connections should
impedance based on board material and tracealways be de-coupled with these capacitors.
dimensions, a matching series resistor into theLarger (6.8 µF or more) tantalum de-coupling
trace from the output of the THS4631 is used ascapacitors, effective at lower frequency, should
well as a terminating shunt resistor at the input ofalso be used on the main supply pins. These may
the destination device. Remember also that thebe placed somewhat farther from the device and
terminating impedance is the parallel combinationmay be shared among several devices in the
of the shunt resistor and the input impedance ofsame area of the PC board.
the destination device: this total effective im-•Careful selection and placement of external
pedance should be set to match the trace im-components preserve the high frequency per-
14
www.ti.com
0.060
0.040
0.075 0.025
0.205
0.010
vias
Pin 1
Top View
0.017
0.035
0.094
0.030
0.013
PowerPAD DESIGN CONSIDERATIONS
0.140
0.060
0.060
0.010
vias
Top View
0.035 0.080
0.050 0.176
0.030
0.026
0.010
0.035
0.100
0.300
Pin 1
All Units in Inches
PowerPAD PCB LAYOUT CONSIDERATIONS
DIE
Side View (a)
DIE
End View (b)
Thermal
Pad
Bottom View (c)
THS4631
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
pedance. If the 6-dB attenuation of a doublyterminated transmission line is unacceptable, along trace can be series-terminated at the sourceend only. Treat the trace as a capacitive load inthis case. This does not preserve signal integrityor a doubly-terminated line. If the input im-pedance of the destination device is low, there issome signal attenuation due to the voltage dividerformed by the series output into the terminatingimpedance.
•Socketing a high-speed part like the THS4631 isnot recommended. The additional lead length andpin-to-pin capacitance introduced by the socketcreates a troublesome parasitic network whichmakes it almost impossible to achieve a smooth,stable frequency response. Best results are ob-tained by soldering the THS4631 part directly
Figure 44. DGN PowerPAD PCB Etch and Viaonto the board.
Pattern
The THS4631 is available in a thermally-enhancedPowerPAD family of packages. These packages areconstructed using a downset leadframe upon whichthe die is mounted [see Figure 43 (a) and Figure 43(b)]. This arrangement results in the lead frame beingexposed as a thermal pad on the underside of thepackage [see Figure 43 (c)]. Because this thermalpad has direct thermal contact with the die, excellentthermal performance can be achieved by providing agood thermal path away from the thermal pad
The PowerPAD package allows for both assemblyand thermal management in one manufacturing oper-ation. During the surface-mount solder operation(when the leads are being soldered), the thermal padcan also be soldered to a copper area underneath thepackage. Through the use of thermal paths within thiscopper area, heat can be conducted away from thepackage into either a ground plane or other heat
Figure 45. DDA PowerPAD PCB Etch and Viadissipating device.
PatternThe PowerPAD package represents a breakthroughin combining the small area and ease of assembly ofsurface mount with the mechanical methods of
1. PCB with a top side etch pattern is shown inheatsinking.
Figure 44 and Figure 45 . There should be etchfor the leads and for the thermal pad.2. Place the recommended number of holes in thearea of the thermal pad. These holes should be10 mils in diameter. Keep them small so thatsolder wicking through the holes is not a problemduring reflow.3. Additional vias may be placed anywhere alongFigure 43. Views of Thermally Enhanced Package
the thermal plane outside of the thermal padarea. This helps dissipate the heat generated bythe THS4631 IC. These additional vias may beAlthough there are many ways to properly heatsink
larger than the 10-mil diameter vias directly underthe PowerPAD package, the following steps illustrate
the thermal pad. They can be larger becausethe recommended approach.
15
www.ti.com
PD max Tmax TA
JA
(9)
POWER DISSIPATION AND THERMAL
4
3.5
3
2.5
2
1.5
1
0.5
0
−40 −20 0 20 40 60 80 100
− Maximum Power Dissipation − W
PD
TA − Free-Air Temperature − °C
θJA = 58.4°C/W
θJA = 98°C/W
θJA = 158°C/W
TJ = 125°C
THS4631
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
they are not in the thermal pad area to besoldered so that wicking is not a problem.4. Connect all holes to the internal ground plane.
where:Although the PowerPAD is electrically isolatedfrom all pins and the active circuitry, connection
P
Dmax
is the maximum power dissipation in theto the ground plane is recommended. This is due
amplifier (W).to the fact that ground planes on most PCBs are
T
max
is the absolute maximum junction tempera-typically the targets copper area. Offering the
ture (°C).best thermal path heat to flow out of the device.
T
A
is the ambient temperature (°C).5. When connecting these holes to the ground
θ
JA
=θ
JC
+θ
CAplane, do not use the typical web or spoke via
θ
JC
is the thermal coefficient from the siliconconnection methodology. Web connections have
junctions to the case (°C/W).a high thermal resistance connection that is
θ
CA
is the thermal coefficient from the case touseful for slowing the heat transfer during
ambient air (°C/W).soldering operations. This makes the soldering ofvias that have plane connections easier. In this
NOTE:application, however, low thermal resistance is
For systems where heat dissipation is moredesired for the most efficient heat transfer. There-
critical, the THS4631 is offered in an 8-pin MSOPfore, the holes under the THS4631 PowerPAD
with PowerPAD package and an 8-pin SOIC withpackage should make their connection to the
PowerPAD package with better thermal perform-internal ground plane with a complete connection
ance. The thermal coefficient for the PowerPADaround the entire circumference of the
packages are substantially improved over theplated-through hole.
traditional SOIC. Maximum power dissipation6. The top-side solder mask should leave the ter-
levels are depicted in Figure 46 for the availableminals of the package and the thermal pad area
packages. The data for the PowerPAD packageswith its via holes exposed. The bottom-side
assume a board layout that follows thesolder mask should cover the via holes of the
PowerPAD layout guidelines referenced abovethermal pad area. This prevents solder from
and detailed in the PowerPAD application notebeing pulled away from the thermal pad area
number SLMA002 . Figure 46 also illustrates theduring the reflow process.
effect of not soldering the PowerPAD to a PCB.7. Apply solder paste to the exposed thermal pad
The thermal impedance increases substantiallyarea and all of the IC terminals.
which may cause serious heat and performanceissues. Be sure to always solder the PowerPAD8. With these preparatory steps in place, the IC is
to the PCB for optimum performance.simply placed in position and run through thesolder reflow operation as any standard sur-face-mount component. This results in a part thatis properly installed.
CONSIDERATIONS
To maintain maximum output capabilities, theTHS4631 does not incorporate automatic thermalshutoff protection. The designer must take care toensure that the design does not violate the absolutemaximum junction temperature of the device. Failuremay result if the absolute maximum junction tempera-ture of 150°C is exceeded. For best performance,design for a maximum junction temperature of 125°C.Between 125°C and 150°C, damage does not occur,
Figure 46. Maximum Power Dissipationbut the performance of the amplifier begins to de-
vs. Ambient Temperaturegrade. The thermal characteristics of the device aredictated by the package and the PC board. Maximumpower dissipation for a given package can be calcu-lated using Equation 9 .
16
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DESIGN TOOLS EVALUATION FIXTURE,
THS4631
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
Results are with no air flow and PCB size = 3" x 3 "θ
JA
= 58.4°C/W for the 8-pin MSOP withPowerPAD (DGN).θ
JA
= 98°C/W for the 8-pin SOIC high-K test PCB(D).
θ
JA
= 158°C/W for the 8-pin MSOP withPowerPAD, without solder.
When determining whether or not the device satisfiesthe maximum power dissipation requirement, it isimportant to not only consider quiescent power dissi-pation, but also dynamic power dissipation. Oftentimes, this is difficult to quantify because the signalpattern is inconsistent, but an estimate of the RMSpower dissipation can provide visibility into a possibleproblem
SPICE MODELS, AND APPLICATIONSSUPPORT
Texas Instruments is committed to providing its cus-tomers with the highest quality of applications sup-port. To support this goal an evaluation board hasbeen developed for the THS4631 operational ampli-
Figure 48. EVM Layers 2 and 3, Groundfier. The board is easy to use, allowing for straightfor-ward evaluation of the device. The evaluation boardcan be ordered through the Texas Instruments website, www.ti.com, or through your local Texas Instru-ments sales representative. The board layers areprovided in Figure 47 , Figure 48 , and Figure 49 . Thebill of materials for the evaluation board is provided inTable 2 .
Figure 49. EVM Bottom Layer
Figure 47. EVM Top Layer
17
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BILL OF MATERIALS
EVM
THS4631
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
Table 2. THS4631DDA EVM
SMD REFERENCE PCB MANUFACTURER'SITEM DESCRIPTION
SIZE DESIGNATOR QUANTITY PART NUMBER
(1)
1 CAP, 2.2 µF, CERAMIC, X5R, 25 V 1206 C3, C6 2 (AVX) 12063D225KAT2A4 CAP, 0.1µF, CERAMIC, X7R, 50 V 0805 C1, C2 2 (AVX) 08055C104KAT2AOPEN 0805 R4, Z4, Z6 36 RESISTOR, 0 OHM, 1/8 W 0805 Z2 1 (KOA) RK73Z2ATTD7 RESISTOR, 499 OHM, 1/8 W, 1% 0805 R3, Z5 2 (KOA) RK73H2ATTD4990F8 OPEN 1206 R8, Z9 29 RESISTOR, 0 OHM, 1/4 W 1206 R1 1 (KOA) RK73Z2BLTD10 RESISTOR, 49.9 OHM, 1/4 W, 1% 1206 R2 1 (KOA) RK73H2BLTD49R9F11 RESISTOR, 953 OHM, 1/4 W, 1% 1206 Z3 1 (KOA) RK73H2BLTD9530F13 CONNECTOR, SMA PCB JACK J1, J2, J3 3 (JOHNSON) 142-0701-801JACK, BANANA RECEPTANCE, 0.25"14 J4, J5, J6 3 (SPC) 813DIA. HOLE15 TEST POINT, BLACK TP1, TP2 2 (KEYSTONE) 5001TEST POINT, RED TP3 1 (KEYSTONE) 500016 STANDOFF, 4-40 HEX, 0.625" LENGTH 4 (KEYSTONE) 180817 SCREW, PHILLIPS, 4-40, .250" 4 SHR-0440-016-SN18 IC, THS4631 U1 1 (TI) THS4631DDA19 BOARD, PRINTED CIRCUIT 1 (TI) EDGE # 6467873 Rev.A
(1) The manufacturer's part numbers are used for test purposes only.
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance ofanalog circuits and systems. This is particularly true for video and RF-amplifier circuits where parasiticcapacitance and inductance can have a major effect on circuit performance. A SPICE model for the THS4631 isavailable through either the Texas Instruments web site (www.ti.com ). These models help in predictingsmall-signal ac and transient performance under a wide variety of operating conditions. They are not intended tomodel the distortion characteristics of the amplifier, nor do they attempt to distinguish between the package typesin their small-signal ac performance. Detailed information about what is and is not modeled is contained in themodel file itself.
18
www.ti.com
THS4631
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
Figure 50. THS4631 EVM Schematic
19
www.ti.com
ADDITIONAL REFERENCE MATERIAL
EVM WARNINGS AND RESTRICTIONS
THS4631
SLOS451A – DECEMBER 2004 – REVISED MARCH 2005
•PowerPAD Made Easy, application brief (SLMA004 )•PowerPAD Thermally Enhanced Package, technical brief (SLMA002 )•Noise Analysis of FET Transimpedance Amplifiers, application bulletin, Texas Instruments Literature NumberSBOA060 .•Tame Photodiodes With Op Amp Bootstrap, application bulletin, Texas Instruments Literature NumberSBBA002 .•Designing Photodiode Amplifier Circuits With OPA128, application bulletin, Texas Instruments LiteratureNumber SBOA061 .•Photodiode Monitoring With Op Amps, application bulletin, Texas Instruments Literature Number SBOA035 .•Comparison of Noise Performance Between a FET Transimpedance Amplifier and a Switched Integrator,Application Bulletin, Texas Instruments Literature Number SBOA034 .
It is important to operate this EVM within the input and output voltage ranges as specified in the table providedbelow.
Input Range, V
S+
to V
S–
10 V to 30 V
Input Range, V
I
10 V to 30 V NOT TO EXCEED VS+ or VS–Output Range, V
O
10 V to 30 V NOT TO EXCEED VS+ or VS–
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. Ifthere are questions concerning the input range, please contact a TI field representative prior to connecting theinput power.
Applying loads outside of the specified output range may result in unintended operation and/or possiblepermanent damage to the EVM. Please consult the product data sheet or EVM user's guide (if user's guide isavailable) prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 30°C. The EVM isdesigned to operate properly with certain components above 50°C as long as the input and output ranges aremaintained. These components include but are not limited to linear regulators, switching transistors, passtransistors, and current sense resistors. These types of devices can be identified using the EVM schematiclocated in the material provided. When placing measurement probes near these devices during operation, pleasebe aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265
20
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
THS4631D ACTIVE SOIC D 8 75 Pb-Free
(RoHS) CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
THS4631DDA ACTIVE SO
Power
PAD
DDA 8 75 TBD CU SNPB Level-1-235C-UNLIM
THS4631DDAR ACTIVE SO
Power
PAD
DDA 8 2500 TBD CU SNPB Level-1-235C-UNLIM
THS4631DGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4631DGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4631DGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4631DGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4631DR ACTIVE SOIC D 8 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
THS4631DRG4 ACTIVE SOIC D 8 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 24-May-2005
Addendum-Page 1
IMPORTANT NOTICE
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