Vishay Siliconix
Si2303CDS
Document Number: 69991
S-83053-Rev. B, 29-Dec-08
www.vishay.com
1
P-Channel 30-V (D-S) MOSFET
FEATURES
• Halogen-free According to IEC 61249-2-21
Available
• TrenchFET® Power MOSFET
• 100 % Rg Tested
• 100 % UIS Tested
APPLICATIONS
• Load Switch
Notes:
a. Based on TC = 25 °C.
b. Surface Mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. Maximum under Steady State conditions is 160 °C/W.
MOSFET PRODUCT SUMMARY
VDS (V) RDS(on) (Ω)ID (A)aQg (Typ.)
- 30
0.190 at VGS = - 10 V - 2.7
2 nC
0.330 at VGS = - 4.5 V - 2.1
G
TO-236
(SOT-23)
S
D
Top View
2
3
1
Si2303CDS (N3)*
* Marking Code
Ordering Information: Si2303CDS-T1-E3 (Lead (Pb)-free)
Si2303CDS-T1-GE3 (Lead (Pb)-free and Halogen-free)
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter Symbol Limit Unit
Drain-Source Voltage VDS - 30 V
Gate-Source Voltage VGS ± 20
Continuous Drain Current (TJ = 150 °C)
TC = 25 °C
ID
- 2.7
A
TC = 70 °C - 2.2
TA = 25 °C - 1.9b, c
TA = 70 °C - 1.5b, c
Pulsed Drain Current IDM - 10
Continuous Source-Drain Diode Current TC = 25 °C IS- 1.75
TA = 25 °C - 0.83b, c
Avalanche Current L = 0.1 mH IAS - 5
Single Pulse Avalanche Energy EAS 1.25 mJ
Maximum Power Dissipation
TC = 25 °C
PD
2.3
W
TC = 70 °C 1.5
TA = 25 °C 1.0b, c
TA = 70 °C 0.7b, c
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C
THERMAL RESISTANCE RATINGS
Parameter Symbol Typical Maximum Unit
Maximum Junction-to-Ambientb, d ≤ 5 s RthJA 80 120 °C/W
Maximum Junction-to-Foot (Drain) Steady State RthJF 35 55
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Document Number: 69991
S-83053-Rev. B, 29-Dec-08
Vishay Siliconix
Si2303CDS
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
MOSFET SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
Drain-Source Breakdown Voltage VDS VDS = 0 V, ID = - 250 µA - 30 V
VDS Temperature Coefficient ΔVDS/TJ ID = - 250 µA - 27 mV/°C
VGS(th) Temperature Coefficient
Δ
V
GS(th)
/T
J
3.8
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = - 250 µA - 1 - 3 V
Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = - 30 V, VGS = 0 V - 1 µA
VDS = - 30 V, VGS = 0 V, TJ = 55 °C - 10
On-State Drain CurrentaID(on) V
DS ≤ - 5 V, VGS = - 10 V - 10 A
Drain-Source On-State ResistanceaRDS(on)
VGS = - 10 V, ID = - 1.9 A 0.158 0.190 Ω
VGS = - 4.5 V, ID = - 1.4 A 0.275 0.330
Forward Transconductanceagfs VDS = - 5 V, ID = - 1.9 A 2S
Dynamicb
Input Capacitance Ciss
VDS = - 15 V, VGS = 0 V, f = 1 MHz
155
pFOutput Capacitance Coss 35
Reverse Transfer Capacitance Crss 25
Total Gate Charge Qg VDS = - 15 V, VGS = - 10 V, ID = - 1.9 A 48
nC
VDS = - 15 V, VGS = - 4.5 V, ID = - 1.9 A
24
Gate-Source Charge Qgs 0.6
Gate-Drain Charge Qgd 1
Gate Resistance Rg f = 1 MHz 1.7 8.5 17 Ω
Tur n - O n D e l ay Time td(on)
VDD = - 15 V, RL = 10 Ω
ID = - 1.5 A, VGEN = - 10 V, RG = 1 Ω
48
ns
Rise Time tr11 18
Turn-Off Delay Time td(off) 11 18
Fall Time tf816
Tur n - O n D e l ay Time td(on)
VDD = - 15 V, RL = 10 Ω
ID ≅ - 1.5 A, VGEN = - 4.5 V, RG = 1 Ω
36 44
Rise Time tr37 45
Turn-Off Delay Time td(off) 12 18
Fall Time tf914
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current ISTC = 25 °C - 1.75 A
Pulse Diode Forward CurrentaISM - 10
Body Diode Voltage VSD IS = - 1.5 A - 0.8 - 1.2 V
Body Diode Reverse Recovery Time trr
IF = - 1.5 A, di/dt = 100 A/µs, TJ = 25 °C
17 26 ns
Body Diode Reverse Recovery Charge Qrr 914nC
Reverse Recovery Fall Time ta12 ns
Reverse Recovery Rise Time tb5
Document Number: 69991
S-83053-Rev. B, 29-Dec-08
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3
Vishay Siliconix
Si2303CDS
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Output Characteristics
On-Resistance vs. Drain Current and Gate Voltage
Gate Charge
0
2
4
6
8
10
012345
VDS - Drain-to-Source Voltage (V)
- Drain Current (A)I D
VGS =10thru5V
VGS =3V
VGS =4V
0
0.1
0.2
0.3
0.4
0.5
0246810
- On-Resistance (Ω)RDS(on)
ID- Drain Current (A)
VGS = 10 V
VGS =4.5V
ID=1.9A
0
2
4
6
8
10
01234
- Gate-to-Source Voltage (V)
Qg- Total Gate Charge (nC)
VGS
VDS =24V
VDS =15V
Transfer Characteristics
Capacitance
On-Resistance vs. Junction Temperature
0.0
0.2
0.4
0.6
0.8
1.0
01234
VGS - Gate-to-Source Voltage (V)
- Drain Current (A)I
D
TC= 25 °C
TC= 125 °C
TC= - 55 °C
Crss
0
60
120
180
240
300
0 6 12 1824 30
Ciss
VDS - Drain-to-Source Voltage (V)
C - Capacitance (pF)
Coss
0.6
0.8
1.0
1.2
1.4
1.6
- 50 - 25 0 25 50 75 100 125 150
TJ-Junction Temperature (°C)
(Normalized)
- On-Resistance
R
DS(on)
VGS =10V,I
D=1.9A
VGS =4.5V,I
D=1.4A
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Document Number: 69991
S-83053-Rev. B, 29-Dec-08
Vishay Siliconix
Si2303CDS
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Source-Drain Diode Forward Voltage
Threshold Voltage
0.0 0.2 0.4 0.6 0.81.0 1.2
TJ= 150 °C
1
VSD -Source-to-Drain Voltage (V)
- Source Current (A)I S
0.1
10
TJ= 25 °C
1.4
1.6
1.8
2.0
2.2
- 50 - 25 0 25 50 75 100 125 150
ID= 250 µA
(V)VGS(th)
TJ- Temperature (°C)
On-Resistance vs. Gate-to-Source Voltage
Single Pulse Power
0.0
0.1
0.2
0.3
0.4
0.5
04812 16 20
- On-Resistance (Ω)RDS(on)
VGS - Gate-to-Source Voltage (V)
TJ= 25 °C
TJ= 125 °C
ID=1.9A
0
1
2
3
4
5
6
0.01 0.1 1 10 100 1000
Time (s)
Power (W)
Safe Operating Area
VDS - Drain-to-Source Voltage (V)
* V
GS > minimumVGS at which RDS(on) is specified
- Drain Current (A)I D
10
0.1
0.1 1 10
1
TA= 25 °C
Single Pulse
1ms
10 ms
100 ms
0.01
1s,10s
DC
BVDSS Limited
100
100 µs
Limited byR
DS(on)*
Document Number: 69991
S-83053-Rev. B, 29-Dec-08
www.vishay.com
5
Vishay Siliconix
Si2303CDS
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
* The power dissipation PD is based on TJ(max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Current Derating*
0.0
0.6
1.2
1.8
2.4
3.0
0 255075100125150
TC- Case Temperature (°C)
ID- Drain Current (A)
Power Derating, Junction-to-Foot
0.0
0.6
1.2
1.8
2.4
3.0
0 25 50 75 100 125 150
TC- Case Temperature (°C)
Power (W)
Power Derating, Junction-to-Ambient
0.0
0.2
0.4
0.6
0.8
1.0
0 25 50 75 100 125 150
TA-Ambient Temperature (°C)
Power (W)
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Document Number: 69991
S-83053-Rev. B, 29-Dec-08
Vishay Siliconix
Si2303CDS
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?69991.
Normalized Thermal Transient Impedance, Junction-to-Ambient
10-3 10-2 110 100010-1
10-4 100
0.2
0.1
0.05
Square WavePulse Duration (s)
Normalized Effective Transient
Thermal Impedance
1
0.1
0.01
Single Pulse
t1
t2
Notes:
PDM
1. Duty Cycle, D =
2. Per Unit Base = RthJA = 104 °C/W
3. TJM -T
A=P
DMZthJA(t)
t1
t2
4. Surface Mounted
Duty Cycle = 0.5
0.02
Normalized Thermal Transient Impedance, Junction-to-Foot
1
0.1
0.01
0.2
Duty Cycle = 0.5
Square WavePulse Duration (s)
Normalized Effective Transient
Thermal Impedance
0.1
10-3 10-2 110-1
10-4
0.05
0.02
Single Pulse
Vishay Siliconix
Package Information
Document Number: 71196
09-Jul-01
www.vishay.com
1
SOT-23 (TO-236): 3-LEAD
b
E
E1
1
3
2
Se
e1
D
A2
A
A1C
Seating Plane
0.10 mm
0.004"
CC
L1
L
q
Gauge Plane
Seating Plane
0.25 mm
Dim MILLIMETERS INCHES
Min Max Min Max
A0.89 1.12 0.035 0.044
A10.01 0.10 0.0004 0.004
A20.88 1.02 0.0346 0.040
b0.35 0.50 0.014 0.020
c0.085 0.18 0.0030.007
D2.80 3.04 0.110 0.120
E2.10 2.64 0.0830.104
E11.20 1.40 0.047 0.055
e0.95 BSC 0.0374 Ref
e11.90 BSC 0.0748 Ref
L0.40 0.60 0.016 0.024
L10.64 Ref 0.025 Ref
S0.50 Ref 0.020 Ref
q3°8°3°8°
ECN: S-03946-Rev. K, 09-Jul-01
DWG: 5479
AN807
Vishay Siliconix
Document Number: 70739
26-Nov-03
www.vishay.com
1
Mounting LITTLE FOOTR SOT-23 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use integrated
circuit and small-signal packages which have been been modified
to provide the heat transfer capabilities required by power devices.
Leadframe materials and design, molding compounds, and die
attach materials have been changed, while the footprint of the
packages remains the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286), for the basis
of the pad design for a LITTLE FOOT SOT-23 power MOSFET
footprint . In converting this footprint to the pad set for a power
device, designers must make two connections: an electrical
connection and a thermal connection, to draw heat away from the
package.
The electrical connections for the SOT-23 are very simple. Pin 1 is
the gate, pin 2 is the source, and pin 3 is the drain. As in the other
LITTLE FOOT packages, the drain pin serves the additional
function of providing the thermal connection from the package to
the PC board. The total cross section of a copper trace connected
to the drain may be adequate to carry the current required for the
application, but it may be inadequate thermally. Also, heat spreads
in a circular fashion from the heat source. In this case the drain pin
is the heat source when looking at heat spread on the PC board.
Figure 1 shows the footprint with copper spreading for the SOT-23
package. This pattern shows the starting point for utilizing the
board area available for the heat spreading copper. To create this
pattern, a plane of copper overlies the drain pin and provides
planar copper to draw heat from the drain lead and start the
process of spreading the heat so it can be dissipated into the
ambient air. This pattern uses all the available area underneath the
body for this purpose.
FIGURE 1. Footprint With Copper Spreading
0.114
2.9
0.059
1.5
0.0394
1.0
0.037
0.95
0.150
3.8
0.081
2.05
Since surface-mounted packages are small, and reflow soldering
is the most common way in which these are affixed to the PC
board, “thermal” connections from the planar copper to the pads
have not been used. Even if additional planar copper area is used,
there should be no problems in the soldering process. The actual
solder connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the drain
pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low-impedance
path for heat to move away from the device.
Application Note 826
Vishay Siliconix
Document Number: 72609 www.vishay.com
Revision: 21-Jan-08 25
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR SOT-23
0.106
(2.692)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.022
(0.559)
0.049
(1.245)
0.029
(0.724)
0.037
(0.950)
0.053
(1.341)
0.097
(2.459)
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Revision: 08-Feb-17 1Document Number: 91000
Disclaimer
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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including but not limited to the warranty expressed therein.
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