TS68EN360VR25L - E2V Technologies (UK), Ltd.

Features

•CPU32+ Processor (4.5 MIPS at 25 MHz)

– 32-bit Version of the CPU32 Core (Fully Compatible with the CPU32)

– Background Debug Mode

– Byte-misaligned Addressing

•Up to 32-bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits)

•Up to 32 Address Lines (At Least 28 Always Available)

•Complete Static Design (0 - 25 MHz Operation)

•Slave Mode to Disable CPU32+ (Allows Use with External Processors)

– Multiple QUICCs Can Share One System Bus (One Master)

– TS68040 Companion Mode Allows QUICC to be a TS68040 Companion Chip and

Intelligent Peripheral (22 MIPS at 25 MHz)

– Peripheral Device of TSPC603e (see DC415/D note)

•Four General-purpose Timers

– Superset of MC68302 Timers

– Four 16-bit Timers or Two 32-bit Timers

– Gate Mode Can Enable/Disable Counting

•Two Independent DMAs (IDMAs)

•System Integration Module (SIM60)

•Communications Processor Module (CPM)

•Four Baud Rate Generators

•Four SCCs (Ethernet/IEEE 802.3 Optional on SCC1-Full 10 Mbps Support)

•Two SMC

•VCC = +5V ± 5%

•fmax = 25 MHz and 33 MHz

•Military Temperature Range: -55°C < TC < +125°C

•PD = 1.4W at 25 MHz; 5.25V

2W at 33 MHz; 5.25V

Description

The TS68EN360 QUad Integrated Communication Controller (QUICC™) is a versatile

one-chip integrated microprocessor and peripheral combination that can be used in a

variety of controller applications. It particularly excels in communications activities.

The QUICC (pronounced “quick”) can be described as a next-generation TS68302

with higher performance in all areas of device operation, increased flexibility, major

extensions in capability, and higher integration. The term “quad” comes from the fact

that there are four serial communications controllers (SCCs) on the device; however,

there are actually seven serial channels: four SCCs, two serial management control-

lers (SMCs), and one serial peripheral interface (SPI).

Screening/Quality

This product is manufactured in full compliance with:

•QML (class Q)

•or according to Atmel standards

32-bit Quad

Integrated

Communication

Controller

TS68EN360

2113B–HIREL–06/05

TS68EN360

1. Introduction

1.1 QUICC Architecture Overview

The QUICC is 32-bit controller that is an extension of other members of the TS68300 family.

Like other members of the TS68300 family, the QUICC incorporates the intermodule bus (IMB).

The TS68302 is an exception, having an 68000 bus on chip. The IMB provides a common inter-

face for all modules of the TS68300 family, which allows the development of new devices more

quickly by using the library of existing modules. Although the IMB definition always included an

option for an on-chip 32-bit bus, the QUICC is the first device to implement this option.

The QUICC is comprised of three modules: the CPU32+ core, the SIM60, and the CPM. Each

module utilizes the 32-bit IMB. The TS68EN360 QUICC block diagram is shown in Figure 1-1.

Figure 1-1. QUICC Block Diagram

R suffix

PGA 241

Ceramic Pin Grid Array Cavity Up

A suffix

CERQUAD 240

Ceramic Leaded Chip Carrier Cavity Down

EXTERNAL

BUS

INTERFACE

SYSTEM

PROTECTION

SIM 60

CPU32+

CORE

IMB (32 BIT)

RISC

CONTROLLER

SYSTEM

I/F

2.5-KBYTE

DUAL-PORT

RAM

DRAM

CONTROLLER

AND

CHIP SELECTS

CPM

PERIODIC

TIMER

CLOCK

GENERATION

OTHER

FEATURES

BREAKPOINT

LOGIC

JTAG

COMMUNICATIONS PROCESSOR

FOUR

GENERAL-

PURPOSE

TIMERS

INTERRUPT

CONTROLLER

OTHER

FEATURES

TIMER SLOT

ASSIGNER

SEVEN

SERIAL

CHANNELS

TWO

IDMAs FOURTEEN SERIAL

DMAs

2113B–HIREL–06/05

TS68EN360

2. Pin Assignments

Figure 2-1. 241-lead Pin Grid Array (PGA)

Note: Pin P9 “NC” is for guide purposes only.

123456789101112131415161718

PA15

D10

D13

D16

D19

CLKO2

CLKO1

D21

D24

D27

D30

FC2

SIZ1

SIZ0

PA12

D12

D15

D18

Vcc

D20

D23

D26

D29

FC3

FC1

A29

A28

XTAL

PA13

PA9

D11

D14

D17

GND

D22

D25

D28

D31

FC0

A30

EXTAL

MODCK0

NC4

PA10

PA6

PA14

GND

Vcc

Vccclk

GND

Vcc

GND

A31

XFC

MODCK1

GND

A26

PA7

PA3

PA11

GND

Vcc

GND

GNDclk

Vcc

GND

Vccsyn

Vcc

A27

A25

A24

PA5

PA2

PA8

GND

GNDsyn

GND

A23

A22

A21

PA1

PB17

PA4

Vcc

GND

A20

A19

A18

PB16

PB15

PA0

Vcc

A17

A16

A15

PB13

PB12

PB14

GND

Vcc

A14

A13

A12

PB10

PB11

PB9

GND

A10

A11

PB7

PB8

PB6

Vcc

GND

PB4

PB5

PB3

Vcc

GND

PB1

PB2

PB0

GND

Vcc

GND

CS7

PC10

PC11

PC8

GND

Vcc

GND

Vcc

GNDs1

Vcc

CS4

IRQ7

PC7

PC9

PC4

GND

Vcc

GND

Vcc

GND

GNDs2

Vcc

GND

Vcc

GND

CS1

CS5

TRIS

PC3

PC6

PC0

IRQ5

HALT

AVEC

TD1

TRST

IRQ4

IFETCH

NC2

IPIPE0

PRTY2

NC3

CAS0

CAS3

CS2

CS6

PC1

PC5

IRQ3

BERR

RMC

TDO

TCK

BKPT

BGACK

NC1

BCLRO

PRTY1

DSACK1

R/W

FREEZE

CAS2

CS3

IRQ2

PC2

IRQ1

RESETS

PERR

TMS

RESETH

IRQ6

IPIPE1

PRTY0

PRTY3

DSACK0

CAS1

CS0

TS68EN360

(BOTTOM VIEW)

2113B–HIREL–06/05

TS68EN360

Figure 2-2. 240-lead Cerquad

IRQ1 240

BERR

GND

HALT

RESETS

Vcc

RMC

AVEC

GND

PERR

TDO 230

TDI

TMS

TCK

TRST

RESETH

BKPT

GND

IRQ6

IRQ4

Vcc 220

BGACK

GND

Vcc

NC1

IFETCH

GND

BCLRO 210

NC2

Vcc

IPIPE1

GNDs2

IPIPE0

PRTY0

PRTY1

Vcc

GND 200

PRTY2

PRTY3

GND

DSACK1

GND

DSACK0

Vcc

NC3

R/W

GND 190

FREEZE

CAS0

GND

CAS1

Vcc

CAS2

CAS3

GNDs1 181

D061 D1

GND

Vcc

GND70 D7

D10

D11

GND

D12

D13

D14

Vcc80 D15

D16

GND

D17

D18

D19

CLKO2

GNDclk

Vccclk

CLKO190 D20

D21

D22

GND

D23

D24

D25

Vcc

D26

D27100 D28

GND

D29

D30

D31

GND

Vcc

FC3

FC2

FC1110 GND

FC0

SIZ1

SIZ0

Vcc

A31

A30

GND

A29

A28120

CS0

180

CS1

CS2

CS3

Vcc

GND

CS4

CS5

CS6

CS7

IRQ7

170

TRIS

GND

Vcc

GND

160

Vcc

GND

A10

A11

Vcc

150

A12

A13

GND

A14

A15

A16

A17

A18

GND

A19

140

A20

A21

Vcc

A22

A23

A24

GND

A25

A26

A27

130

NC4

GND

MODCK1

MODCK0

XTAL

EXTAL

GNDsyn

XFC

Vccsyn

121

IRQ5

IRQ3

IRQ2

PC0

PC1

PC2

GND

PC3

PC4

PC5

PC6

Vcc

PC7

PC8

PC9

PC10

GND

PC11

PB0

PB1

PB2

PB3

PB4

PB5

PB6

GND

PB7

PB8

PB9

PB10

Vcc

PB11

PB12

PB13

PB14

GND

PB15

PB16

PB17

PA0

GND

Vcc

PA1

PA2

PA3

PA4

GND

PA5

PA6

PA7

PA8

Vcc

PA9

PA10

PA11

PA12

GND

PA13

PA14

PA15

TS68EN360

(TOP VIEW)

PIN ONE INDICATOR

2113B–HIREL–06/05

TS68EN360

3. Signal Description

3.1 Functional Signal Group

Figure 3-1. QUICC Functional Signal Groups

QUICC

A31±A28/WE0±WE3

A27±A0

DATA BUS

D31±D16

D15±D0

PRTY3/16BM

BUS CONTROL

SIZ0

SIZ1

R/W

BUS ARBITRATION

BCLRO/CONFIG1/RAS2DD

SYSTEM CONTROL

RESETH

RESETS

HALT

PERR

INTERRUPT CONTROL

AVEC/IACK5/AVECO

MEMORY CONTROLLER

CS6±CS0/RAS6±RAS0

CS/RAS7/IACK7

CAS3±CAS0/IACK6,3,2,1

TCK

TMS

TDI

TDO

TRST

CLOCK

XTAL

EXTAL

XFC

MODCK1±MODCK0

CLKO2±CLKO1

ADDRESS BUS

RXD1/PA0

PORT A

TXD1/PA1

RXD2/PA2

TXD2/PA3

L1TXDB/RXD3/PA4

L1RXDB/TXD3/PA5

L1TXDA/RXD4/PA6

L1RXDA/TXD4/PA7

TIMERs/SCCs/SIs/CLOCKs/BRG

TIN1/L1RCLKA/BRGO1/CLK1/PA8

BRGCLK1/TOUT1/CLK2/PA9

TIN2/L1TCLKA/BRGO2/CLK3/PA10

TOUT2/CLK4/PA11

TIN3/BRGO3/CLK5/PA12

BRGCLK2/L1RCLKB/TOUT3/CLK6/PA13

TIN4/BRGO4/CLK7/PA14

L1TCLKB/TOUT4/CLK8/PA15

PORT B (PIP)

RRJCT1/SPISEL/PB0

RSTRT2/SPICLK/PB1

RRJCT2/SPIMOSI(SPITXD)/PB2

BRGO4/SPIMISO(SPIRXD)/PB3

DREQ1/BRGO1/PB4

DACK1/BRGO2/PB5

DONE1/SMTXD1/PB6

DONE2/SMRXD1/PB7

DREQ2/SMSYN1/PB8

DACK2/SMSYN2/PB9

L1CLKOB/SMTXD2/PB10

L1CLKOA/SMRXD2/PB11

L1ST1/RTS1/PB12

L1ST2/RTS2/PB13

L1ST3/L1RQB/RTS3/PB14

L1ST4/L1RQA/RTS4/PB15

STRBO/BRGO3/PB16

STRBI/RSTRT1/PB17

PORT C (INTERRUPT PARALLEL I/O)

L1ST1/RTS1/PC0

L1ST2/RTS2/PC1

L1ST3/L1RQB/RTS3/PC2

L1ST4/L1RQA/RTS4/PC3

CTS1/PC4

TGATE1/CD1/PC5

CTS2/PC6

TGATE2/CD2/PC7

SDACK2/L1TSYNCB/CTS3/PC8

L1RSYNCB/CD3/PC9

SDACK1/L1TSYNCA/CTS4/PC10

L1RSYNCA/CD4/PC11

TS68360

240 PINS

TEST

FC2±FC0/

TM2±TM0

FC3/

TT0

PRTY1±PRTY2/

IOUT1±IOUT2

PRTY2/IOUT0/

RQOUT

DSACK0/

TBI

DSACK1/

DS/

TT1

OE/AMUX

RMC/CONFIG0/

LOCK

BGACK/

BERR/

TEA

IRQ1/

OUT0

/RQOUTIRQ1/

OUT0

/RQOUT

IRQ4/

OUT1

IRQ6/

OUT2

IRQ2,3,5,7

TRIS/

BKPT/

BKPT0

/DSCLK

FREEZE/CONFIG2/

MBARE

IPIPE1/RAS1DD/

BCLRI

IPIPE0/

BADD2

/DSO

IFETCH/

BADD3

/DSI

2113B–HIREL–06/05

TS68EN360

3.2 Signal Index

Table 1. System Bus Signal Index (Normal Operation)

Group Signal Name Mnemonic Function

Address

Address Bus A27-A0 Lower 27 bits of address bus. (I/O)(1)

Address Bus/Byte Write

Enables

A31-A28

WE3-WE0

Upper four bits of address bus (I/O), or byte write enable

signals (O)(1) for accesses to external memory or peripherals.

Function Codes FC3-FC0 Identifies the processor state and the address space of the

current bus cycle. (I/O)

Data

Data Bus 31 - 16 D31-D16 Upper 16-bit data bus used to transfer byte or word data.

Used in 16-bit bus mode. (I/O)

Data Bus 15 - 0 D15-D0

Lower 16-bit data bus used to transfer 3-byte or long-word

data. (I/O)

Not used in 16-bit bus mode.

Parity

Parity 2 - 0 PRTY2-PRTY0 Parity signals for byte writes/reads from/to external memory

module. (I/O)

Parity 3/16BM PRTY3/16BM Parity signals for byte writes/reads from/to external memory

module or defines 16-bit bus mode. (I/O)

Parity Error PERR Indicates a parity error during a read cycle. (O)

Memory

Controller

Chip Select

Row Address Select 7

Interrupt Acknowledge 7

RAS7

IACK7

Enables peripherals or DRAMs at programmed addresses (O)

or interrupt level 7 acknowledge line. (O)

Chip Select 6-0

Row Address Select 6-0

CS6-CS0

RAS6-RAS0

Enables peripherals or DRAMs at programmed addresses.

(O)

Column Address Select

3 - 0/Interrupt

Acknowledge 1, 2, 3, 6

CAS3-CAS0/

IACK6,3,2,1

DRAM column address select or interrupt level acknowledge

lines. (O)

Bus Arbitration

Bus Request BR Indicates that an external device requires bus mastership.

(I)(1)

Bus Grant BG Indicates that the current bus cycle is complete and the

QUICC has relinquished the bus. (O)

Bus Grand Acknowledge BGACK Indicates that an external device has assumed bus

mastership. (I)

Read-Modify-Write Cycle

Initial Configuration 0

RMC

CONFIG0

Identifies the bus cycle as part of an indivisible

read-modify-write operation (I/O) or initial QUICC

configuration select. (I)

Bus Clear Out/Initial

Configuration 1/Row

Address Select 2

Double-Drive

BCLRO/CONFIG1/

RAS2DD

Indicates that an internal device requires the external bus

(Open-Drain O) or initial QUICC configuration select (I) or row

address select 2 double-drive output. (O)

2113B–HIREL–06/05

TS68EN360

Bus Control

Data and Size

Acknowledge DSACK1 - DSACK0

Provides asynchronous data transfer acknowledgement and

dynamic bus sizing (open-drain I/O but driven high before

three-stated)

Address Strobe AS Indicates that a valid address is on the address bus. (I/O)

Data Strobe DS

During a read cycle, DS indicates that an external device

should place valid data on the data bus. During a write cycle,

DS indicates that valid data is on the data bus. (I/O)

Size SIZ1-SIZ0 Indicates the number of bytes remaining to be transferred for

this cycle. (I/O)

Read/Write R/W Indicates the direction of data transfer on the bus. (I/O)

Output Enable Address

Multiplex OE/AMUX

Active during a read cycle indicates that an external device

should place valid data on the data bus (O) or provides a

strobe for external address multiplexing in DRAM accesses if

internal multiplexing is not used. (O)

Interrupt

Control

Interrupt Request

Level 7-1 IRQ7-IRQ1 Provides external interrupt requests to the CPU32+ at priority

levels 7-1. (I)

Autovector/Interrupt

Acknowledge 5 AVEC/IACK5 Autovector request during an interrupt acknowledge cycle

(open-drain I/O) or interrupt level 5 acknowledge line. (O)

System

Control

Soft Reset RESETS Soft system reset. (open-drain I/O)

Hard Reset RESETH Hard system reset. (open-drain I/O)

Halt HALT Suspends external bus activity. (open-drain I/O)

Bus Error BERR Indicates an erroneous bus operation is being attempted.

(open-drain I/O)

Clock and Test

System Clock Out 1 CLKO1 Internal system clock output 1. (O)

System Clock Out 2 CLKO2 Internal system clock output 2 - normally 2x CLKO1. (O)

Crystal Oscillator EXTAL, XTAL Connections for an external crystal to the internal oscillator

circuit. EXTAL (I), XTAL (O)

External Filter Capacitor XFC Connection pin for an external capacitor to filter the circuit of

the PLL. (I)

Clock Mode Select 1-0 MODCK1-MODCK0 Selects the source of the internal system clock. (I) THESE

PINS SHOULD NOT BE SET TO 00

Instruction Fetch/

Development Serial Input IFETCH/DSI

Indicates when the CPU32+ is performing an instruction word

prefetch (O) or input to the CPU32+ background debug mode.

(I)

Instruction Pipe 0/

Development Serial

Output

IPIPE0/DSO

Used to track movement of words through the instruction

pipeline (O) or output from the CPU32+ background debug

mode. (O)

Instruction Pipe 1/Row

Address Select 1

Double-Drive

IPIPE1/RAS1DD

Used to track movement of words through the instruction

pipeline (O), or a row address select 1 “double-drive” output

(O)

Breakpoint/Development

Serial Clock BKPT/DSCLK Signals a hardware breakpoint to the QUICC (open-drain I/O),

or clock signal for CPU32+ background debug mode (I)

Freeze/Initial

Configuration 2 FREEZE/CONFIG2 Indicates that the CPU32+ has acknowledged a breakpoint

(O), or initial QUICC configuration select (I)

Table 1. System Bus Signal Index (Normal Operation) (Continued)

Group Signal Name Mnemonic Function

2113B–HIREL–06/05

TS68EN360

Note: 1. I denotes input, O denotes output and I/O is input/output.

Clock and Test

(Cont’d)

Three-State TRIS Used to three-state all pins if QUICC is configured as a

master. Always Sampled except during system reset. (I)

Test Clock TCK Provides a clock for Scan test logic. (I)

Test Mode Select TMS Controls test mode operations. (I)

Test Data In TDI Serial test instructions and test data signal. (I)

Test Data Out TDO Serial test instructions and test data signal. (O)

Test Reset TRST Provides an asynchronous reset to the test controller. (I)

Power

Clock Synthesizer Power VCCSYN Power supply to the PLL of the clock synthesizer

Clock Synthesizer

Ground GNDSYN Ground supply to the PLL of the clock synthesizer

Clock Out Power VCCCLK Power supply to clock out pins

Clock Out Ground GNDCLK Ground supply to clock out pins

Special Ground 1 GNDS1 Special ground for fast AC timing on certain system bus

signals

Special Ground 2 GNDS2 Special ground for fast AC timing on certain system bus

signals

System Power Supply

and Return VCC, GND Power supply and return to the QUICC

-- No Connect NC4-NC1 Four no-connect pins

Table 1. System Bus Signal Index (Normal Operation) (Continued)

Group Signal Name Mnemonic Function

2113B–HIREL–06/05

TS68EN360

Table 3-1. Peripherals Signal Index

Group Signal Name Mnemonic Function

SCC

Receive Data RXD4-RXD1 Serial receive data input to the SCCs. (I)

Transmit Data TXD4-TXD1 Serial transmit data output from the SCCs. (O)

Request to Send RTS4-RTS1 Request to send outputs indicate that the SCC is ready to

transmit data. (O)

Clear to Send CTS4-CTS1 Clear to send inputs indicate to the SCC that data

transmission may begin. (I)

Carrier Detect CD4-CD1 Carrier detect inputs indicate that the SCC should begin

reception of data. (I)

Receive Start RSTRT1

This output from SCC1 identifies the start of a receive frame.

Can be used by an Ethernet CAM to perform address

matching. (O)

Receive Reject RRJCT1

This input to SCC1 allows a CAM to reject the current

Ethernet frame after it determines the frame address did not

match. (I)

Clocks CLK8-CLK1 Input clocks to the SCCs, SCMs, SI, and the baud rate

generators. (I)

IDMA

DMA Request DREQ2-DREQ1 A request (input) to an IDMA channel to start an IDMA

transfer. (I)

DMA Acknowledge DACK2-DACK1 An acknowledgement (output) by the IDMA that an IDMA

transfer is in progress. (O)

DMA Done DONE2-DONE1 A bidirectional signal that indicates the last IDMA transfer in

a block of data. (I/O)

TIMER

Timer Gate TGATE2-TGATE1 An input to a timer that enables/disables the counting

function. (I)

Timer Input TIN4-TIN1 Time reference input to the timer that allows it to function as

a counter. (I)

Timer Output TOUT4-TOUT1 Output waveform (pulse or toggle) from the timer as a result

of a reference value being reached. (O)

SPI

SPI Master In Slave Out SPIMISO Serial data input to the SPI master (I); serial data output from

an SPI slave. (O)

SPI Master Out Slave In SPIMOSI Serial data output from the SPI master (O); serial data input

to an SPI slave. (I)

SPI Clock SPICLK Output clock from the SPI master (O); input clock to the SPI

slave. (I)

SPI Select SPISEL SPI slave select input. (I)

SMC

SMC Receive Data SMRXD2-SMRXD1 Serial data input to the SMCs. (I)

SMC Transmit Data SMTXD2-SMTXD1 Serial data output from the SMCs. (O)

SMC Sync SMSYN2-SMSYN1 SMC synchronization signal. (I)

2113B–HIREL–06/05

TS68EN360

SI Receive Data L1RXDA, L1RXDB Serial input to the time division multiplexed (TDM) channel A

or channel B

SI Transmit Data L1TXDA, L1TXDB Serial output from the TDM channel A or channel B

SI Receive Clock L1RCLKA, L1RCLKB Input receive clock to TDM channel A or channel B

SI Transmit Clock L1TCLKA, L1TCLKB Input transmit clock to TDM channel A or channel B

SI Transmit Sync Signals L1TSYNCA,

L1TSYNCB

Input transmit data sync signal to TDM channel A or

channel B

SI Receive Sync Signals L1RSYNCA,

L1RSYNCB

Input receive data sync signal to TDM channel A or

channel B

IDL Interface Request L1RQA, L1RQB IDL interface request to transmit on the D channel. Output

from the SI

SI Output Clock L1CLKOA, L1CLKOB Output serial data rate clock. Can output a data rate clock

when the input clock is 2x the data rate

SI Data Strobes L1ST4-L1ST1

Serial data strobe outputs can be used to gate clocks to

external devices that do not have a built-in time slot assigner

(TSA)

BRG

Baud Rate Generator

Out 4-1 BRGO4-BRGO1 Baud rate generator output clock allows baud rate generator

to be used externally

BRG Input Clock CLK2, CLK6 Baud rate generator input clock from which BRG will derive

the baud rates

PIP

Port B 15-0 PB15-BP0 PIP Data I/O Pins

Strobe Out STRBO This input causes the PIP output data to be placed on the

PIP data pins

Strobe In STRBI This input causes data on the PIP data pins to be latched by

the PIP as input data

SDMA SDMA Acknowledge 2-1 SDACK2-SDACK1 SDMA output signals used in RISC receiver to mark fields in

the Ethernet receive frame

Table 3-1. Peripherals Signal Index (Continued)

Group Signal Name Mnemonic Function

2113B–HIREL–06/05

TS68EN360

4. Detailed Specification

This specification describes the specific requirements for the microcontroller TS68EN360 -

25 MHz and 33 MHz in compliance with MIL-STD-883 class B or Atmel standard screening.

5. Applicable Documents

1. MIL-STD-883: test methods and procedures for electronics

2. MIL-PRF-38535: general specifications for microcircuits

3. DESC 5962-SMD-97607

The microcircuits are in accordance with the applicable document and as specified herein.

5.1 Design and Construction

5.1.1 Terminal Connections

Depending on the package, the terminal connections shall be as shown in Figure 2-1 and Figure

2-2.

5.1.2 Lead Material and Finish

Lead material and finish shall be as specified in MIL-STD-883 (see enclosed ”Ordering Informa-

tion” on page 79)

5.1.3 Package

The macrocircuits are packaged in hermetically sealed ceramic packages which are conform to

case outlines of MIL-STD-1835 or as follow:

• PGA but see ”241-pin – PGA” on page 77

• CERQUAD

The precise case outlines are described at the end of the specification (”Package Mechanical

Data” on page 77) and into MIL-STD-1835.

5.2 Absolute Maximum Ratings

Notes: 1. Permanent damage can occur if maximum ratings are exceeded. Exposure to voltages or cur-

rents in excess of recommended values affects device reliability. Device modules may not

operate normally while being exposed to electrical extremes.

2. Although sections of the device contain circuitry to protect against damage from high static

voltages or electrical fields, take normal precautions to avoid exposure to voltages higher than

maximum-rated voltages.

3. The supply voltage VCC must start and restart from 0.0V; otherwise, the 360 will not come out

of reset properly.Unless otherwise stated, all voltages are referenced to the reference terminal.

Table 5-1. Absolute Maximum Ratings

Rating Symbol Value Unit

Supply Voltage(1)(2) VCC -0.3 to +6.5 V

Input Voltage(1)(2) VIN -0.3 to +6.5 V

Storage Temperature Range TSTG -55 to +150 °C

2113B–HIREL–06/05

TS68EN360

This device contains protective circuitry against damage due to high static voltages or electrical

fields; however, it is advised that normal precautions be taken to avoid application of any volt-

ages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation

is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or

VDD)

TJ = TA + (PD · θJA)

PD = (VDD · IDD) + PI/O

Where PI/O is the power dissipation on pins.

5.3 Power Considerations

The average chip-junction temperature, TJ, in °C can be obtained from:

TJ = TA ÷ (PD · ΘJA)(1)

where:

TA = Ambient Temperature, °C

ΘJA = Package Thermal Resistance,

Junction-to-Ambient, C/W

PD = PINT + P I/O

PINT = ICC · VCC, Watts-chip Internal Power

PI/O = Power Dissipation on Input and Output Pins-User Determined

For most applications, PI/O < 0.3 · PINT and can be neglected.

Table 5-2. Recommended Conditions of Use

Unless otherwise stated, all voltages are referenced to the reference terminal

Symbol Parameter Min Typ Max Unit

VCC Supply Voltage Range +4.75 +5.25 V

VIL Logic Low Level Input Voltage Range GND +0.8 V

VIH Logic High Level Input Voltage Range +2.0 VCC V

Tcase Operating Temperature -55 +125 °C

VOH High Level Output Voltage +2.4 V

fsys System Frequency (For 25 MHz version) 25 MHz

(For 33 MHz version) 33 MHz

Table 5-3. Thermal Characteristics

Symbol Parameter Value Unit

θJC Thermal Resistance - Junction to Case 240-pin Cerquad 2

°C/W

241-pin PGA 7

θJA Thermal Resistance - Junction to Ambient 240-pin Cerquad 27.4

°C/W

241-pin PGA 22.8

2113B–HIREL–06/05

TS68EN360

An approximate relationship between PD and TJ (if PI/O is neglected) is:

PD = K ÷ (TJ + 273°C) (2)

Solving Equations (1) and (2) for K gives:

K = PD · (TA + 273°C) + ΘJA · PD2(3)

where K is a constant pertaining to the particular part. K can be determined from Equation (3) by

measuring PD (at thermal equilibrium) for a know TA. Using this value of K, the values of PD and

TJ can be obtained by solving Equations (1) and (2) iteratively for any value of TA.

5.4 Mechanical and Environment

The microcircuits shall meet all mechanical environmental requirements of either MIL-STD-883

for class B devices or for Atmel standard screening.

5.5 Marking

The document where are defined the marking are identified in the related reference documents.

Each microcircuit are legible and permanently marked with the following information as

minimum:

• Atmel logo

• Manufacturer’s part number

• Class B identification

• Date-code of inspection lot

• ESD identifier if available

• Country of manufacturing

6. Quality Conformance Inspection

6.1 DESC/MIL-STD-883

Is in accordance with MIL-M-38535 and method 5005 of MIL-STD-883. Group A and B inspec-

tions are performed on each production lot. Group C and D inspections are performed on a

periodical basis.

7. Electrical Characteristics

7.1 General Requirements

All static and dynamic electrical characteristics specified for inspection purposes and the rele-

vant measurement conditions are given below:

• Static electrical characteristics for the electrical variants

• Dynamic electrical characteristics for TS68EN360 (25 MHz, 33 MHz)

For static characteristics, test methods refer to IEC 748-2 method number, where existing.

For dynamic characteristics, test methods refer to clause Table 7-1 of this specification.

2113B–HIREL–06/05

TS68EN360

7.2 Static Characteristics

The electrical specifications in this document are preliminary. (See numbered notes)

7.3 Dynamic Characteristics

The AC specifications presented consist of output delays, input setup and hold times, and signal

skew times. All signals are specified relative to an appropriate edge of the clock and possibly to

one or more other signals.

The measurement of the AC specifications is defined by the waveforms shown in Figure 7-1. To

test the parameters guaranteed by Atmel inputs must be driven to the voltage levels specified in

the figure. Outputs are specified with minimum and/or maximum limits, as appropriate, and are

measured as shown. Inputs are specified with minimum setup and hold times and are measured

as shown. Finally, the measurement for signal-to-signal specifications are shown.

Note that the testing levels used to verify conformance to the AC specifications do not affect the

guaranteed DC operation of the device as specified in the DC electrical characteristics.

Table 7-1. Static Characteristics – GND = 0 VDC, TC = -55 to +125°C

Characteristic Symbol Min Max Unit

Input High Voltage (except EXTAL) VIH 2.0 VCC V

Input Low Voltage (5V Part) VIL GND 0.8 V

Input Low Voltage (Part Only; PA8-15, PB1, PC5, PC7, TCK) VIL GND 0.5 V

Input Low Voltage (Part Only; All Other Pins) VIL GND 0.8 V

EXTAL Input High Voltage VIHC 0.8*(VCC)V

CC + 0.3 V

Undershoot ––-0.8V

Input Leakage Current (All Input Only Pins except for TMS, TDI and TRST)

Vin = 0/5V Iin -2.5 2.5 µA

Hi-Z (Off-State) Leakage Current (All Noncrystal Outputs and I/O Pins except

TMS,TDI and TRST) Vin = 0/5V IOZ -2.5 -2.5 µA

Signal Low Input Current VIL = 0.8V (TMS, TDI and TRST Pins Only)

Signal High Input Current VIH = 2.0V (TMS, TDI and TRST Pins Only)

-0.5

0.5

Output High Voltage

IOH = -0.8 mA, VCC = 4.75V

AII Noncrystal Outputs Except Open Drain Pins

VOH 2.4 – V

Output Low Voltage

IOL = 2.0 mA, CLKO1-2, FREEZE, IPIPE0-1, IFETCH, BKPTO

IOL = 3.2 mA, A31-A0, D31-D0, FC3-0, SIZ0-1, PA0, 2, 4, 6, 8-15, PB0-5,

PB8-17, PC0-11, TDO, PERR, PRTY0-3, IOUT0-2, AVECO, AS, CAS3-0,

BLCRO, RAS0-7

IOL = 5.3 mA, DSACK0-1, R/W, DS, OE, RMC, BG, BGACK, BERR

IOL = 7 mA, TXD1-4

IOL = 8.9 mA, PB6, PB7, HALT, RESET, BR (Output)

VOL –

0.5

Input Capacitance

AII I/O Pins Cin – 20 pF

Load Capacitance (except CLKO1-2) CL– 100 pF

Load Capacitance (CLKO1-2) CLc– 50pF

Power VCC 4.75 5.25 V

2113B–HIREL–06/05

TS68EN360

Figure 7-1. Drive Levels and Test Points For AC Specifications

Notes: 1. This output timing is applicable to all parameters specified relative to the rising edge of the clock

2. This output timing is applicable to all parameters specified relative to the falling edge of the clock

3. This input timing is applicable to all parameters specified relative to the rising edge of the clock

4. This input timing is applicable to all parameters specified relative to the falling edge of the clock

5. This timing is applicable to all parameters specified relative to the assertion/negation of another signal

Legend:

a) Maximum output delay specification

b) Minimum output hold time

c) Minimum input setup time specification

d) Minimum input hold time specification

e) Signal valid to signal valid specification (maximum or minimum)

f) Signal valid to signal invalid specification (maximum or minimum)

0.8V

2.0V

0.8V

VALID

OUTPUT nVALID

OUTPUT n + 1

2.0V

0.8V

2.0V

0.8V

2.0V

0.8V

VALID

OUTPUT nVALID

OUTPUT n+1

2.0V

0.8V

VALID

INPUT

2.0V

0.8V

2.0V

0.8V

VALID

INPUT

2.0V

0.8V

2.0V

0.8V

DRIVE

TO 0.5V

DRIVE

TO 2.4V

2.0V

0.8V

2.0V

0.8V

CLKOUT

OUTPUTS(1)

OUTPUTS(2)

INPUTS(3)

INPUTS(4)

ALL SIGNALS(5)

2113B–HIREL–06/05

TS68EN360

7.4 AC Power Dissipation

Notes: 1. Rev A mask is C63T

2. Rev B masks are C69T and F35G

3. Current Rev C masks are E63C, E68C and F15W

4. EXTAL frequency is 32 kHz

All measurements were taken with only CLKO1 enabled, VCC = 5.0V, VIL = 0V and VIH = VCC

Notes: 1. Rev A mask is C63T

2. Rev B masks are C69T and F35G

3. Current Rev C masks are E63C, E68C and F15W

Table 7-2. Typical Current Drain

Mode of Operation Symbol

System Clock

Frequency

BRGCLK Clock

Frequency

SyncCLK Clock

Frequency Typ Unit

Normal mode (Rev A(1) and Rev B(2))I

DD 25 MHz 25 MHz 25 MHz 250 mA

Normal Mode (Rev C(3) and Newer) IDD 25 MHz 25 MHz 25 MHz 237 mA

Normal Mode IDD 33 MHz 33 MHz 33 MHz 327 mA

Low Power Mode IDDSB

Divide by 2

12.5 MHz

Divide by 16

1.56 MHz

Divide by 2

12.5 MHz 150 mA

Low Power Mode IDDSB

Divide by 4

6.25 MHz

Divide by 16

1.56 MHz

Divide by 4

6.25 MHz 85 mA

Low Power Mode IDDSB

Divide by 16

1.56 MHz

Divide by 16

1.56 MHz

Divide by 4

6.25 MHz 35 mA

Low Power Mode IDDSB

Divide by 256

97.6 kHz

Divide by 16

1.56 MHz

Divide by 4

6.25 MHz 20 mA

Low Power Mode IDDSB

Divide by 256

97.6 kHz

Divide by 64

390 kHz

Divide by 64

390 kHz 13 mA

Low Power Stop VCO Off(4) IDDSP 0.5 mA

PLL Supply Current

PLL Disabled

PLL Enabled

IDDPD

IDDPE

TBD

Table 7-3. Maximum Power Dissipation

System Frequency VCC Max PDUnit Mask

25 MHz 5.25V 1.80 W REV A(1) and REV B(2)

25 MHz 5.25V 1.45 W REV C(3) and Newer

25 MHz 3.6V 0.65 W REV C(3) and Newer

33 MHz 5.25V 2.00 W REV C(3) and Newer

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TS68EN360

7.5 AC Electrical Specifications Control Timing

Note: 1. Note that the minimum VCO frequency and the PLL default values put some restrictions on the minimum system frequency.

The following calculation should be used to determine the actual value for specifications 5B, 5C and 5D.

5B: 25 MHz ±(0.9 ns + 0.25 x (rise time)) (1.4 ns at rise = 2 ns; 1.9 ns at rise = 4 ns)

33 MHz ±(0.5 ns + 0.25 x (rise time)) (1 ns at rise = 2 ns; 1.5 ns at rise = 4 ns)

5C: 25/33 MHz ±(2 ns + 0.25 x (rise time)) (2.5 ns at rise = 2 ns; 3 ns at rise = 4 ns)

5D: 25 MHz ±(3 ns + 0.5 x (rise time)) (4 ns at rise = 2 ns; 5 ns at rise = 4 ns)

33 MHz ±(2.5 ns + 0.5 x (rise time)) (3.5 ns at rise = 2 ns; 4.5 ns at rise = 4 ns)

Table 7-4. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure

7-2)

Number Characteristic Symbol

25 MHz 33.34 MHz

UnitMin Max Min Max

System Frequency fsys dc(1) 25.00 33.34 MHz

Crystal Frequency fXTAL 25 6000 25 6000 kHz

On-Chip VCO System Frequency fsys 20 50 20 67 MHz

Start-up Time

With external clock (oscillator disabled) or after

changing the multiplication factor MF

tpll 2500 clks

CLKO1-2 stability ∆CLK TBD TBD %

1 CLKO1 Period tcyc 40 – 30 – ns

1A EXTAL Duty Cycle, MF tdcyc 40 60 40 60 %

1C External Clock Input Period tEXTcyc 40 – 30 – ns

2, 3 CLKO1 Pulse Width (Measured at 1.5V) tCW1 19 – 14 – ns

2A, 3A CLKO2 Pulse Width (Measured at 1.5V) tCW2 9.5 – 7 – ns

4, 5 CLKO1 Rise and Fall Times (Full drive) tCrf1 –2–2ns

4A, 5A CLKO2 Rise and Fall Times (Full drive) tCrf2 –2–1.6ns

5B EXTAL to CLKO1 Skew-PLL enabled (MF< 5) tEXTP1 aans

5C EXTAL to CLKO2 Skew-PLL enabled (MF< 5) tEXTP2 aans

5D CLKO1 to CLKO2 Skew AtmelKW aans

2113B–HIREL–06/05

TS68EN360

Figure 7-2. Clock Timing

7.6 External Capacitor For PLL

Note: 1. MF – multiplication factor.

7.6.1 Examples:

Notes: 1. MODCK1 pin = 0, MF = 1 ⇒ CXFC = 400 pF

2. MODCK1 pin = 1, crystal is 32.768 kHz (or 4.192 MHz), initial MF = 401, initial frequency =

13.14 MHz, later on MF is changed to 762 to support a frequency of 25 MHz. Minimum CXFC

is: 762 x 380 = 289 nF, Maximum CXFC is: 401 x 970 = 390 nF. The recommended CXFC for 25

MHz is: 762 x 540 = 414 nF. 289 nF < CXFC < 390 nF and closer to 414 nF. The proper avail-

able value for CXFC is 390 nF.

3. MODCK1 pin = 1, crystal is 32.768 kHz (or 4.192 MHz), initial MF = 401, initial frequency =

13.14 MHz, later on MF is changed to 1017 to support a frequency of 33.34 MHz. Minimum

CXFC is: 1017 x 380 = 386 nF, Maximum CXFC is: 401 x 970 = 390 nF ⇒ 386 nF < CXFC < 390

nF. The proper available value for CXFC is 390 nF.

4. In order to get higher range, higher crystal frequency can be used (i.e. 50 kHz), in this case:

Minimum CXFC is: 667 x 380 = 253 nF, Maximum CXFC is: 401 x 970 = 390 nF ⇒ 386 nF <

CXFC < 390 nF.

EXTAL

CLKO1

CLKO2

(INPUT)

(OUTPUT)

2A 3A

4A 5A

5C 5B

VOLTAGE MIDPOINT

Table 7-5. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary.

Characteristic Symbol Min Max Unit

PLL External Capacitor (XFC to VCCSYN) cXFC

MF< 5 (Recommended value MF x 400 pF)(1) MF x 340 MF x 480 pF

MF> 4 (Recommended value MF x 540 pF)(1) MF x 380 MF x 970 pF

2113B–HIREL–06/05

TS68EN360

7.7 Bus Operation AC Timing Specifications

Table 7-6. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary

(See Figure 7-3 to Figure 7-19)

Number Characteristic Symbol

25 MHz 33.34 MHz

UnitMin Max Min Max

6 CLKO1 High to Address, FC, SIZ, RMC Valid tCHAV 0 15 0 12 ns

6A CLKO1 High to Address Valid (GAMX = 1) tCHAV 0 20 0 15 ns

7CLKO1 High to Address, Data, FC, SIZ, RMC High

Impedance tCHAZx 0 40 0 30 ns

8CLKO1 High to Address, Data, FC, SIZ, RMC

Invalid tCHAZn -2 – -2 – ns

9CLKO1 Low to AS, DS, OE, WE, IFETCH, IPIPE,

IACKx Asserted tCLSA 3 20 3 15 ns

9(10) CLKO1 Low to CSx/RASx Asserted tCLSA 4 16 4 12 ns

9B(11) CLKO1 High to CSx/RASx Asserted tCHCA 4 16 4 12 ns

9A(2)(10) AS to DS or CSx/RASx or OE Asserted (Read) tSTSA -6 6 -5.625 5.625 ns

9C(2)(11) AS to CSx/RASx Asserted tSTCA 14 26 9 21 ns

11(10) Address, FC, SIZ, RMC, valid to AS, CSx/RASx,

OE, WE, (and DS Read) Asserted tAVSA 10 – 8 – ns

11A(11) Address, FC, SIZ, RMC, Valid to CSx/RASx

Asserted tAVCA 30 – 22.5 – ns

12 CLKO1 Low to AS, DS, OE, WE, IFETCH, IPIPE,

IACKx Negated tCLSN 3 20 3 15 ns

12(16) CLKO1 Low to CSx/RASx Negated tCLSN 4 16 4 12 ns

12A(13)(16) CLKO1 High to CSx/RASx Negated tCHCN 4 16 4 12 ns

12B CS negate to WE negate (CSNTQ = 1) AtmelTW 15 – 12 – ns

13(12) AS, DS, CSx, OE, WE, IACKx Negated to Address,

FC, SIZ Invalid (Address Hold) tSNAI 10 – 7.5 – ns

13A(13) CSx Negated to Address, FC, SIZ, Invalid (Address

Hold) tCNAI 30 – 22.5 – ns

14(10)(12) AS, CSx, OE, WE (and DS Read) Width Asserted tSWA 75 – 56.25 – ns

14C(11)(13) CSx Width Asserted tCWA 35 – 26.25 – ns

14A DS Width Asserted (Write) tSWAW 35 – 26.25 – ns

14B AS, CSx, OE, WE, IACKx, (and DS Read) Width

Asserted (Fast Termination Cycle) tSWDW 35 – 26.25 – ns

14D(13) CSx Width Asserted (Fast Termination Cycle) tCWDW 15 – 10 – ns

15(3)(10)(12) AS, DS, CSx, OE, WE Width Negated tSN 35 – 26.25 – ns

16 CLKO1 High to AS, DS, R/W High Impedance tCHSZ – 40 – 30 ns

17(12) AS, DS, CSx, WE Negated to R/W High tSNRN 10 – 7.5 – ns

17A(13) CSx Negated to R/W High tCNRN 30 – 22.5 – ns

18 CLKO1 High to R/W High tCHRH 0 20 0 15 ns

2113B–HIREL–06/05

TS68EN360

20 CLKO1 High to R/W Low tCHRL 3 20 3 15 ns

21(10) R/W High to AS, CSx, OE Asserted tRAAA 10 – 7.5 – ns

21A(11) R/W High to CSx Asserted tRACA 30 – – ns

22 R/W Low to DS Asserted (Write) tRASA 47 – 36 – ns

23 CLKO1 High to Data-Out tCHDO – 23 – 18 ns

23A CLKO1 High to Parity Valid tCHPV – 25 – 20 ns

23B Parity Valid to CAS Low tPVCL 3–3–ns

24(12) Data-Out, Parity-Out Valid to Negating Edge of AS,

CSx, WE, (Fast Termination Write) tDVASN 10 – 7.5 – ns

25(12) DS, CSX, WE Negated to Data-Out, Parity-Out

Invalid (Data-Out, Parity-Out Hold) tSNDOI 10 – 7.5 – ns

25A(13) CSx Negated to Data-Out, Parity-Out Invalid (Data-

Out, Parity-Out Hold) tCNDOI 35 – 25 – ns

26 Data-Out, Parity-Out Valid to DS Asserted (Write) tDVSA 10 – 7.5 – ns

27(15) Data-In, Parity-In to CLKO1 Low (Data-Setup) tDICL 1–1–ns

27B(14) Data-In, Parity-In Valid to CLKO1 Low (Data-Setup) tDICL 20 – 15 – ns

27A Late BERR, HALT, BKPT Asserted to CLKO1 Low

(Setup Time) tBELCL 10 – 7.5 – ns

28(18) AS, DS Negated to DSACKx, BERR, HALT

Negated tSNDN 050037.5ns

29(4) DS, CSx, OE, Negated to Data-In Parity-In Invalid

(Data-In, Parity-In Hold) tSNDI 0–0–ns

29A(4) DS, CSx, OE Negated to Data-In High Impedance tSHDI – 40 – 30 ns

30(4) CLKO1 Low to Data-In, Parity-In Invalid (Fast

Termination Hold) tCLDI 10 – 7.5 – ns

30A(4) CLKO1 Low to Data-In High Impedance tCLDH – 60 – 45 ns

31(5)(15) DSACKx Asserted to Data-in, Parity-In Valid tDADI – 32 – 24 ns

31A DSACKx Asserted to DSACKx Valid (Skew) tDADV –10–7.5ns

31B(5)(14) DSACKx Asserted to Data-in, Parity-In Valid tDADI – 35 – 26 ns

32 HALT an RESET Input Transition Time tHRrf –140– ns

33 CLKO1 High to BG Asserted tCLBA – 20 – 15 ns

34 CLKO1 High to BG Negated tCLBN – 2022.515 ns

35(6) BR Asserted to BG Asserted (RMC Not Asserted) tBRAGA 1–1–CLKO1

37 BGACK Asserted to BG Negated tGAGN 12.512.5CLKO1

39 BG Width Negated tGH 2–2–CLKO1

39A BG Width Asserted tGA 1–1–CLKO1

46 R/W Width Asserted (Write or Read) tRWA 100 – 75 – ns

Table 7-6. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary

(See Figure 7-3 to Figure 7-19) (Continued)

Number Characteristic Symbol

25 MHz 33.34 MHz

UnitMin Max Min Max

2113B–HIREL–06/05

TS68EN360

46A R/W Width Asserted (Fast Termination Write or

Read) tRWAS 75 – 56 – ns

47A Asynchronous Input Setup Time tAIST 5–4–ns

47B Asynchronous Input Hold Time tAIHT 10 – 7.5 – ns

48(5)(7) DSACKx Asserted to BERR, HALT Asserted tDABA –30–22.5ns

53 Data-Out, Parity-Out Hold from CLKO1 High tDOCH 0–0–ns

54 CLKO1 High to Dat-Out, Parity-Out High

Impedance tCHDH – 20 – 15 ns

55 R/W Asserted to Data Bus Impedance Change tRADC 25 – 19 – ns

56 RESET Pulse Width (Reset Instruction) tHRPW 512 – 512 – CLKO1

56A RESET Pulse Width (Input from External Device) tRPWI 20 – 20 – CLKO1

57 BERR Negated to HALT Negated (Return) tBNHN 0–0–ns

58 CLKO1 High to BERR, RESETS, RESETH Driven

Low tCHBRL –30 26ns

58A CLKO1 Low RESETS Driven Low (upon Reset

Instruction execution only) tCLRL –30 26ns

58B CLKO1 High to BERR, RESETS, RESETH

tri-stated tCLRL – 20 – 15 ns

60 CLKO1 High to BCLRO Asserted tCHBCA – 20 – 15 ns

61 CLKO1 High to BCLRO Negated tCHBCN – 20 – 15 ns

62(9) BR Synchronous Setup Time tBRSU 5 – 3.75 – ns

63(9) BR Synchronous Hold Time tBRH 10 – 7.5 – ns

64(9) BGACK Synchronous Setup Time tBGSU 5 – 3.75 – ns

65(9) BGACK Synchronous Hold Time tBGH 10 – 7.5 – ns

66 BR Low to CLKO1 Rising Edge (040 comp. mode) tBRCH 5–5–ns

70 CLKO1 Low to Data Bus Driven (Show Cycle) tSCLDD 030022.5ns

71 Data Setup Time to CLKO1 Low (Show Cycle) tSCLDS 10 – 7.5 – ns

72 Data Hold from CLKO1 Low (Show Cycle) tSCLDH 6 – 3.75 – ns

73 BKPT Input Setup Time tBKST 10 – 7.5 – ns

74 BKPT Input Hold Time tBKHT 6 – 3.75 – ns

75 RESETH Low to Config2-0, MOD1-0, B16M Valid tMST –500–500CLKO1

76 Config2-0 tMSH 0–0–ns

77 MOD1-0 Hold Time, B16M Hold Time tMSH 10 – 10 – CLKO1

80 DSI Input Setup Time tDSISU 10 – 7.5 – ns

81 DSI Input Hold Time tDSIH 6 – 3.75 – ns

82 DSCLC Setup Time tDSCSU 10 – 7.5 – ns

Table 7-6. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary

(See Figure 7-3 to Figure 7-19) (Continued)

Number Characteristic Symbol

25 MHz 33.34 MHz

UnitMin Max Min Max

2113B–HIREL–06/05

TS68EN360

Notes: 1. All AC timing is shown with respect to 0.8V and 2.0V levels unless otherwise noted.

2. This number can be reduced to 5 ns if strobes have equal loads.

3. If multiple chip selects are used, the CSx width negated (#15) applies to the time from the negation of a heavily loaded chip

select to the assertion of a lightly loaded chip select.

4. Hold times are specified with respect to DS or CSx on asynchronous reads and with respect to CLKO1 on fast termination

reads. The user is free to use either hold time for fast termination reads.

5. If the asynchronous setup (#17) requirements are satisfied, the DSACKx low to data setup time (#31) and DSACKx low to

BERR low setup time (#48) can be ignored. The data must only satisfy the data-in to CLKO1 low setup time (#27) for the fol-

lowing clock cycle: BERR must only satisfy the late BERR low to CLKO1 low setup time (#27A) for the following clock cycle.

6. To ensure coherency during every operand transfer, BG will not be asserted in response to BR until after cycles of the cur-

rent operand transfer are complete and RMC is negated.

7. In the absence of DSACKx, BERR is an asynchronous input using the asynchronous setup time (#47).

8. During interrupt acknowledge cycles, the processor may insert up to two wait states between states S0 and S1.

9. Specs are for Synchronous Arbitration only. ASTM = 1.

10. CSx specs are for TRLX = 0.

11. CSx specs are for TRLX = 1.

12. CSx specs are for CSNTQ = 0.

13. CSx specs are for CSNTQ = 1; or RASx specs for DRAM accesses.

14. Specs are read cycles with parity check and PBEE = 1.

15. Specs are read cycles with parity check and PBEE = 0, PAREN = 1.

16. RASx specs are for page miss case.

17. Specifications only apply to CSx/RASx pins.

18. Specification applies to non fast termination cycles. In fast termination cycles, the BERR signal must be negated by 20 ns

after negation of AS, DS.

83 DSCLC Hold Time tDSCH 6 – 3.75 – ns

84 DSO Delay Time tDSOD –tcyc+2

0–tcyc+2

0ns

85 DSCLK Cycle tDSCCYC 2–2–CLKO1

86 CLKO1 High to Freeze Asserted tFRZA 0 35 0 26.25 ns

87 CLKO1 High to Freeze Negated tFRZN 0 35 0 26.25 ns

88 CLKO1 High to IFETCH High Impedance tIFZ 0 35 0 26.25 ns

89 CLKO1 High to IFETCH Valid tIF 0 35 0 26.25 ns

90 CLKO1 High to PERR Asserted tCHPA 0 20 0 15 ns

91 CLKO1 High to PERR Negated tCHPN 0 20 0 15 ns

92 VCC Ramp-Up Time At Power-On Reset tRMIN 5–5–ns

Table 7-6. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary

(See Figure 7-3 to Figure 7-19) (Continued)

Number Characteristic Symbol

25 MHz 33.34 MHz

UnitMin Max Min Max

2113B–HIREL–06/05

TS68EN360

Figure 7-3. Read Cycle

Note: All timing is shown with respect to 0.8V and 2.0V levels.

DSACK0

R/W

BERR,

FC3-FC0

A31-A0

CLKO1

S0 S2 S4S1 S3 S5

6 8

12 13

47A 28

29A

D31-D0

27A

47B

47A

SIZ1-SIZ0

DSACK1

IFETCH

IPIPE1,0

ASYNCHRONOUS

INPUTS

HALT

BKPT

RMC

CSx

(OUTPUT)

(INPUT)

(OUTPUT)

(INPUT)

(I/O)

(OUTPUT)

31A

2113B–HIREL–06/05

TS68EN360

Figure 7-4. Fast Termination Read Cycle (Parity Check PAREN = 1, PBEE = 0)

(OUTPUT)

A31-A0

(OUTPUT)

CLKO1

(OUTPUT)

S0 S4 S0

S1 S5

(OUTPUT)

D31-D0

(INPUT)

14B

46A

30A

R/W

(OUTPUT)

CSx

(OUTPUT)

BKPT

(INPUT)

FC3-FC0

(OUTPUT)

SIZ1-SIZ0

(OUTPUT)

PERR

(OUTPUT)

73 74

CPU CLEARS PERn BIT

2113B–HIREL–06/05

TS68EN360

Figure 7-5. Read Cycle (With Parity Check, PBEE = 1)

Note: All timing is shown with respect to 0.8V and 2.0V levels.

R/W

(OUTPUT)

A31-A0, FC3-FC0,

SIZ1-SIZ0 (OUTPUT)

CSx

(OUTPUIT)

DSACK1

(I/O)

BERR

(INPUT)

D31-D0

(INPUT)

47A

27A

47A

HALT

(INPUT)

IFETCH

(OUTPUT)

ASYNCHRONOUS

INPUTS

BKPT

(INPUT)

RMC

(OUTPUT)

47B

29A

CLKO1

(OUTPUT)

S0 S2 S4S1 S3 S5

DSACK0

(I/O)

(OUTPUT)

31B

PRTY0-PRTY3

(INPUT)

73 74

27B

31A

IPIPE1,0

(OUTPUT)

2113B–HIREL–06/05

TS68EN360

Figure 7-6. SRAM: Read Cycle (TRLX = 1)

DSACK0

(I/O)

R/W

(OUTPUT)

A31-A0

(OUTPUT)

CLKO1

(OUTPUT)

S0 S1 S2 S3 S5S4

FC3-FC0

(OUTPUT)

SIZ1-SIZ0

(OUTPUT)

29A

D31-D0

(INPUT)

47A

DSACK1

(I/O)

RMC

(OUTPUT)

31A

11A

CSx

(OUTPUT)

21A

(OUTPUT) 18

2113B–HIREL–06/05

TS68EN360

Figure 7-7. CPU32+ IACK Cycle

Note: Up to two wait states may be inserted by the processor between states S0 and S1.

DSACK0

(I/O)

R/W

(OUTPUT)

A31-A0

(OUTPUT)

CLKO1

(OUTPUT)

S0 S1 S2 S3 S5S4

IACKx

(OUTPUT)

FC3-FC0

(OUTPUT)

29A

D31-D0

(INPUT)

47A

31A

DSACK1

(I/O)

0-2 CLOCKS*

A1 A2 A3 A4

(OUTPUT)

SIZ1-SIZ0

(OUTPUT)

2113B–HIREL–06/05

TS68EN360

Figure 7-8. Write Cycle

Note: All timing is shown with respect to 0.8V and 2.0V levels.

R/W

(OUTPUT)

A31-A0

(OUTPUT)

CLKO1

(OUTPUT)

S0 S2 S4

S1 S3 S5

14 15

912 13

CSn

(OUTPUT)

14A

DSACK0

(I/O)

BERR

(INPUT)

D31-D0

(OUTPUT)

47A

HALT

(INPUT)

23 54

BKPT

(INPUT)

DSACK1

(I/O)

FC3-FC0

(OUTPUT)

SIZ1-SIZ0

(OUTPUT)

WEn

(OUTPUT) 20

31A

PRTY3-PRTY0

(OUTPUT)

2113B–HIREL–06/05

TS68EN360

Figure 7-9. Fast Termination Write Cycle

Figure 7-10. SRAM: Fast Termination Write Cycle (CSNTQ = 1)

A31-A0

CLKO1

S0 S1 S0

R/W

S4 S5

D31-D0

WEx

SIZ1-SIZ0

FC3-FC0

CSx

BKPT

PRTY3-PRTY0

(INPUT)

(OUTPUT)

R/W

914B

20 46A

(OUTPUT)

A31-A0

(OUTPUT)

CLKO1

(OUTPUT)

S0 S1 S0

R/W

(OUTPUT)

S4 S5

D31-D0

WEx

SIZ1-SIZ0

(OUTPUT)

FC3-FC0

(OUTPUT)

CSx

(OUTPUT)

PRTY3-PRTY0

(OUTPUT)

12A

25A

46A

14D

2113B–HIREL–06/05

TS68EN360

Figure 7-11. SRAM: Write Cycle (TRLX = 1, CSNTQ = 1, TCYC = 0)

Note: All timing is shown with respect to 0.8V and 2.0V levels.

Figure 7-12. ASYNC Bus Arbitration – IDLE Bus Case

R/W

(OUTPUT)

A31-A0

(OUTPUT)

CLKO1

(OUTPUT)

S0 S2 S4

S1 S3 S5

CSx

(OUTPUT)

DSACK0

(I/O)

D31-D0

(OUTPUT)

DSACK1

(I/O)

WEx

(OUTPUT)

PRTY0-PRTY3

(OUTPUT)

9B 12A

13A

17A

11A

25A

47A

31A

14C

CLKO1

(OUTPUT)

D31-D0

(OUTPUT)

A31-A0

(OUTPUT)

(INPUT)

(OUTPUT)

BCLRO

(OUTPUT)

47A

33 34

47A

6160

47A

BGACK

(INPUT)

2113B–HIREL–06/05

TS68EN360

Figure 7-13. ASYNC Bus Arbitration – Active Bus Case

Figure 7-14. SYNC Bus Arbitration – IDLE Bus Case

CLKO1

(OUTPUT)

A31-A0

(OUTPUT)

R/W

(OUTPUT)

D31-D0

(OUTPUT)

DSACK1

(I/O)

(INPUT)

(OUTPUT)

BGACK

(INPUT)

S0 S1 S2 S3 S4

39A

DSACK0

(I/O)

BCLRO

(OUTPUT)

47A 47A

47A

CLKO1

(OUTPUT)

D31-D0

(OUTPUT)

A31-A0

(OUTPUT)

(INPUT)

(OUTPUT)

BGACK

(INPUT)

33 34

BCLRO

(OUTPUT)

2113B–HIREL–06/05

TS68EN360

Figure 7-15. SYNC Bus Arbitration – Active Bus Case

Figure 7-16. Configuration and Clock Mode Select Timing

CLKO1

(OUTPUT)

A31-A0

(OUTPUT)

R/W

(OUTPUT)

D31-D0

(OUTPUT)

DSACK1

(I/O)

(INPUT)

(OUTPUT)

BGACK

(INPUT)

S0 S1 S2 S3 S4

39A35

DSACK0

(I/O)

S98

BCLRO

(OUTPUT)

RESETH

CONFIG2-CONFIG0,

MODCK1-MODCK0,

16BM

75 77

2113B–HIREL–06/05

TS68EN360

Figure 7-17. Show Cycle

Figure 7-18. Background Debug Mode FREEZE Timing

Figure 7-19. Background Debug Mode Serial Port Timing

A31-A0

CLKO1

S0 S42 S1S41 S43 S2

70 72

R/W

D31-D0

BKPT

27A

(OUTPUT)

(INPUT)

SHOW CYCLE START OF EXTERNAL CYCLE

FREEZE

CLKO1

IFETCH/DSI

FREEZE

CLKO1

82 83

BKPT/DSCLK

IFETCH

IPIPE0/DSO

DSI

2113B–HIREL–06/05

TS68EN360

Figure 7-20. DRAM: Normal Read Cycle (Internal Mux, TRLX = 0)

Note: All timing is shown with respect to 0.8V and 2.0V levels.

A31-A0

CLKO1

S0 S2 S4S1 S3 S5

RASx

PARITY3-PARITY0

CAS3-CAS0

106

109

102 103

R/W 18

D31-D0

S2S1 S3 SW SW

105

104

DSACK1,0

D31ÐD0

(OUTPUT)

(I/O)

(INPUT)

110 111

27B

101

100

107

108

PBEE = 0

PBEE = 1

2113B–HIREL–06/05

TS68EN360

7.8 Bus Operation – DRAM Accesses AC Timing Specification

Table 7-7. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure

7-20 to Figure 7-24)

Number Characteristic

25.0 MHz 33.34 MHz Unit

Min Max Min Max

100 RASx Asserted to Row Address Invalid 15 11.25 ns

101 RASx Asserted to column Address Valid 20 15 ns

102 RASx Width Asserted 75 56.25 ns

103A RASx width Negated (Back to back Cycle) Non page mode at

WBTQ = 0 75 56.25 ns

103B RASx width Negated (Back to back Cycle) Page mode at WBTQ = 0 55 41.25 ns

103C RASx width Negated (Back to back Cycle) Non page mode at

WBTQ = 1 115 86.25 ns

103D RASx width Negated (Back to back Cycle) Page mode at WBTQ = 1 95 69.23 ns

104 RASx Asserted to CASx Asserted 35 26.25 ns

105 CLKO1 Low to CASx Asserted 3 13 2 10 ns

105A CLKO1 High to CASx Asserted (Refresh Cycle) 3 13 2 10 ns

106 CLKO1 High to CASx Negated 3 13 2 10 ns

107 Column Address Valid to CASx Asserted 15 11.25 ns

108 CASx Asserted to Column Address Negated 40 30 ns

109 CASx Asserted to RASx Negated 35 27 ns

110 CASx Width Asserted 50 37.5 ns

1111CASx Width Negated (Back to Back Cycles) 95 71.25 ns

111A CASx Width Negated (Page Mode) 20 15 ns

113 WE Low to CASx Asserted 35 27 ns

114 CASx Asserted to WE Negated 35 27 ns

115 R/W Low to CASx Asserted (Write) 52.5 40 ns

116 CASx Asserted to R/W High (Write) 55 41.25 ns

117 Data-Out, Parity-Out Valid to CASx Asserted 10 7.5 ns

119 CLKO1 High to AMUX Negated 3 16 2 12 ns

120 CLKO1 High to AMUX Asserted 3 16 2 12 ns

121 AMUX High to RASx Asserted 15 11.25 ns

122 RASx Asserted to AMUX Low 15 11.25 ns

123 AMUX Low to CASx Asserted 15 11.25 ns

124 CASx Asserted to AMUX High 55 41.25 ns

125 RAS/CASx Negated to R/W change 0 0 ns

2113B–HIREL–06/05

TS68EN360

Figure 7-21. DRAM: Normal Write Cycle

Note: All timing is shown with respect to 0.8V and 2.0V levels.

R/W

A31-A0

CLKO1

S0 S2 S4

S1 S3 S5

912

WEx

DSACK1,0

D31-D0

RASx

PARITY0-PARITY3

CAS3-CAS0

66A

23 53

(OUTPUT)

(I/O)

(OUTPUT)

108

106

102

105

114

110

113

115 116

117

100

101

107

2113B–HIREL–06/05

TS68EN360

Figure 7-22. DRAM: Refresh Cycle

Note: All timing is shown with respect to 0.8V and 2.0V levels.

Figure 7-23. DRAM: Page Mode – Page-Hit

Note: All timing is shown with respect to 0.8V and 2.0V levels.

(OUTPUT)

A31-A0

CLKO1

RASx

NOT IN PAGE MODE PAGE MODE

RASx

S4 S5 S0 S1

105A

106

12A

CAS3-CAS0

A31-A0

CLKO1

RASx

AMUX

INTERNAL MUX

(OUTPUT)

S0 S2 S4S1 S3 S5

108

100

105

107

106

S0 S4S1 S5 S0 S1

107

105

124

122 123

120

121

119

101

111A

INTERNAL MUX

EXTERNAL MUX

CAS3-CAS0

2113B–HIREL–06/05

TS68EN360

Figure 7-24. DRAM: Page Mode – Page-Miss

Note: All timing is shown with respect to 0.8V and 2.0V levels.

A31-A0

CLKO1

RASn

AMUX

INTERNAL MUX

(OUTPUT)

S0 S2 S4S1 S3 S5 S0 S1 S2 SWS3 SW

105

123

106

120 119 120

12A

CAS3-CAS0

EXTERNAL MUX

122

2113B–HIREL–06/05

TS68EN360

7.9 040 Bus Type Slave Mode Bus Arbitration AC Electrical Specifications

Note: 1. BG remains low until either the SDMA or the IDMA requests the external bus.

Figure 7-25. TS68040 Companion Mode Arbitration

Notes: 1. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.

2. BG always remains asserted until either the SDMA or the IDMA requests the external bus

Table 7-8. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure

7-25)

Number Characteristic

25.0 MHz 33.34 MHz

UnitMin Max Min Max

231Address, Transfer Attributes High Impedance to Clock High 7–6–ns

232(1) Clock High to BG Low – 20 – 15 ns

233 Clock High to BG High 4 20 4 15 ns

234 BB High to Clock High (040 output) 7–6–ns

235 BB High Impedance to Clock High (040 output) 0–0–ns

236 Clock High to BB Low (360 Output) – 20 – 15 ns

237 Clock High to BB High (360 Output) – 20 – 15 ns

238 Clock Low to BB High Impedance (360 output) – 20 – 15 ns

(OUTPUT)

BCLRO

(OUTPUT)

(I/O)

A31-A0

(I/O)

CLKO1

TRANSFER

ATTRIBUTES

(INPUT)

(OUTPUT)

(INPUT)

BCLRI

S0 S1 S2 S3 S4 S5

238

040 BUS MASTER 360 BUS MASTER

237

234

231

233 232

235

140 141

236

2113B–HIREL–06/05

TS68EN360

7.10 040 Bus Type Slave Mode Internal Read/Write/Lack Cycles AC Electrical Specifications

Notes: 1. Transfer attributes signals = SIZx, TTx, TMx, R/W and LOCK.

2. When TS68040 is accessing the internal registers, specification 258 is from clock low not clock high.

3. The clock reference is EXTAL, not CLK01.TS68040 Internal Registers Read Cycles

Table 7-9. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary

(See Figure 7-26 to Figure 7-29)

Number Characteristic

25.0 MHz 33.34 MHz

UnitMin Max Min Max

251(1) Address, Transfer Attributes Valid to Clock Low 15 – 11.25 – ns

252 TS Low to Clock High 7 – 6 – ns

253 Clock High to TS High 5 – 3 – ns

254 Clock high to Address, Transfer Attributes Invalid 0 – 0 – ns

255 Data-In, MBARE Valid to Clock High (040 Write) 0 – 0 – ns

256 Clock High to Data-In, MBARE Hold Time 0–0–ns

257 Clock High to TA, TBI Low (External to External) 4 20 4 15 ns

257 Clock High to TA, TBI Low (External to Internal) 4 23 4 18 ns

258(2)(3) Clock High to TA, TBI High 420415ns

259 TA, TBI High to TA, TBI High Impedance – 15 – 11.25 ns

260 Clock Low to Data-Out Valid (040 Read) – 20 – 15 ns

262 Clock Low to Data-Out Invalid – 20 – 15 ns

263 Clock Low to Data-Out High Impedance – 15 – ns

264 Clock High to AVECO Low –20–15ns

265 Clock Low to AVECO High Impedance – 30 – 23 ns

266 Clock Low to IACK Low – 30 – 23 ns

267 Clock High to IACK High –30–23ns

268 Clock Low to AVEC Low – 30 – 23 ns

2113B–HIREL–06/05

TS68EN360

Figure 7-26. TS68040 Internal Registers Read Cycles

Notes: 1. Three wait states are inserted when reading the SIM, dual-port RAM, and CPM. Four wait states are inserted when reading

the SI RAM. Additional wait states may be inserted when the SHEN1-SHEN0 = 10 and one of the internal masters is

accessing an internal peripheral.

2. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.

Figure 7-27. TS68040 Internal Registers Write Cycles

Notes: 1. Two wait states are inserted when writing. Three wait states are inserted when writing to the dual-port RAM and CPM. Four

wait states are inserted when writing to the SI RAM. Additional wait states may be inserted when the SHEN1-SHEN0 = 10

and one of the internal masters is accessing an internal peripheral.

2. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.

CLKO1

(INPUT)

A31-A0

(INPUT)

TRANSFER

ATTRIBUTES

(INPUT)

C1 C2 CW CW

(OUTPUT)

D31-D0

(040 WRITE)

TBI

(OUTPUT)

3Ð4 CLOCKS

(OUTPUT)

252 253

251

254

263

258

257

CW CW

260

259

(INPUT)

CLKO1

A31-A0

TRANSFER

ATTRIBUTES

(INPUT)

D31-D0

(040 WRITE)

MBARE

TBI

2Ñ4 CLOCKS

(OUTPUT)

(INPUT)

252 253

251

255

254

258

257

C1 C2 CW CW CW C1

(INPUT)

(OUTPUT)

256

259

2113B–HIREL–06/05

TS68EN360

Figure 7-28. TS68040 IACK Cycles (Vector Driven)

Notes: 1. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.

2. Up to two wait states may be inserted for internal peripheral.

Figure 7-29. TS68040 IACK Cycles (No Vector Driven)

Note: TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.

CLKO1

253

A31-A0

(INPUT)

TRANSFER

ATTRIBUTES

C1 C2 CW CW CW

D31-D0

TBI

CW CW

266

IACK7-1

0Ð2 CLOCKS

(OUTPUT)

252

254

263

262

258

257

260

267

251

(INPUT)

(OUTPUT)

259

CLKO1

253

(INPUT)

A31-A0

(INPUT)

TRANSFER

ATTRIBUTES

(INPUT)

C1 C2 CW CW

(INPUT)

TBI

(OUTPUT)

266

IACK7-1

(OUTPUT)

252

254

290

267

251

289

257 250

AVECO

(OUTPUT)

264 265

2113B–HIREL–06/05

TS68EN360

7.11 040 Bus Type SRAM/DRAM Cycles AC Electrical Specifications

Notes: 1. Transfer attributes signals = SIZx, TTx, TMx, R/W and LOCK.

2. TEA/TA should not be asserted on a DRAM burst access, or on the same clock or before RASx/CSx is asserted.

3. The clock reference is EXTAL, not CLK01.

Table 7-10. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary

(See Figure 7-30 to Figure 7-34)

Number Characteristic

25.0 MHz 33.34 MHz

UnitMin Max Min Max

280 Address Valid to BADD2-3 Valid – 20 – 15 ns

280A BADD2-3 Valid to CAS Assertion 15 – 10 – ns

281Address Invalid to BADD2-3 Invalid 0–0–ns

282 Clock High to CSx/RASx Low (TSS40 = 0) 4 16 4 12 ns

283 Clock High to CSx/RASx High (CSNT40 = 0) 4 16 4 12 ns

284 Clock High to BRK Low – 20 – 15 ns

284A Clock Low to BRK Low – 20 – 15 ns

285 Clock high to BRK High – 20 – 15 ns

286 Clock Low to CSx/RASx Low (TSS40 = 1) 4 16 4 12 ns

287 Clock Low to CSx/RASx High (CSNT40 = 1) 4 16 4 12 ns

288(1) Address Transfer Attributes Valid to Clock High (TSS40 = 0) 10 – 10 – ns

289(2) TA Low to Clock High (External Termination) 11 – 9 – ns

290(2) Clock High to TA High (External Termination) – 20 – 15 ns

291 Clock High to OE Low (Read Cycles) – 20 – 15 ns

292 Clock High to OE High (Read Cycles) – 20 – 15 ns

293 Clock High to WE Low (Write Cycles) – 20 – 15 ns

294 Clock High to WE High (Write Cycles) – 20 – 15 ns

295 Clock High to CASx Low 4 13 4 10 ns

295A Clock Low to CASx Low (040 Burst Read only) 4 13 4 10 ns

296(3) Clock High to CASx High 4 13 4 10 ns

297 Clock Low to AMUX Low 3 16 3 12 ns

298 Clock High to AMUX High 3 16 3 12 ns

299 Clock High to BADD2-3 Valid (040 Burst Cycles) 4 20 4 15 ns

300(2) TEA Low to Clock High 11 – – ns

301(2) Clock High to TEA High 2 20 2 15 ns

302Data, Parity Valid to Clock High (Data, Parity Setup) 7–6–ns

303Clock High to Data, Parity Invalid (Data, Parity Hold) 7–5–ns

305 CLKO1 High (After TS Low) to Parity Valid – 20 – 15 ns

306 CLKO1 High (After TA Low) to Parity Hi-Z 4 20 15 ns

2113B–HIREL–06/05

TS68EN360

Figure 7-30. TS68040 SRAM Read/Write Cycles (TSS40 = 0, CSNT40 = 0)

Note: TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.

CLKO1

(OUTPUT)

(INPUT)

A31-A0

(INPUT)

TRANSFER

ATTRIBUTES

(INPUT)

C1 C2

(OUTPUT)

TBI

(OUTPUT)

CSx

(OUTPUT)

BADD3-

BADD2

(OUTPUT)

BKPTO

(OUTPUT)

(READ

CYCLES)

(OUTPUT)

TEA

(INPUT)

288

254

281

253

280

282

258

257

284 285

292

291

293 294

301

252

283

300

259

(WRITE

CYCLES)

2113B–HIREL–06/05

TS68EN360

Figure 7-31. TS68040 SRAM Read/Write Cycles (TSS40 = 1, CSNT40 = 1)

C1 C2

CLKO1

(OUTPUT)

(INPUT)

A31-A0

(INPUT)

TRANSFER

ATTRIBUTES

(INPUT)

BADD3-

BADD2

(OUTPUT)

BKPTO

(OUTPUT)

TEA

(INPUT)

CSn

(OUTPUT)

(INPUT)

251

280

252 253

254

281

289 290

300 301

285

284A

TBI

(OUTPUT)

258

(OUTPUT)

257

286

287

259

2113B–HIREL–06/05

TS68EN360

Figure 7-32. External TS68040 DRAM Cycles Timing Diagram

C1 C2Cw

CLKO1

(OUTPUT)

(WRITE CYCLE

OUTPUT)

CAS3-

CAS0

AMUX

(INPUT)

A31-A0

(INPUT)

TRANSFER

ATTRIBUTES

(INPUT)

RASx

(OUTPUT)

BADD3-

BADD2

(OUTPUT)

TBI

(OUTPUT)

TEA

(INPUT)

288

280

252 253

282

121

298

122

123

295

254

281

283

296

298

294

293

297

259

258

257

300 301

2113B–HIREL–06/05

TS68EN360

Figure 7-33. External TS68040 DRAM Burst Cycles Timing Diagram

C1 C2Cw

CLKO1

(OUTPUT)

(WRITE

CYCLE

OUTPUT)

CAS3-

CAS0

AMUX

(INPUT)

A31-A0

(INPUT)

TRANSFER

ATTRIBUTES

(INPUT)

RASx

(OUTPUT)

BADD3-

BADD2

(OUTPUT)

TBI

(OUTPUT)

299299

288

280

252 253

282

295

296

295

296

297

293

257

258

257

258

295A

2113B–HIREL–06/05

TS68EN360

Figure 7-34. External TS68040 Parity Bit Checking Timing Diagram

(a) Generation Timing Diagram

213

212

D31-D0

(INPUT)

PRTY3-

PRTY0

(OUTPUT)

(b) Checking Timing Diagram

CLKO1

(OUTPUT)

(INPUT)

A31-A0

(INPUT)

TRANSFER

ATTRIBUTES

(INPUT)

C1 C2

(OUTPUT)

BADD3-

BADD2

(OUTPUT)

PERR

(OUTPUT)

CPU Clears PERn Bit

D31-D0,

(INPUT)

302

303

90 91

PRTY3-

PRTY0

(INPUT)

305

306

2113B–HIREL–06/05

TS68EN360

7.12 IDMA AC Electrical Specifications

Notes: 1. These specifications are for asynchronous mode.

2. These specifications are for synchronous mode.

Table 7-11. GND = 0 VDC, TC = -55 to +125°C.The electrical specifications in this document are preliminary

(See Figure 7-35 and Figure 7-36)

Number Characteristic

25.0 MHz 33.34 MHz

UnitMin Max Min Max

1 CLKO1 Low to DACK, DONE Asserted 3 24 3 18 ns

2 CLKO1 Low to DACK, DONE Negated 3 24 3 18 ns

3(1) DREQx Asserted to AS Asserted (for DMA Bus Cycle) 3tcyc + tAIST + tCLSA

4(1) Asynchronous Input Setup Time to CLKO1 Low 12 – 9 – ns

5(1) Asynchronous Input Hold Time from CLKO1 Low 0 – 0 – ns

6AS

to DACK Assertion Skew 0 20 0 15 ns

7DACK

to DONE Assertion Skew -88-66ns

8AS

, DACK, DONE Width Asserted 70 – 52.5 – ns

8A AS, DACK, DONE Width Asserted (Fast Termination Cycle) 28 – 20.5 – ns

10(1) Asynchronous Input Setup Time to CLKO1 Low 5 – 4 – ns

11(1) Asynchronous Input Hold Time from CLKO1 Low 10 – 7.5 – ns

12(2) DREQ Input Setup Time to CLKO1 Low 20 – 15 – ns

13(2) DREQ Input Hold Time from CLKO1 Low 5 – 3.75 – ns

14(2) DONE Input Setup Time to CLKO1 Low 20 – 15 – ns

15(2) DONE Input Hold Time From CLKO1 Low 5 – 3.75 – ns

16(2) DREQ Asserted to AS Asserted 2 – 2 – clk

2113B–HIREL–06/05

TS68EN360

Figure 7-35. IDMA Signal Asynchronous Timing Diagram

Figure 7-36. IDMA Signal Synchronous Timing Diagram

CLKO1

DREQ

DACK

DONE

(OUTPUT)

DONE

(INPUT)

S0 S2 S4 S0 S2 S4

S1 S3 S5 S1 S3 S5

CPU_CYCLE

(IDMA REQUEST) IDMA_CYCLE

(OUTPUT)

(INPUT)

(OUTPUT)

CLKO1

DREQ

12 1

DACK

DONE

(OUTPUT)

DONE

(INPUT)

S0 S2 S4 S0 S2 S4

S1 S3 S5 S1 S3 S5

CPU_CYCLE

(IDMA REQUEST) IDMA_CYCLE

(OUTPUT)

(INPUT)

(OUTPUT)

2113B–HIREL–06/05

TS68EN360

7.13 PIP/PIO Electrical Specifications

Note: 1. t3 = spec. 3 on Table 7-4.

Figure 7-37. PIP Rx (Interlock Mode)

Table 7-12. GND = 0 VDC, TC = -55 to +125°C.The electrical specifications in this document are preliminary

(See Figure 7-37 to Figure 7-41)

Number Characteristic

25.0 MHz 33.34 MHz

UnitMin Max Min Max

21Data-In Setup Time to STBI Low 0–0–ns

22 Data-In Hold Time to STBI High 2.5 – t3 – 2.5 – t3 – clk

23 STBI Pulse Width 1.5 – 1.5 – clk

24 STBO Pulse Width 1 CLKO1 –

5 ns –1 CLKO1 –

5 ns ––v

25Data-Out Setup Time to STBO Low 2–2–clk

26Data-Out Hold Time from STBO High 5–5–clk

27STBI Low to STBO Low (Rx Interlock) –2–2clk

28STBI Low to STBO High (Tx Interlock) 2–2–clk

29 Data-In Setup Time to Clock Low 20 – 15 – ns

30 Data-In Hold Time from Clock Low 10 – 7.5 – ns

Clock High to Data-Out Valid (CPU Writes Data,

Control, or Direction) – 25 – 25 ns

DATA OUT

STRBO

STRBI

(INPUT)

(OUTPUT)

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TS68EN360

Figure 7-38. PIP Tx (Interlock Mode)

Figure 7-39. PIP Tx (Pulse Mode)

DATA IN

STRBI

STRBO

(INPUT)

(OUTPUT)

DATA IN

STBI

STBO

(INPUT)

(OUTPUT)

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TS68EN360

Figure 7-40. PIP Tx (Pulse Mode)

Figure 7-41. Parallel I/O Data-in/Data-out Timing Diagram

7.14 Interrupt Controller AC Electrical Specifications

DATA OUT

STBO

STBI

(INPUT)

(OUTPUT)

DATA OUT

DATA IN

CPU WRITE S4

CLKO1

(OUTPUT)

Table 7-13. GND = 0 VDC, TC = -55 to +125°C.The electrical specifications in this document are preliminary.

(See Figure 7-42 and Figure 7-43)

Number Characteristic

25.0 MHz 33.34 MHz

UnitMin Max Min Max

35 Port C Interrupt Pulse Width Low (Edge Triggered Mode) 70 – 55 – ns

36 Minimum Time Between Active Edges Port C 70 – 55 – clk

37 Clock High to IOUT Valid (Slave Mode) – 20 – 17 ns

38 Clock High to RQOUT Valid (Slave Mode) – 20 – 17 ns

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TS68EN360

Figure 7-42. Interrupts Timing Diagram

Figure 7-43. Slave Mode: Interrupts Timing Diagram

7.15 BAUD Rate Generator AC Electrical Specifications

Figure 7-44. Baud Rate Generator Output Signals

Port C

(INPUT)

IOUT2-

IOUT0

CLKO1

RQOUT

(OUTPUT)

Table 7-14. GND = 0 VDC, TC = -55 to +125

C.The electrical specifications in this document are preliminary (See Figure

7-44)

Number Characteristic

25.0 MHz 33.34 MHz

UnitMin Max Min Max

50 BRGO Rise and Fall Time – 10 – 7.5 ns

51BRGO Duty Cycle 40604060%

52 BRGO Cycle 40 30 ns

51 51

BRGOx

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TS68EN360

7.16 Timer Electrical Specifications

Figure 7-45. CPM General-purpose Timers

Table 7-15. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure

7-45)

Number Characteristic Symbol

25.0 MHz 33.34 MHz

UnitMin Max Min Max

61 TIN/TGATE Rise and Fall Time trf 10 – 10 – ns

62TIN/TGATE Low Time – 1–1–clk

63TIN/TGATE High Time – 2–2–clk

64TIN/TGATE Cycle Time – 3–3–clk

65 CLKO1 High to TOUT Valid tTO 3 25 3 22 ns

CLKO1

(OUTPUT)

TIN/TGATE

(INPUT)

TOUT

(OUTPUT)

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TS68EN360

7.17 SI Electrical Specifications

Notes: 1. The ratio SyncCLK/L1RC LK must be greater than 2.5/1.

2. Where P = 1/CLKO1. Thus for a 25 MHz CLKO1 rate, P = 40 ns.

3. These specs are valid for IDL mode only.

4. The strobes and Txd on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later.

Table 7-16. GND = 0 VDC, TC = -55 to +125°C.The electrical specifications in this document are preliminary

(See Figure 7-46 to Figure 7-50)

Number Characteristic

25.0 MHz 33.34 MHz

UnitMin Max Min Max

70(1)(3) L1RCLK, L1TCLK Frequency (DCS = 0) – 10 – 10 MHz

71(1) L1RCLK, L1TCLK Width Low (DCS = 0) P+10 – P+10 – ns

71A(2) L1RCLK, L1TCLK Width High (DCS = 0) P+10 – P+10 – ns

72 L1TXD, L1ST(1-4), L1RQ, L1CLKO Rise/Fall Time – 15 – 15 ns

73 L1RSYNC, L1TSYNC Valid to L1CLK Edge (SYNC Setup Time) 20 – 20 – ns

74 L1CLK Edge to L1RSYNC, L1TSYNC Invalid (SYNC Hold Time) 35 – 35 – ns

75 L1RSYNC, L1TSYNC Rise/Fall Time – 15 – 15 ns

76 L1RXD Valid to L1CLK Edge (L1RXD Setup Time) 42 – 42 – ns

77 L1CLK Edge to L1RXD Invalid (L1RXD Hold Time) 35 – 35 – ns

78 L1CLK Edge to L1ST(1-4) Valid 10 45 10 45 ns

78A(4) L1SYNC Valid to L1ST(1-4) Valid 10 45 10 45 ns

79 L1CLK Edge to L1ST(1-4) Invalid 10 45 10 45 ns

80 L1CLK Edge to L1TXD Valid 10 65 10 65 ns

80A(4) L1TSYNC Valid to L1TXD Valid 10651065 ns

81 L1CLK Edge to L1TXD High Impedance 0 42 0 42 ns

82 L1RCLK, L1TCLK Frequency (DSC = 1) – 12.5 – 16 MHz

83 L1RCLK, L1TCLK Width Low (DSC = 1) P+10 – P+10 – ns

83A(2) L1RCLK, L1TCLK Width High (DSC = 1) P+10 – P+10 – ns

84 L1CLK Edge to L1CLKO Valid (DSC = 1) – 30 – 30 ns

85(3) L1RQ Valid Before Falling Edge of L1TSYNC 1–1–L1TCLK

86(3) L1GR Setup Time 42 – 42 – ns

87(3) L1RG Hold Time 42 – 42 – ns

88 L1CLK Edge to L1SYNC Valid (FSD = 00, CNT = 0000, BYT = 0,

DSC = 0) –0–0ns

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TS68EN360

Figure 7-46. SI Receive Timing with Normal Clocking (DSC = 0)

L1RSYNC

(INPUT)

L1ST (4-1)

(OUTPUT)

RFCD = 1

73 74

L1RXD

(INPUT)

BIT0

L1RCLK

(FE =1,CE = 1)

(INPUT)

L1RCLK

(FE = 0,CE = 0)

(INPUT)

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TS68EN360

Figure 7-47. SI Receive Timing with Double Speed Clocking (DSC = 1)

L1RSYNC

(INPUT)

L1ST (4-1)

(OUTPUT)

RFCD = 1

73 74

L1RXD

(INPUT)

BIT0

L1RCLK

(FE = 1,

CE = 1)

(INPUT)

L1RCLK

(FE = 0,

CE = 0)

(INPUT) 82

72 83A

L1CLKO

(OUTPUT)

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TS68EN360

Figure 7-48. SI Transmit Timing with Normal Clocking (DSC = 0)

L1TXD

(INPUT) BIT0

L1TSYNC

(OUTPUT)

L1ST (4-1)

(OUTPUT)

TFCD = 0

73 74

L1TCLK

(FE = 1,

CE = 1)

(INPUT)

L1TCLK

(FE = 0,

CE = 0)

(INPUT)

80A

78A

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TS68EN360

Figure 7-49. SI Transmit Timing with Double Speed Clocking (DSC = 1)

Figure 7-50. IDL Timing SI Transmit Timing with Double Speed Clocking (DSC = 1)

L1TXD

(OUTPUT) BIT0

L1TSYNC

(INPUT)

L1ST (1-4)

(OUTPUT)

TFCD = 0

73 74

80A

78A

L1RCLK

(FE = 1,

CE = 1)

(INPUT)

L1RCLK

(FE = 0,

CE = 0)

(INPUT)

72 83A

L1CLKO

(OUTPUT)

1 2 3 4 5 6 7 8 9 10111213141516171819 20

L1RSYNC

(INPUT)

L1RCLK

(INPUT)

L1TXD

(OUTPUT)

L1RXD

(INPUT)

L1ST (4-1)

(OUTPUT)

L1RQ

(OUTPUT)

L1GR

(INPUT)

77 72

B17 B16 B15 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M

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TS68EN360

7.18 SCC in NMSI Mode-external Clock Electrical Specifications

Notes: 1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2.25/1.

2. Also applies to CD and CTS hold time when they are used as external sync signals.

7.19 SCC in NMSI Mode-internal Clock Electrical Specifications

Notes: 1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 3/1.

2. Also applies to CD and CTS hold time when they are used as external sync signals.

Table 7-17. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary

(See Figure 7-51 to Figure 7-53)

Number Characteristic

25.0 MHz 33.34 MHz

UnitMin Max Min Max

100(1) RCLK1 and TCLK1 Width High CLKO1 – CLKO1 –

101 RCLK1 and TCLK1 Width Low CLKO1 + 5 ns – CLKO1 + 5 ns –

102 RCLK1 and TCLK1 Rise/Fall Time – 15 – 15 ns

103 TXD1 Active Delay (From TCLK1 Falling Edge) 0 50 0 50 ns

104 RTS1 Active/Inactive Delay (From TCLK1 Falling Edge) 0 50 0 50 ns

105 CTS1 Setup Time to TCLK1 Rising Edge 40 – 40 – ns

106 RXD1 Setup Time to RCLK1 Rising Edge 40 – 40 – ns

107(2) RXD1 Hold Time from RCLK1 Rising Edge 0 – 0 – ns

108 CD1 Setup Time to RCLK1 Rising Edge 40 – 40 – ns

Table 7-18. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary

(See Figure 7-51 to Figure 7-53)

Number Characteristic

25.0 MHz 33.34 MHz

UnitMin Max Min Max

100(1) RCLK1 and TCLK1 Frequency 0 8.3 0 11 MHz

102RCLK1 and TCLK1 Rise/Fall Time ––––ns

103 TXD1 Active Delay (From TCLK1 Falling Edge) 0 30 0 30 ns

104 RTS1 Active/Inactive Delay (From TCLK1 Falling Edge) 0 30 40 – ns

105 CTS1 Setup Time to TCLK1 Rising Edge 40 – 40 – ns

106 RXD1 Setup Time to RCLK1 Rising Edge 40 – 0 – ns

107(2) RXD1 Hold Time from RCLK1 Rising Edge 0 – 40 – ns

108 CD1 Setup Time to RCLK1 Rising Edge 40 – 0 30 ns

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TS68EN360

Figure 7-51. SCC NMSI Receive

Figure 7-52. SCC NMSI Transmit

RXD1

(INPUT)

RCLK1

108

107

106

102 102

100

101

CD1

(INPUT)

107

CD1

(SYNC-

INPUT)

TXD1

(OUTPUT

)

TCLK1

102

CTS1

(INPUT)

RTS1

(OUTPUT

)

104

CTS1

(SYNC

INPUT)

102

101

100

103

104

105

107

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TS68EN360

Figure 7-53. HDLC BUS Timing

TXD1

(

OUTPUT)

TCLK1

104

100

101

102

105

RTS1

(

OUTPUT)

104

CTS1

(ECHO

INPUT)

103

107

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TS68EN360

7.20 Ethernet Electrical Specifications

Notes: 1. SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2.25/1

2. SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.

Figure 7-54. Ethernet Collision Timing

Table 7-19. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary

(See Figure 7-54 to Figure 7-59)

Number Characteristic

25.0 MHz 33.34 MHz

UnitMin Max Min Max

120 CLSN Width High 40 – 40 – ns

121 RCLK1 Rise/Fall Time – 15 – 15 ns

122 RCLK1 Width Low CLKO1 +

5 ns –CLKO1 +

5 ns –

123(1) RCLK1 Width High CLKO1 – CLKO1 –

124 RXD1 Setup Time 20 – 20 – ns

125RXD1 Hold Time 5–5–ns

126 RENA Active Delay (from RCLK1 rising edge of the last

data bit) 10 – 10 – ns

127 RENA Width Low 100 – 100 – ns

128 TCLK1 Rise/Fall Time – 15 – 15 ns

129 TCLK1 Width Low CLKO1 +

5 ns –CLKO1 +

5 ns –

130(1) TCLK1 Width High CLKO1 – CLKO1 –

131 TXD1 Active Delay (from TCLK1 rising edge) 10 50 10 50 ns

132 TXD1 Inactive Delay (from TCLK1 rising edge) 10 50 10 50 ns

133 TENA Active Delay (from TCLK1 rising edge) 10 50 10 50 ns

134 TENA Inactive Delay (from TCLK1 rising edge) 10 50 10 50 ns

135 RSTRT Active Delay (from TCLK1 falling edge) 10 50 10 50 ns

136 RSTRT Inactive Delay (from TCLK1 falling edge) 10 50 10 50 ns

137RRJCT Width Low 1–1–CLKO1

138(2) CLKO1 Low to SDACK Asserted – 20 – 20 ns

139(2) CLKO1 Low to SDACK Negated – 20 – 20 ns

CLSN (CTS1)

(INPUT)

120

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TS68EN360

Figure 7-55. Ethernet Receive Timing

Figure 7-56. Ethernet Transmit Timing

Notes: 1. Transmit clock invert (TCI) bit in GSMR is set.

2. If RENA is deasserted before TENA, or RENA is not asserted at all during transit, then CSL bit is set in the buffer descriptor

at the end of frame transmission.

RXD1

(INPUT)

RCLK1

125

124

121

123

122

RENA (CD1)

(INPUT)

LAST BIT

127

126

121

TXD1

(OUTPUT)

TCLK1

(NOTE 1)

132

131

128 128

130

129

TENA (RTS1)

(OUTPUT)

RENA (CD1)

(INPUT)

(NOTE 2)

133

134

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TS68EN360

Figure 7-57. CAM Interface Receive Start Timing

Note: Valid for the ethernet protocol only.

Figure 7-58. CAM Interface Reject Timing

Note: Valid for the ethernet protocol only.

Figure 7-59. SDACK Timing Diagram

Note: SDACKx is asserted when the SDMA writes the received Ethernet frame into memory.

RXD1

(INPUT)

RCLK1

RSTRT

(OUTPUT)

011

START FRAME DELIMITER

Bit # 1 Bit # 2

135 136

RRJCT

(INPUT)

137

CLKO1

138

SDACKx

S0 S2 S4S1 S3 S5

SDMA CYCLE

(OUTPUT)

139

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7.21 SMC Transparent Mode Electrical Specifications

Note: 1. The ratio SyncCLK/SMCLK must be greater or equal to 2/1. SMC Transparent.

Figure 7-60. SMC Transparent

Note: This delay is equal to an integer number of “Character length” clocks

Table 7-20. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure

7-60)

Number Characteristic

25.0 MHz 33.34 MHz

UnitMin Max Min Max

150(1) SMCLK Clock Period 100 – 100 – ns

151 SMCLK Width Low 50 – 50 – ns

151A SMCLK Width High 50 – 50 – ns

152 SMCLK Rise/Fall Time – 15 – 15 ns

153 SMTXD Active Delay (from SMCLK falling edge) 10 50 10 50 ns

154 SMRXD/SYNC1 Setup Time 20 – 20 – ns

155SMRXD/SYNC1 Hold Time 5–5–ns

RXD1

(INPUT)

155

154

TXD1

(OUTPUT)

153

150

151

152

SYNC1

154

155

Note 1

SMCLK

151A

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7.22 SPI Master Electrical Specifications

Figure 7-61. SPI Master (CP = 0)

Table 7-21. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary

(See Figure 7-61 and Figure 7-62)

Number Characteristic

25.0 MHz 33.34 MHz

UnitMin Max Min Max

160 Master Cycle Time 4 1024 4 1024 tcyc

161 Master Clock (SPICLK) High or Low Time 2 512 2 512 tcyc

162 Master Data Setup Time (Inputs) 50 – 50 – ns

163Master Data Hold Time (Inputs) 0–0–ns

164 Master Data Valid (after SPICLK Edge) – 20 – 20 ns

165Master Data Hold Time (Outputs) 0–0–ns

166 Rise Time: Output 15 15 ns

167 Fall Time: Output 15 15 ns

MSB IN

MSB OUT

MSB OUT DATA LSB OUT "1"

"1"

DATA LSB IN

MSB IN

SPICLK

CI=0

OUTPUT

SPICLK

CI=1

OUTPUT

SPIMISO

INPUT

SPIMOSI

OUTPUT

167

166

161 160

161 166

165

167 166

167

163

162

164

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TS68EN360

Figure 7-62. SPI Master (CP = 1)

7.23 SPI Slave Electrical Specifications

MSB

MSBMSB OUT DATA LSB OUT "1"

"1"

DATA LSB IN

MSB IN

SPICLK

CI=0

OUTPUT

SPICLK

CI=1

OUTPUT

SPIMISO

INPUT

SPIMOSI

OUTPUT

167

166

161 160

161 166

162

160

163

164

165

167 166

Table 7-22. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary

(See Figure 7-63 and Figure 7-64)

Number Characteristic

25.0 MHz 33.34 MHz

UnitMin Max Min Max

170Slave Cycle Time 2–2–tcyc

171 Slave Enable Lead Time 15 15 ns

172 Slave Enable Lag Time 15 15 ns

173Slave Clock (SPICLK) High or Low Time 1–1–tcyc

174 Slave Sequential Transfer Delay (Does Not Require Deselect) 1 1 tcyc

175 Slave Data Setup Time (Inputs) 20 – 20 – ns

176 Slave Data Hold Time (Inputs) 20 – 20 – ns

177 Slave Access Time 50 50 ns

178 Slave SPIMISO Disable Time 50 50 ns

179 Slave Data Valid (after SPICLK Edge) – 50 – 50 ns

180Slave Data Hold Time (Outputs) 0–0–ns

181 Rise Time: Input 15 15 ns

182 Fall Time: Input 15 15 ns

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TS68EN360

Figure 7-63. SPI Slave (CP = 0)

Figure 7-64. SPI Slave (CP = 1)

DATA LSB OUT UNDEF. MSB OUT

MSB IN

MSB OUT

MSB IN DATA LSB IN

SPISEL

INPUT

SPICLK

CI=0

INPUT

SPICLK

CI=1

INPUT

SPIMISO

OUTPUT

SPIMOSI

INPUT

172 171

174

182

181

173 170

173 181 182 180 178

179

182181

180

176

177

175

MSB OUT DATA SLAVE

LSB OUT UNDEF.UNDEF.

MSB IN DATA LSB IN

SPISEL

INPUT

SPICLK

CI=0

INPUT

SPICLK

CI=1

INPUT

SPIMISO

OUTPUT

SPIMOSI

INPUT

174

182

181

173

182

181

178

179

181

179

177

175

170 173

171 172

180

176

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TS68EN360

7.24 JTAG Electrical Specifications

Figure 7-65. Test Clock Input Timing Diagram

Figure 7-66. TRST Timing Diagram

Table 7-23. GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary

(See Figure 7-65 and Figure 7-68)

Number Characteristic

25.0 MHz 33.34 MHz

UnitMin Max Min Max

TCK Frequency of Operation 0 25 0 25 MHz

1 TCK Cycle Time in Crystal Mode 40 – 40 – ns

2 TCK Clock Pulse Width Measured at 1.5V 18 – 18 – ns

3TCK rise and Fall Times 0303ns

6 Boundary Scan Input Data Setup Time 10 – 10 – ns

7 Boundary Scan Input Data Hold Time 18 – 18 – ns

8 TCK Low to Output Data Valid 0 30 0 30 ns

9 TCK Low to Output High Impedance 0 40 0 40 ns

10 TMS, TDI Data Setup Time 10 – 10 – ns

11 TMS, TDI Data Hold Time 10 – 10 – ns

12 TCK Low to TDO Data Valid 0 20 0 20 ns

13 TCK Low to TDO High Impedance 0 20 0 20 ns

14 TRST Assert Time 100 – 100 – ns

15 TRST Setup Time to TCK Low 40–40–ns

TCK

VM VM

(INPUT)

TCK

TRST

(INPUT)

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TS68EN360

Figure 7-67. Boundary Scan (JTAG) Timing Diagram

Figure 7-68. Test Access Port Timing Diagram

DATA

OUTPUT

DATA

INPUTS

OUTPUT DATA VALID

DATA

OUTPUT

OUTPUT DATA VALID

DATA

OUTPUT

INPUT DATA VALID

(INPUT)

TDO

TDI

TMS

OUTPUT DATA VALID

TDO OUTPUT DATA VALID

TDO

INPUT DATA VALID

(INPUT)

(OUTPUT

)

(OUTPUT

)

(OUTPUT

)

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TS68EN360

8. Functional Description

8.1 CPU32+ Core

The CPU32+ core is a CPU32 that has been modified to connect directly to the 32-bit IMB and

apply the larger bus width. Although the original CPU32 core had a 32-bit internal data path and

32-bit arithmetic hardware, its interface to the IMB was 16 bits. The CPU32+ core can operate

on 32-bit external operands with one bus cycle. This allows the CPU32+ core to fetch a long-

word instruction in one bus cycle an to fetch two word-length instructions in one bus cycle, filling

the internal instruction queue more quickly. The CPU32+ core can also read and write 32-bit of

data in one bus cycle.

Although the CPU32+ instruction timings are improved, its instruction set is identical to that of

the CPU32. It will also execute the entire 68000 instruction set. It contains the same background

debug mode (BDM) features as the CPU32. No new compilers, assemblers or other software

support tools need be implemented for the CPU32+; standard CPU32 tools can be used.

The CPU32+ delivers approximately 4.5 MIPS at 25 MHz, based on the standard (accepted)

assumption that a 10-MHz 68000 delivers 1 VAX MIPS. If an application requires more perfor-

mance, the CPU32+ can be disabled, allowing the rest of the QUICC to operate as an intelligent

peripheral to a faster processor. The QUICC provides a special mode called TS68040 compan-

ion mode to allow it to conveniently interface to members of the TS68040 family. This two-chip

solution provides a 22-MIPS performance at 25 MHz.

The CPU32+ also offers automatic byte alignment features that are not offered on the CPU32.

These features allow 16- or 32-bit data to be read or written at an odd address. The CPU32+

automatically performs the number of bus cycles required.

8.2 System Integration Module (SIM60)

The SIM60 integrates general-purpose features that would be useful in almost any 32-bit pro-

cessor system. The term “SIM60” is derived from the QUICC part number, TS68EN360. The

SIM60 is an enhanced version of the SIM40 that exists on the TS68332 device.

First, new features, such as a DRAM controller and breakpoint logic, have been added. Second,

the SIM40 was modified to support a 32-bit IMB as well as a 32-bit external system bus. Third,

new configurations, such as slave mode and internal accesses by an external master, are

supported.

Although the QUICC is always a 32-bit device internally, it may be configured to operate with a

16-bit data bus. Regardless of the choice of the system bus size, dynamic bus sizing is sup-

ported. Bus sizing allows 8-16-, and 32-bit peripherals and memory to exist in the 32-bit system

bus mode and 8- and 16-bit peripherals and memory to exist in the 16-bit system bus mode.

8.3 Communications Processor Module (CPM)

The CPM contains features that allow the QUICC to excel in communications and control appli-

cations. These features may be divided into three sub-groups:

• Communications Processor (CP)

• Two IDMA Controllers

• Four General-purpose Timers

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TS68EN360

The CP provides the communication features of the QUICC. Included are a RISC processor,

four SCCs, two SMCs, one SPI, 2.5K bytes of dual-port RAM, an interrupt controller, a time slot

assigner, three parallel ports, a parallel interface port, four independent baud rate generators,

and fourteen serial DMA channels to support the SCCs, SMCs, and SPI.

The IDMAs provide two channels of general-purpose DMA capability. They offer high-speed

transfers, 32-bit data movement, buffer chaining, and independent request and acknowledge

logic. The RISC controller may access the IDMA registers directly in the buffer chaining modes.

The QUICC IDMAs are similar to, yet enhancements of, the one IDMA channel found on the

TS68302.

The four general-purpose timers on the QUICC are functionally similar to the two general-pur-

pose timers found on the TS68302. However, they offer some minor enhancements, such as the

internal cascading of two timers to form a 32-bit timer. The QUICC also contains a periodic inter-

val timer in the SIM60, bringing the total to five on-chip timers.

8.4 Ethernet on QUICC

The Ethernet protocol is available only on the Ethernet version of the QUICC called the

TS68EN360. The non-Ethernet version of the QUICC is the MC68360. The term “QUICC” is the

overall device name that denotes all versions of the device.

The TS68EN360 is a superset of the MC68360, having the additional option allowing Ethernet

operation on any of the four SCCs. Due to performance reason not ass SCCs can be configured

as Ethernet controller at the same time. The TS68EN360 is not restricted only to Ethernet oper-

ation. HDLC, UART, and other protocols may be used to allow dynamic switching between

protocols. See Appendix A Serial Performance for available SCC performance.

When the MODE bits of the SCC GSMR select the Ethernet protocol, then that SCC performs

the full set of IEEE 802.3/Ethernet CSMA/CD media access control and channel interface func-

tions (see Figure 8-1)

Figure 8-1. Ethernet Block Diagram

IMB

CONTROL

REGISTERS

SLOT TIME

AND DEFER

COUNTER

CLOCK

GENERATOR

PERIPHERAL BUS

RECEIVER

CONTROL

UNIT

RECEIVE

DATA

FIFO

TRANSMITTER

CONTROL

UNIT

TRANSMIT

DATA

FIFO

SHIFTER SHIFTER TXD

RXD

RRJCT

RSTRT

CD = RENA CD = RENA

CTS = CLSN CTS = CLSN

RTS = TENA

INTERNAL CLOCKS

RX CLOCK

TX CLOCK

RANDOM NO.

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TS68EN360

8.5 Upgrading Designs from the TS68302

Since the QUICC is a next-generation TS68302, many designers currently using the TS68302

may wish to use the QUICC in a follow-on design. The following paragraphs briefly discuss this

endeavor in terms of architectural approach, hardware issues, and software issues.

8.5.1 Architectural Approach

The QUICC is the logical extension of the TS86302, but the overall architecture and philosophy

of the TS86302 design remains intact in the QUICC. The QUICC keeps the best features of the

TS86302, while making the changes required to provide for the increased flexibility, integration,

and performance requested by customers. Because the CPM is probably the most difficult mod-

ule to learn, anyone who has used the TS86302 can easily become familiar with the QUICC

since the CPM architectural approach remains intact.

The most significant architectural change made on the QUICC was the translation of the design

into the standard 68300 family IMB architecture, resulting in a faster CPU and different system

integration features.

Although the features of the SIM60 do not exactly correspond to those of the TS86302 SIM, they

are very similar.

Because of the similarity of the QUICC SIM60 and CPU to other members of the 68300 family,

such as the TS68332, previous users of these devices will be comfortable with these same fea-

tures on the QUICC.

8.5.2 Hardware Compatibility Issues

The following list summarizes the hardware differences between the TS86302 and the QUICC:

• Pinout – The pinout is not the same. The QUICC has 240 pins; the TS86302 has 132 pins

• Package – Both devices offer PGA and PQFP packages. However, the QUICC QFP package

has a 20-mil pitch; whereas, the TS86302 QFP package has a 25-mil pitch

• System Bus – The system bus signals now look like those of the TS68020 as opposed to

those of the 68000. It is still possible to interface 68000 peripherals to the QUICC, utilizing the

same techniques used to interface them to a TS68020

• System Bus in Slave Mode – A number of QUICC pins take on new functionality in slave

mode to support an external TS68EC040. On the TS68302, the pin names generally

remained the same in slave mode

• Peripheral Timing – The external timings of the peripherals (SCCs, timers, etc.) are very

similar (if not identical) to corresponding peripherals on the TS68302

• Pin Assignments – The assignment of peripheral functions to I/O pins is different in several

ways. First, the QUICC contains more general-purpose parallel I/O pins than the TS68302.

However, the QUICC offers many more functions than even a 240-pin package would

normally allow, resulting in more multifunctional pins than the TS68302

8.5.3 Software Compatibility Issues

The following list summarizes the major software differences between the TS68302 and the

QUICC:

• Since the CPU32+ is a superset of the 68000 instruction set, all previously written code will

run. However, if such code is accessing the TS68302 peripherals, it will require some

modification

2113B–HIREL–06/05

TS68EN360

• The QUICC contains an 8-Kbyte block of memory as opposed to a 4-Kbyte block on the

TS68302. The register addresses within that memory map are different

• The code used to initialize the system integration features of the TS68302 has to be modified

to write the corresponding features on the QUICC SIM60

• As much as possible, QUICC CPM features were made identical to those of the TS68302 CP.

The most important benefit is that the code flow (if not the code itself) will port easily from the

TS68302 to the QUICC. The nuances learned from the TS68302 will still be useful in the

QUICC

• Although the registers used to initialize the QUICC CPM are new (for example, the SCM on

the TS68302 is replaced with the GSMR and PSMR on the QUICC), most registers retain

their original purpose such as the SCC event, SCC mask, SCC status, and command

registers. The parameter RAM of the SCCs is very similar, and most parameter RAM register

names and usage are retained. More importantly, the basic structure of a buffer descriptor

(BD) on the QUICC is identical to that of the TS68302, except for a few new bit functions that

were added. (In a few cases, a bit in a BD status word had to be shifted)

• When porting code from the TS68302 CP to the QUICC CPM, the software writer may find

that the QUICC has new options to simplify what used to be a more code-intensive process.

For specific examples, see the INIT TX AND RX PARAMETERS, GRACEFUL STOP

TRANSMIT, and CLOSE BD commands

9. Preparation for Delivery

9.1 Packaging

Microcircuits are prepared for delivery in accordance with MIL-PRF-38535 or Atmel standards.

9.2 Certificate of Compliance

Atmel offers a certificate of compliances with each shipment of parts, affirming the products are

in compliance either with MIL-STD-883 or Atmel standard and guarantying the parameters not

tested at temperature extremes for the entire temperature range.

10. Handling

MOS devices must be handled with certain precautions to avoid damage due to accumulation of

static charge. Input protection devices have been designed in the chip to minimize the effect of

this static buildup. However, the following handling practices are recommended:

a) Devices should be handled on benches with conductive and grounded surfaces

b) Ground test equipment, tools and operator

c) Do not handle devices by the leads

d) Store devices in conductive foam or carriers

e) Avoid use of plastic, rubber, or silk in MOS areas

f) Maintain relative humidity above 50% if practical

2113B–HIREL–06/05

TS68EN360

11. Package Mechanical Data

11.1 241-pin – PGA

(top view)

Dim

Inches Millimeters

Min Max Min Max

A 1.840 1.880 46.74 47.75

C 0.110 0.140 2.79 3.56

D 0.016 0.020 0.41 0.51

E 0.045 0.055 1.143 1.4

F 0.045 0.055 1.143 1.4

G 0.100 BASIC 2.54 BASIC

K 0.150 0.170 3.81 4.32

118

(BOTTOM VIEW)

2113B–HIREL–06/05

TS68EN360

11.2 240-pin – CERQUAD

240

181

120

180 121

1 60

0.25 (0.010) T L–N M MH S

L–N S

0.20 (0.008) M

0.10 (0.004)

–H– DATUM

PLANE

SEATING

PLANE

VIEW AC

4 PLACES

θ2

VIEW AE

–H– DATUM

PLANE

VIEW AE

–T–

4 x 60 TIPS

–L–

–M– A

–N–

–X–

X = L, M or N

VIEW AC

T M S

L–N S

0.08 (0.003) M

SECTION AD

240 PLACES

DIM

MILLIMETERS INCHES

MINMAXMINMAX

A 30.86 31.75 1.215 1.250

B 30.86 31.75 1.215 1.250

C 3.67 4.15 0.144 0.163

D 0.20 0.30 0.0079 0.012

E 3.10 3.90 0.122 0.154

F 0.19 0.25 0.0075 0.010

G 0.50 BSC 0.019 BSC

J 0.13 0.175 0.005 0.007

K 0.45 0.55 0.018 0.021

P 0.25 BSC 0.010 BSC

R 0.15 BSC 0.006 BSC

S 34.41 34.75 1.355 1.37

U 17.30 BSC 0.681 BSC

V 34.41 34.75 1.355 1.37

W 0.25 0.75 0.0035 0.0232

Y 17.30 BSC 0.681 BSC

Z 0.12 0.13 0.005 0.005

AA 1.80 REF 0.071 REF

AB 0.95 REF 0.037 REF

θ21°7°1°7°

Notes: 1. Dimensioning and tolerancing per ASME Y 14.5, 1994.

2. Controlling dimension: millimeter.

3. Datum plane -H- is located at bottom of lead and is coincident with the

lead where the lead exits the ceramic body at the bottom of the parting

line.

4. Datums -L-, -M- and -N- to be determined at datum plane -H-.

5. Dimensions S and V to be determined at seating plane -T-.

6. Dimensions A and B define maximum ceramic body dimensions

including glass protrusion and top and bottom mismatch.

2113B–HIREL–06/05

TS68EN360

12. Ordering Information

12.1 Hi-REL Product

Commercial Atmel

Part-Number Norms Package

Temperature

Range Tc (°C)

Frequency

(MHz) DSCC

TS68EN360MRB/Q25L MIL-PRF-38535 PGA 241 Gold -55/+125 25 5962-9760701MXC

TS68EN360MRB/Q33L MIL-PRF-38535 PGA 241 Gold -55/+125 33 5962-9760702MXC

TS68EN360MR1B/Q25L MIL-PRF-38535 PGA 241 Tinned -55/+125 25 5962-9760701MXA

TS68EN360MR1B/Q33L MIL-PRF-38535 PGA 241 Tinned -55/+125 33 5962-9760702MXA

TS68EN360MAB/Q25L MIL-PRF-38535 CERQUAD 240 -55/+125 25 5962-9760701MYA

TS68EN360MAB/Q33L MIL-PRF-38535 CERQUAD 240 -55/+125 33 5962-9760702MYA

12.2 Standard Product

Commercial Atmel

Part-Number Norms Package

Temperature

Range Tc (°C)

Frequency

(MHz) Drawing Number

TS68EN360VR25L Atmel Standard PGA 241 -40/+85 25 Internal

TS68EN360MR25L Atmel Standard PGA 241 -55/+125 25 Internal

TS68EN360VA25L Atmel Standard CERQUAD 240 -40/+85 25 Internal

TS68EN360MA25L Atmel Standard CERQUAD 240 -55/+125 25 Internal

TS68EN360VR33L Atmel Standard PGA 241 -40/+85 33 Internal

TS68EN360MR33L Atmel Standard PGA 241 -55/+125 33 Internal

TS68EN360VA33L Atmel Standard CERQUAD 240 -40/+85 33 Internal

TS68EN360MA33L Atmel Standard CERQUAD 240 -55/+125 33 Internal

Operating frequency :

Generic

TS68EN360 M R B/Q

M : -55˚C, +125˚C

V : -40˚C, +110˚C

25 L

Temperature range : (TC )

R = Pin grid array 241 (gold)

A = CERQUAD 240 (tin)

Package :

25 : 25 MHz

33 : 33 MHz

Revision level

___ = Standard

B/Q = MIL-PRF-38535

Screening :

_ = Gold (for PGA)

_ = Hot solder dip (for CERQUAD)

1 = Hot solder dip (for PGA - On request)

Hirel lead finish :

(TSX)

Prototype version

2113B–HIREL–06/05

TS68EN360

13. Document Revision History

Table 13-1 provides a revision history for this hardware specification.

Table 13-1. Revision History

Revision Number Date Substantive Change(s)

2113B 04/2005 Cerquad Package Change. See page 77

2113A 03/2002 Initial Revision

2113B–HIREL–06/05

TS68EN360

Table of Contents

Features .................................................................................................... 1

Description ............................................................................................... 1

Screening/Quality 1

1 Introduction .............................................................................................. 2

1.1 QUICC Architecture Overview ..................................................................................2

2 Pin Assignments ...................................................................................... 3

3 Signal Description ................................................................................... 5

3.1 Functional Signal Group ...........................................................................................5

3.2 Signal Index ..............................................................................................................6

4 Detailed Specification ............................................................................ 11

5 Applicable Documents .......................................................................... 11

5.1 Design and Construction ........................................................................................11

5.2 Absolute Maximum Ratings ....................................................................................11

5.3 Power Considerations ............................................................................................12

5.4 Mechanical and Environment .................................................................................13

5.5 Marking ...................................................................................................................13

6 Quality Conformance Inspection .......................................................... 13

6.1 DESC/MIL-STD-883 ...............................................................................................13

7 Electrical Characteristics ...................................................................... 13

7.1 General Requirements ...........................................................................................13

7.2 Static Characteristics ..............................................................................................14

7.3 Dynamic Characteristics .........................................................................................14

7.4 AC Power Dissipation .............................................................................................16

7.5 AC Electrical Specifications Control Timing ...........................................................17

7.6 External Capacitor For PLL ....................................................................................18

7.7 Bus Operation AC Timing Specifications ................................................................19

7.8 Bus Operation – DRAM Accesses AC Timing Specification ..................................35

7.9 040 Bus Type Slave Mode Bus Arbitration AC Electrical Specifications ................39

7.10 040 Bus Type Slave Mode Internal Read/Write/Lack Cycles AC Electrical

Specifications ................................................................................................40

7.11 040 Bus Type SRAM/DRAM Cycles AC Electrical Specifications ........................43

7.12 IDMA AC Electrical Specifications ........................................................................49

2113B–HIREL–06/05

TS68EN360

7.13 PIP/PIO Electrical Specifications ..........................................................................51

7.14 Interrupt Controller AC Electrical Specifications ...................................................53

7.15 BAUD Rate Generator AC Electrical Specifications .............................................54

7.16 Timer Electrical Specifications ..............................................................................55

7.17 SI Electrical Specifications ...................................................................................56

7.18 SCC in NMSI Mode-external Clock Electrical Specifications ...............................61

7.19 SCC in NMSI Mode-internal Clock Electrical Specifications ................................61

7.20 Ethernet Electrical Specifications .........................................................................64

7.21 SMC Transparent Mode Electrical Specifications ................................................67

7.22 SPI Master Electrical Specifications .....................................................................68

7.23 SPI Slave Electrical Specifications .......................................................................69

7.24 JTAG Electrical Specifications ............................................................................71

8 Functional Description .......................................................................... 73

8.1 CPU32+ Core .........................................................................................................73

8.2 System Integration Module (SIM60) .......................................................................73

8.3 Communications Processor Module (CPM) ...........................................................73

8.4 Ethernet on QUICC ................................................................................................74

8.5 Upgrading Designs from the TS68302 ...................................................................75

9 Preparation for Delivery ........................................................................ 76

9.1 Packaging ...............................................................................................................76

9.2 Certificate of Compliance .......................................................................................76

10 Handling .................................................................................................. 76

11 Package Mechanical Data ..................................................................... 77

11.1 241-pin – PGA .....................................................................................................77

11.2 240-pin – CERQUAD ...........................................................................................78

12 Ordering Information ............................................................................. 79

12.1 Hi-REL Product ....................................................................................................79

12.2 Standard Product .................................................................................................79

13 Document Revision History .................................................................. 80

Printed on recycled paper.

2113B–HIREL–06/05 xM

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