NT5DS8M16HS-6KI - Nanya Technology Corporation

NT5DS8M16HS

128Mb DDR SDRAM

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Feature

CAS Latency Frequency

Speed Sorts

DDR-333

-6K/-6KI

DDR400

-5T/-5TI Units

CL-tRCD-tRP 2.5-3-3 3-3-3 tCK

CL2 266 266

CL2.5 333 333

Speed

CL3 333 400

Mbps

z Power Supply Voltage:

VDD=VDDQ=2.5V±0.2V (DDR-333)

VDD=VDDQ=2.6V±0.1V (DDR-400)

z 4 internal memory banks for concurrent operation.

z CAS Latency: 2, 2.5 and 3

z Double Data Rate Architecture

z Bidirectional data strobe (DQS) is transmitted and

received with data, to be used in capturing data at

the receiver.

z Industrial grade device support -40℃~95℃

Operating Temperature (-6KI/5TI)

z 2KB page size for all configurations.

z DQS is edge-aligned with data for reads and is

center-aligned with data for WRITEs

z Differential clock inputs (CK and CK)

z Data mask (DM) for write data

z DLL aligns DQ and DQS transition with CK

transitions.

z Commands entered on each positive CK edge;

data and data mask referenced to both edges of

DQS

z Burst Lengths: 2, 4 or 8

z Auto Precharge option for each burst access

z Auto-Refresh and Self-Refresh Mode

z 15.6 µs max. Average Periodic Refresh Interval

z 2.5V (SSTL_2 compatible) I/O

z RoHS + Halogen Free compliance

z JEDEC Standard Compliance

z Packages: 66 pin TSOPII

NT5DS8M16HS

128Mb DDR SDRAM

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Description

Nanya 128Mb SDRAM is a high-speed CMOS Double Data Rate SDRAM containing 134,217,728 bits. It is

internally configured as a qual-bank DRAM.

The 128Mb chip is organized as 2Mbit x 4banks x16 I/O device. These synchronous devices achieve high speed

double-data-rate transfer rates of up to 500 (400 or 333) MHz for general applications.

The 128Mb DDR SDRAM uses a double-data-rate architecture to achieve high speed operation. The double data

rate architecture is essentially a 2ηprefetch architecture with an interface designed to transfer two data words per

clock cycle at the I/O pins. A single read or write access for the 128Mb DDR SDRAM effectively consists of a single

2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide,

one-half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver.

DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is

edge-aligned with data for Reads and center-aligned with data for Writes.

The 128Mb DDR SDRAM operates from a differential clock (CK and CK; the crossing of CK going high and CK going

LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every

positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of

DQS, as well as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue

for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active

command, which is then followed by a Read or Write command. The address bits registered coincident with the

Active command are used to select the bank and row to be accessed. The address bits registered coincident with

the Read or Write command are used to select the bank and the starting column location for the burst access.

The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4, or 8 locations. An Auto Precharge

function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.

As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation,

thereby providing high effective bandwidth by hiding row precharge and activation time.

An auto refresh mode is provided along with a power-saving Power Down mode. All inputs are compatible with the

JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.

The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of

operation.

NT5DS8M16HS

128Mb DDR SDRAM

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Ordering Information

Standard Grade

Speed

Organization Part Number Clock (MHz) CL-TRCD-TRP

NT5DS8M16HS–6K 166 2.5-3-3

8Mx16

NT5DS8M16HS–5T

66 pin TSOP-II

RoHS + Halogen Free Compliant

200 3-3-3

Industrial Grade

Speed

Organization Part Number Clock (MHz) CL-TRCD-TRP

NT5DS8M16HS–6KI 166 2.5-3-3

8Mx16

NT5DS8M16HS–5TI

66 pin TSOP-II

RoHS + Halogen Free Compliant

200 3-3-3

NT5DS8M16HS

128Mb DDR SDRAM

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REV 1.1 CONSUMER DRAM

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Pin Configuration – 400 mil TSOP II (x16)

< TOP View>

See the balls through the package

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128Mb DDR SDRAM

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Input / Output Functional Description

Symbol Type Function

CK, CK Input

Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on

the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to

the crossings of CK and CK (both directions of crossing).

CKE Input

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device

input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER--DOWN and

SELF REFRESH operation (all banks idle), or ACTIVE POWER--DOWN (row ACTIVE in any bank).

CKE is synchronous for POWER-- DOWN entry and exit, and for SELF REFRESH entry. CKE is

asynchronous for SELF REFRESH exit, and for output disable. CKE must be maintained high

throughout READ and WRITE accesses. Input buffers, excluding CK, CK and CKE are disabled during

POWER--DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CKE is an

SSTL_2 input, but will detect an LVCMOS LOW level after Vdd is applied upon 1st power up. After

VREF has become stable during the power on and initialization sequence, it must be maintained for

proper operation of the CKE receiver. For proper self--refresh entry and exit, VREF must be

maintained to this input The standard pinout includes one CKE pin.

CS Input Chip Select: All commands are masked when CS is registered high. CS provides for external rank

selection on systems with multiple memory ranks. CS is considered part of the command code.

RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

DM

( LDM),(UDM) Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is

sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of

DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the

X16, LDM corresponds to the data on DQ0--DQ7; UDM corresponds to the data on DQ8--DQ15. DM

may be driven high, low, or floating during READs.

BA0 – BA1 Input Bank Address Inputs: BA# defines to which bank an Active, Read, Write or Pre-charge command is

being applied.

A0 – A11 Input

Address Inputs: Provide the row address for ACTIVE commands, and the column address and

AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array

in the respective bank. A10 is sampled during a Precharge command to determine whether the

PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be

precharged, the bank is selected by BA0, BA1. The address inputs also provide the op--code during a

MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the

MODE REGISTER SET command (MRS or EMRS).

DQ Input/output Data Bus: Inputs/Output

DQS,

(LDQS,

UDQS)

Input/output

Data Strobe: Output with read data, input with write data. Edge--aligned with read data, centered in

write data. Used to capture write data. For the X16, LDQS corresponds to the data on DQ0--DQ7;

UDQS corresponds to the data on DQ8--DQ15.

NC No Connect: No internal electrical connection is present.

VDDQ Supply

DQ Power Supply: 2.5V ± 0.2V (-6K/-6KI); VDD=VDDQ=2.6V±0.1V (-5T/-5TI/-4T)

VSSQ Supply DQ Ground

VDD Supply Power Supply: 2.5V ± 0.2V (-6K/-6KI); VDD=VDDQ=2.6V±0.1V (-5T/-5TI/-4T)

VSS Supply Ground

VREF Supply SSTL_2 reference voltage

NT5DS8M16HS

128Mb DDR SDRAM

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NT5DS8M16HS

128Mb DDR SDRAM

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REV 1.1 CONSUMER DRAM

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Initialization

At least one of the following two conditions must be met.

• No power sequencing is specified during power up or power down given the following criteria:

VDD and VDDQ are driven from a single power converter output, and

VTT is limited to 1.35V, and

VREF tracks VDDQ /2

Or

• The following relationships must be followed:

VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3V

VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3V

VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3V

The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read access).

After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs

delay prior to applying an executable command.

Once the 200µs delay has been satisfied, a Deselect or NOP command should be applied, and CKE must be brought

HIGH. Following the NOP command, a Precharge ALL command must be applied. Next a Mode Register Set command

must be issued for the Extended Mode Register, to enable the DLL, and then a Mode Register Set command must be

issued for the Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required

between the DLL reset and any read command. A Precharge ALL command should be applied, placing the device in the

“all banks idle” state

Once in the idle state, two auto refresh cycles must be performed. Additionally, a Mode Register Set command for the

Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must

be performed. Following these cycles, the DDR SDRAM is ready for normal operation.

DDR SDRAM’s may be reinitialized at any time during normal operation by asserting a valid MRS command to either the

base or extended mode registers without affecting the contents of the memory array. The contents of either the mode

register or extended mode register can be modified at any valid time during device operation without affecting the state

of the internal address refresh counters used for device refresh.

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128Mb DDR SDRAM

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Register Definition

Mode Register

The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the

selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is programmed via

the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored information until it is programmed

again or the device loses power (except for bit A8, which is self-clearing).

Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6

specify the CAS latency, and A7-A11 specify the operating mode.

The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before

initiating the subsequent operation, violating either of these requirements results in unspecified operation.

Burst Length

Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst

length determines the maximum number of column locations that can be accessed for a given Read or Write command.

Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All

accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is

reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set

to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given

configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block.

The programmed burst length applies to both Read and Write bursts.

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128Mb DDR SDRAM

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Mode Register Operation

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128Mb DDR SDRAM

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Burst Definition

Starting Column Address Order of Accesses Within a Burst

Burst Length A2 A1 A0 Type=Sequential Type=Interleaved

- - 0 0-1 0-1

2 - - 1 1-0 1-0

- 0 0 0-1-2-3 0-1-2-3

- 0 1 1-2-3-0 1-0-3-2

- 1 0 2-3-0-1 2-3-0-1

4

- 1 1 3-0-1-2 3-2-1-0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

8

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Notes:

1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block.

2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the

block.

3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the

block.

4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within

the block.

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst

type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type

and the starting column address, as shown in Burst Definition.

Read Latency

The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the

availability of the first burst of output data.

If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident

with clock edge n + m.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

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128Mb DDR SDRAM

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Operating Mode

The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A11 to zero, and bits

A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and

A9-A11 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register Set command

issued to reset the DLL should always be followed by a Mode Register Set command to select normal operating mode.

All other combinations of values for A7-A11 are reserved for future use and/or test modes. Test modes and reserved

states should not be used as unknown operation or incompatibility with future versions may result.

CAS Latencies

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128Mb DDR SDRAM

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Extended Mode Register

The Extended Mode Register controls functions beyond those controlled by the Mode Register; these

additional functions include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC

output enable/disable, bit A2 (NTC optional). These functions are controlled via the bit settings shown in the

Extended Mode Register Definition. The Extended Mode Register is programmed via the Mode Register Set

command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is programmed again or the

device loses power. The Extended Mode Register must be loaded when all banks are idle, and the controller

must wait the specified time before initiating any subsequent operation, violating either of these requirements

result in unspecified operation.

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and

upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The

DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit

of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur to allow time for the

internal clock to lock to the externally applied clock before a Read command can be issued. This is the

reason for introducing timing parameter tXSRD for DDR SDRAM’s (Exit Self Refresh to Read Command).

Non- Read commands can be issued 2 clocks after the DLL is enabled via the EMRS command (tMRD) or

10 clocks after the DLL is enabled via self refresh exit command (tXSNR, Exit Self Refresh to Non-Read

Command).

Output Drive Strength

The normal drive strength for all outputs is specified to be SSTL_2, Class II.

QFC Enable/Disable (Not support in this product; only for information)

The QFC signal is an optional DRAM output control used to isolate module loads (DIMMs) from the system

memory bus by means of external FET switches when the given module (DIMM) is not being accessed. The

QFC function is an optional feature for NANYA and is not included on all DDR SDRAM devices.

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128Mb DDR SDRAM

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Extended Mode Register Definition

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128Mb DDR SDRAM

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Commands

Truth Tables 1a and 1b provide a reference of the commands supported by DDR SDRAM devices. A verbal description

of each command follows.

Truth Table 1a Commands

Name (Function) CS RAS CAS WE Address Notes

Deselect (Nop) H X X X X 9

No Operation (Nop) L H H H X 9

Active (Select Bank and Activate Row) L L H H Bank / Row 3

Read (Select Bank, Column and Start Read Burst) L H L H Bank / Col 4

Write (Select Bank, Column and Start Write Burst) L H L L Bank / Col 4

Burst Terminate L H H L X 8

Pre-Charge (Deactivate Row In Bank or Banks) L L H L Code 5

Auto Refresh or Self Refresh (Enter Self Refresh

Mode) L L L H X 6,7

Mode Register Set L L L L Op-Code 2

1. CKE is high for all commands shown except Self Refresh.

2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects

Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A11 provide the op-code to be written to the selected Mode

Register.)

3. BA0-BA1 provides bank address and A0-A11 provides row address.

4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 9 for x8 and 9, 11 for x4); A10 high enables the Auto

Precharge feature (non-persistent), A10 low disables the Auto Precharge feature.

5. A10 LOW: BA0, BA1 determine which bank is precharged.

A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.”

6. This command is auto refresh if CKE is high; Self Refresh if CKE is low.

7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with

Auto Precharge enabled or for write bursts.

9. Deselect and NOP are functionally interchangeable.

Truth Table 1b: DM Operation

Name (Function) DM DQs Note

Write Enable L Valid 1

Write Inhibit H X 1

Used to mask write data; provided coincident with the corresponding data.

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Deselect

The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR

SDRAM is effectively deselected. Operations already in progress are not affected.

No Operation (NOP)

The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted

commands from being registered during idle or wait states. Operations already in progress are not affected.

Mode Register Set

The mode registers are loaded via inputs A0-A11, BA0 and BA1 while issuing the Mode Register Set

Command. See mode register descriptions in the Register Definition section. The Mode Register Set

command can only be issued when all banks are idle and no bursts are in progress. A subsequent

executable command cannot be issued until tMRD is met.

Active

The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The

value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row.

This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is

issued to that bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and

completed before opening a different row in the same bank.

Read

The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0,

BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8;

where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether

or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the

end of the Read burst; if Auto Precharge is not selected, the row remains open for subsequent accesses.

Write

The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0,

BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8;

where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether

or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the

end of the Write burst; if Auto Precharge is not selected, the row remains open for subsequent accesses.

Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing

coincident with the data. If a given DM signal is registered low, the corresponding data is written to memory;

if the DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to

that byte/column location.

Precharge

The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s)

in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the

Precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in

the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1

are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated

prior to any Read or Write commands being issued to that bank. A precharge command is treated as a NOP

if there is no open row in that bank, or if the previously open row is already in the process of precharging.

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Auto Precharge

Auto Precharge is a feature which performs the same individual-bank precharge function described above,

but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in

conjunction with a specific Read or Write command. A precharge of the bank/row that is addressed with the

Read or Write command is automatically performed upon completion of the Read or Write burst. Auto

Precharge is non-persistent in that it is either enabled or disabled for each individual Read or Write

command. Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst.

This is determined as if an explicit Precharge command was issued at the earliest possible time without

violating tRAS (min). The user must not issue another command to the same bank until the precharge (tRP)

is completed.

NTC DDR SDRAM device supports the optional tRAS lockout feature. This feature allows a Read command

with Auto Precharge to be issued to a bank that has been activated (opened) but has not yet satisfied the

tRAS (min) specification. The tRAS lockout feature essentially delays the onset of the auto precharge

operation until two conditions occur. One, the entire burst length of data has been successfully prefetched

from the memory array; and two, tRAS (min) has been satisfied.

As a means to specify whether a DDR SDRAM device supports the tRAS lockout feature, a new parameter

has been defined; tRAP (RAS Command to Read Command with Auto Precharge or better stated Bank

Activate to Read Command with Auto Precharge). For devices that support the tRAS lockout feature, tRAP

= tRCD (min). This allows any Read Command (with or without Auto Precharge) to be issued to an open

bank once tRCD (min) is satisfied.

tRAP Definition

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Burst Terminate

The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most

recently registered Read command prior to the Burst Terminate command is truncated, as shown in the

Operation section of this data sheet. Write burst cycles are not to be terminated with the Burst Terminate

command.

Auto Refresh

Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS before RAS

(CBR) Refresh in previous DRAM types. This command is non-persistent, so it must be issued each time a

refresh is required.

The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t

Care” during an Auto

Refresh command. The 128Mb DDR SDRAM requires Auto Refresh cycles at an average periodic interval

of 15.6µs (maximum).

Self Refresh

The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is

powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The

Self Refresh command is initiated as an Auto Refresh command coincident with CKE transitioning low. The

DLL is automatically disabled upon entering Self Refresh, and is automatically enabled upon exiting Self

Refresh (200 clock cycles must then occur before a Read command can be issued). Input signals except

CKE (low) are “Don’t Care” during Self Refresh operation.

The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior

to CKE returning high. Once CKE is high, the SDRAM must have NOP commands issued for tXSNR because

time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both

refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.

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Operations

Bank/Row Activation

Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must be

“opened” (activated). This is accomplished via the Active command and addresses A0-A11, BA0 and BA1 (see

Activating a Specific Row in a Specific Bank), which decode and select both the bank and the row to be activated. After

opening a row (issuing an Active command), a Read or Write command may be issued to that row, subject to the tRCD

specification. A subsequent Active command to a different row in the same bank can only be issued after the previous

active row has been “closed” (precharged). The minimum time interval between successive Active commands to the

same bank is defined by tRC. A subsequent Active command to another bank can be issued while the first bank is being

accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive

Active commands to different banks is defined by tRRD.

Activating a Specific Row in a Specific Bank

tRCD and tRRD Definition

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Reads

Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated

with a Read command.

The starting column and bank addresses are provided with the Read command and Auto Precharge is either enabled or

disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge at the completion

of the burst, provided tRAS has been satisfied. For the generic Read commands used in the following illustrations, Auto

Precharge is disabled.

During Read bursts, the valid data-out element from the starting column address is available following the CAS latency

after the Read command. Each subsequent data-out element is valid nominally at the next positive or negative clock

edge (i.e. at the next crossing of CK and CK). The following timing figure entitled “Read Burst: CAS Latencies (Burst

Length=4)” illustrates the general timing for each supported CAS latency setting. DQS is driven by the DDR SDRAM

along with output data. The initial low state on DQS is known as the read preamble; the low state coincident with the last

data-out element is known as the read post amble. Upon completion of a burst, assuming no other commands have

been initiated, the DQs and DQS go High-Z. Data from any Read burst may be concatenated with or truncated with data

from a subsequent Read command. In either case, a continuous flow of data can be maintained. The first data element

from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst

which is being truncated. The new Read command should be issued x cycles after the first Read command, where x

equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown in

timing figure entitled “Consecutive Read Bursts: CAS Latencies (Burst Length =4 or 8)”. A Read command can be

initiated on any positive clock cycle following a previous Read command. Nonconsecutive Read data is shown in timing

figure entitled “Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)”. Full-speed Random Read Accesses:

CAS Latencies (Burst Length = 2, 4 or 8) within a page (or pages) can be performed.

Read Command

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Read Burst: CAS Latencies (Burst Length = 4)

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Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8)

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Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)

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Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)

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Data from any Read burst may be truncated with a Burst Terminate command, as shown in timing figure

entitled Terminating a Read Burst: CAS Latencies (Burst Length = 8) on page 25. The Burst Terminate

latency is equal to the read (CAS) latency, i.e. the Burst Terminate command should be issued x cycles after

the Read command, where x equals the number of desired data element pairs.

Data from any Read burst must be completed or truncated before a subsequent Write command can be

issued. If truncation is necessary, the Burst Terminate command must be used, as shown in timing figure

entitled Read to W rite: C AS Lat encies (Burst Length = 4 o r 8) on page 26. The example is shown for tDQSS

(min). The tDQSS (max) case, not shown here, has a longer bus idle time. tDQSS (min) and tDQSS (max)

are defined in the section on Writes.

A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that

Auto Precharge was not activated). The Precharge command should be issued x cycles after the Read

command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch

architecture). This is shown in timing figure on page 27 for Read latencies of 3. Following the Precharge

command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the

row precharge time is hidden during the access of the last data elements.

In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as

described above) provides the same operation that would result from the same Read burst with Auto

Precharge enabled. The disadvantage of the Precharge command is that it requires that the command and

address busses be available at the appropriate time to issue the command. The advantage of the Precharge

command is that it can be used to truncate bursts.

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Terminating a Read Burst: CAS Latencies (Burst Length = 8)

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Read to Write: CAS Latencies (Burst Length = 4 or 8)

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Read to Precharge: CAS Latencies (Burst Length = 4 or 8)

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Writes

Write bursts are initiated with a Write command, as shown in timing figure Write Command on page 29.

The starting column and bank addresses are provided with the Write command, and Auto Precharge is

either enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is

precharged at the completion of the burst. For the generic Write commands used in the following illustrations,

Auto Precharge is disabled.

During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the

write command, and subsequent data elements are registered on successive edges of DQS. The Low state

on DQS between the Write command and the first rising edge is known as the write preamble; the Low state

on DQS following the last data-in element is known as the write postamble. The time between the Write

command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range

(from 75% to 125% of one clock cycle), so most of the Write diagrams that follow are drawn for the two

extreme cases (i.e. tDQSS(min) and tDQSS(max)). Timing figure Write Burst (Burst Length = 4) on page 30

shows the two extremes of tDQSS for a burst of four. Upon completion of a burst, assuming no other

commands have been initiated, the DQs and DQS enter High-Z and any additional input data is ignored.

Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either

case, a continuous flow of input data can be maintained. The new Write command can be issued on any

positive edge of clock following the previous Write command. The first data element from the new burst is

applied after either the last element of a completed burst or the last desired data element of a longer burst

which is being truncated. The new Write command should be issued x cycles after the first Write command,

where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture).

Timing figure Write to Write (Bur st Length = 4) on page 31 shows concatenated bursts of 4. An example of

nonconsecutive Writes is shown in timing figure Write to Write: Max DQSS, Non-Consecutive (Burst L eng th

= 4) on page 32. Full speed random write accesses within a page or pages can be performed as shown in

timing figure Random Write Cycles (Burst Length = 2, 4 or 8) on page 33. Data for any Write burst may be

followed by a subsequent Read command. To follow a Write without truncating the write burst, tWTR (Write

to Read) should be met as shown in timing figure Write to Read: Non-Interrupting (CAS Latency = 3; Burst

Length = 4).

Data for any Write burst may be truncated by a subsequent (interrupting) Read command. This is illustrated

in timing figures “Write to Read: Interrupting (CAS Latency =2; Burst Length = 8)”, “Write to Read: Minimum

DQSS, Odd Number of Data (3 bit Write), Interrupting (CAS Latency = 2; Burst Length = 8)”, and “Write to

Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8)”. Note that only the data-in pairs

that are registered prior to the tWTR period are written to the internal array, and any subsequent data-in

must be masked with DM, as shown in the diagrams noted previously.

Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without

truncating the write burst, tWR should be met as shown in timing figure Write to Precharge: Non-Interrupting

(Burst Length = 4) on page 34.

Data for any Write burst may be truncated by a subsequent Precharge command, as shown in timing figures

Write to Precharge: Interrupting (Burst Length = 4 or 8) on page 35 to Write to Precharge: Nominal DQSS (2

bit Write), Interrupting (Burst Length = 4 or 8). Note that only the data-in pairs that are registered prior to the

tWR period are written to the internal array and any subsequent data in should be masked with DM,

Following the Precharge command, a subsequent command to the same bank cannot be issued until tRP is

met.

In the case of a Write burst being executed to completion, a Precharge command issued at the optimum

time (as described above) provides the same operation that would result from the same burst with Auto

Precharge. The disadvantage of the Precharge command is that it requires that the command and address

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busses be available at the appropriate time to issue the command. The advantage of the Precharge

command is that it can be used to truncate bursts.

Write Command

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Write Burst (Burst Length = 4)

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Write to Write (Burst Length = 4)

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Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4)

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Random Write Cycles (Burst Length = 2, 4 or 8)

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Write to Read: Non-Interrupting (CAS Latency = 3; Burst Length = 4)

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Write to Read: Interrupting (CAS Latency = 3; Burst Length = 8)

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Write to Read: Minimum DQSS, Odd Number of Data (3 bit Write), and Interrupting

(CAS Latency = 3; Burst Length = 8)

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Write to Read: Nominal DQSS, Interrupting (CAS Latency = 3; Burst Length = 8)

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Write to Precharge: Non-Interrupting (Burst Length = 4)

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Write to Precharge: Interrupting (Burst Length = 4 or 8)

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Write to Precharge: Minimum DQSS, Odd Number of Data (1 bit Write), Interrupting

(Burst Length = 4 or 8)

Write to Precharge: Nominal DQSS (2 bi t Write), Interrupting (Burst Length = 4 or 8)

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Precharge Command

Precharge

The Precharge command is used to deactivate the open row in a particular bank or the open row in all

banks. The bank(s) is available for a subsequent row access some specified time (tRP) after the Precharge

command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case

where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be

precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the

idle state and must be activated prior to any Read or Write commands being issued to that bank.

Power Down

Power Down is entered when CKE is registered low (no accesses can be in progress). If Power Down occurs when all

banks are idle, this mode is referred to as Precharge Power Down; if Power Down occurs when there is a row active in

any bank, this mode is referred to as Active Power Down. Entering Power Down deactivates the input and output

buffers, excluding CK, CK and CKE. The DLL is still running in Power Down mode, so for maximum power savings, the

user has the option of disabling the DLL prior to entering Power Down. In that case, the DLL must be enabled after

exiting Power Down, and 200 clock cycles must occur before a Read command can be issued. In Power Down mode,

CKE Low and a stable clock signal must be maintained at the inputs of the DDR SDRAM, and all other input signals

are “Don’t Care”. However, Power Down duration is limited by the refresh requirements of the device, so in most

applications, the self refresh mode is preferred over the DLL-disabled Power Down mode.

The Power Down state is synchronously exited when CKE is registered high (along with a Nop or Deselect command).

A valid, executable command may be applied one clock cycle later.

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Truth Table 2: Clock Enable (CKE)

1. CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.

2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.

3. Command n is the command registered at clock edge n, and action n is a result of command n.

4. All states and sequences not shown are illegal or reserved.

CKE n-1 CKEn

Cur ren t State Previous

Cycle Current

Cycle

Command n Action n Notes

Self Refresh L L X Maintain Self-Refresh

Self Refresh L H Deselect or NOP Exit Self-Refresh 1

Power Down L L X Maintain Power Down

Power Down L H Deselect or NOP Exit Power Down

All Banks Idle H L Deselect or NOP Precharge Power Down Entry

All Banks Idle H L Auto Refresh Self Refresh Entry

Bank(s) A ctive H L Deselect or NOP Active Power Down Entry

H H See Truth Table 3

1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A

minimum of

200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.

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Truth Table 3: Current State Banks n – Command to Bank n (Same Bank)

Current

State CS RAS CAS WE Command Action Notes

H X X X Deselect NOP. Continue previous operation

Any L H H H No Operation NOP. Continue previous operation

L L H H Active Select and activate row

L L L H Auto Refresh Auto Refresh 7

Idle

L L L L Mode Register Set Mode Register Set 7

L H L H Read Select column and start Read burst 10

L H L L Write Select column and start Write burst 10

Row

Active L L H L Precharge Deactivates row in bank(s) 8

L H L H Read Select column and start new Read

burst 10

L H L L Write Select column and start new Write burst 10,12

L L H L Precharge Truncate Read burst, start precharge 8

Read

(Auto

Precharge

Disabled) L H H L Burst Termination Burst Terminate 9

L H L H Read Select column and start Read burst 10,11

L H L L Write Select column and start Write burst 10

Write

(Auto

Precharge

Disabled) L L H L Precharge truncate Write burst, start precharge) 8,11

1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has

been met (if the previous state was self refresh).

2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those

allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Activ e : A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are

in progress.

Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands or allowable

commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank

are determined by its current state and Truth Table 3, and according to Truth Table 4.

Precharging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle

state.

Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the

“row active” state.

Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when tRP

has been met. Once tRP is met, the bank is in the idle state.

Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP

has been met. Once tRP is met, the bank is in the idle state.

5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each

positive clock edge during these states.

Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is met, the DDR SDRAM

is in the “all banks idle” state.

Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once

tMRD is met, the DDR SDRAM is in the “all banks idle” state.

Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in

the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle.

8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.

9. Not bank-specific; Burst terminate affects the most recent Read burst, regardless of bank.

10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes

with Auto Precharge disabled.

11. Requires appropriate DM masking.

12. A WRITE command may be applied after the completion of the READ burst; otherwise, a Burst Terminate must be used to end the

READ prior to asserting a WRITE command,

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Truth Table 4: Current State Banks n – Command to Bank m (different Bank)

Current State CS RAS CAS WE Command Action Notes

H X X X Deselect NOP. Continue previous operation

Any

L H H H No Operation NOP. Continue previous operation

Idle X X X X Any Command Otherwise Allowed to Bank m

L L H H Active Select and active Row

L H L H Read Select column and start Read burst 7

L H L L Write Select column and start Write burst 7

Row Activating,

Active or

Precharge

L L H L Precharge

L L H H Active Select and activate row

L H L H Read Select column and start new Read burst 7

L H L L Write Select column and start new Write burst 7,9

Read (Auto

Precharge

Disabled)

L L H L Precharge

L L H H Active Select and active Row

L H L H Read Select column and start Read burst 7,8

L H L L Write Select column and start Write burst 7

Write (Auto

Precharge

Disabled)

L L H L Precharge

L L H H Active Select and active Row

L H L H Read Select column and start Read burst 3a,7

L H L L Write Select column and start Write burst 3a,7,9

Read (with Auto

Precharge)

L L H L Precharge

L L H H Active Select and active Row

L H L H Read Select column and start Read burst 3a,7

L H L L Write Select column and start Write burst 3a,9

Write (with Auto

Precharge)

L L H L Precharge

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1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has

been met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are

those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are

covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Activ e : A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are

in progress.

Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Read with Auto Precharge Enable: See following text, notes 3a, 3b, and 3c:

Write with Auto Precharge Enable: See following text, notes 3a, 3b, and 3c:

3a. For devices which do not support the optional “concurrent auto precharge” feature, the Read with Auto Precharge Enabled or

Write with Auto Precharge Enabled states can each be broken into two parts: the access period and the precharge period. For Read

with Auto Precharge, the precharge period is defined as if the same burst was executed with Auto Precharge disabled and then

followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For Write with Auto

Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period

starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period of the

Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, ACTIVE, PRECHARGE, READ and WRITE

commands to the other bank may be applied; during the access period, only ACTIVE and PRECHARGE commands to the other

bank may be applied. In either case, all other related limitations apply (e.g., contention between READ data and WRITE data must

be avoided).

3b. For devices which do support the optional “concurrent auto precharge” feature, a read with auto precharge enabled, or a write

with auto precharge enabled, may be followed by any command to the other banks, as long as that command does not interrupt the

read or write data transfer, and all other related limitations apply (e.g., contention between READ data and WRITE data must be

avoided.)

3c. The minimum delay from a read or write command with auto precharge enable, to a command to a different bank, is

summarized below, for both cases of “concurrent auto precharge,” supported or not:

From

Command

To Command

(Different bank)

Minimum Delay Without

Concurrent Auto Precharge

Support

Minimum Delay WithConcurrent

Auto Precharge Support Units

Read or Read w/AP 1+(BL/2) + (tWR/tCK) (rounded

up) 1+(BL/2) + tWTR

Write or Write w/AP 1+(BL/2) + (tWR/tCK) (rounded

up) BL/2

Write w/AP

Precharge or Activate 1

Read or Read w/AP BL/2

Write or Write w/AP CL (rounded up) + (BL/2)

Read w/AP

Precharge or Activate 1

tCK

4. AUTO REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle.

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with AUTO PRECHARGE enabled and READs

or WRITEs with AUTO PRECHARGE disabled.

8. Requires appropriate DM masking.

9. A WRITE command may be applied after the completion of data output, otherwise a Burst Terminate must be used to the READ prior

to asserting a WRITE command.

10. Operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be

powered down and then restarted through the specified initialization sequence before normal operation can continue.

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Simplified State Diagram

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Absolute Maximum Ratings

Symbol Parameter Rating Units

VIN, VOUT Voltage on I/O pins relative to VSS -0.5 to VDDQ+ 0.5 V

VIN Voltage on Inputs relative to VSS -1.0 to +3.6 V

VDD Voltage on VDD supply relative to VSS -1.0 to +3.6 V

VDDQ Voltage on VDDQ supply relative to VSS -1.0 to +3.6 V

TA Operating Temperature (Ambient) 0 to +70 ℃

TSTG Storage Temperature (Plastic) -55 to +150 ℃

PD Power Dissipation 1.0 W

IOUT Short Circuit Output Current 50 mA

Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Capacitance

Parameter Symbol Min. Max. Units Notes

Input Capacitance: CK, CK CI1 2.0 3.0 pF 1

Delta Input Capacitance: CK, CK delta CI1 - 0.25 pF 1

Input Capacitance: All other input-only pins (except DM) CI2 2.0 3.0 pF 1

Delta Input Capacitance: All other input-only pins (except

DM) delta CI2 - 0.5 pF 1

Input/Output Capacitance: DQ, DQS, DM CIO 4.0 5.0 pF 1,2

Delta Input/Output Capacitance: DQ, DQS, DM delta CIO - 0.5 pF 1

1. VDDQ = VDD = 2.5V ± 0.2V (DDR333); 2.6V ± 0.1V (DDR400/500) (minimum range to maximum range), f = 100MHz, TA = 25°C,

VODC = VDDQ/2, VOPeak -Peak = 0.2V.

2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is

required to match input propagation times of DQ, DQS and DM in the system.

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DC Electrical Characteristics and Operating Conditions

(For DDR333, VDDQ = VDD = +2.5V±0.2V; For DDR400/DDR500, VDDQ = VDD = + 2.6V ± 0.1V)

Min

Symbol Parameter DDR

333 DDR

400/500 Max Units Notes

VDD Supply Voltage 2.3 2.5 2.7 V 1

VDDQ I/O Supply Voltage 2.3 2.5 2.7 V 1

VREF I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V 1,2

VTT I/O Termination Voltage (System) VREF - 0.04 VREF + 0.04 V 1,3

VIH(DC) Input High (Logic1) Voltage VREF + 0.15 VDDQ + 0.3 V 1

VIL(DC) Input Low (Logic0) Voltage - 0.3 VREF - 0.15 V 1

VIN(DC) Input Voltage Level, CK and CK Inputs - 0.3 VDDQ + 0.3 V 1

VID(DC) Input Differential Voltage, CK and CK

Inputs 0.36 VDDQ + 0.6 V 1,4

VIX(DC) Input Crossing Point Voltage, CK and CK

Inputs 0.30 VDDQ + 0.6 V 1,4

VIRATIO V-I Matching Pullup Current to Pulldown

Current Ratio 0.71 1.4

5

II

Input Leakage Current

Any input 0V ≦ VIN ≦ VDD; (All other

pins not under test = 0V)

-2 2

µA

IOZ

Output Leakage Current

(DQs are disabled; 0V ≦ Vout ≦

VDDQ

-5 5

µA 1

IOH -16.2

IOL

Output Current: Nominal Strength Driver

High current (VOUT= VDDQ -0.373V,

min VREF, min VTT)

Low current (VOUT= 0.373V, max

VREF, max VTT)

16.2

mA 1

1. Inputs are not recognized as valid until VREF stabilizes.

2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak

noise on VREF may not exceed ± 2% of the DC value.

3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF,

and must track variations in the DC level of VREF.

4. VID is the magnitude of the difference between the input level on CK and the input level on CK.

5. The ratio of the pull-up current to the pull down current is specified for the same temperature and voltage, over the entire temperature

and voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum

difference between pull-up and pull down drivers due to process variation.

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Normal Strength Driver Pull-dow n and Pull-up Characteristics

1. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie

within the outer bounding lines of the V-I curve.

2. It is recommended that the “typical” IBIS pull down V-I curve lie within the shaded region of the V-I curve.

3. The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within

the outer bounding lines of the V-I curve.

4. It is recommended that the “typical” IBIS pull-up V-I curve lie within the shaded region of the V-I curve.

5. The full variation in the ratio of the maximum to minimum pull-up and pull-down current will not exceed 1.7, for device

drain to source voltages from 0.1 to 1.0.

6. The full variation in the ratio of the “typical” IBIS pull-up to “typical” IBIS pull-down current should be unity + 10%, for

device drain to source voltages from 0.1 to 1.0. This specification is a design objective only. It is not guaranteed.

7. These characteristics are intended to obey the SSTL_2 class II standard.

8. This specification is intended for DDR SDRAM only.

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Normal Strengt h Dri ver Pu ll - down and Pull-up Cur rents

Pull Down Current (mA) Pull up Current (mA)

Voltage

(V) Typical

Low Typical

High Min Max

Typical

Low Typical

High Min Max

0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0

0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0

0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8

0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8

0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8

0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4

0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8

0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5

0.9 47.5 55.2 39.6 69.9 -43.8 -59.4 -38.2 -77.3

1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2

1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0

1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6

1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1

1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5

1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0

1.6 60.5 85.9 48.0 108.4 -51.0 -101.3 -40.1 -130.4

1.7 61.0 89.1 48.4 112.1 -51.1 -107.1 -40.2 -136.7

1.8 61.5 92.2 48.9 115.9 -51.3 -112.4 -40.3 -144.2

1.9 62.0 95.3 49.1 119.6 -51.5 -118.7 -40.4 -150.5

2.0 62.5 97.2 49.4 123.3 -51.6 -124.0 -40.5 -156.9

2.1 62.9 99.1 49.6 126.5 -51.8 -129.3 -40.6 -163.2

2.2 63.3 100.9 49.8 129.5 -52.0 -134.6 -40.7 -169.6

2.3 63.8 101.9 49.9 132.4 -52.2 -139.9 -40.8 -176.0

2.4 64.1 102.8 50.0 135.0 -52.3 -145.2 -40.9 -181.3

2.5 64.6 103.8 50.2 137.3 -52.5 -150.5 -41.0 -187.6

2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9

2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2

Normal Strength Driver Evaluation Conditions

Item Typical Minimum Maximum

Temperature (Tambient) 25℃ 70℃ 0℃

VDDQ 2.5V 2.3V 2.7V

Process conditions Typical Process slow-slow process fast-fast process

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AC Characteristics

(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating

Conditions, IDD Specifications and Conditions, and Electrical Characteristics and AC Timing.)

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply

voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.

4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still

referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified

AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between

VIL (AC) and VIH (AC).

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches

as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back

above (below) the DC input low (high) level.

AC Output Load Circuit Diagrams

AC Input Operating Conditions

(VDDQ = VDD = + 2.5V ± 0.2V (DDR333); + 2.6V ± 0.1V (DDR400/500);

Symbol Parameter / Condition Min Max Unit Note

VIH(AC) Input High (Logic 1) Voltage, DQ, DQS, and DM Signals VREF + 0.31 - V 1,2

VIL(AC) Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals - VREF − 0.31 V 1,2

VID(AC) Input Differential Voltage, CK and CK Inputs 0.7 VDDQ + 0.6 V 1,2,3

VIX(AC) Input Crossing Point Voltage, CK and CK Inputs 0.5*VDDQ − 0.2 0.5*VDDQ + 0.2 V 1,2,4

1. Input slew rate = 1V/ns.

2. Inputs are not recognized as valid until VREF stabilizes.

3. VID is the magnitude of the difference between the input level on CK and the input level on CK.

4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.

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IDD Specifications and Conditions

(VDDQ = VDD = + 2.5V ± 0.2V (DDR333); + 2.6V ± 0.1V (DDR400/500); See AC Characteristics)

DDR333 DDR400

Symbol Parameter/Condition

I/O -6K/6KI -5T/5TI Unit Notes

IDD0

Operating Current: one bank; active / precharge; tRC = tRC

(min); DQ, DM, and DQS inputs changing twice per clock

cycle; address and control inputs changing once per clock

cycle.

x16 75 90

mA 1,2

IDD1 Oper ating Cur rent: one bank; active / read / precharge; Burst

= 2; tRC = tRC (min); CL = 2.5; IOUT = 0mA; address and

control inputs changing once per clock cycle

x16 95 110 mA 1,2

IDD2P Precharge Power Down Standby Current: all banks idle;

Power Down mode; CKE ≦ V

IL (max) X16 7 7

mA 1

IDD2F Idle Standb y Current: CS ≧ VIH (min); all banks idle; CKE ³

VIH (min); address and control inputs changing once per clock

cycle

X16 30 35

mA 1

IDD2Q Precharge floating standby current: CS ≧VIH (min); all

banks idle; CKE ≧ V

IH (min); address and control inputs

changing once per clock cycle

X16 30 35

mA 1

IDD3P Active Power Down Standby Current: one bank active;

Power Down mode; CKE ≦ V

IL(max) X16 15 20

mA 1

IDD3N

Active Standby Current: one bank; active / precharge; CS

≧ V

IH (min);CKE ≧ VIH (min); tRC = tRAS (max); DQ, DM,

and DQS inputs changing twice per clock cycle; address and

control inputs changing once per clock cycle

X16 45 50

mA 1,2

IDD4R

Operating Current: one bank; Burst = 2; reads; continuous

burst; address and control inputs changing once per clock

cycle; DQ and DQS outputs changing twice per clock cycle;

CL = 2.5; IOUT = 0mA

x16 100 120 mA 1,2

IDD4W

Operating Current: one bank; Burst = 2; writes; continuous

burst; address and control inputs changing once per clock

cycle; DQ and DQS inputs changing twice per clock cycle; CL

= 2.5

x16 110 130 mA 1,2

IDD5 Auto-Refresh Current: tRC = tRFC (min) X16 160 190 mA 1

IDD6 Self-Refresh Current: CKE ≦0.2V X16 3 3

mA 1

IDD7 Oper ati ng cu rren t: four bank; four bank interleaving with BL =

4, address and control inputs randomly changing; 50% of data

changing at every transfer; t RC = t RC (min); I OUT = 0mA.

x16 215 250 mA 1,2

1. IDD specifications are tested after the device is properly initialized.

2. Enables on-chip refresh and address counters. Values are averaged from high and low temp values using x16 devices.

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Electrical Characteristics & AC Timing - Absolute Specifications

(VDDQ = VDD = + 2.5V ± 0.2V (DDR333); + 2.6V ± 0.1V (DDR400/500); See AC Characteristics)

DDR333

(-6K/-6KI) DDR400

(-5T/-5TI)

Symbol Parameter

Min Max Min Max

Unit Notes

tAC DQ output access time from CK/CK − 0.70 0.7 − 0.70 + 0.7 ns

tDQSCK DQS output access time from CK/CK − 0.60 + 0.60 − 0.60 + 0.60 ns

tCH CK high-level width 0.45 0.55 0.45 0.55 tCK

tCL CK low-level width 0.45 0.55 0.45 0.55 tCK

tHP CK half period min

(tCL, tCH) min

(tCL, tCH) ns

CL= 2 7.5 12 7.5 12 ns

CL=2.5 6 12 6 12 ns

tCK Clock cycle time

CL=3 5 10 5 7 ns

3

tDH DQ and DM input hold time 0.45 0.4 ns 4

tDS DQ and DM input setup time 0.45 0.4 ns 4

tIPw Input pulse width 2.2 2.2 ns 5

tDIPw DQ and DM input pulse width (each input) 1.75 1.75 ns 5

tHZ Data-out high-impedance time from CK/CK 0.7 0.7 ns 6

tLZ Data-out low-impedance time from CK/CK − 0.7 0.7 − 0.7 0.7 ns 6

tDQSQ DQS-DQ skew (DQS & associated DQ signals)-TSOP 0.45 0.4 ns

tQH Data output hold time from DQS tHP - tQHS tHP - tQHS ns

tQHS Data hold Skew Factor-TSOP 0.55 0.5 ns

tDQSS write command to 1st DQS latching 0.75 1.25 0.72 1.25 tCK

tDQSH DQS input high pulse width (write cycle) 0.35 0.35 tCK

tDQSL DQS input low pulse width (write cycle) 0.35 0.35 tCK

tDSS DQS falling edge to CK setup time (write cycle) 0.2 0.2 tCK

tDSH DQS falling edge hold time from CK (write cycle) 0.2 0.2 tCK

tMRD Mode register set command cycle time 2 2 tCK

twPRES write preamble setup time 0 0 ns

twPST write postamble 0.4 0.6 0.4 0.6 tCK 9

twPRE write preamble 0.25

max(0.25

*tCK, 1.5

ns)

ns 8

tIH Address and control input hold time (fast slew rate) 0.75 0.6 ns 5, 10-12

tIS Address and control input setup time (fast slew rate) 0.75 0.6 ns 5, 10-12

tIH Address and control input hold time (slow slew rate) 0.8 0.7 ns 5, 11-13

tIS Address and control input setup time (slow slew rate) 0.8 0.7 ns 5, 11-13

tRPRE Read preamble 0.9 1.1 0.9 1.1 tCK 14

tRPRES Read preamble setup time (Optional CL=1.5) N/A N/A ns

tRPST Read postamble 0.4 0.6 0.4 0.6 tCK

tRAS Active to Precharge 42 70K 40 70K ns

tRC Active to Active/Auto-refresh command period 60 55 ns

tRFC Auto-refresh to Active/Auto-refresh command period 72 70 ns

tRCD Active to Read or write delay 18 15 ns

tRP Precharge command period 18 15 ns

tRAP Active to Read Command with Auto Precharge (tRCD,

tRAS) (tRCD,

tRAS) ns

tRRD Active bank A to Active bank B command 12 10 ns

twR write recovery time 15 15 ns

tDAL Auto precharge write recovery + precharge time -- -- tCK 15

twTR Internal write to read command delay 1 2 tCK

tXSNR Exit self-refresh to non-read command 75 75 ns 16

tXSRD Exit self-refresh to read command 200 200 tCK

tREFI Average Periodic Refresh Interval 15.6 15.6 µs 4-17

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Component Notes

1. Min (tCL, tCH) referes to the smaller of the actual clock low time and actual clock high time as provided to

the device. (i.e. this value can be greater than the minimum specification limits for tCL and tCH).

2. tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high

or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2)

The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next

transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to

n-channel variation of the output drivers.

3. The only time that the clock frequency is allowed to change is during self-refresh mode.

4. If refresh time or tDS/tDH is viloated, data corruption may occur and the data must be re-written with valid

data before a valid READ can be executed.

5. These parameters guarantee device timing, but they are not necessarily tested on each device. They may

be guaranteed by device design or tester correlation.

6. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters

are reference to a specific voltage level that specifies when the device output is no longer driving (tHZ) or

begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement

points are not critical as long as the calculation is consistent.

7. tDQSQ consists of data pin skew and output pattern effects and p-channel to n-channel variation of the

output drivers for any given cycle.

8. The specific requirement is that DQS be valid (High, Low, or at same point on a valid transition) on or before

this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the

device. When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to

logic Low. If a previous write was in process, DQS could be HIGH, LOW, or transitioning from High to Low at

this time, depending on DQSS.

9. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for

this parameter, but system performance (bus turn-around) will degrade accordingly.

10. For command/address input slew rate >= 1.0V/ns.

11. For CK & CK slew rate >= 1.0V/ns (single-ended).

12. Slew Rate is measured between VOH(ac) and VOL(ac).

13. For command/address input slew rate >= 0.5V/ns and <1.0V/ns.

14. tRPST end point and tRPRE begin point are not reference to a specific voltage level but specify when the

device output is no longer driving (tRPRE) by measuring the signal at two different voltages. The actual

voltage measurement points are not critical as long as the calculation is consistent.

15. tDAL = (tWR/tCK) + (tRP/tCK)

16. In all circumstances, tXSNR can be satisfied using tXSNR = tRFCmin + 1*tCK.

17. A maximum of eight Auto Refresh commands can be posted to any given DDR SDRAM.

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Data Input (Write) (Timing Burst Length =4)

Data Output (Read) (Timing Burst Length =4)

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Initialize and Mode Register Set

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Power Down Mode

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Auto Refresh

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Self Refresh Mode

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Read without Auto Precharge (Burst Length = 4)

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Read with Auto Precharge (Burst Length = 4)

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Bank Read Access (burst Length = 4)

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Write without Auto Precharge (Burst Length = 4)

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Write with Auto Precharge (Burst Length = 4)

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Bank Write Access (Burst Length = 4)

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Write DM Operation (Burst Length = 4)

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Package Dimensions (400mil; 66 pin TSOP Package)

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Revision Log

Rev Date Modification

0.1 March 2010 Preliminary Edition

1.0 May 2010 Official Release

1.1 July 2010 Modified IDD specification and Removed -4T support

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Nanya Technology Corporation.

Printed in Taiwan, R.O.C.

The following are trademarks of NANYA TECHNOLOGY CORPORATION: NANYA and the NANYA logo

Other company, product and service names may be trademarks or service marks of others.

NANYA TECHNOLOGY CORPORATION (NTC) reserves the right to make changes without notice. NTC warrants

performance of its semiconductor products and related software to the specifications applicable at the time of sale in

accordance with NTC’s standard warranty. Testing and other quality control techniques are utilized to the extent NTC

deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed,

except those mandated by government requirements.

Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe

property or environmental damage (“Critical Applications”).

NTC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTEND, AUTHORIZED, OR WARRANTED TO BE

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