ICS843AGI-106LFT - Integrated Device Technology

843AGI-106 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 8, 2005

Integrated

Circuit

Systems, Inc.

ICS843I-106

106.25MHZ, LVCMOS, LVPECL

DUAL OUTPUT OSCILLATOR

PRELIMINARY

GENERAL DESCRIPTION

The ICS843I-106 is a Fibre Channel Dual

Output Oscillator and a member of the

HiPerClocksTM family of high performance

devices from ICS. The ICS843I-106 uses a

25MHz crystal to synthesize 106.25MHz.

The ICS843I-106 has excellent jitter performance. The

ICS843I-106 is packaged in a small 8-pin TSSOP,

making it ideal for use in systems with limited board space.

FEATURES

•One LVCMOS/LVTTL output, 15Ω output impedence

One LVPECL output pair

•Crystal oscillator interface designed for 25MHz,

18pF parallel resonant crystal

•Output frequency: 106.25MHz

•Random jitter: 3.14ps (typical)

•Deterministic jitter: 0.92ps (typical)

•3.3V operating supply

•-40°C to 85°C ambient operating temperature

•Available in both standard and lead-free RoHS-compliant

packages

HiPerClockS™

ICS

ICS843I-106

8-Lead TSSOP

4.40mm x 3.0mm x 0.925mm

package body

G Package

Top View

VCC

XTAL_IN

XTAL_OUT

VEE

nQ1

VCCO

BLOCK DIAGRAM PIN ASSIGNMENT

Clock

Synthesizer

XTAL_IN

XTAL_OUT

25MHz

LVCMOS

106.25MHz

nQ1

LVPECL

106.25MHz

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on

initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications

without notice.

ICS843I-106

8-Lead SOIC

3.90mm x 4.92mm x 1.37mm body package

M Package

Top View

843AGI-106 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 8, 2005

Integrated

Circuit

Systems, Inc.

ICS843I-106

106.25MHZ, LVCMOS, LVPECL

DUAL OUTPUT OSCILLATOR

PRELIMINARY

TABLE 2. PIN CHARACTERISTICS

TABLE 1. PIN DESCRIPTIONS

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

ecnaticapaCtupnI 4Fp

TUO

ecnadepmItuptuO0Q51Ω

rebmuNemaNepyTnoitpircseD

rewoP.nipylppuseroC

3,2 ,NI_LATX

TUO_LATX tupnI ,tupniehtsiNI_LATX.ecafretnirotallicsolatsyrC

.tuptuoehtsiTU

O_LATX

rewoP.nipylppusevitageN

50QtuptuO .slevelecafretniLTTVL/SOMCVL.tuptuokcolcdedne-elgniS

51 Ω.ecnedepmituptuo

OCC

rewoP.nipylppustuptuO

8,71Q,1QntuptuO.riaptuptuoLCEPVLlaitnereffiD

843AGI-106 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 8, 2005

Integrated

Circuit

Systems, Inc.

ICS843I-106

106.25MHZ, LVCMOS, LVPECL

DUAL OUTPUT OSCILLATOR

PRELIMINARY

TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±0.3V, TA = -40°C TO 85°C

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

CC 4.6V

Inputs, VI-0.5V to VCC + 0.5 V

Outputs, V

O (LVCMOS) -0.5V to VCCO + 0.5V

Outputs, IO (LVPECL)

Continuous Current 50mA

Surge Current 100mA

Package Thermal Impedance, θJA

8 Lead TSSOP 101.7°C/W (0 mps)

8 Lead SOIC 112.7°C/W (0 lfpm)

Storage Temperature, T

STG -65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional

operation of product at these conditions or any conditions be-

yond those listed in the DC Characteristics or AC Character-

istics is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V±0.3V, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

1ETON;egatloVhgiHtuptuO 6.2V

1ETON;egatloVwoLtuptuO 5.0V

05htiwdetanimretstuptuO:1ETON ΩVot

OCC

,noitceSnoitamrofnItnemerusaeMretemaraPeeS.2/

."tiucriCtseTdaoLtuptuOV3.3"

TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±0.3V, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

1ETON;egatloVhgiHtuptuOV

OCC

4.1-V

OCC

9.0-V

1ETON;egatloVwoLtuptuOV

OCC

0.2-V

OCC

7.1-V

GNIWS

gniwSegatloVtuptuOkaeP-ot-kaeP6.00.1V

05htiwdetanimretstuptuO:1ETON ΩVot

OCC

.V2-

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 0.33.36.3V

OCC

egatloVylppuStuptuO 0.33.36.3V

tnerruCylppuSrewoP 19Am

OCC

tnerruCylppuStuptuO 24Am

843AGI-106 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 8, 2005

Integrated

Circuit

Systems, Inc.

ICS843I-106

106.25MHZ, LVCMOS, LVPECL

DUAL OUTPUT OSCILLATOR

PRELIMINARY

TABLE 4. CRYSTAL CHARACTERISTICS (NOTE 1)

TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V±0.3V, TA = -40°C TO 85°C

retemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

noitallicsOfoedoM latnemadnuF

ycneuqerF 52zHM

)RSE(ecnatsiseRs

eireStnelaviuqE DBT Ω

ecnareloTycneuqerF 03±mpp

gnitarepOrevOytilibatSycneuqerF

egnaRerutarepmeT 03±mpp

C(ecnat

icapaCdaoL

2ETON;) 81Fp

sraeY01rofgnigA 51±mpp

leveLevirD 1Wm

.ycaruccampp001±tegratevobanwohssretemarapeht,egakcapDMSSU/

94CHnagnisU:1ETON

eeS:2ETON ecafretnItupnIlatsyrC .noitceSnoitamrofnInoitacilppAehtni

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

TUO

ycneuqerFtuptuO 52.601zHM

1ETON;rettiJcitsinimreteD 29.0sp

1ETON;rettiJmodnaR 41.3sp

SMR

(noitubirtsiDlatoTfoSMR σ;)

2ETON 51.3sp

p-p

2ETON;rettiJkaeP-ot-kaeP 41sp

cca

(rettiJdetalumuccA σ;)

1ETON selcyc00005ot2=n4sp

Δf/f

3ETON;ytilibatSycneuqerF 01±mpp

CSO

emiTpUtratSnoitallicsO 01sm

tuptuO

emiTllaF/esiR

0Q %08ot%02 DBTsp

1Qn/1Q084sp

cdo tuptuO

elcyCytuD

0Q05%

1Qn/1Q05%

.0003-AIStsercevaWgnisuderusaeM

:1ETON

.41ybdedividtluserREB21-e01@jT,0003-AIStsercevaWgnisuderusaeM:2ETON

ehtmorfrorregnimitycneuqerfe

htotdeddaebtsumdnarotallicsoehtybdetubirtnocrorreycneuqerfehtsisihT:3ETON

eeS.ytilibatsycneuqerflatote

htniatbootlatsyrc ytilibatSycneuqerF .noitceSnoitamrofnInoitacilppAehtni

843AGI-106 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 8, 2005

Integrated

Circuit

Systems, Inc.

ICS843I-106

106.25MHZ, LVCMOS, LVPECL

DUAL OUTPUT OSCILLATOR

PRELIMINARY

PARAMETER MEASUREMENT INFORMATION

LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

LVPECL OUTPUT RISE/FALL TIME

3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT

SCOPE

LVCMOS

1.65V ± 0.15V

-1.65V ± 0.15V

Clock

Outputs

20%

80% 80%

20%

tRtF

PERIOD

odc = x 100%

GND

VCC,

VCCO

LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

LVCMOS OUTPUT RISE/FALL TIME

nQ1

Clock

Outputs 20%

80% 80%

20%

SWING

PERIOD

odc = x 100%

3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT

SCOPE

nQx

LVPECL

-1.3V ± 0.3V

VEE

VCC,

VCCO

843AGI-106 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 8, 2005

Integrated

Circuit

Systems, Inc.

ICS843I-106

106.25MHZ, LVCMOS, LVPECL

DUAL OUTPUT OSCILLATOR

PRELIMINARY

APPLICATION INFORMATION

Figure 1. CRYSTAL INPUt INTERFACE

CRYSTAL INPUT INTERFACE

The ICS843I-106 has been characterized with 18pF parallel

resonant crystals. The capacitor values, C1 and C2, shown in

Figure 1 below were determined using a 25MHz, 18pF parallel

resonant crystal and were chosen to minimize the ppm error.

The optimum C1 and C2 values can be slightly adjusted for

different board layouts.

LVCMOS OUTPUT:

An unused LVCMOS output should be terminated with 100Ω

to ground as close as possible to the device.

LVPECL OUTPUT

All unused LVPECL outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential

output pair should either be left floating or terminated.

RECOMMENDATIONS FOR UNUSED OUTPUT PINS

18pF Parallel Cry stal

12p

XTA L_OU T

XTA L_ I N

12p

843AGI-106 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 8, 2005

Integrated

Circuit

Systems, Inc.

ICS843I-106

106.25MHZ, LVCMOS, LVPECL

DUAL OUTPUT OSCILLATOR

PRELIMINARY

TERMINATION FOR 3.3V LVPECL OUTPUT

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs. The two different layouts mentioned

are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, termi-

nating resistors (DC current path to ground) or current sources

must be used for functionality. These outputs are designed to

FIGURE 2B. LVPECL OUTPUT T ERMINATION

FIGURE 2A. LVPECL OUTPUT T ERMINATION

drive 50Ω transmission lines.Matched impedance techniques

should be used to maximize operating frequency and mini-

mize signal distortion. Figures 2A and 2B show two different

layouts which are recommended only as guidelines. Other

suitable clock layouts may exist and it would be recommended

that the board designers simulate to guarantee compatibility

across all printed circuit and clock component process varia-

tions.

- 2V

50Ω50Ω

RTT

= 50Ω

FOUT FIN

RTT = Z

((V

+ V

) / (V

– 2)) – 2

3.3V

125Ω125Ω

84Ω84Ω

Zo = 50Ω

FOUT FIN

FREQUENCY STABILITY

The table shown provides a basic guideline in selecting

the proper quartz crystal that meets a timing budget of

±100ppm. For more information on selecting the proper

retemaraPlacipyTstinU

ecnareloTycneuqerF

03±

mpp

ytilibatSycneuqerF

03±

mpp

sraeY01rofgnigA51±mpp

rotallicsOSCIfoycaruccA01±mpp

ycaruccAecnaticapaCdaoL3±mpp

rorrEgnimiTllarevOlatoT 88±m

crystal, see the application note, Crystal Timing Budget

and Accuracy for FemtoClock™ .

843AGI-106 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 8, 2005

Integrated

Circuit

Systems, Inc.

ICS843I-106

106.25MHZ, LVCMOS, LVPECL

DUAL OUTPUT OSCILLATOR

PRELIMINARY

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS843I-106.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS843I-106 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for VCC = 3.3V + 0.3V = 3.6V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•Power (core)MAX = VCC_MAX * IEE_MAX = 3.6V * 91mA = 327.6mW

•Power (outputs)MAX = 30mW/Loaded Output pair

Total Power_MAX (3.465V, with all outputs switching) = 327.6mW + 30mW = 357.6mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of

the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA

must be used.

Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6A

below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.358W * 90.5°C/W = 117.4°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air

flow, and the type of board (single layer or multi-layer).

TABLE 6A. THERMAL RESISTANCE θθ

θθ

θJA FOR 8-PIN TSSOP, FORCED CONVECTION

θθ

θJA by Velocity (Meters per Second)

0 1 2.5

Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W

TABLE 6B. THERMAL RESISTANCE θθ

θθ

θJA FOR 8 LEAD SOIC FORCED CONVECTION

θθ

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

843AGI-106 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 8, 2005

Integrated

Circuit

Systems, Inc.

ICS843I-106

106.25MHZ, LVCMOS, LVPECL

DUAL OUTPUT OSCILLATOR

PRELIMINARY

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVPECL output driver circuit and termination are shown in Figure 3.

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a

termination

voltage of V

- 2V.

• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V

(VCCO_MAX - VOH_MAX

) = 0.9V

• For logic low, VOUT = VOL_MAX = VCC_MAX

– 1.7V

(VCCO_MAX - VOL_MAX

) = 1.7V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(VOH_MAX

– (VCC_MAX

- 2V))/R

] * (VCC_MAX

- VOH_MAX) = [(2V - (V

CC_MAX - VOH_MAX

))/R

] * (VCC_MAX

- VOH_MAX) =

[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW

Pd_L = [(VOL_MAX

– (VCC_MAX

- 2V))/R

] * (VCC_MAX

- VOL_MAX) = [(2V - (V

CC_MAX - VOL_MAX

))/R

] * (VCC_MAX

- VOL_MAX) =

[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

FIGURE 3. LVPECL DRIVER CIRCUIT AND T ERMINATION

VOUT

VCC

VCC - 2V

843AGI-106 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 8, 2005

Integrated

Circuit

Systems, Inc.

ICS843I-106

106.25MHZ, LVCMOS, LVPECL

DUAL OUTPUT OSCILLATOR

PRELIMINARY

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for ICS843I-106 is: 2376

TABLE 7A. θJAVS. AIR FLOW T ABLE FOR 8 LEAD TSSOP

θθ

θJA by Velocity (Meters per Second)

0 1 2.5

Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W

TABLE 7B. θJAVS. AIR FLOW T ABLE 8 LEAD SOIC

θθ

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

843AGI-106 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 8, 2005

Integrated

Circuit

Systems, Inc.

ICS843I-106

106.25MHZ, LVCMOS, LVPECL

DUAL OUTPUT OSCILLATOR

PRELIMINARY

PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP

TABLE 8A. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MO-153

LOBMYS sretemilliM

muminiMmumixaM

A--02.1

1A50.051.0

2A08.050.1

b91.003.0

c90.002.0

D09.201.3

ECISAB04.6

1E03.405.4

eCISAB56.0

L54

.057.0

α°0°8

aaa--01.0

PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC

TABLE 8B. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MS-012

LOBMYS sretemilliM

MUMINIMMUMIXAM

A53.157.1

1A01.052.0

B33.015.0

C91.052.0

D08.400.5

E08.300.4

eCISAB72.1

H08.502.6

h52.005.0

L04.07

2.1

α°0°8

843AGI-106 www.icst.com/products/hiperclocks.html REV. A NOVEMBER 8, 2005

Integrated

Circuit

Systems, Inc.

ICS843I-106

106.25MHZ, LVCMOS, LVPECL

DUAL OUTPUT OSCILLATOR

PRELIMINARY

TABLE 9. ORDERING INFORMATION

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are

not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS

product for use in life support devices or critical medical instruments.

The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.

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