935285417551 - NXP SEMICONDUCTORS

1. General description

The LPC2388 microcontroller is based on a 16-bit/32-bit ARM7TDMI-S CPU with

real-time emulation that combines the microcontroller with 512 kB of embedded

high-speed flash memory. A 128-bit wide memory interface and a un ique accelerator

architecture enable 32-bit code execution at the maximum clock rate. For critical

performance in interrupt ser vice routines and DSP algorithms, this increases pe rformance

up to 30 % over Thumb mode. For critical code size applications, the alternative 16-bit

Thumb mode reduces code by more than 30 % with minimal performance penalty.

The LPC2388 is ideal for mu lti-purpo se serial communication applications. It incorpora tes

a 10/100 Ethernet Media Access Controller (MAC), USB device/host/OTG with 4 kB of

endpoin t RAM, four UAR Ts, two CAN channels, an SPI inter face, two Synchronous Seria l

Ports (SSP), three I2C-bus interfaces, an I2S-bus interface, and an External Memory

Controller (EMC). This blend of serial communications interfaces combined with an

on-chip 4 MHz internal oscillator , SRAM of 64 kB, 16 kB SRAM for Ethernet, 16 kB SRAM

for USB and general purpose use, together with 2 kB battery powered SRAM make this

device very well suite d for com m un ica tio n ga te wa ys an d protocol convert ers . Various

32-bit timers, an improved 10-bit ADC, 10-bit DAC, PWM unit, a CAN control unit, and up

to 104 fast GPIO lines with up to 50 edge and up to four level sensitive external interrupt

pins make these microcontrollers particularly suitable for industrial control and medical

systems.

2. Features and benefits

ARM7TDMI-S processor, running at up to 72 MHz.

Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and

In-Application Programming (IAP) capabilities. Flash program memory is on th e ARM

local bus for high performance CPU access.

64 kB of SRAM on the ARM local bus for high performance CPU access.

16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.

16 kB SRAM for general purpose DM A use also accessible by the USB.

Dual Advanced High-performance Bus (AHB) system that provides for simultaneous

Ethernet DMA, USB DMA, and program execution from on-chip flash with no

contention between those functions. A bus bridge allows the Ethernet DMA to access

the other AHB subsy ste m .

EMC provides support for static devices such as flash and SRAM as well as off- chip

memory mapped peripherals.

Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.

LPC2388

Single-chip 16-bit/32-bit micro; 512 kB flash with ISP/IAP,

Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit ADC/DAC

Rev. 3 — 15 October 2013 Product data sheet

Product data sheet Rev. 3 — 15 October 2013 2 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP

serial interfaces, the I2S-bus port, and the Secure Digital/MultiMediaCard (SD/MMC)

card port, as well as for memory-to-memory transfers.

Serial Interfaces:

Ethernet MAC with associated DMA controller. These functions reside on an

independent AHB.

USB 2.0 device/ho st/O T G with on- ch ip PHY an d as so ciat ed DMA co nt ro ller.

Four UARTs with fr actiona l bau d rate ge ner ation, o ne with mo dem cont rol I/O, one

with IrDA support, all with FIFO.

CAN controller with two channels.

SPI controller.

Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate

for the SPI port, sharing it s interrupt and pin s. These can be used with the GPDMA

controller.

Three I2C-bus interfaces (one with open-drain and two with standard port pins).

I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with

the GPDMA.

Other periph er als :

SD/MMC memory card interface.

104 General purpose I/O pins with configurable pull-up/down resistors.

10-bit ADC with input multiplexing among 8 pins.

10-bit DAC.

Four general purpose timers/counters with 8 capture inputs and 10 compare

outputs. Each timer block has an external count input.

One PWM/timer block with support for three-phase motor control. The PWM has

two external count inputs.

Real-Time Clock (RTC) with separate power pin, clock source can be the RTC

oscillator or the APB clock.

2 kB SRAM powered from the R TC power pin, allowing dat a to be sto red when the

rest of the chip is powered off.

WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,

the RTC oscillator, or the APB clock.

Standard ARM test/debug interface for compatibility with existing tools.

Emulation trace module supports real-time trace.

Single 3.3 V power supply (3.0 V to 3.6 V).

Four reduced power modes: Idle, Sleep, Power-down and Deep power-down.

Four external interrupt inputs configurable as edge/level sensitive. All pins on Port 0

and Port 2 can be used as edge sensitive interrupt sources.

Processor wake-up from Power-down mode via any interrupt able to operate during

Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet

wake-up interrupt).

Two independent power domains allow fine tuning of power consumption based on

needed features.

Each peripheral ha s its own clock divider for further power saving.

Brownout detect with separate thresholds for interrupt and forced reset.

On-chip power-on reset.

On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.

Product data sheet Rev. 3 — 15 October 2013 3 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as

the system clock. When used as the CPU clock, does not allow CAN and USB to run.

On-chip PLL allows CPU operation up to the maximum CPU rate without the need for

a high frequency crystal. May be run from the main oscillator, the internal RC oscillator ,

or the RTC oscillator.

Boundary scan for simplified board testing.

Versatile pin function selections allow more possibilities for using on-chip peripheral

functions.

3. Applications

Industrial control

Medical systems

Protocol converter

Communications

4. Ordering information

4.1 Ordering options

Table 1. Ordering information

Type number Package

Name Description Version

LPC2388FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1

Table 2. Ordering options

Type number Flash

(kB) SRAM (kB) External bus Ether

net USB

device

host

OTG+

4kB

FIFO

CAN channels

SD/

MMC GP

DMA

ADC channels

DAC channels

Temp

range

Local bus

Ethernet buffer

GP/USB

RTC

Total

LPC2388FBD144 512 64 16 16 2 98 MiniBus: 8 data, 16

address, and 2 chip

select lines

RMII yes 2 yes yes 8 1 40 C to

+85 C

Product data sheet Rev. 3 — 15 October 2013 4 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

5. Block diagram

Fig 1. LPC2388 block diagram

PWM1

ARM7TDMI-S

PLL

EINT3 to EINT0

FLASH

P3, P4

P0, P1, P2,

LEGACY GPI/O

56 PINS TOTAL

P0, P1

SCK, SCK0

MOSI, MOSI0

SSEL, SSEL0

SCK1

MOSI1

MISO1

SSEL1

SCL0, SCL1, SCL2

I2SRX_CLK

I2STX_CLK

I2SRX_WS

I2STX_WS

8 × AD0

RTCX1

RTCX2

MCICLK, MCIPWR

RXD0, RXD2, RXD3

TXD1

RXD1

RD1, RD2

TD1, TD2

CAN1, CAN2

USB port 1

XTAL1

TCK TDOEXTIN0

XTAL2

RESET

TRST

TDITMS

HIGH-SPEED

GPI/O

104 PINS

TOTAL

LPC2388

USB port 2

64 kB

SRAM 512 kB

FLASH

INTERNAL

CONTROLLERS

TEST/DEBUG

INTERFACE

EMULATION

TRACE MODULE

trace signals

AHB

BRIDGE AHB

BRIDGE

ETHERNET

MAC WITH

DMA

16 kB

SRAM

MASTER

PORT AHB T O

AHB BRIDGE SLAVE

PORT

system

clock

SYSTEM

FUNCTIONS

INTERNAL RC

OSCILLATOR

VDDA

VDD(3V3)

VREF

VSSA, VSS

VECTORED

INTERRUPT

CONTROLLER

16 kB

SRAM

USB WITH

4 kB RAM

AND DMA

GP DMA

CONTROLLER

I2S INTERFACE

SPI, SSP0 INTERFACE

I2SRX_SDA

I2STX_SDA

MISO, MISO0

SSP1 INTERFACE

SD/MMC CARD

INTERFACE MCICMD,

MCIDAT[3:0]

TXD0, TXD2, TXD3

UART0, UART2, UART3

UART1 DTR1, RTS1

DSR1, CTS1, DCD1,

RI1

I2C0, I2C1, I2C2 SDA0, SDA1, SDA2

EXTERNAL INTERRUPTS

CAPTURE/COMPARE

TIMER0/TIMER1/

TIMER2/TIMER3

A/D CONVERTER

D/A CONVERTER

2 kB BATTERY RAM

RTC

OSCILLATOR

REAL-

TIME

CLOCK

W ATCHDOG TIMER

SYSTEM CONTROL

2 × CAP0/CAP1/

CAP2/CAP3

4 × MAT2,

2 × MAT0/MAT1/

MAT3

6 × PWM1

2 × PCAP1

AOUT

VBAT

AHB T O

APB BRIDGE

SRAM

RMII(8)

VBUS

002aad332

P0, P2

power domain 2

AHB2 AHB1

power domain 2

VDD(DCDC)(3V3)

A[15:0]

D[7:0]

EXTERNAL

MEMORY

CONTROLLER OE, CS0, CS1,

BLS0

ALARM

Product data sheet Rev. 3 — 15 October 2013 5 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 2. LPC2 388 pinning

LPC2388FBD144

108

144

109

002aad333

Table 3. Pin description

Symbol Pin Type Description

P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The

operation of port 0 pins depends upon the pin function selected via the Pin Connect

block.

P0[0]/RD1/TXD3/

SDA1 66[1] I/O P0[0] — General purpose digital input/output pin.

IRD1 — CAN1 receiver input.

OTXD3 — Transmitter output for UART3.

I/O SDA1 — I2C1 data input/output (this is not an open-drain pin).

P0[1]/TD1/RXD3/

SCL1 67[1] I/O P0[1] — General purpose digital input/output pin.

OTD1 — CAN1 transmitter output.

IRXD3 — Receiver input for UART3.

I/O SCL1 — I2C1 clock input/output (this is not an open-drain pin).

P0[2]/TXD0 141[1] I/O P0[2] — General purpose digital input/output pin.

OTXD0 — Transmitter output for UART0.

P0[3]/RXD0 142[1] I/O P0[3] — General purpose digital input/output pin.

IRXD0 — Receiver input for UART0.

P0[4]/

I2SRX_CLK/

RD2/CAP2[0]

116[1] I/O P0[4] — General purpose digital input/output pin.

I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave.

Corresponds to the signal SCK in the I2S-bus specification.

IRD2 — CAN2 receiver input.

ICAP2[0] — Capture input for Timer 2, channel 0.

Product data sheet Rev. 3 — 15 October 2013 6 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

P0[5]/

I2SRX_WS/

TD2/CAP2[1]

115[1] I/O P0[5] — General purpose digital input/output pin.

I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the

slave. Corresponds to the signal WS in the I2S-bus specification.

OTD2 — CAN2 transmitter output.

ICAP2[1] — Capture input for Timer 2, channel 1.

P0[6]/

I2SRX_SDA/

SSEL1/MAT2[0]

113[1] I/O P0[6] — General purpose digital input/output pin.

I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the I2S-bus specification.

I/O SSEL1 — Slave Select for SSP1.

OMAT2[0] — Match output for Timer 2, channel 0.

P0[7]/

I2STX_CLK/

SCK1/MAT2[1]

112[1] I/O P0[7] — General purpose digital input/output pin.

I/O I2STX_CLK — T ransmit Clock. It is driven by the master and received by the slave.

Corresponds to the signal SCK in the I2S-bus specification.

I/O SCK1 — Serial Clock for SSP1.

OMAT2[1] — Match output for Timer 2, channel 1.

P0[8]/

I2STX_WS/

MISO1/MAT2[2]

111[1] I/O P0[8] — General purpose digital input/output pin.

I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the

slave. Corresponds to the signal WS in the I2S-bus specification.

I/O MISO1 — Master In Slave Out for SSP1.

OMAT2[2] — Match output for Timer 2, channel 2.

P0[9]/

I2STX_SDA/

MOSI1/MAT2[3]

109[1] I/O P0[9] — General purpose digital input/output pin.

I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the I2S-bus specification.

I/O MOSI1 — Master Out Slave In for SSP1.

OMAT2[3] — Match output for Timer 2, channel 3.

P0[10]/TXD2/

SDA2/MAT3 [0] 69[1] I/O P0[10] — General purpose digital input/output pin.

OTXD2 — Transmitter output for UART2.

I/O SDA2 — I2C2 data input/output (this is not an open-drain pin).

OMAT3[0] — Match output for Timer 3, channel 0.

P0[11]/RXD2/

SCL2/MAT3[1] 70[1] I/O P0[11] — General purpose digital input/output pin.

IRXD2 — Receiver input for UART2.

I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin).

OMAT3[1] — Match output for Timer 3, channel 1.

P0[12]/

USB_PPWR2/

MISO1/AD0[6]

29[2] I/O P0[12] — General purpose digital input/output pin.

OUSB_PPWR2 — Port power enable signal for USB port 2.

I/O MISO1 — Master In Slave Out for SSP1.

IAD0[6] — A/D converter 0, input 6.

Table 3. Pin description …continued

Symbol Pin Type Description

Product data sheet Rev. 3 — 15 October 2013 7 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

P0[13]/

USB_UP_LED2/

MOSI1/AD0[7]

32[2] I/O P0[13] — General purpose digital input/output pin.

OUSB_UP_LED2 — USB port 2 GoodLink LED indicator. It is LOW when device is

configured (non-control endpoints enabled), or when host is enabled and has

detected a device on the bus. It is HIGH when the device is not configured, or when

host is enabled and has not detected a device on the bus, or during global suspend.

It transitions between LOW and HIGH (flashes) when host is enabled and detects

activity on the bus.

I/O MOSI1 — Master Out Slave In for SSP1.

IAD0[7] — A/D converter 0, input 7.

P0[14]/

USB_HSTEN2/

USB_CONNECT2/

SSEL1

48[1] I/O P0[14] — General purpose digital input/output pin.

OUSB_HSTEN2 — Host Enabled status for USB port 2.

OUSB_CONNECT2 — SoftConnect control for USB port 2. Signal used to switch an

external 1.5 k resistor under software control. Used with the SoftConnect USB

feature.

I/O SSEL1 — Slave Select for SSP1.

P0[15]/TXD1/

SCK0/SCK 89[1] I/O P0[15] — General purpose digital input/output pin.

OTXD1 — Transmitter output for UART1.

I/O SCK0 — Serial clock for SSP0.

I/O SCK — Serial clock for SPI.

P0[16]/RXD1/

SSEL0/SSEL 90[1] I/O P0[16] — General purpose digital input/output pin.

IRXD1 — Receiver input for UART1.

I/O SSEL0 — Slave Select for SSP0.

I/O SSEL — Slave Select for SPI.

P0[17]/CTS1/

MISO0/MISO 87[1] I/O P0[17] — General purpose digital input/output pin.

ICTS1 — Clear to Send input for UART1.

I/O MISO0 — Master In Slave Out for SSP0.

I/O MISO — Master In Slave Out for SPI.

P0[18]/DCD1/

MOSI0/MOSI 86[1] I/O P0[18] — General purpose digital input/output pin.

IDCD1 — Data Carrier Detect input for UART1.

I/O MOSI0 — Master Out Slave In for SSP0.

I/O MOSI — Master Out Slave In for SPI.

P0[19]/DSR1/

MCICLK/SDA1 85[1] I/O P0[19] — General purpose digital input/output pin.

IDSR1 — Data Set Ready input for UART1.

OMCICLK — Clock output line for SD/MMC interfa ce.

I/O SDA1 — I2C1 data input/output (this is not an open-drain pin).

P0[20]/DTR1/

MCICMD/SCL1 83[1] I/O P0[20] — General purpose digital input/output pin.

ODTR1 — Data Terminal Ready output for UART1.

IMCICMD — Command line for SD/MMC interface.

I/O SCL1 — I2C1 clock input/output (this is not an open-drain pin).

P0[21]/RI1/

MCIPWR/RD1 82[1] I/O P0[21] — General purpose digital input/output pin.

IRI1 — Ring Indicator input for UART1.

OMCIPWR — Power Supply Enable for external SD/MMC power supply.

IRD1 — CAN1 receiver input.

Table 3. Pin description …continued

Symbol Pin Type Description

Product data sheet Rev. 3 — 15 October 2013 8 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

P0[22]/RTS1/

MCIDAT0/TD1 80[1] I/O P0[22] — General purpose digital input/output pin.

ORTS1 — Request to Send output for UART1.

OMCIDAT0 — Data line for SD/MMC interface.

OTD1 — CAN1 transmitter output.

P0[23]/AD0[0]/

I2SRX_CLK/

CAP3[0]

13[2] I/O P0[23] — General purpose digital input/output pin.

IAD0[0] — A/D converter 0, input 0.

I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave.

Corresponds to the signal SCK in the I2S-bus specification.

ICAP3[0] — Capture input for Timer 3, channel 0.

P0[24]/AD0[1]/

I2SRX_WS/

CAP3[1]

11[3] I/O P0[24] — General purpose digital input/output pin.

IAD0[1] — A/D converter 0, input 1.

I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the

slave. Corresponds to the signal WS in the I2S-bus specification.

ICAP3[1] — Capture input for Timer 3, channel 1.

P0[25]/AD0[2]/

I2SRX_SDA/

TXD3

10[2] I/O P0[25] — General purpose digital input/output pin.

IAD0[2] — A/D converter 0, input 2.

I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the I2S-bus specification.

OTXD3 — Transmitter output for UART3.

P0[26]/AD0[3]/

AOUT/RXD3 8[2] I/O P0[26] — General purpose digital input/output pin.

IAD0[3] — A/D converter 0, input 3.

OAOUT — D/A converter output.

IRXD3 — Receiver input for UART3.

P0[27]/SDA0 35[4] I/O P0[27] — General purpose digital input/output pin. The output is open-drain.

I/O SDA0 — I2C0 data input/output. Open-drain output (for I2C-bus compliance).

P0[28]/SCL0 34[4] I/O P0[28] — General purpose digital input/output pin. The output is open-dr ain.

I/O SCL0 — I2C0 clock input/output. Open-drain output (for I2C-bus compliance).

P0[29]/USB_D+1 42[5] I/O P0[29] — General purpose digital input/output pin.

I/O USB_D+1 — USB port 1 bidirectional D+ line.

P0[30]/USB_D143

[5] I/O P0[30] — General purpose digital input/output pin.

I/O USB_D1 — USB port 1 bidirectional D line.

P0[31]/USB_D+2 36[5] I/O P0[31] — General purpose digital input/output pin.

I/O USB_D+2 — USB port 2 bidirectional D+ line.

P1[0] to P1[31] I/O Port 1: Port 1 is a 32-bit I/O port with individual direction controls for each bit. The

operation of port 1 pins depends upon the pin function selected via the Pin Connect

block. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available.

P1[0]/

ENET_TXD0 136[1] I/O P1[0] — General purpose digital input/o utput pin.

OENET_TXD0 — Ethernet tr an smi t da ta 0.

P1[1]/

ENET_TXD1 135[1] I/O P1[1] — General purpose digital input/o utput pin.

OENET_TXD1 — Ethernet tr an smi t da ta 1.

P1[4]/

ENET_TX_EN 133[1] I/O P1[4] — General purpose digital input/o utput pin.

OENET_TX_EN — Ethernet transmit data enable.

Table 3. Pin description …continued

Symbol Pin Type Description

Product data sheet Rev. 3 — 15 October 2013 9 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

P1[8]/

ENET_CRS 132[1] I/O P1[8] — General purpose digital input/output pin.

IENET_CRS — Ethernet carrier sense.

P1[9]/

ENET_RXD0 131[1] I/O P1[9] — General purpose di gital input/o utput pin.

IENET_RXD0 — Ethernet receive data.

P1[10]/

ENET_RXD1 129[1] I/O P1[10] — General purpose digital input/output pin.

IENET_RXD1 — Ethernet receive data.

P1[14]/

ENET_RX_ER 128[1] I/O P1[14] — General purpose digital input/output pin.

IENET_RX_ER — Ethernet receive error.

P1[15]/

ENET_REF_CLK 126[1] I/O P1[15] — General purpose digital input/output pin.

IENET_REF_CLK/ENET_RX_CLK — Ethernet receiver clock.

P1[16]/

ENET_MDC 125[1] I/O P1[16] — General purpose digital input/output pin.

OENET_MDC — Ethernet MIIM clock.

P1[17]/

ENET_MDIO 123[1] I/O P1[17] — General purpose digital input/output pin.

I/O ENET_MDIO — Ethernet MI data input and output.

P1[18]/

USB_UP_LED1/

PWM1[1]/

CAP1[0]

46[1] I/O P1[18] — General purpose digital input/output pin.

OUSB_UP_LED1 — USB port 1 GoodLink LED indicator. It is LOW when device is

configured (non-control endpoints enabled), or when host is enabled and has

detected a device on the bus. It is HIGH when the device is not configured, or when

host is enabled and has not detected a device on the bus, or during global suspend.

It transitions between LOW and HIGH (flashes) when host is enabled and detects

activity on the bus.

OPWM1[1] — Pulse W idth Modulator 1, channel 1 output.

ICAP1[0] — Capture input for Timer 1, channel 0.

P1[19]/

USB_TX_E1/

USB_PPWR1/

CAP1[1]

47[1] I/O P1[19] — General purpose digital input/output pin.

OUSB_TX_E1 — Transmit Enable signal for USB port 1 (OTG transceiver).

OUSB_PPWR1 — Port Power enable signal for USB port 1.

ICAP1[1] — Capture input for Timer 1, channel 1.

P1[20]/

USB_TX_DP1/

PWM1[2]/SCK0

49[1] I/O P1[20] — General purpose digital input/output pin.

OUSB_TX_DP1 — D+ transmit data for USB port 1 (OTG transceiver).

OPWM1[2] — Pulse W idth Modulator 1, channel 2 output.

I/O SCK0 — Serial clock for SSP0.

P1[21]/

USB_TX_DM1/

PWM1[3]/SSEL0

50[1] I/O P1[21] — General purpose digital input/output pin.

OUSB_TX_DM1 — D transmit data for USB port 1 (OTG transceiver).

OPWM1[3] — Pulse W idth Modulator 1, channel 3 output.

I/O SSEL0 — Slave Select for SSP0.

P1[22]/

USB_RCV1/

USB_PWRD1/

MAT1[0]

51[1] I/O P1[22] — General purpose digital input/output pin.

IUSB_RCV1 — Differential receive data for USB port 1 (OTG transceiver).

IUSB_PWRD1 — Power Status for USB port 1 (host power switch).

OMAT1[0] — Match output for Timer 1, channel 0.

Table 3. Pin description …continued

Symbol Pin Type Description

Product data sheet Rev. 3 — 15 October 2013 10 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

P1[23]/

USB_RX_DP1/

PWM1[4]/MISO0

53[1] I/O P1[23] — General purpose digital input/output pin.

IUSB_RX_DP1 — D+ receive data for USB port 1 (OTG transceiver).

OPWM1[4] — Pulse W idth Modulator 1, channel 4 output.

I/O MISO0 — Master In Slave Out for SSP0.

P1[24]/

USB_RX_DM1/

PWM1[5]/MOSI0

54[1] I/O P1[24] — General purpose digital input/output pin.

IUSB_RX_DM1 — D receive data for USB port 1 (OTG transceiver).

OPWM1[5] — Pulse W idth Modulator 1, channel 5 output.

I/O MOSI0 — Master Out Slave in for SSP0.

P1[25]/

USB_LS1/

USB_HSTEN1/

MAT1[1]

56[1] I/O P1[25] — General purpose digital input/output pin.

OUSB_LS1 — Low-speed status for USB port 1 (OTG transceiver).

OUSB_HSTEN1 — Host Enabled status for USB port 1.

OMAT1[1] — Match output for Timer 1, channel 1.

P1[26]/

USB_SSPND1/

PWM1[6]/

CAP0[0]

57[1] I/O P1[26] — General purpose digital input/output pin.

OUSB_SSPND1 — USB port 1 bus suspend status (OTG transceiver).

OPWM1[6] — Pulse W idth Modulator 1, channel 6 output.

ICAP0[0] — Capture input for Timer 0, channel 0.

P1[27]/

USB_INT1/

USB_OVRCR1/

CAP0[1]

61[1] I/O P1[27] — General purpose digital input/output pin.

IUSB_INT1 — USB port 1 OTG transceiver interrupt (OTG transceiver).

IUSB_OVRCR1 — USB port 1 Over-Current status.

ICAP0[1] — Capture input for Timer 0, channel 1.

P1[28]/

USB_SCL1/

PCAP1[0]/

MAT0[0]

63[1] I/O P1[28] — General purpose digital input/output pin.

I/O USB_SCL1 — USB port 1 I2C-bus serial clock (OTG transceiver).

IPCAP1[0] — Capture input for PWM1, chan nel 0.

OMAT0[0] — Match output for Timer 0, channel 0.

P1[29]/

USB_SDA1/

PCAP1[1]/

MAT0[1]

64[1] I/O P1[29] — General purpose digital input/output pin.

I/O USB_SDA1 — USB port 1 I2C-bus serial data (OTG transceiver).

IPCAP1[1] — Capture input for PWM1, chan nel 1.

OMAT0[1] — Match output for Timer 0, channel 0.

P1[30]/

USB_PWRD2/

VBUS/AD0[4]

30[2] I/O P1[30] — General purpose digital input/output pin.

IUSB_PWRD2 — Power Status for USB port 2.

IVBUS — Monitors the presence of USB bus power.

Note: This signal must be HIGH for USB reset to occur.

IAD0[4] — A/D converter 0, input 4.

P1[31]/

USB_OVRCR2/

SCK1/AD0[5]

28[2] I/O P1[31] — General purpose digital input/output pin.

IUSB_OVRCR2 — Over-Current status for USB port 2.

I/O SCK1 — Serial Clock for SSP1.

IAD0[5] — A/D converter 0, input 5.

P2[0] to P2[31] I/O Port 2: Port 2 is a 32 bit I/O port with individual direction controls for each bit. The

operation of port 2 pins depends upon the pin function selected via the Pin Connect

block. Pins 14 through 31 of this port are not available.

Table 3. Pin description …continued

Symbol Pin Type Description

Product data sheet Rev. 3 — 15 October 2013 11 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

P2[0]/PWM1[1]/

TXD1/

TRACECLK

107[1] I/O P2[0] — General purpose digital input/output pin.

OPWM1[1] — Pulse W idth Modulator 1, channel 1 output.

OTXD1 — Transmitter output for UART1.

OTRACECLK — Trace Clock.

P2[1]/PWM1[2]/

RXD1/

PIPESTAT0

106[1] I/O P2[1] — General purpose digital input/output pin.

OPWM1[2] — Pulse W idth Modulator 1, channel 2 output.

IRXD1 — Receiver input for UART1.

OPIPESTAT0 — Pipelin e Status, bit 0.

P2[2]/PWM1[3]/

CTS1/

PIPESTAT1

105[1] I/O P2[2] — General purpose digital input/output pin.

OPWM1[3] — Pulse W idth Modulator 1, channel 3 output.

ICTS1 — Clear to Send input for UART1.

OPIPESTAT1 — Pipelin e Status, bit 1.

P2[3]/PWM1[4]/

DCD1/

PIPESTAT2

100[1] I/O P2[3] — General purpose digital input/output pin.

OPWM1[4] — Pulse W idth Modulator 1, channel 4 output.

IDCD1 — Data Carrier Detect input for UART1.

OPIPESTAT2 — Pipelin e Status, bit 2.

P2[4]/PWM1[5]/

DSR1/

TRACESYNC

99[1] I/O P2[4] — General purpose digital input/output pin.

OPWM1[5] — Pulse W idth Modulator 1, channel 5 output.

IDSR1 — Data Set Ready input for UART1.

OTRACESYNC — Trace Synchronization.

P2[5]/PWM1[6]/

DTR1/

TRACEPKT0

97[1] I/O P2[5] — General purpose digital input/output pin.

OPWM1[6] — Pulse W idth Modulator 1, channel 6 output.

ODTR1 — Data Terminal Ready output for UART1.

OTRACEPKT0 — Trace Packet, bit 0.

P2[6]/PCAP1[0]/

RI1/

TRACEPKT1

96[1] I/O P2[6] — General purpose digital input/output pin.

IPCAP1[0] — Capture input for PWM1, chan nel 0.

IRI1 — Ring Indicator input for UART1.

OTRACEPKT1 — Trace Packet, bit 1.

P2[7]/RD2/

RTS1/

TRACEPKT2

95[1] I/O P2[7] — General purpose digital input/output pin.

IRD2 — CAN2 receiver input.

ORTS1 — Request to Send output for UART1.

OTRACEPKT2 — Trace Packet, bit 2.

P2[8]/TD2/

TXD2/

TRACEPKT3

93[1] I/O P2[8] — General purpose digital input/output pin.

OTD2 — CAN2 transmitter output.

OTXD2 — Transmitter output for UART2.

OTRACEPKT3 — Trace Packet, bit 3.

Table 3. Pin description …continued

Symbol Pin Type Description

Product data sheet Rev. 3 — 15 October 2013 12 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

P2[9]/

USB_CONNECT1/

RXD2/

EXTIN0

92[1] I/O P2[9] — General purpose digital input/output pin.

OUSB_CONNECT1 — USB port 1 SoftConnect control. Signal used to switch an

external 1.5 k resistor under the software control. Used with the SoftConnect USB

feature.

IRXD2 — Receiver input for UART2.

IEXTIN0 — External Trigger Input.

P2[10]/EINT0 76[6] I/O P2[10] — General purpose digital input/output pin.

Note: LOW on this pin while RESET is LOW forces on-chip boot-loader to take over

control of the part after a reset.

IEINT0 — External interrupt 0 input.

P2[11]/EINT1/

MCIDAT1/

I2STX_CLK

75[6] I/O P2[11] — Ge neral purpose digital input/output pin.

IEINT1 — External interru pt 1 input.

OMCIDAT1 — Data line for SD/MMC interface.

I/O I2STX_CLK — T ransmit Clock. It is driven by the master and received by the slave.

Corresponds to the signal SCK in the I2S-bus specification.

P2[12]/EINT2/

MCIDAT2/

I2STX_WS

73[6] I/O P2[12] — General purpose digital input/output pin.

IEINT2 — External interru pt 2 input.

OMCIDAT2 — Data line for SD/MMC interface.

I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the

slave. Corresponds to the signal WS in the I2S-bus specification.

P2[13]/EINT3/

MCIDAT3/

I2STX_SDA

71[6] I/O P2[13] — General purpose digital input/output pin.

IEINT3 — External interru pt 3 input.

OMCIDAT3 — Data line for SD/MMC interface.

I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the I2S-bus specification.

P3[0] to P3[31] I/O Port 3: Port 3 is a 32 bit I/O port with individual direction controls for each bit. The

operation of port 3 pins depends upon the pin function selected via the Pin Connect

block. Pins 8 through 22, and 27 through 31 of this port are not available.

P3[0]/D0 137[1] I/O P3[0] — General purpose digital input/output pin.

I/O D0 — External memory data line 0.

P3[1]/D1 140[1] I/O P3[1] — General purpose digital input/output pin.

I/O D1 — External memory data line 1.

P3[2]/D2 144[1] I/O P3[2] — General purpose digital input/output pin.

I/O D2 — External memory data line 2.

P3[3]/D3 2[1] I/O P3[3] — General purpose digital input/output pin.

I/O D3 — External memory data line 3.

P3[4]/D4 9[1] I/O P3[4] — General purpose digital input/output pin.

I/O D4 — External memory data line 4.

P3[5]/D5 12[1] I/O P3[5] — General purpose digital input/output pin.

I/O D5 — External memory data line 5.

P3[6]/D6 16[1] I/O P3[6] — General purpose digital input/output pin.

I/O D6 — External memory data line 6.

Table 3. Pin description …continued

Symbol Pin Type Description

Product data sheet Rev. 3 — 15 October 2013 13 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

P3[7]/D7 19[1] I/O P3[7] — General purpose digital input/output pin.

I/O D7 — External memory data line 7.

P3[23]/CAP0[0]/

PCAP1[0] 45[1] I/O P3[23] — General purpose digital input/output pin.

ICAP0[0] — Capture input for Timer 0, channel 0.

IPCAP1[0] — Capture input for PWM1, chan nel 0.

P3[24]/CAP0[1]/

PWM1[1] 40[1] I/O P3[24] — General purpose digital input/output pin.

ICAP0[1] — Capture input for Timer 0, channel 1.

OPWM1[1] — Pulse W idth Modula tor 1, output 1.

P3[25]/MAT0[0]/

PWM1[2] 39[1] I/O P3[25] — General purpose digital input/output pin.

OMAT0[0] — Match output for Timer 0, channel 0.

OPWM1[2] — Pulse W idth Modula tor 1, output 2.

P3[26]/MAT0[1]/

PWM1[3] 38[1] I/O P3[26] — General purpose digital input/output pin.

OMAT0[1] — Match output for Timer 0, channel 1.

OPWM1[3] — Pulse W idth Modula tor 1, output 3.

P4[0] to P4[31] I/O Port 4: Port 4 is a 32 bit I/O port with individual direction controls for each bit. The

operation of port 4 pins depends upon the pin function selected via the Pin Connect

block. Pins 16 through 23, 26, and 27 of this port are not available.

P4[0]/A0 52[1] I/O P4[0] — ]Gene ral purpose digital input/output pin.

I/O A0 — External memory address line 0.

P4[1]/A1 55[1] I/O P4[1] — Gen eral purpose digital input/output pin.

I/O A1 — External memory address line 1.

P4[2]/A2 58[1] I/O P4[2] — Gen eral purpose digital input/output pin.

I/O A2 — External memory address line 2.

P4[3]/A3 68[1] I/O P4[3] — Gen eral purpose digital input/output pin.

I/O A3 — External memory address line 3.

P4[4]/A4 72[1] I/O P4[4] — Gen eral purpose digital input/output pin.

I/O A4 — External memory address line 4.

P4[5]/A5 74[1] I/O P4[5] — Gen eral purpose digital input/output pin.

I/O A5 — External memory address line 5.

P4[6]/A6 78[1] I/O P4[6] — Gen eral purpose digital input/output pin.

I/O A6 — External memory address line 6.

P4[7]/A7 84[1] I/O P4[7] — Gen eral purpose digital input/output pin.

I/O A7 — External memory address line 7.

P4[8]/A8 88[1] I/O P4[8] — Gen eral purpose digital input/output pin.

I/O A8 — External memory address line 8.

P4[9]/A9 91[1] I/O P4[9] — Gen eral purpose digital input/output pin.

I/O A9 — External memory address line 9.

P4[10]/A10 94[1] I/O P4[10] — General purpose digital input/output pin.

I/O A10 — External memory address line 10.

P4[11]/A11 101[1] I/O P4[11] — General purpose digital input/output pin.

I/O A11 — External memory address line 11.

Table 3. Pin description …continued

Symbol Pin Type Description

Product data sheet Rev. 3 — 15 October 2013 14 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

P4[12]/A12 104[1] I/O P4[12] — General purpose digital input/output pin.

I/O A12 — External memory address line 12.

P4[13]/A13 108[1] I/O P4[13] — General purpose digital input/output pin.

I/O A13 — External memory address line 13.

P4[14]/A14 110[1] I/O P4[14] — General purpose digital input/output pin.

I/O A14 — External memory address line 14.

P4[15]/A15 120[1] I/O P4[15] — General purpose digital input/output pin.

I/O A15 — External memory address line 15.

P4[24]/OE 127[1] I/O P4[24] — General purpose digital input/output pin.

OOE — LOW active Output Enable signal.

P4[25]/BLS0 124[1] I/O P4[25] — General purpose digital input/output pin.

OBLS0 — LOW active Byte Lane select signal 0.

P4[28]/MAT2[0]/

TXD3 118[1] I/O P4[28] — General purpose digital input/output pin.

OMAT2[0] — Match output for Timer 2, channel 0.

OTXD3 — Transmitter output for UART3.

P4[29]/MAT2[1]/

RXD3 122[1] I/O P4[29] — General purpose digital input/output pin.

OMAT2[1] — Match output for Timer 2, channel 1.

IRXD3 — Receiver input for UART3.

P4[30]/CS0 130[1] I/O P4[30] — General purpose digital input/output pin.

OCS0 — LOW active Chip Select 0 signal.

P4[31]/CS1 134[1] I/O P4[31] — General purpose digital input/output pin.

OCS1 — LOW active Chip Select 1 signal.

ALARM 26[8] OALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH when a RTC

alarm is generated.

USB_D2 37 I/O USB_D2 — USB port 2 bidirectional D line.

DBGEN 6[1][9] IDBGEN — JTAG interface control signal. Also used for boundary scanning.

TDO 1[1][10] OTDO — Test Data out for JTAG interface.

TDI 3[1][9] ITDI — Test Data in for JTAG interface.

TMS 4[1][9] ITMS — Test Mode Select for JTAG interface.

TRST 5[1][9] ITRST — Test Reset for JTAG interface.

TCK 7[1][10] ITCK — Test Clock for JTAG interface. Th is clock must be slower than 1⁄6 of the CPU

clock (CCLK) for the JTAG interface to operate.

RTCK 143[1][9] I/O RTCK — JTAG interface control signal.

Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate

as Trace port after reset.

RSTOUT 20 O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2388 being in Reset

state.

RESET 24[7] Iexternal reset input: A LOW on this pin re sets the device, causing I/O ports and

peripherals to take on their default states, and processor execution to begin at

address 0. TTL with hysteresis, 5 V tolerant.

XTAL1 31[8][11] I Input to the oscilla tor circuit and internal clock generator circuits.

XTAL2 33[8][11] O Output from the oscillator amplifier.

Table 3. Pin description …continued

Symbol Pin Type Description

Product data sheet Rev. 3 — 15 October 2013 15 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.

[2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a DAC input,

digital section of the pad is disabled.

[3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,

digital section of the pad is disabled.

[4] Open-drain 5 V tolerant digital I/O pad compatible with I2C-bus 400 kHz specification. It requires an external pull-up to provide output

functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain

configuration applies to all functions on this pin.

[5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and

Low-speed mode only).

[6] 5 V tolerant pad with 10 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.

[7] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.

[8] Pad provides special analog functionality.

[9] This pin has a built-in pull-up resistor.

[10] This pin has no built-in pull-up and no built-in pull-down resistor.

[11] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding

is preferred to reduce susceptibility to noise). XTAL2 should be left floating.

[12] If the RTC is not used, these pins can be left floating.

[13] Pad provides special analog functionality.

[14] Pad provides special analog functionality.

[15] Pad provides special analog functionality.

[16] Pad provides special analog functionality.

[17] Pad provides special analog functionality.

RTCX1 23[8][12] I Input to the RTC oscillator circuit.

RTCX2 25[8][12] O Output from the RTC oscillator circuit.

VSS 22, 44,

59, 65,

79, 103,

117,119,

139[13]

Iground: 0 V reference.

VSSA 15[14] Ianalog ground: 0 V reference. This should nominally be the same voltage as VSS,

but should be isolated to minimize noise and error.

VDD(3V3) 41, 62,

77, 102,

114,

138[15]

I3.3 V supply voltage: This is the power supply voltage for the I/O ports.

n.c. 21, 81,

98[16] I Leave these pins unconnected.

VDD(DCDC)(3V3) 18, 60,

121[17] I3.3 V DC-to-DC converter supply voltage: This is the power supply for the on-chip

DC-to-DC converter only.

VDDA 14[18] Ianalog 3.3 V pad supply voltage: This should be nominally the same voltage as

VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to

power the ADC and DAC.

VREF 17[18] IADC reference: This should be nominally the same voltage as VDD(3V3) but should

be isolated to minimize noise and error. The level on this pin is used as a reference

for ADC and DAC.

VBAT 27[18] IRTC power supply: 3.3 V on this pin supplies the power to the RTC peripheral.

Table 3. Pin description …continued

Symbol Pin Type Description

Product data sheet Rev. 3 — 15 October 2013 16 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

[18] Pad provides special analog functionality.

Product data sheet Rev. 3 — 15 October 2013 17 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

7. Functional description

7.1 Architectural overview

The LPC2388 microcontroller consists of an ARM7TDMI-S CPU with emulation support,

the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip

memory, the AMBA AHB interfacing to high-speed on-chip peripherals and external

memory, and the AMBA APB for connection to other on-chip peripheral functions. The

microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte

order.

The LPC2388 implement s two AHB in order to allo w the Ethernet block to ope rate without

interference caused by other system activity. The primary AHB, referred to as AHB1,

includes the VIC, GPDMA controller, and EMC.

The second AHB, referred to as AHB2, includes only the Ethernet block and an

associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary

AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into

off-chip memory or unused space in memory residing on AHB1.

In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function,

and the Ethernet bl ock (via the bus bridge fr om AHB2). Bus masters with access to AHB2

are the ARM7 and the Ethernet block.

AHB peripherals are allocated a 2 MB range of addresses at th e very top of the 4 GB

ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the

AHB address space. Lower speed peripheral functions are connected to the APB bus.

The AHB to APB bridge interfaces the APB to the AHB. APB peripherals are also

allocated a 2 MB range of addresses, beginning at the 3.5 GB address point. Each APB

peripheral is allocated a 16 kB address space within the APB address space.

The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers

high performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, a nd the instruction set and related

decode mechanism are much simpler than those of microprogrammed complex

instruction set computers. This simplicity results in a high instructio n thro ug h pu t an d

impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all p arts o f the processing and m emory systems

can operate continuously. Typically, while one instruction is b eing e xecuted, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory

restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

•The standard 32-bit ARM set

•A 16-bit Thumb set

Product data sheet Rev. 3 — 15 October 2013 18 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

The Thumb set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memor y system.

7.2 On-chip flash programming memory

The LPC2388 incorporates a 51 2 kB flash memory system. This memory may be used for

both code and data storage. Programming of the flash memory may be accomplished in

several ways. It may be programmed In System via the serial port (UART0). The

application program may also erase and/or program the flash while the application is

running, allowing a great degree of flexibility for data storage field and firmware upgrades.

The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to

allow it to operate at SRAM speeds of 72 MHz.

7.3 On-chip SRAM

The LPC2388 includes a SRAM memory of 64 kB reserved for the ARM processor

exclusive use. This RAM may be used for code and/or dat a storage and ma y be accessed

as 8 bits, 16 bits, and 32 bits.

A 16 kB SRAM block serving as a buffer for the Ethernet controller and a 16 kB SRAM

associated with the USB device can be used both for data and code storage, too. The

2 kB RTC can be used for data storage only. The RTC SRAM is battery po wered and

retains the content in the absence of the main power supply.

7.4 Memory map

The LPC2388 memory map incorporates several distinct regions as shown in Figure 3.

In addition, the CPU interrupt vectors may be remapped to allow them to reside in either

flash memory (default), boot ROM, or SRAM (see Section 7.26.6).

Product data sheet Rev. 3 — 15 October 2013 19 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

7.5 Interrupt controller

The ARM processor cor e has two interrupt in puts called Interrupt Request (I RQ) and Fast

Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be

programmed as FIQ or vectored IRQ types. The programmable assignment scheme

means that priorities of interrupts from the various peripherals can be dynamically

assigned and adjusted.

Fig 3. LPC2388 memory map

0.0 GB

1.0 GB

TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY

0x0000 0000

0x0007 FFFF

0x0008 0000

RESERVED FOR ON-CHIP MEMORY

64 kB LOCAL ON-CHIP STATIC RAM

RESERVED ADDRESS SPACE

0x4000 0000

0x4001 0000

0x7FD0 0000

0x7FE0 0000

0x7FD0 3FFF

0x7FE0 3FFF

0x4000 FFFF

2.0 GB

BOOT ROM AND BOOT FLASH

(BOOT FLASH REMAPPED FROM ON-CHIP FLASH)

3.0 GB 0xC000 0000

RESERVED ADDRESS SPACE

3.75 GB

4.0 GB

3.5 GB

AHB PERIPHERALS

APB PERIPHERALS 0xE000 0000

0xF000 0000

0xFFFF FFFF

USB RAM (16 kB)

ETHERNET RAM (16 kB)

002aad331

0x8000 0000

0x8000 FFFF

0x8100 FFFF

0x8100 0000

EXTERNAL MEMORY BANK 0 (64 kB)

EXTERNAL MEMORY BANK 1 (64 kB)

Product data sheet Rev. 3 — 15 October 2013 20 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs

the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ

latency is achieved when only one request is classified as FIQ, because then the FIQ

service routine can simply start dealing with that device. But if more than one request is

assigned to the FIQ class, the FIQ service routine can read a word from the VIC that

identifies which FIQ source(s) is (are) requesting an inte rr up t.

Vectored IRQs, which include all interrupt requests that ar e not clas sified as FIQs, have a

programmable interrupt priority. When more than one interrupt is assigned the same

priority and occu r simultaneously, the one connected to the lowest numbered VIC chan nel

will be serviced first.

The VIC ORs the requests from all of the vectored IRQs to produce the IRQ signal to the

ARM processor. The IRQ service routine can sta rt by reading a register from the VIC and

jumping to the address supplied by that register.

7.5.1 Interrupt sources

Each peripheral device has one interrupt line connected to the VIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

Any pin on Port 0 and Port 2 (total of 46 pins) regardless of the selected function, can be

programmed to generate an interrupt on a rising edge, a falling edge, or both. Such

interrupt request coming from Port 0 and/or Port 2 will be combined with the EINT3

interrupt requests.

7.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on chip peripherals.

Peripherals should be conn ected to the appro priate pins prior to being activated and pr ior

to any related interrup t(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

7.7 External memory controller

The LPC2388 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering

support for asynchronous static memory devices such as RAM, ROM, and flash. In

addition, it can be used as an interface with off-chip memory-mapped devices and

peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant

peripheral.

7.7.1 Features

•Asynchronous static memory device support including RAM, ROM, and flash, with or

without asynchronous page mode

•Low transaction latency

•Read and write buffers to reduce latency and to improve performance

•8 data and 16 address lines wide static memor y support

•Tw o chip selects for static memory devices

Product data sheet Rev. 3 — 15 October 2013 21 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

•Static memory features include:

–Asynchronous page mode read

–Programmable Wait States (WST)

–Bus turnaround delay

–Output enable and write enable delays

–Extended wait

7.8 General purpose DMA controller

The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2388

peripherals to have DMA support.

The GPDMA enables peripheral-to-memory, memory-to-peripheral,

peripheral- to -p erip he ra l, an d m em o ry- to -me mo ry transactions. Eac h DM A stre am

provides unidirectional serial DMA transfers for a single source and destination. For

example, a bidirectional port requires one stream for transmit and one for receive. The

source and destination areas can each be either a memory region or a peripheral, and

can be accessed through the AHB master.

7.8.1 Features

•Two DMA channels. Each channel can support a unidirectional transfer.

•The GPDMA can transfer dat a between the 16 kB SRAM and periphera ls such as the

SD/MMC, two SSP, and I2S-bus interfaces.

•Single DMA and burst DMA request signals. Each peripheral connected to the

GPDMA can assert either a burst DMA request or a single DMA request. The DMA

burst size is set by programming the GPDMA.

•Memory-to-memory, memory-to-peripheral, peripheral-to- memory, and

peripheral-to-peripheral transfers.

•Scatter or gather DMA is supported through the use of linked lists. This means that

the source and destination areas do not have to occupy contiguous areas of memory.

•Hardware DMA channel priority. Each DMA channel has a specific hardware priority.

DMA channel 0 has the highest priority and channel 1 has the lowest priority. If

requests from two channels become active at the same time, the channel with the

highest priority is serviced first.

•AHB slave DMA programming interface. The GPDMA is programmed by writing to th e

DMA control register s ove r the AHB slav e int er fa ce.

•One AHB master for transferring data. This interface transfers data when a DMA

request goes active.

•32-bit AHB master bus width.

•Incrementing or non-incrementing addressing for source and destination.

•Programmable DMA burst size. The DMA burst size can be programmed to more

efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the

peripheral.

•Internal four-word FIFO per channel.

•Supports 8-bit, 16-bit, and 32-bit wide transactions.

Product data sheet Rev. 3 — 15 October 2013 22 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

•An interrupt to the pr ocessor ca n be gene rate d on a DMA comp letion or when a DMA

error has occurred.

•Interrupt masking. The DMA error and DMA terminal count interrupt requests can be

masked.

•Raw interrupt status. The DMA error and DMA count raw interrupt status can be read

prior to masking.

7.9 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any nu mber of outp uts simultan eou sly. The value of the

output register may be read back as well as the current state of the port pins.

LPC2388 use accelerated GPIO functions:

•GPIO registers are relocated to the ARM local bus so that the fastest possible I/O

timing can be achieved.

•Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

•All GPIO registers are byte and half-word addressable.

•Entire port value can be written in one instruction.

Additionally, any pin on Po rt 0 an d Por t 2 (total of 46 pins) providing a digital function can

be programmed to generate an interrupt on a rising edge, a falling edge, or both. The

edge detection is asynchronous, so it may operate when clocks are not present such as

during Power-down mode. Each enabled interrupt can be used to wake up the chip from

Power-down mode.

7.9.1 Features

•Bit level set and clear registers allow a single instr uction to set or clear any nu mber of

bits in one port.

•Direction control of individual bits.

•All I/O default to inputs after reset.

•Backward compatibility with other earlier devices is maintained with legacy Port 0 and

Port 1 registers appearing at the original addresses on the APB bus.

7.10 Ethernet

The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC

designed to provide optimized performance through the use of DMA hardware

acceleration. Features include a generous suite of control registers, half or full duplex

operation, flow control, control frames, hardware acceleration for transmit retry, receive

packet filtering an d wa ke-u p on LAN activity. Automatic frame transmission and reception

with scatter-gather DMA off-loads many operations from the CPU.

The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access

the Ethernet SRAM for Ethernet da ta, control, and st atus information. All other AHB traffic

in the LPC2388 t akes pla ce on a dif ferent AHB subsystem, ef fectively separ ating Ethernet

activity from the rest of the system. The Ethernet DMA can also access off-chip memory

Product data sheet Rev. 3 — 15 October 2013 23 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

via the EMC, as well as the SRAM located on another AHB, if it is not being used by the

USB block. However, using memory other than the Ethernet SRAM, especially off-chip

memory, will slow Ethernet access to memory and increase the loading of its AHB.

The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII

(RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial

bus.

7.10.1 Features

•Ethernet standards support:

–Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,

100 Base-FX, and 100 Base-T4.

–Fully compliant with IEEE standard 802.3.

–Fully compliant with 802.3x full duplex flow contro l and half duplex back pressure.

–Flexible transmit and receive frame options.

–Virtual Local Area Network (VLAN) frame support.

•Memory management:

–Independent transmit and receive buffers memory mapped to shared SRAM.

–DMA managers with scatter/gather DMA and arrays of frame descriptors.

–Memory traffic optimized by buffering and pre-fetching.

•Enhanced Ethernet features:

–Receive filtering.

–Multicast and broadcast frame support for both transmit and receive.

–Optional automatic Frame Check Sequence (FCS) insertion with Circular

Redundancy Check (CRC) for transmit.

–Selectable automatic transmit frame padding.

–Over-length frame support for both transmit and receive allows any length frames.

–Promiscuous receive mode.

–Automatic collision back-off and frame retransmission.

–Includes power management by clock switching.

–Wake-on-LAN power management support allows system wake-up: using the

receive filters or a magic frame detection filter.

•Physical interface:

–Attachment of external PHY chip through standard RMII interface.

–PHY register access is available via the MIIM interface.

7.11 USB interface

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The host controller allocates the USB

bandwidth to attached devices through a token-based protocol. The bus supports hot

plugging and dynamic configuration of the devices. All transactions are initiated by the

host controller.

Product data sheet Rev. 3 — 15 October 2013 24 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

The LPC2388 USB interface includes a device, host, and OTG controller. Details on

typical USB interfacing solutions can be found in Section 14.1.

7.11.1 USB device controller

The device controller enables 12 Mbit/s data exchange with a USB host controller. It

consists of a register interface, serial interface engine, endpoint buffer memory, and a

DMA controller. The serial interface e ngine dec odes the USB data stream a nd writes dat a

to the appropriate endpoint buffer. The status of a completed USB transfer or error

condition is indicated via status registers. An interrupt is also generated if enabled. When

enabled, the DMA controller transfers data between the end point buf fer and the USB

RAM.

7.11.1.1 Features

•Fully compliant with USB 2.0 specification (full speed).

•Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.

•Supports Control, Bulk, Interrupt and Isochronous endpoints.

•Scalable realization of endpoints at run time.

•Endpoint Maximum packet size selection (up to USB maximum specification) by

software at run time.

•Supports SoftConnect and GoodLink features.

•While the USB is in the Suspend mode, the LPC2388 can enter one of the reduced

power modes and wake up on USB activity.

•Supports DMA transfers with th e DM A RAM of 16 kB on all non- co nt ro l endpoints.

•Allows dynamic switching between CPU-controlled and DMA modes.

•Double buffer implementation for Bulk and Isochronous endpoints.

7.11.2 USB host controller

The host controller ena bles full- and low-speed dat a exchange with USB devices attached

to the bus. It consists of register inter face, serial interface engine , and DMA controller . The

7.11.2.1 Features

•OHCI compliant.

•Tw o do wn str e am por ts.

•Supports per-port power switching.

7.11.3 USB OTG controller

USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that augments the

capability of existing mobile devices and USB peripherals by adding host functionality for

connection to USB peripherals.

The OTG controller integrates the host controller, device controller, and a master-only

I2C-bus interface to implement OTG dual-role device functionality. The dedicated I2C-bus

interface controls an external OTG transceiver.

Product data sheet Rev. 3 — 15 October 2013 25 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

7.11.3.1 Features

•Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision

1.0a.

•Hardware support for Host Negotiation Protocol (HNP).

•Includes a programmable timer required for HNP and Session Request Protocol

(SRP).

•Supports any OTG transceiver compliant with the OTG Transceiver Specification

(CEA-2011), Rev. 1.0.

7.12 CAN controller and acceptance filters

The Controller Area Network (CAN) is a serial communications protocol which efficiently

supports distributed real-time control with a very high level of security. Its domain of

application ranges from high-speed networks to low cost multiplex wiring.

The CAN block is intended to support multiple CAN buses simultaneously, allowing the

device to be used as a gateway, switch, or router among a number of CAN buses in

industrial or automotive applications.

Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN

Library block, but the 8-bit registers of those devices have been combined in 32-bit words

to allow simult aneous access in the ARM environment. The main operational d iff erence is

that the recognition of received Identifiers, known in CAN terminology as Acceptance

Filtering, has been removed from the CAN controllers and centralized in a global

Acceptance Filter.

7.12.1 Features

•Two CAN controllers and buses.

•Data rates to 1 Mbit/s on each bus.

•32-bit register and RAM access.

•Compatible with CAN specification 2.0B, ISO 11898-1 .

•Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN

buses.

•Acceptance Filter can provide FullC AN- style automatic reception for selected

Standard Identifiers.

•FullCAN messages can generate interrupts.

7.13 10-bit ADC

The LPC2388 contains one ADC. It is a single 10-bit successive approximation ADC with

eight channels.

7.13.1 Features

•10-bit successive approximation ADC

•Input multiplexing among 8 pins

•Power-down mode

•Measurement range 0 V to Vi(VREF)

Product data sheet Rev. 3 — 15 October 2013 26 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

•10-bit conver sio n time  2.44 s

•Burst conversion mode for single or multiple inputs

•Optional conversion on transition of input pin or Timer Match signal

•Individual result registers for each ADC channel to reduce interrupt overhead

7.14 10-bit DAC

The DAC allows the LPC2388 to generate a var iable analog ou tput. The maximum outp ut

value of the DAC is Vi(VREF).

7.14.1 Features

•10-bit DAC

•Resistor string architecture

•Buffered output

•Power-down mode

•Selectable output drive

7.15 UARTs

The LPC2388 contains four UARTs. In addition to standard transmit and receive data

lines, UART1 also provides a full modem control handshake interface.

The UARTs include a fractional baud rate gene rator. St anda rd baud r ates such as 115200

can be achieved with an y cry s tal frequen cy ab ov e 2 MHz.

7.15.1 Features

•16 B Receive and Transmit FIFOs.

•Register locations conform to 16C550 industry standard.

•Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

•Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

•Fractional divider for baud rate control, auto baud capabilities and FIFO control

mechanism that enables software flow control implementation.

•UART1 equipped with standard modem interface signals. This module also provides

full support for hardware flow control (auto-CTS/RTS).

•UART3 includes an IrDA mode to support infrared communication.

7.16 SPI serial I/O controller

The LPC2388 cont ains on e SPI controller. SPI is a full duplex serial interface designed to

handle multiple maste rs and slaves co nnected to a given bus. Only a single maste r and a

single slave can communicate on the inte rface during a given data transfer. During a data

transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave

always sends 8 bits to 16 bits of data to the master.

Product data sheet Rev. 3 — 15 October 2013 27 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

7.16.1 Features

•Compliant with SPI specification

•Synchronous, Serial, Full Duplex Communication

•Combined SPI master and slave

•Maximum data bit rate of one eighth of the input clock rate

•8 bits to 16 bits per transfer

7.17 SSP serial I/O controller

The LPC2388 cont ains two SSP controllers. The SSP controller is cap able of operation on

a SPI, 4-wire SSI, or Microwire bus. It can intera ct with multiple masters and slaves on the

bus. Only a single maste r an d a sin gle slav e can communicate on the bus during a given

data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of

data flowing from the master to the slave and from the slave to the master. In practice,

often only one of these data flows carries meaningful data.

7.17.1 Features

•Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire

buses

•Synchronous serial communication

•Master or slave operation

•8-frame FIFOs for both transmit and receive

•4-bit to 16-bit frame

•DMA transfers supp or te d by GPDM A

7.18 SD/MMC card interface

The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD

memory cards. The SD card interface conforms to the SD Multimedia Card Specification

Ver sio n 2. 11.

7.18.1 Features

•The MCI provides all functions specific to the SD/MMC memory card. These include

the clock generation unit, power management control, and command and data

transfer.

•Conforms to Multimedia Card Specification v2.11.

•Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96.

•Can be used as a multimedia card bus or a secure d igit al memo ry card bus ho st. The

SD/MMC can be connected to several multimedia cards or a single secure digital

memory card.

•DMA supported through the GPDMA controller.

7.19 I2C-bus serial I/O controllers

The LPC2388 contains three I2C-bus controllers.

Product data sheet Rev. 3 — 15 October 2013 28 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

The I2C-bus is bidirectional, for inter-IC control using only two wires: a Ser ial Clo ck Lin e

(SCL), and a Serial DAta line (SDA). Each device is recognized by a unique address and

can operate as either a r eceiver-o nly device ( e.g., an LCD driver) or a tra nsmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can oper ate in eithe r master or sl ave mo de, dependin g on wheth er the chip has

to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus and can

be controlled by more than one bus master connected to it.

The I2C-bus implemented in LPC2388 supports bit rates up to 400 kbit/s (Fast I2C-bus).

7.19.1 Features

•I2C0 is a standard I2C compliant bus interface with open-drain pins.

•I2C1 and I2C2 use standard I/O pins and do not support powering off of individual

devices connected to the same bus lines.

•Easy to configure as master, slave, or master/slave.

•Programmable clocks allow versatile rate control.

•Bidirectional data transfer between masters and slaves.

•Multi-master bus (no central master).

•Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

•Serial clock synchronization allows devices with differ ent bit rates to communicate via

one serial bus.

•Serial clock synchronization can be used as a handshake mech anism to suspend and

resume serial transfer.

•The I2C-bus can be used for test and diagnostic purposes.

7.20 I2S-bus serial I/O controllers

The I2S-bus provides a standard communication interface for digital audio applications.

The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line,

and one word select signal. The basic I2S-bus connection has one master, which is

always the master, and one slave. The I2S-bus interface on the LPC2388 provides a

separate transmit and rece ive chann el, each of which can opera te as either a master or a

slave.

7.20.1 Features

•The interface has sep arate input/output channels each of which can o perate in master

or slave mode.

•Capable of handling 8-bit, 16-bit, and 32-bit word sizes.

•Mono and stereo audio data supported.

•The sampling frequency can range from 16 kHz to 48 kHz ((16, 22.05, 32, 44.1,

48) kHz).

•Configurable word select period in master mode (separately for I2S-bus input and

output).

•Two 8 word FIFO data buffers are provided, one for transmit and one for receive.

Product data sheet Rev. 3 — 15 October 2013 29 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

•Generates interrupt requests when buffer levels cross a programmable boundary.

•Two DMA requests, controlled by programmable buffer levels. These are connected

to the GPDMA block.

•Controls include reset, stop and mute options separately for I2S-bus input and output.

7.21 General purpose 32-bit timers/external event counters

The LPC2388 includes four 32-bit Timer/Counters. The Timer/Counter is designed to

count cycles of the system derived clock or an externally-supplied clock. It can optionally

generate interrupts or perform other actions at specified timer values, based on four

match registers. The Timer/Counter also includes four capture inputs to trap the timer

value when an input signal transitions, optionally generating an interrupt.

7.21.1 Features

•A 32-bit Timer/Counter with a programmable 32-bit prescaler.

•Counter or Timer operation.

•Up to four 32-bit capture channels per timer, that can take a snapshot of the timer

value when an input signal transitions. A capture event may also optionally generate

an interrupt.

•Four 32-bit matc h re gist er s tha t allo w:

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional interrupt generation.

•Up to four external outputs corresponding to match registers, with the following

capabilities:

–Set LOW on match.

–Set HIGH on match.

–Toggle on match.

–Do nothing on match.

7.22 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although

only the PWM function is pinned out on the LPC2388. The Timer is designed to count

cycles of the system derived clock and optionally switch pins, generate interrupts or

perform other actions when spe cified timer values occur , based on seven match registers.

The PWM function is in addition to these features, and is based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be

used for more applications. For instance, multi-phase motor control typically requires

three non-overlapping PWM outputs with individual control of all three pulse widths and

positions.

Two match registers can be used to provide a single edge controlled PWM output. One

match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon

match. The other match register controls the PWM edge position. Additional single edge

Product data sheet Rev. 3 — 15 October 2013 30 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

controlled PWM ou tp u ts require only on e m atc h register each, since the repetition rate is

the same for all PWM outputs. Multiple single edge controlled PWM output s will all have a

rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.

Three match registers can be used to provide a PWM output with both ed ge s co ntr olled .

Again, the PWMMR0 match register controls the PWM cycle rate. The other match

registers control the two PWM edge positions. Additional double edge controlled PWM

outputs require only two match registers each, since the repetition rate is the same for all

PWM outputs.

With double edge controlled PWM outputs, specific match registers control the rising and

falling edge of the output. This allows both positive going PWM pulses (when the rising

edge occurs prior to the falling edge), and negative going PWM pulses (when the falling

edge occurs prior to the rising edge).

7.22.1 Features

•LPC2388 has one PWM block with Counter or Timer operation (may use the

peripheral clock or one of the capture inputs as the clock source).

•Seven match registers allow up to 6 single edge controlled or 3 double edge

controlled PWM outputs, or a mix of both types. The match registers also allow:

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional interrupt generation.

•Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go high at the beginning of each cycle unless the

output is a constant low. Double edge controlled PWM outputs can have either edge

occur at any position within a cycle. This allows for both positive going and negative

going pulses.

•Pulse period and width can be any number of timer counts. This allows complete

flexibility in the trade-off between resolution and repetition rate. All PWM outputs will

occur at the same repetition rate.

•Double edge controlled PWM outputs can be programmed to be either positive going

or negative going pulses.

•Match register updates are synchronized with pulse outputs to prevent ge ne ra tio n of

erroneous pulses. Sof tware must ‘release’ new ma tch values before they ca n become

effective.

•May be used as a standard timer if the PWM mode is not enabled.

•A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

7.23 Watchdog timer

The purpose of the watchdog is to reset the mi crocontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined

amount of time.

7.23.1 Features

•Internally resets chip if not periodically reloaded.

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NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

•Debug mode.

•Enabled by soft ware but requires a har dware reset or a watchdog reset/interrupt to be

disabled.

•Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

•Flag to indicate watchdog reset.

•Programmable 32-bit timer with internal prescaler.

•Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 232 4) in

multiples of Tcy(WDCLK) 4.

•The Watchdog Clock (WDCLK) source can be selected from the RTC clock, the

Internal RC oscillator (IRC), or the APB peripheral clock. This gives a wide range of

potential timing choices of Watchdog operation under different power reduction

conditions. It also provides the ability to run the WDT from an entirely internal source

that is not dependent on an external crystal and its associated components and

wiring, for increased reliability.

7.24 RTC and battery RAM

The RTC is a set of counte rs for measur ing time when system power is on, and optio nally

when it is off. It uses little power in Power-down and Deep power-down modes. On the

LPC2388, the RTC can be clocked by a separate 32.768 kHz oscillator or by a

programmable prescale divider based on the APB clock. Also, the RTC is powered by its

own power supply pin, VBAT, which can be connected to a battery or to the same 3.3 V

supply used by the rest of the device.

The VBAT pin supplies power only to the RTC and the battery RAM. These two functions

require a minimum of power to operate, which can be supplied by an external battery.

When the CPU and the rest of chip functions are stopped and power removed, the RTC

can supply an alarm output that can be used by external hardware to restore chip power

and resume operation.

7.24.1 Features

•Measures the passage of time to maintain a calendar and clock.

•Ultra low power design to support battery powered systems.

•Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and

Day of Year.

•Dedicated 32 kHz oscillator or programmable prescaler from APB clock.

•Dedicated power supply pin can be connected to a battery or to the main 3.3 V.

•An alarm output pin is included to assist in waking up from Power-down mode, or

when the chip has had power removed to all functions except the RTC and battery

RAM.

•Periodic interru pts can be generated fr om increments o f any field of the time registers,

and selected fractional second values.

•2 kB data SRAM powered by VBAT.

•RTC and battery RAM power sup p ly is isol at ed from th e re st of the ch ip.

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NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

7.25 Clocking and power control

7.25.1 Crystal oscillators

The LPC2388 includes three independent oscillators. These are the Main Oscillator, the

Internal RC oscillator, and the RTC oscillator. Each oscillator can be used for more than

one purpose as req uir ed in a particular applica tio n. Any of th e three clock so urce s can be

chosen by software to drive the PLL and ultimately the CPU.

Following reset, the LPC2388 will operate from the Internal RC oscillator until switched by

software. This allows systems to operate without any external crystal and the bootloader

code to operate at a known frequency.

7.25.1.1 Internal RC oscillator

The IRC may be used as the clock so urce for th e WDT, and/or as the clock that drives the

PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is

trimmed to 1 % accuracy.

Upon power-up or any chip reset, the LPC2388 uses the IRC as the clock source.

Software may later switch to one of the other available clock sources.

7.25.1.2 Main oscillator

The main oscillator can be used as the clock source for the CPU, with or withou t using the

PLL. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can

be boosted to a higher frequency, up to the maximum CPU operating frequency, by the

PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock

frequency is referred to as CCLK elsewhere in this document. The frequencies of

PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The

clock frequency for each peripheral can be selected individually and is referred to as

PCLK. Refer to Section 7.25.2 for additional information.

7.25.1.3 RTC oscillator

The RTC oscillator can be used as the clock source for the R TC and/or the WDT. Also, the

RTC oscillator can be used to drive the PLL and the CPU.

7.25.2 PLL

The PLL accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input

frequency is multiplied up to a high frequency, then divided down to provide the actual

clock used by the CPU and the USB block.

The PLL input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value

‘N’, which may be in the range of 1 to 256. This input division provides a wide range of

output frequencies from the same input frequency.

Following the PLL input divider is the PLL multiplier. This can multiply the input divider

output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the

range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to

550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a

phase-frequency detector to compare the divided CCO output to the multiplier input. The

error value is used to adjust the CCO frequency.

Product data sheet Rev. 3 — 15 October 2013 33 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

The PLL is turned off and bypassed following a chip Reset and by entering Power-down

mode. PLL is enabled by sof tware only. The program must configure an d activate the PLL,

wait for the PLL to lock, then connect to the PLL as a clock source.

7.25.3 Wake-up timer

The LPC2388 begins operation at power-up and when awakened from Power-down and

Deep power-down modes by using the 4 MHz IRC oscillator as the clock source. This

allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the

application, software will need to enable these features and wait for them to stabilize

before they are used as a clock source.

When the main oscillator is initially activate d, the wake-up timer allows sof tware to e nsure

that the main oscillator is fully functional before the processor uses it as a clock source

and starts to execute instructions. This is important at power on, all types of Reset, and

whenever any of the aforementioned functions are turned off for any reason. Since the

oscillator and other functions are turned off during Power-down and Deep power-down

modes, any wake-up of the processor from Powe r-down mode make s use of the wake- up

Timer.

The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin

code execution. When power is applied to the chip, or when some eve nt caused the chip

to exit Power-down mode, some time is required for the oscillator to produce a signal of

sufficie nt amplitude to drive the clock logic. The amount of time d epends on many factors,

including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its

electrical characteristics (if a q uartz cr yst al is used) , as well as any other external cir cuitry

(e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient

conditions.

7.25.4 Power control

The LPC2388 suppo rts a variety of powe r control features. There are four special modes

of processor power reduction: Idle mode, Sleep mode, Power-down mode, and Deep

power-down mode. The CPU clock rate may also be controlled as needed by changing

clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This

allows a trade-off of power versus processing speed based on application requirements.

In addition, Periph eral Power Contro l allows shutting down the clo cks to individual on-chip

peripherals, allowing fine tuning of power consumption by eliminating all dynamic power

use in any periphera ls th at are not re qu ire d for th e ap plic at ion . Each of the peripherals

has its own clock divider which provides even better power control.

The LPC2388 also implements a separate power domain in order to allow turning off

power to the bulk of the device while ma intaining opera tion of the RTC and a small SRAM,

referred to as the battery RAM.

7.25.4.1 Idle mode

In Idle mode, execution of instructions is suspended until either a Reset or interrupt

occurs. Peripheral functions continue operation during Idle mode and may generate

interrupts to cause the processor to resume execution. Idle mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

Product data sheet Rev. 3 — 15 October 2013 34 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

7.25.4.2 Sleep mode

In Sleep mode, the oscillator is shut down and the chip receives no internal clocks. The

processor state an d re gis te rs, per i phe ra l registers, and internal SRAM values are

preserved throughout Sleep mode and the logic levels of chip pins remain static. The

output of the IRC is disabled but the IRC is not powered down fo r a fast wake-up later . The

32 kHz RTC oscillator is not stopped because the RTC interrupts may be used as the

wake-up source. The PLL is automatically turned off and disconnected. The CCLK and

USB clock dividers automatically get reset to zero.

The Sleep mode can be terminated and normal operation resumed by either a Reset or

certain specific interrupts that are able to function without clocks. Since all dynamic

operation of the chip is suspended, Sleep mode reduces chip power consumption to a

very low value. The flash memory is left on in Sleep mode, allowing a very quick wake-up.

On the wake-up of Sleep mode, if the IRC was used before entering Sleep mode, the

code execution and peripherals activities will resume after 4 cycles expire. If the main

external oscillator was used, the code execution will resume when 4096 cycles expire.

The customers need to reconfigure the PLL and clock dividers accordingly.

7.25.4.3 Power-down mode

Power-down mode does everything that Sleep mode does, but also turns off the IRC

oscillator and the flash memory. This saves more power, but requires waiting for

resumption of flash oper ation before execution of code or dat a access in the flash memory

can be accomplished.

On the wake-up of Power-down mode, if the IRC was used before entering Power-down

mode, it will take IRC 60 s to start-up. After this 4 IRC cycles will expire before the code

execution can then be resumed if the code was running from SRAM. In the meantime, the

flash wake-up timer then coun ts 4 MHz IRC clock cycles to make the 100 s flash start-up

time. When it times out, access to the flash will be allowed. The customers need to

reconfigure the PLL and clock dividers accordingly.

7.25.4.4 Deep power-down mode

Deep power-down mode is similar to the Power-down mode, but now the on-chip

regulator that supplies power to the intern al logic is also shut of f. This produce s the lowest

possible power consumption without removing power from the entire chi p. Since the Deep

power-down mode shuts down the on-chip logic power supply, there is no register or

memory retention, and resumption of operation involves the same activities as a full chip

reset.

If power is supplied to the LPC2388 during Deep power-down mode, wake-up can be

caused by the RTC Alarm interrupt or by external Reset.

While in Deep power-down mode, external device power may be removed. In this case,

the LPC2388 will start up when external power is restored.

Essential data may be retained through Deep power-down mode (or through complete

powering of f of the chip) by storing dat a in the battery RAM, as long as the external power

to the VBAT pin is maintained.

Product data sheet Rev. 3 — 15 October 2013 35 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

7.25.4.5 Power domains

The LPC2388 provides two independent power domains that allow the bulk of the device

to have power removed while maintaining operation of the RTC and the battery RAM.

On the LPC2388, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the

VDD(DCDC)(3V3) pin powers the on-chip DC-to-DC converte r which in turn provides power to

the CPU and most of the peripherals.

Depending on the LPC2388 application, a design can use two power options to manage

power consum p tion .

The first option assumes that power consumption is not a conce rn and th e design ties the

VDD(3V3) and VDD(DCDC)(3V3) pins together. This approach requires only one 3.3 V power

supply for both pads, the CPU, and peripherals. While this solution is simple, it does not

support powering down the I/O pad ring “on the fly” while keeping the CPU and

peripherals alive.

The second option uses two power supplie s; a 3.3 V supply for the I/O pads (VDD(3V3)) and

a dedicated 3.3 V supply for the CPU (VDD(DCDC)(3V3)). Having the on-chip DC-to-DC

converter powered independently from the I/O pad ring enables shutting down of the I/O

pad power supply “on the fly”, while the CPU and peripherals stay active.

The VBAT pin supplies power only to the RTC and the battery RAM. These two functions

require a minimum of power to operate, which can be supplied by an external battery.

When the CPU and the rest of chip functions are stopped and power removed, the RTC

can supply an alarm output that may be used by external hardware to restore chip power

and resume operation.

7.26 System control

7.26.1 Reset

Reset has four sources on the LPC2388: the RESET pin, the Watchdog reset, power-on

reset, and the BrownOut Detection (BOD) cir cuit. The RESET pin is a Schmitt trig ger input

pin. Assertion of chip Reset by any source, once the operating voltage attains a usable

level, starts the Wake-up timer (see description in Section 7.25.3 “W ake-up timer”),

causing reset to remain asserted until the external Reset is de-asserted, the oscillator is

running, a fixed number of clocks have passed, and the flash control l er has comp leted it s

initialization.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the Boot Block. At th at poin t, all of the pr ocessor

and peripheral registers have been initialized to predetermin ed values.

7.26.2 Brownout detection

The LPC2388 includ es 2-st age moni toring of the volta ge on the V DD(DCDC)(3V3) pins. If this

voltage falls below 2.95 V, the BOD asser ts an interr upt signal to the VIC. This signal can

be enabled for interrupt in the Interrupt Enable Register in the VIC in order to cause a

CPU interrupt; if not, software can monitor the signal by reading a dedicated status

Product data sheet Rev. 3 — 15 October 2013 36 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

The second stage of low-volt age detection asserts Reset to inactivate the LPC23 88 when

the volt age on the V DD(DCDC)(3V3) pins falls below 2.65 V. This Reset preven ts al teration o f

the flash as operation of the various elements of the chip would otherwise becom e

unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at

which point the power-on reset circuitry maintains the overall Reset.

Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this

hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly executed event

loop to sense the condition.

7.26.3 Code security (Code Read Protection - CRP)

This feature of the LPC2388 allows user to ena ble differ ent levels of security in the system

so that access to the on-chip flash and use of the JTAG and ISP can be restrict ed . Whe n

needed, CRP is invoked by pr ogramming a specific pattern into a dedicated flash location.

IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection.

CRP1 disables access to chip via the JTAG and allows partial flash update (excluding

flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is

required and flash field updates are needed but all sectors can not be erased.

CRP2 disables ac ce ss to chip via th e JTAG and only allows full flash erase and upd at e

using a reduced set of the ISP commands.

Running an application with level CRP3 selected fully disables any access to chip via the

JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too.

It is up to the user’s application to provide (if needed) flash update mechanism using IAP

calls or call reinvoke ISP command to enable flash update via UART0.

7.26.4 AHB

The LPC2388 implements two AHBs in order to allow the Ethernet block to operate

without interference caused by other system activity. The primary AHB, referred to as

AHB1, includes the VIC, GPDMA controller, USB interface, and 8 kB SRAM primarily

intended for use by the USB.

The second AHB, referred to as AHB2, includes only the Ethernet block and an

associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary

AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into

off-chip memory or unused space in memory residing on AHB1.

In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, the

GPDMA function, and the Etherne t block (via the bus bridge from AHB2). B us mast er s

with access to AHB2 are the ARM7 and the Ethernet block.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Product data sheet Rev. 3 — 15 October 2013 37 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

7.26.5 External interrupt inputs

The LPC2388 includes up to 50 edge sensitive interrupt inputs combined with up to four

level sensitive external interrupt inputs as selectable pin functions. The external interrupt

inputs can optionally be used to wake up the processor from Power-down mode.

7.26.6 Memory mapping control

The memory mapping control alters th e mapping of the interrupt vectors that appear at the

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot

ROM, the SRAM, or external memory. This allows code running in different memory

spaces to have control of the interrupts.

7.27 Emulation and debugging

The LPC2388 support emulation and debugging via a JTAG serial port. A trace port allows

tracing program execution. Debugging and trace functions are multiplexed only with

GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface

peripherals residing on other pins are available during the development and debugging

phase as they are when the application is run in the embedded system itself.

7.27.1 EmbeddedICE

The EmbeddedICE logic provides on-chip debug support. The debugging of the target

system requires a host computer running the debugger software and an EmbeddedICE

protocol convertor. The EmbeddedICE protocol convertor converts the Remote Debug

Protocol commands to the JTAG data needed to access the ARM7TDMI-S core present

on the target system.

The ARM core has a Debu g Co mmunication Channel (DCC) function built-in. The DCC

allows a program running on the target to communica te with the host debugger or another

separate host without stopping the program flow or even entering the debug state. The

DCC is accessed as a coprocessor 1 4 by the program running on the ARM7TDMI-S core.

The DCC allows the JTAG port to be used for sending and receivin g data without a ffecting

the normal progr am flow. The DCC dat a and contro l registers are mapped in to addresses

in the EmbeddedICE logic.

The JTAG clock (TCK) must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG

interface to operate.

7.27.2 Embedded trace

Since the LPC2388 have significant amounts of on-chip memories, it is not possible to

determine how the processor core is operating simply by observing the external pins. The

ETM provides real-time trace capability for deeply embedded processor cores. It outputs

information about processor execution to a trace port. A software debugger allows

configuration of the ETM using a JTAG interface and displays the trace information that

has been captured.

The ETM is connected directly to the ARM core and not to the main AMBA system bus. It

compresses the trace information and exports it through a narrow trace port. An external

Trace Port Analyzer captures the trace information under software debugger control. The

trace port can broadcast the Instruction trace information. Instruction trace (or PC trace)

shows the flow of execution of the processor and pro vides a list of all the instructions th at

were executed. Instruction trace is significantly compressed by only broadcasting branch

Product data sheet Rev. 3 — 15 October 2013 38 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

addresses as well as a set of status signals that indicate the pipeline status on a cycle by

cycle basis. Trace information generation can be controlled by selecting the trigger

resource. Trigger resources include address comparators, counters and sequencers.

Since trace information is compressed the software debugger requires a static image of

the code being executed. Self-modifying code can not be traced because of this

restriction.

7.27.3 RealMonitor

RealMonitor is a configurable software module, developed by ARM Inc., which enables

real-time debug. It is a lightweight debug monitor that runs in the background while users

debug their fo reground application. It co mmunicates with the host using the DCC, which is

present in the EmbeddedICE logic. The LPC2388 contain a specific configuration of

RealMonitor software programmed into the on-chip ROM memory.

Product data sheet Rev. 3 — 15 October 2013 39 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

8. Limiting values

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operat ing temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] Not to exceed 4.6 V.

[4] The peak current is limited to 25 times the corresponding maximum current.

[5] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined

based on required shelf lifetime. Please refer to the JEDEC specification (J-STD-033B.1) for further details.

[6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

VDD(3V3) supply voltage (3.3 V) core and external

rail 3.0 3.6 V

VDD(DCDC)(3V3) DC-to-DC converter supply voltage

(3.3 V) 3.0 3.6 V

VDDA analog 3.3 V pad supply voltage 0.5 +4.6 V

Vi(VBAT) input voltage on pin VBAT for the RTC 0.5 +4.6 V

Vi(VREF) input voltage on pin VREF 0.5 +4.6 V

VIA analog input voltage on ADC related

pins 0.5 +5.1 V

VIinput voltage 5 V tolerant I/O

pins; only valid

when the VDD(3V3)

supply voltage is

present

[2] 0.5 +6.0 V

other I/O pins [2][3] 0.5 VDD(3V3) +

0.5 V

IDD supply current per supply pin [4] - 100 mA

ISS ground current per ground pin [4] - 100 mA

Tstg storage temperature non-operating [5] 65 +150 C

Ptot(pack) total power dissipation (per package) based on package

heat transfer, not

device pow e r

consumption

-1.5W

VESD electrostatic discharge voltage human body

model; all pins [6] 2500 +2500 V

Product data sheet Rev. 3 — 15 October 2013 40 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

9. Thermal characteristics

The average chip junction temperature, Tj (C), can be calculated using the following

equation:

(1)

•Tamb = ambient temperature (C),

•Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)

•PD = sum of internal and I/O power dissipation

The internal power dissipation is the product of IDD and VDD. The I/O po wer dissipation of

the I/O pins is of ten small and ma ny times can be n egligible. However it can be significant

in some applications.

TjTamb PDRth j a–

+=

Table 5. Thermal characteristics

VDD = 3.0 V to 3.6 V; Tamb =





C to +85



C unless otherwise specified;

Symbol Parameter Conditions Min Typ Max Unit

Tj(max) maximum junction

temperature --125 C

Table 6. Thermal resistance value (C/W): ±15 %

VDD = 3.0 V to 3.6 V; Tamb =





C to +85



C unless otherwise specified

LQFP144

ja

JEDEC (4.5 in  4 in)

0 m/s 31.5

1 m/s 28.1

2.5 m/s 26.2

Single-layer (4.5 in  3 in)

0 m/s 43.2

1 m/s 35.7

2.5 m/s 32.8

jc 7.8

jb 13.8

Product data sheet Rev. 3 — 15 October 2013 41 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

10. Static characteristics

Table 7. Static characteristics

Tamb =





C to +85



C for commercial applications, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

VDD(3V3) supply voltage (3.3 V) core and external rail 3.0 3.3 3.6 V

VDD(DCDC)(3V3) DC-to-DC converter

supply voltage (3.3 V) 3.03.3 3.6V

VDDA analog 3. 3 V pad

supply voltage 3.03.3 3.6V

Vi(VBAT) input voltage on pin

VBAT [2] 2.03.3 3.6V

Vi(VREF) input voltage on pin

VREF 2.5 3.3 VDDA V

IDD(DCDC)act(3V3) active mode DC-to-DC

converter supply

current (3.3 V)

VDD(DCDC)(3V3) =3.3V;

Tamb =25C; code

while(1){}

executed from flash; no

peripherals enabled;

PCLK = CCLK

CCLK = 10 MHz - 15 - mA

CCLK = 72 MHz - 63 - mA

all peripherals enabled;

PCLK = CCLK / 8

CCLK = 10 MHz - 21 - mA

CCLK = 72 MHz - 92 - mA

all peripherals enabled;

PCLK = CCLK

CCLK = 10 MHz - 27 - mA

CCLK = 72 MHz - 125 - mA

IDD(DCDC)pd(3V3) Power-down mode

DC-to-DC converter

supply current (3.3 V)

VDD(DCDC)(3V3) = 3.3 V;

Tamb =25C[3] -113-A

IDD(DCDC)dpd(3V3) Deep power-down

mode DC-to- DC

converter supply

current (3.3 V)

[3]

-20-A

IBATact active mode battery

supply current [4] -20-A

IBAT battery supply current Deep power-down mode [3] -20-A

Standa rd port pins, RESET , RTCK

IIL LOW-level input

current VI= 0 V; no pull-up - - 3 A

IIH HIGH-level input

current VI=V

DD(3V3); no pull-down - - 3 A

IOZ OFF-state output

current VO=0V; V

O=V

DD(3V3);

no pull-up/down -- 3A

Product data sheet Rev. 3 — 15 October 2013 42 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

Ilatch I/O latch-up current (0.5VDD(3V3)) < VI <

(1.5VDD(3V3));

Tj < 125 C

-- 100mA

VIinput voltage pin configured to provide a

digital function [5][6][7]

[8] 0- 5.5V

VOoutput voltage output active 0 - VDD(3V3) V

VIH HIGH-level input

voltage 2.0 - - V

VIL LOW-level input

voltage -- 0.8V

Vhys hysteresis voltage 0.4 - - V

VOH HIGH-level output

voltage IOH =4 mA [9] VDD(3V3) 

0.4 --V

VOL LOW-level output

voltage IOL =4 mA [9] -- 0.4V

IOH HIGH-level output

current VOH =V

DD(3V3) 0.4 V [9] 4- - mA

IOL LOW-level output

current VOL =0.4V [9] 4- - mA

IOHS HIGH-level

short-circuit output

current

VOH =0V [10] -- 45 mA

IOLS LOW-level short-circuit

output current VOL =V

DDA [10] -- 50mA

Ipd pull-down current VI=5V [11] 10 50 150 A

Ipu pull-up current VI=0V 15 50 85 A

VDD(3V3) <V

I<5V [11] 00 0A

I2C-bus pins (P0[27] and P0[28])

VIH HIGH-level input

voltage 0.7VDD(3V3) --V

VIL LOW-level input

voltage - - 0.3VDD(3V3) V

Vhys hysteresis voltage - 0.05VDD(3V3) -V

VOL LOW-level output

voltage IOLS =3 mA [9] -- 0.4V

ILI input leakage current VI=V

DD(3V3) [12] -2 4A

VI=5V - 10 22 A

Oscillator pins

Vi(XTAL1) input voltage on pin

XTAL1 0.5 1.8 1.95 V

Vo(XTAL2) output voltage on pin

XTAL2 0.5 1.8 1.95 V

Vi(RTCX1) input voltage on pin

RTCX1 0.5 1.8 1.95 V

Table 7. Static characteristics …continued

Tamb =





C to +85



C for commercial applications, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 3 — 15 October 2013 43 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

[2] The RTC typically fails when Vi(VBAT) drops below 1.6 V.

[3] VDD(DCDC)(3V3) = 3.3 V; VDD(3V3) = 3.3 V; Vi(VBAT) = 3.3 V; Tamb =25C.

[4] On pin VBAT.

[5] Including voltage on outputs in 3-state mode.

[6] VDD(3V3) supply voltages must be present.

[7] 3-state outputs go into 3-state mode when VDD(3V3) is grounded.

[8] Please also see the errata note in errata sheet.

[9] Accounts for 100 mV voltage drop in all supply lines.

[10] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[11] Minimum condition for VI= 4.5 V, maximum condition for VI=5.5V.

[12] To VSS.

[13] Includes external resistors of 33 1 % on D+ and D.

Vo(RTCX2) output voltage on pin

RTCX2 0.5 1.8 1.95 V

USB pins

IOZ OFF-state output

current 0V<V

I<3.3V - - 10 A

VBUS bus supply voltage - - 5.25 V

VDI differential input

sensitivity voltage (D+) (D)0.2 - - V

VCM differential common

mode voltage range includes VDI range 0.8 - 2.5 V

Vth(rs)se single-ended receiver

switching threshold

voltage

0.8- 2.0V

VOL LOW-level output

voltage for

low-/full-speed

RL of 1.5 k to 3.6 V - - 0.18 V

VOH HIGH-level output

voltage (driven) for

low-/full-speed

RL of 15 k to GND 2.8 - 3.5 V

Ctrans transceiver

capacitance pin to GND - - 20 pF

ZDRV driver output

impedance for driver

which is not

high-speed capable

with 33  series resistor;

steady state drive [13] 36 - 44.1 

Table 7. Static characteristics …continued

Tamb =





C to +85



C for commercial applications, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 3 — 15 October 2013 44 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

10.1 Power-down mode

Vi(VBAT) = VDD(DCDC)(3V3) = 3.3 V; Tamb =25C.

Fig 4. I/O maximum supply current IDD(IO) versus temperature in Power-down mode

VDD(3V3) = VDD(DCDC)(3V3) = 3.3 V; Tamb =25C.

Fig 5. RTC battery maximum supply current IBAT versus temperature in Power-down

mode

002aae049

−2

IDD(IO)

(μA)

−4

temperature (°C)

−40 853510 60−15

VDD(3V3) = 3.3 V

VDD(3V3) = 3.0 V

002aae050

Vi(VBAT) = 3.3 V

Vi(VBAT) = 3.0 V

IBAT

(μA)

temperature (°C)

−40 853510 60−15

Product data sheet Rev. 3 — 15 October 2013 45 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

10.2 Deep power-down mode

VDD(3V3) = Vi(VBAT) = 3.3 V; Tamb =25C.

Fig 6. Total DC-to-DC converter supply current IDD(DCDC)pd(3V3) at different temperatures

in Power-down mode

002aae051

200

600

400

800

temperature (°C)

−40 853510 60−15

VDD(DCDC)(3V3) = 3.3 V

VDD(DCDC)(3V3) = 3.0 V

IDD(DCDC)pd(3v3)

(μA)

VDD(3V3) = VDD(DCDC)(3V3) = 3.3 V; Tamb =25C.

Fig 7. I/O maximum supply current IDD(IO) versus temperature in Deep power-down

mode

temperature (°C)

−40 853510 60−15

002aae046

100

200

300

IDD(IO)

(μA)

VDD(3V3) = 3.3 V

VDD(3V3) = 3.0 V

Product data sheet Rev. 3 — 15 October 2013 46 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

VDD(3V3) = VDD(DCDC)(3V3) = 3.3 V; Tamb =25C

Fig 8. RTC battery maximum supply current IBAT versus temperature in Deep

power-down mode

VDD(3V3) = Vi(VBAT) = 3.3 V; Tamb =25C.

Fig 9. Total DC-to-DC converter maximum supply current IDD(DCDC)dpd(3V3) versus

temperature in Deep power-down mode

002aae047

IBAT

(μA)

temperature (°C)

−40 853510 60−15

Vi(VBAT) = 3.3 V

Vi(VBAT) = 3.0 V

002aae048

temperature (°C)

−40 853510 60−15

IDD(DCDC)dpd(3v3)

(μA)

100

VDD(DCDC)(3V3) = 3.3 V

VDD(DCDC)(3V3) = 3.0 V

Product data sheet Rev. 3 — 15 October 2013 47 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

10.3 Electrical pin characteristics

Conditions: VDD(3V3) = 3.3 V; standard port pins.

Fig 10. Typical HIGH-level output voltage VOH versus HIGH-level output sourc e current

IOH

Conditions: VDD(3V3) = 3.3 V; standard port pins.

Fig 11. Typical LOW-level output current IOL versus LOW-level output voltage VOL

IOH (mA)

0 24168

002aaf112

2.8

2.4

3.2

3.6

VOH

(V)

2.0

T = 85 °C

25 °C

−40 °C

VOL (V)

0 0.60.40.2

002aaf111

IOL

(mA)

T = 85 °C

25 °C

−40 °C

Product data sheet Rev. 3 — 15 October 2013 48 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

11. Dynamic characteristics

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

[3] Bus capacitance Cb in pF, from 10 pF to 400 pF.

Table 8. Dynamic characteristics

Tamb =





C to +85



C for commercial applications; VDD(3V3) over specified ranges.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

External clock (see Figure 12)

fosc oscillator frequency 1 - 25 MHz

Tcy(clk) clock cycle time 40 - 1000 ns

tCHCX clock HIGH time Tcy(clk) 0.4--ns

tCLCX clock LOW time Tcy(clk) 0.4--ns

tCLCH clock rise time - - 5 ns

tCHCL clock fall time - - 5 ns

I2C-bus pins (P0[27] and P0[28])

tf(o) output fall time VIH to VIL 20 + 0.1  Cb[3] --ns

SSP interface

tsu(SPI_MISO) SPI_MISO set-up time Tamb = 25 C; measured

in SPI Master mode; see

Figure 16

-11-ns

Fig 12. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)

tCHCL tCLCX tCHCX

Tcy(clk)

tCLCH

002aaa907

Product data sheet Rev. 3 — 15 October 2013 49 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

11.1 Internal oscillators

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

11.2 I/O pins

[1] Applies to standard I/O pins and RESET pin.

11.3 USB interface

[1] Characterized but not implemented as production test. Guaranteed by design.

Table 9. Dynamic characteristic: internal oscillators

Tamb =





C to +85



C; 3.0 V



VDD(3V3)



3.6 V.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc(RC) internal RC oscillator frequency - 3.96 4.02 4.04 MHz

fi(RTC) R TC input frequency - - 32.768 - kHz

Table 10. Dynamic characteristic: I/O pins[1]

Tamb =





C to +85



C; VDD(3V3) over specified ranges.

Symbol Parameter Conditions Min Typ Max Unit

trrise time pin configured as output 3.0 - 5.0 ns

tffall time pin configured as output 2.5 - 5.0 ns

Table 1 1 . Dynamic characteristics of USB pins (full-speed)

CL = 50 pF; Rpu = 1.5 k



on D+ to VDD(3V3),unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

trrise time 10 % to 90 % 8.5 - 13.8 ns

tffall time 10 % to 90 % 7.7 - 13.7 ns

tFRFM differential rise and fall time

matching tr/t

f--109%

VCRS output signal crossover voltage 1.3 - 2.0 V

tFEOPT source SE0 interval of EOP see Figure 15 160 - 175 ns

tFDEOP source jitter for differential transition

to SE0 transition see Figure 15 2-+5ns

tJR1 receiver jitter to next transition 18.5 - +18.5 ns

tJR2 receiver jitter for paired transitions 10 % to 90 % 9-+9ns

tEOPR1 EOP width at receiver must reject as

EOP; see

Figure 15

[1] 40 --ns

tEOPR2 EOP width at receiver must accept as

EOP; see

Figure 15

[1] 82 --ns

Product data sheet Rev. 3 — 15 October 2013 50 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

11.4 Flash memory

[1] Number of program/erase cycles.

[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes.

Table 12. Dynamic characteristics of flash

Tamb =





C to +85



C, unless otherwise specified; VDD(3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to

ground.

Symbol Parameter Conditions Min Typ Max Unit

Nendu endurance [1] 10000 100000 - cycles

tret retention time powered; 100 cycles [2] 10--years

unpowered;  100 cycles 20 - - years

ter erase time sector or mu ltiple

consecutive sectors 95 100 105 ms

tprog programming time [2] 0.95 1 1.05 ms

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 3 — 15 October 2013 51 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

11.5 Static external memory interface

[1] VOH = 2.5 V, VOL = 0.2 V.

[2] VIH = 2.5 V, VIL = 0.5 V.

[3] Tcy(CCLK) = 1⁄CCLK.

[4] Latest of address valid, CS LOW, OE LOW to data valid.

[5] Earliest of CS HIGH, OE HIGH, address change to data invalid.

Table 13. Dynamic characteristics: Static external memory interface

CL=30pF, T

amb =





C to 85



C, VDD(DCDC)(3V3) = VDD(3V3) = 3.0 V to 3.6 V.

Symbol Parameter Conditions Min Typ Max Unit

Common to read and write cycles[1]

tCSLAV CS LOW to address valid time 0.29 0.20 2.54 ns

Read cycle parameters[1][2]

tOELAV OE LOW to address valid time 0.29 0.20 2.54 ns

tCSLOEL CS LOW to OE LOW time 0.78 + Tcy(CCLK)  WA ITOEN 0 + Tcy(CCLK)  WAITOEN 0.49 + Tcy(CCLK)  WAITOEN ns

tam memory access time [3][4] (WAITRD  WAITOEN + 1) 

Tcy(CCLK)  12.70 (WAITRD  WAITOEN + 1) 

Tcy(CCLK)  9.57 (WAITRD  WAITOEN + 1) 

Tcy(CCLK)  8.11 ns

th(D) data input hold time [5] 0--ns

tCSHOEH CS HIGH to OE HIGH time 0.49 0 0.20 ns

tOEHANV OE HIGH to address invalid

time 0.20 0.20 2.44 ns

tOELOEH OE LOW to OE HIGH time 0.59 + (WAITRD 

WAITOEN + 1)  Tcy(CCLK)

0 + (W AITRD  WAITOEN +

1)  Tcy(CCLK)

0.10 + (WAITRD 

WAITOEN + 1)  Tcy(CCLK)

Write cycle parameters[1]

tCSLBLSL CS LOW to BLS LOW time 0.88 + Tcy(CCLK)  (1 +

WAITWEN) 0.10 + Tcy(CCLK)  (1 +

WAITWEN) 0.20 + Tcy(CCLK)  (1 +

WAITWEN) ns

tBLSLDV BLS LOW to data valid time 0.68 2.54 5.86 ns

tCSLDV CS LOW to data valid time 0 2.64 4.79 ns

tBLSLBLSH BLS LOW to BLS HIGH time [3] 0.78 + Tcy(CCLK) 

(WAITWR  WAITWEN + 1) 0 + Tcy(CCLK)  (WAITWR 

WAITWEN + 1) 0.10 + Tcy(CCLK) 

(WAITWR  WAITWEN + 1) ns

tBLSHANV BLS HIGH to address invalid

time [3] 0 + Tcy(CCLK) 0.20 + Tcy(CCLK) 2.74 + Tcy(CCLK) ns

tBLSHDNV BLS HIGH to data invalid time [3] 0.78 2.54 5.96 ns

Product data sheet Rev. 3 — 15 October 2013 52 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

11.6 Timing

Fig 13. External memory read access

addr

data

tCSLAV

tOELAV

tOELOEH

tCSLOEL

tam th(D)

tCSHOEH

tOEHANV

002aaf489

Fig 14. External memory write access

addr

data

BLS

tCSLBLSL tBLSDV

tCSLDV

tBLSLBLSH

tBLSHANV

tBLSHDNV

002aaf490

tCSLAV

Product data sheet Rev. 3 — 15 October 2013 53 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

Fig 15. D iffe ren t ia l da ta-to-EOP transition skew and EOP width

002aab561

TPERIOD

differential

data lines

crossover point

source EOP width: tFEOPT

receiver EOP width: tEOPR1, tEOPR2

crossover point

extended

differential data to

SE0/EOP skew

n × TPERIOD + tFDEOP

Fig 16. MISO line set-up time in SSP Master mode

tsu(SPI_MISO)

SCK

shifting edges

MOSI

MISO

002aad326

sampling edges

Product data sheet Rev. 3 — 15 October 2013 54 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

12. ADC electrical characteristics

[1] Conditions: VSSA =0V, V

DDA =3.3V.

[2] The ADC is monotonic, there are no missing codes.

[3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 17.

[4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 17.

[5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 17.

[6] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

error, and the straight line which fits the ideal transfer curve. See Figure 17.

[7] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

ADC and the ideal transfer curve. See Figure 17.

[8] See Figure 18.

Table 14. ADC electrical characteristics

VDDA = 2.5 V to 3.6 V; Tamb =





C to +85



C unless otherwise specified; ADC frequency 4.5 MHz.

Symbol Parameter Conditions Min Typ Max Unit

VIA analog input vol tage 0 - VDDA V

Cia analog input capacitance - - 1 pF

EDdifferential linearity error [1][2][3] --1LSB

EL(adj) integral non-linearity [1][4] --2LSB

EOoffset error [1][5] --3LSB

EGgain error [1][6] --0.5 %

ETabsolute er ror [1][7] --4LSB

Rvsi voltage source interface

resistance [8] --40k

Product data sheet Rev. 3 — 15 October 2013 55 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (ED).

(4) Integral non-linearity (EL(adj)).

(5) Center of a step of the actual transfer curve.

Fig 17. ADC characteristics

1023

1022

1021

1020

1019

(2)

(1)

10241018 1019 1020 1021 1022 1023

7123456

1018

(5)

(4)

(3)

1 LSB

(ideal)

code

out

offset

error

gain

error

offset error

VIA (LSBideal)

002aae604

Vi(VREF) − VSSA

1024

1 LSB =

Product data sheet Rev. 3 — 15 October 2013 56 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

Fig 18. Suggested ADC interface - LPC2388 AD0[y] pin

LPC23XX

AD0[y]SAMPLE AD0[y]

20 kΩ

3 pF 5 pF

Rvsi

VSS

VEXT

002aac610

Product data sheet Rev. 3 — 15 October 2013 57 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

13. DAC electrical characteristics

14. Application information

14.1 Suggested USB interface solutions

Table 15. DAC electrical characteristics

VDDA = 3.0 V to 3.6 V; Tamb =





C to +85



C unless otherwise specified

Symbol Parameter Conditions Min Typ Max Unit

EDdifferential linearity error - 1- LSB

EL(adj) integral non-linearity - 1.5 - LSB

EOoffset error - 0.6 - %

EGgain error - 0.6 - %

CLload capacitance - 200 - pF

RLload resistance 1 - - k

Fig 19. LPC2388 USB interface on a self-powered device (applies to USB ports 1 and 2)

LPC23XX

USB-B

connector

USB_D+

USB_CONNECT

SoftConnect switch

USB_D−

BUS

DD(3V3)

1.5 kΩ

RS = 33 Ω

002aac578

RS = 33 Ω

USB_UP_LED

Product data sheet Rev. 3 — 15 October 2013 58 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

Fig 20. LPC2388 USB interface on a bus-powered device (applies to USB ports 1 and 2)

LPC23XX

VDD(3V3)

1.5 kΩ

USB_UP_LED

002aac579

USB-B

connector

USB_D+

USB_D−

VBUS

VSS

RS = 33 Ω

Product data sheet Rev. 3 — 15 October 2013 59 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

Fig 21. LPC2388 USB OTG port configu rat i on: USB port 1 OTG dual-role device, USB port 2 host

USB_UP_LED1

USB_D+1

USB_D−1

USB_PWRD2

USB_SDA1

USB_SCL1

RSTOUT

15 kΩ15 kΩ

LPC2388

USB-A

connector

Mini-AB

connector

33 Ω

VDD

USB_UP_LED2 VDD

USB_OVRCR2

LM3526-L

ENA

5 V

OUTA

FLAGA

VDD

D+

D−

VBUS

USB_PPWR2

USB_D+2

USB_D−2

002aad336

R4 R5 R6

R1 R2 R3 R4

USB_INT1

RESET_N

ADR/PSW

SPEED

SUSPEND

OE_N/INT_N

SCL

SDA

INT_N

VBUS

ISP1301 VSS

VSS

Product data sheet Rev. 3 — 15 October 2013 60 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

Fig 22. LPC2388 USB OTG port configuration: VP_VM mode

USB_TX_DP1

USB_TX_DM1

USB_RCV1

USB_RX_DP1

USB_RX_DM1

USB_SCL1

USB_SDA1

SPEED

ADR/PSW

SDA

SCL

RESET_N

INT_N

SUSPEND

OE_N/INT_N

SE0_VM

DAT_VP

RCV

VBUS

LPC2388 ISP1301 USB MINI-AB

connector

33 Ω

002aad337

USB_TX_E1

RSTOUT

VDD

USB_INT1

USB_UP_LED1 VDD

VSS

Product data sheet Rev. 3 — 15 October 2013 61 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

Fig 23. LPC2388 USB OTG port configuration: USB port 2 device, USB port 1 host

USB_UP_LED1

USB_D+1

USB_D−1

USB_PWRD1

15 kΩ15 kΩ

LPC2388

USB-A

connector

USB-B

connector

33 Ω

002aad335

VDD

USB_UP_LED2

USB_CONNECT2

VDD

USB_OVRCR1

USB_PPWR1

LM3526-L

ENA

5 V

FLAGA

OUTA

VDD

D+

D−

D+

D−

VBUS

USB_D+2

USB_D−2

VBUS VBUS

VSS

Product data sheet Rev. 3 — 15 October 2013 62 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

14.2 Crystal oscillator XTAL input and component selection

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommende d that the inpu t be coupled throug h a cap acitor with

Ci = 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground Cg which attenuates the input voltage by a factor Ci / (Ci + Cg). In

slave mode, a minimum of 200 mV (RMS) is needed.

Fig 24. LPC2388 USB OTG port configuration: USB port 1 host, USB port 2 host

USB_UP_LED1

USB_D+1

USB_D−1

USB_PWRD1

USB_PWRD2

15 kΩ

15 kΩ15 kΩ

15 kΩ

LPC2388

USB-A

connector

USB-A

connector

33 Ω

002aad338

VDD

USB_UP_LED2 VDD

USB_OVRCR1

USB_OVRCR2

USB_PPWR1

LM3526-L

ENA

ENB

5 V

FLAGA

OUTA

OUTB

FLAGB

VDD

D+

D−

D+

D−

VBUS

USB_PPWR2

USB_D+2

USB_D−2

VSS

Fig 25. Slave mode operation of the on-chip oscillator

LPC2xxx

XTAL1

100 pF Cg

002aae718

Product data sheet Rev. 3 — 15 October 2013 63 of 74

NXP Semiconductors LPC2388

Single-chip 16-bit/32-bit microcontroller

In slave mode the input clock signal should be coup led by means of a cap acitor of 100 pF

(Figure 25), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This

corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

The XTALOUT pin in this configuration can be left unconnected.

External components and models used in oscillation mode are shown in Figure 26 and in

Table 16 and Tab