IC41C4405x and IC41LV4405x Series
Integrated Circuit Solution Inc. 1
DR013-0B 10/17/2002
Document Title
4Mx4 bit Dynamic RAM with Fast Page Mode
Revision History
Revision No History Draft Date Remark
0A Initial Draft June 10,2001 Preliminary
0B add Industrial grade parts October 17,2002
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
IC41C4405x and IC41LV4405x Series
2 Integrated Circuit Solution Inc.
DR013-0B 10/17/2002
FEATURES
• Fast Page Mode Access Cycle
• TTL compatible inputs and outputs
• Refresh Interval:
-- 2,048 cycles/32 ms
-- 4,096 cycles/64 ms
• Refresh Mode: RAS-Only,
CAS-before-RAS (CBR), and Hidden
• JEDEC standard pinout
• Single power supply:
5V ± 10% or 3.3V ± 10%
• Byte Write and Byte Read operation via
two CAS
DESCRIPTION
The ICSI 4405x Series is a 4,194,304 x 4-bit high-performance
CMOS Dynamic Random Access Memory. The Fast Page
Mode allows 2,048 or 4096 random accesses within a single
row with access cycle time as short as 20 ns per 4-bit word.
These features make the 4405x Series ideally suited for high-
bandwidth graphics, digital signal processing, high-performance
computing systems, and peripheral applications.
The 4405x Series is packaged in a 24-pin 300mil SOJ and a 24
pin TSOP-2
4M x 4 (16-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
KEY TIMING PARAMETERS
Parameter -50 -60 Unit
RAS Access Time (tRAC)5060ns
CAS Access Time (tCAC)1315ns
Column Address Access Time (tAA)2530ns
Fast Page Mode Cycle Time (tPC)2025ns
Read/Write Cycle Time (tRC) 84 104 ns
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
PRODUCT SERIES OVERVIEW
Part No. Refresh Voltage
IS41C44052 2K 5V ± 10%
IS41C44054 4K 5V ± 10%
IS41LV44052 2K 3.3V ± 10%
IS41LV44054 4K 3.3V ± 10%
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O0
I/O1
WE
RAS
*A11(NC)
A10
A0
A1
A2
A3
VCC
GND
I/O3
I/O2
CAS
OE
A9
A8
A7
A6
A5
A4
GND
* A11 is NC for 2K Refresh devices.
PIN DESCRIPTIONS
A0-A11 Address Inputs (4K Refresh)
A0-A10 Address Inputs (2K Refresh)
I/O0-3 Data Inputs/Outputs
WE Write Enable
OE Output Enable
RAS Row Address Strobe
CAS Column Address Strobe
Vcc Power
GND Ground
NC No Connection
PIN CONFIGURATION
24 (26) Pin SOJ, TSOP-2
IC41C4405x and IC41LV4405x Series
Integrated Circuit Solution Inc. 3
DR013-0B 10/17/2002
FUNCTIONAL BLOCK DIAGRAM
OE
WE
CAS CAS WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
4,194,304 x 4
ROW DECODER
DATA I/O BUFFERS
CAS
CONTROL
LOGIC
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O3
RAS
RAS
A0-A10(A11)
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
TRUTH TABLE
Function RASRAS
RASRAS
RAS CASCAS
CASCAS
CAS WEWE
WEWE
WE OEOE
OEOE
OE Address tR/tCI/O
Standby H H X X X High-Z
Read L L H L ROW/COL DOUT
Write: Word (Early Write) L L L X ROW/COL DIN
Read-Write L L H→LL→H ROW/COL DOUT, DIN
Hidden Refresh Read L→H→L L H L ROW/COL DOUT
Write
(1)
L→H→L L L X ROW/COL DOUT
RAS-Only Refresh L H X X ROW/NA High-Z
CBR Refresh H→L L X X X High-Z
Note:
1. EARLY WRITE only.
IC41C4405x and IC41LV4405x Series
4Integrated Circuit Solution Inc.
DR013-0B 10/17/2002
Functional Description
The IC41C4405x and IC41LV4405x are CMOS DRAMs
optimized for high-speed bandwidth, low power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 11 or 12 address bits.
These are entered 11 bits (A0-A10) at a time for the 2K
refresh device or 12 bits (A0-A11) at a time for the 4K
refresh device. The row address is latched by the Row
Address Strobe (RAS). The column address is latched by
the Column Address Strobe (CAS). RAS is used to latch
the first nine bits and CAS is used the latter ten bits.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC
and tOEA are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs
last.
Refresh Cycle
To retain data, 2,048 refresh cycles are required in each
32 ms period, or 4,096 refresh cycles are required in each
64ms period. There are two ways to refresh the memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) or 4096 row addresses (A0 through A11)
with RAS at least once every 32 ms or 64ms respectively.
Any read, write, read-modify-write or RAS-only cycle
refreshes the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 11(12)-bit counter provides the row
addresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
IC41C4405x and IC41LV4405x Series
Integrated Circuit Solution Inc. 5
DR013-0B 10/17/2002
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameters Rating Unit
VTVoltage on Any Pin Relative to GND 5V −1.0 to +7.0 V
3.3V −0.5 to +4.6
VCC Supply Voltage 5V −1.0 to +7.0 V
3.3V −0.5 to +4.6
IOUT Output Current 50 mA
PDPower Dissipation 1 W
TACommercial Operation Temperature 0 to +70 oC
Industrial Operation Temperature −40 to +85 oC
TSTG Storage Temperature −55 to +125 oC
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 5V 4.5 5.0 5.5 V
3.3V 3.0 3.3 3.6
VIH Input High Voltage 5V 2.4 −VCC + 1.0 V
3.3V 2.0 −VCC + 0.3
VIL Input Low Voltage 5V −1.0 −0.8 V
3.3V −0.3 −0.8
TACommercial Ambient Temperature 0 −70 oC
Industrial Operation Temperature −40 −85 oC
CAPACITANCE(1,2)
Symbol Parameter Max. Unit
CIN1Input Capacitance: A0-A10(A11) 5 pF
CIN2Input Capacitance: RAS, CAS, WE, OE 7pF
CIO Data Input/Output Capacitance: I/O0-I/O3 7 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25oC, f = 1 MHz.
IC41C4405x and IC41LV4405x Series
6Integrated Circuit Solution Inc.
DR013-0B 10/17/2002
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter Test Condition Speed Min. Max. Unit
IIL Input Leakage Current Any input 0V < VIN < Vcc −55µA
Other inputs not under test = 0V
IIO Output Leakage Current Output is disabled (Hi-Z) −55µA
0V < V OUT < Vcc
VOH Output High Voltage Level IOH = −5.0 mA with VCC=5V 2.4 −V
IOH = −2.0 mA with VCC=3.3V
VOL Output Low Voltage Level IOL = 4.2 mA with VCC=5V −0.4 V
IOL = 2 mA with VCC=3.3V
ICC1Standby Current: TTL RAS, CAS − VIH 5V −2mA
3.3V −0.5
ICC2Standby Current: CMOS RAS, CAS > VCC − 0.2V 5V −1mA
3.3V −0.5
ICC3Operating Current: RAS, CAS, -50 −120 mA
Random Read/Write(2,3,4) Address Cycling, tRC = tRC (min.) -60 −110
Average Power Supply Current
ICC4Operating Current: RAS = VIL, CAS > VIH -50 −90 mA
Fast Page Mode(2,3,4) tRC = tRC (min.) -60 −80
Average Power Supply Current
ICC5Refresh Current: RAS Cycling, CAS > V IH -50 −120 mA
RAS-Only(2,3) tRC = tRC (min.) -60 −110
Average Power Supply Current
ICC6Refresh Current: RAS, CAS Cycling -50 −120 mA
CBR(2,3,5) tRC = tRC (min.) -60 −110
Average Power Supply Current
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each Fast page cycle.
5. Enables on-chip refresh and address counters.
IC41C4405x and IC41LV4405x Series
Integrated Circuit Solution Inc. 7
DR013-0B 10/17/2002
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50 -60
Symbol Parameter Min. Max. Min. Max. Units
tRC Random READ or WRITE Cycle Time 84 −104 −ns
tRAC Access Time from RAS(6, 7) −50 −60 ns
tCAC Access Time from CAS(6, 8, 15) −13 −15 ns
tAA Access Time from Column-Address(6) −25 −30 ns
tRAS RAS Pulse Width 50 10K 60 10K ns
tRP RAS Precharge Time 30 −40 −ns
tCAS CAS Pulse Width(23) 8 10K 10 10K ns
tCP CAS Precharge Time(9) 9−9−ns
tCSH CAS Hold Time (21) 38 −40 −ns
tRCD RAS to CAS Delay Time(10, 20) 12 37 14 45 ns
tASR Row-Address Setup Time 0 −0−ns
tRAH Row-Address Hold Time 8 −10 −ns
tASC Column-Address Setup Time(20) 0−0−ns
tCAH Column-Address Hold Time(20) 8−10 −ns
tAR Column-Address Hold Time 30 −40 −ns
(referenced to RAS)
tRAD RAS to Column-Address Delay Time(11) 10 25 12 30 ns
tRAL Column-Address to RAS Lead Time 25 −30 −ns
tRPC RAS to CAS Precharge Time 5 −5−ns
tRSH RAS Hold Time 8 −10 −ns
tRHCP RAS Hold Time from CAS Precharge 30 −35 −ns
tCLZ CAS to Output in Low-Z(15, 24) 0−0−ns
tCRP CAS to RAS Precharge Time(21) 5−5−ns
tOD Output Disable Time(19, 24) 315 315 ns
tOE Output Enable Time(15, 16) −12 −15 ns
tOED Output Enable Data Delay (Write) 12 −15 −ns
tOEHC OE HIGH Hold Time from CAS HIGH 5 −5−ns
tOEP OE HIGH Pulse Width 10 −10 −ns
tOES OE LOW to CAS HIGH Setup Time 5 −5−ns
tRCS Read Command Setup Time(17, 20) 0−0−ns
tRRH Read Command Hold Time 0 −0−ns
(referenced to RAS)(12)
tRCH Read Command Hold Time 0 −0−ns
(referenced to CAS)(12, 17, 21)
tWCH Write Command Hold Time(17) 8−10 −ns
tWCR Write Command Hold Time 40 −50 −ns
(referenced to RAS)(17)
tWP Write Command Pulse Width(17) 8−10 −ns
tWPZ WE Pulse Widths to Disable Outputs 7 −7−ns
tRWL Write Command to RAS Lead Time(17) 13 −15 −ns
tCWL Write Command to CAS Lead Time(17, 21) 8−10 −ns
tWCS Write Command Setup Time(14, 17, 20) 0−0−ns
tDHR Data-in Hold Time (referenced to RAS)39−39 −ns
IC41C4405x and IC41LV4405x Series
8Integrated Circuit Solution Inc.
DR013-0B 10/17/2002
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50 -60
Symbol Parameter Min. Max. Min. Max. Units
tACH Column-Address Setup Time to CAS 15 −15 −ns
Precharge during WRITE Cycle
tOEH OE Hold Time from WE during 8 −10 −ns
READ-MODIFY-WRITE cycle(18)
tDS Data-In Setup Time(15, 22) 0−0−ns
tDH Data-In Hold Time(15, 22) 8−10 −ns
tRWC READ-MODIFY-WRITE Cycle Time 108 −133 −ns
tRWD RAS to WE Delay Time during 64 −77 −ns
READ-MODIFY-WRITE Cycle(14)
tCWD CAS to WE Delay Time(14, 20) 26 −32 −ns
tAWD Column-Address to WE Delay Time(14) 39 −47 −ns
tPC Fast Page Mode READ or WRITE 20 −25 −ns
Cycle Time
tRASP RAS Pulse Width 50 100K 60 100K ns
tCPA Access Time from CAS Precharge(15) −30 −35 ns
tPRWC READ-WRITE Cycle Time 5 6 −68 −ns
tCOH Data Output Hold after CAS LOW 5 −5−ns
tOFF Output Buffer Turn-Off Delay from 0 12 0 15 ns
CAS or RAS(13,15,19, 24)
tWHZ Output Disable Delay from WE 310 310 ns
tCSR CAS Setup Time (CBR REFRESH)(20, 25) 5−5−ns
tCHR CAS Hold Time (CBR REFRESH)( 21, 25) 8−10 −ns
tORD OE Setup Time prior to RAS during 0 −0−ns
HIDDEN REFRESH Cycle
tREF Auto Refresh Period 2,048 Cycles −32 −32 ms
4,096 Cycles −64 −64
tTTransition Time (Rise or Fall)(2, 3) 150 150 ns
AC TEST CONDITIONS
Output load: Two TTL Loads and 50 pF (Vcc = 5.0V + 10%)
One TTL Load and 50 pF (Vcc = 3.3V + 10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V + 10%)
VIH = 2.4V, VIL = 0.8V (Vcc = 3.3V + 10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5.0V + 10%, 3.3V + 10%)
IC41C4405x and IC41LV4405x Series
Integrated Circuit Solution Inc. 9
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Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH
and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
by the amount that tRCD exceeds the value shown.
8. Assumes that tRCD > tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS > tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD > tRWD
(MIN), tAWD > tAWD (MIN) and tCWD > tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a
LATE WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW
and OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. Determined by falling edge of CAS.
21. Determined by rising edge of CAS.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
23. CAS must meet minimum pulse width.
24. The 3 ns minimum is a parameter guaranteed by design.
25. Enables on-chip refresh and address counters.
IC41C4405x and IC41LV4405x Series
10 Integrated Circuit Solution Inc.
DR013-0B 10/17/2002
FAST-PAGE-MODE READ CYCLE
tRAS tRC tRP
tAR
tCAH
tASC
tRAD tRAL
OE
I/O
WE
ADDRESS
CAS
RAS
Row Column Row
Open Open
Valid Data
tCSH
tCAS
tRSH
tCRP tCLCH
tRCD
tRAHtASR
tRRH
tRCHtRCS
tAA
tCAC tOFF
(1)
tRAC
tCLC
tOES
tOE tOD
Don’t Care
IC41C4405x and IC41LV4405x Series
Integrated Circuit Solution Inc. 11
DR013-0B 10/17/2002
FAST PAGE MODE READ-MODIFY-WRITE CYCLE
Don’t Care
OUT
t
AR
t
RWD
t
AWD
I/O
WE
OE
ADDRESS
CAS
RAS
Row Column Column Column
t
AR
t
CSH
t
CAS
t
CAS
t
CAS
t
RASP
t
RSH
t
PRWC
t
RCD
t
CWD
t
CWD
t
CWD
t
CRP
t
ASR
t
RAD
t
RCS
t
ASC
t
ASC
t
ASC
t
RAL
t
CAH
t
CP
t
CP
t
RP
t
CAH
t
AWD
t
AWD
t
CAC
t
AA
t
DH
t
CLZ
t
RAC
t
DH
t
DH
t
OE
t
CLZ
t
CAC
t
OE
t
CAC
t
OE
OUT
OUT ININ IN
t
OEZ
t
OEZ
t
OED
t
OED
t
DS
t
OEZ
t
OED
t
DS
t
CLZ
t
AA
t
AA
t
WP
t
RAH
t
WP
t
WP
t
CWL
t
CWL
t
CWL
t
RWL
t
CPWD
t
CPWD
t
CAH
t
CRP
t
DS
IC41C4405x and IC41LV4405x Series
12 Integrated Circuit Solution Inc.
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FAST-PAGE-MODE EARLY WRITE CYCLE (OE = DON'T CARE)
tRAS tRC tRP
tAR
tCAH
tASC
tRAD tRAL
tACH
I/O
WE
ADDRESS
CAS
RAS
Row Column Row
tCSH
tCAS
tRSH
tCRP tCLCH
tRCD
tRAHtASR
tCWL
tWCR tWCH
tRWL
tWP
tWCS
tDH
tDS
tDHR
Valid Data
Don’t Care
IC41C4405x and IC41LV4405x Series
Integrated Circuit Solution Inc. 13
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FAST-PAGE-MODE READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
t
RAS
t
RWC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
WE
OE
ADDRESS
CAS
RAS
Row Column Row
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
RWD
t
CWL
t
CWD
t
RWL
t
AWD
t
WP
t
RCS
t
CAC
t
CLZ
t
DS
t
DH
t
OEH
t
OD
t
OE
t
RAC
t
AA
I/O Open Open
Valid DOUT Valid DIN
Don’t Care
IC41C4405x and IC41LV4405x Series
14 Integrated Circuit Solution Inc.
DR013-0B 10/17/2002
FAST PAGE MODE EARLY WRITE CYCLE
Don’t Care
tAR
I/O
WE
OE
ADDRESS
CAS
RAS
Row Column Column Column
tAR
tCWL
tWCR
tDHR
tCSH tCAS tCAS tCAS
tRASP
tRSH
tRHCP
tPC
tRCD
tCRP
tASR
tWCS
tDS
tRAD tASC tASC tASC
tRAL
tCAH
tWCH
tDH tDS tDS
tDH tDH
tCP tCP
tRP
tCAH
tRAH tCAH
tCRP
tCWL
tWCS tWCS
tWCH
tWP tWP
tCWL
tWCH
tWP
Valid D
IN
Valid D
IN
Valid D
IN
IC41C4405x and IC41LV4405x Series
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AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RASRAS
RASRAS
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
tAR
tCAH tASC
tASC
tRAD
OE
I/O
WE
ADDRESS
CAS
RAS
Row Column
Open Open
Valid Data
tCSH tCAS
tCRP tRCD tCP
tRAHtASR
tRCH tRCStRCS
tAA
tCAC tWHZ
tRAC
tCLZ
tCLZ
tOE tOD
Column
tRAS tRC tRP
I/O
ADDRESS
CAS
RAS
Row Row
Open
tCRP
tRAHtASR
tRPC
Don’t Care
Don’t Care
IC41C4405x and IC41LV4405x Series
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HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
CBRCBR
CBRCBR
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
t
RAS
t
RAS
t
RP
t
RP
I/O
CAS
RAS
Open
t
CP
t
RPC
t
CSR
t
CHR
t
RPC
t
CSR
t
CHR
t
RAS
t
RAS
t
RP
CAS
RAS
t
CRP
t
RCD
t
RSH
t
CHR
t
AR
t
ASC
t
RAD
ADDRESS Row Column
t
RAH
t
ASR
t
RAL
t
CAH
I/O Open Open
Valid Data
t
AA
t
CAC
t
RAC
t
CLZ
t
OFF
(2)
OE
t
OE
t
ORD
t
OD
Don’t Care
Don’t Care
IC41C4405x and IC41LV4405x Series
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ORDERING INFORMATION
Commercial Range: 0°°
°°
°C to 70°°
°°
°C
Voltage: 5V
Speed (ns) Order Part No. Refresh Package
50 IC41C44052-50J 2 K 300mil SOJ
50 IC41C44052-50T 2K 300mil TSOP-2
60 IC41C44052-60J 2 K 300-mil SOJ
60 IC41C44052-60T 2K 300mil TSOP-2
Speed (ns) Order Part No. Refresh Package
50 IC41C44054-50J 4 K 300mil SOJ
50 IC41C44054-50T 4K 300mil TSOP-2
60 IC41C44054-60J 4 K 300mil SOJ
60 IC41C44054-60T 4K 300mil TSOP-2
Voltage: 3.3V
Speed (ns) Order Part No. Refresh Package
50 IC41LV44052-50J 2K 300mil SOJ
50 IC41LV44052-50T 2K 300mil TSOP-2
60 IC41LV44052-60J 2K 300mil SOJ
60 IC41LV44052-60T 2K 300mil TSOP-2
Speed (ns) Order Part No. Refresh Package
50 IC41LV44054-50J 4K 300mil SOJ
50 IC41LV44054-50T 4K 300mil TSOP-2
60 IC41LV44054-60J 4K 300mil SOJ
60 IC41LV44054-60T 4K 300mil TSOP-2
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
IC41C4405x and IC41LV4405x Series
18 Integrated Circuit Solution Inc.
DR013-0B 10/17/2002
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
ORDERING INFORMATION
Industrial Range: -40°°
°°
°C to 85°°
°°
°C
Voltage: 5V
Speed (ns) Order Part No. Refresh Package
50 IC41C44052-50JI 2K 300mil SOJ
50 IC41C44052-50TI 2K 300mil TSOP-2
60 IC41C44052-60JI 2K 300-mil SOJ
60 IC41C44052-60TI 2K 300mil TSOP-2
Speed (ns) Order Part No. Refresh Package
50 IC41C44054-50JI 4K 300mil SOJ
50 IC41C44054-50TI 4K 300mil TSOP-2
60 IC41C44054-60JI 4K 300mil SOJ
60 IC41C44054-60TI 4K 300mil TSOP-2
Voltage: 3.3V
Speed (ns) Order Part No. Refresh Package
50 IC41LV44052-50JI 2K 300mil SOJ
50 IC41LV44052-50TI 2K 300mil TSOP-2
60 IC41LV44052-60JI 2K 300mil SOJ
60 IC41LV44052-60TI 2K 300mil TSOP-2
Speed (ns) Order Part No. Refresh Package
50 IC41LV44054-50JI 4K 300mil SOJ
50 IC41LV44054-50TI 4K 300mil TSOP-2
60 IC41LV44054-60JI 4K 300mil SOJ
60 IC41LV44054-60TI 4K 300mil TSOP-2
