Low Cost 225 MHz
16 × 16 Crosspoint Switches
AD8114/AD8115
Rev. B
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
16 × 16 high speed nonblocking switch arrays
AD8114; G = 1
AD8115; G = 2
Serial or parallel programming of switch array
Serial data out allows daisy-chaining of multiple
16 × 16 arrays to create larger switch arrays
High impedance output disable allows connection of
multiple devices without loading the output bus
For smaller arrays see the AD8108/AD8109 (8 × 8) or
AD8110/AD8111 (16× 8) switch arrays
Complete solution
Buffered inputs
Programmable high impedance outputs
16 output amplifiers, AD8114 (G = 1), AD8115 (G = 2)
Drives 150 Ω loads
Excellent video performance
25 MHz, 0.1 dB gain flatness
0.05%/0.05° differential gain/differential phase error
(RL = 150 Ω)
Excellent ac performance
−3 dB bandwidth: 225 MHz
Slew rate: 375 V/µs
Low power of 700 mW (2.75 mW per point)
Low all hostile crosstalk of −70 dB @ 5 MHz
Reset pin allows disabling of all outputs (connected through
a capacitor to ground provides power-on reset capability)
100-lead LQFP (14 mm × 14 mm)
APPLICATIONS
Routing of high speed signals including
Video (NTSC, PAL, S, SECAM, YUV, RGB)
Compressed video (MPEG, wavelet)
3-level digital video (HDB3)
Datacomms
Telecomms
GENERAL DESCRIPTION
The AD8114/AD81151 are high speed 16 × 16 video crosspoint
switch matrices. They offer a −3 dB signal bandwidth greater
than 200 MHz and channel switch times of less than 50 ns
with 1% settling. With −70 dB of crosstalk and −90 dB isolation
(@ 5 MHz), the AD8114/AD8115 are useful in many high speed
applications. The differential gain and differential phase of better
than 0.05% and 0.05°, respectively, along with 0.1 dB
FUNCTIONAL BLOCK DIAGRAM
AD8114/AD8115
OUTPUT
BUFFER
G = +1,
G = +2
80
80
256
80-BIT SHIFT REGISTER
WITH 5-BIT
PARALLEL LOADING
PARALLEL LATCH
DECODE
16 × 5:16 DECODERS 16
CLK
DATA IN
UPDATE
CE
RESET
16 INPUTS
A0
DATA
OUT
16
OUTPUTS
SET
INDIVIDUAL
OR RESET
ALL OUTPUTS
TO "OFF"
A1
A2
SER/PAR D0 D1 D2 D3 D4
ENABLE/DISABLE
A3
SWITCH
MATRIX
01070-001
Figure 1.
flatness out to 25 MHz while driving a 75 Ω back-terminated
load, make the AD8114/AD8115 ideal for all types of signal
switching.
The AD8114/AD8115 include 16 independent output buffers
that can be placed into a high impedance state for paralleling
crosspoint outputs so that off channels do not load the output
bus. The AD8114 has a gain of 1, while the AD8115 offers a
gain of 2. They operate on voltage supplies of ±5 V while
consuming only 70 mA of idle current. The channel switching is
performed via a serial digital control (which can accommodate
daisy-chaining of several devices) or via a parallel control,
allowing updating of an individual output without
reprogramming the entire array.
The AD8114/AD8115 is packaged in 100-lead LQFP package
and is available over the extended industrial temperature range
of −40°C to +85°C.
1Patent pending.
AD8114/AD8115
Rev. B | Page 2 of 32
TABLE OF CONTENTS
AD8114/AD8115—Specifications ................................................. 3
Timing Characteristics (Serial) .................................................. 5
Timing Characteristics (Parallel) ............................................... 6
Absolute Maximum Ratings............................................................ 8
Maximum Power Dissipation ..................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
I/O Schematics................................................................................ 17
Theory of Operation ...................................................................... 18
Applications................................................................................. 18
Power-On Reset .......................................................................... 19
Gain Selection............................................................................. 19
Creating Larger Crosspoint Arrays.......................................... 20
Multichannel Video ................................................................... 21
Crosstalk ...................................................................................... 22
PCB Layout...................................................................................... 25
Evaluation Board ............................................................................ 29
Control the Evaluation Board from a PC................................ 30
Overshoot of PC Printer Ports’ Data Lines............................. 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
REVISION HISTORY
9/05—Rev. A to Rev. B
Updated Format.................................................................. Universal
Change to Figure 3 ............................................................................6
Change to Absolute Maximum Ratings..........................................8
Changes to Maximum Power Dissipation Section........................8
Updated Outline Dimensions........................................................31
Changes to Ordering Guide ...........................................................31
11/01—Rev. 0 to Rev. A
Edits to ORDERING GUIDE...........................................................5
Comments added to Outline Dimensions ...................................26
Revision 0: Initial Version
AD8114/AD8115
Rev. B | Page 3 of 32
AD8114/AD8115—SPECIFICATIONS
VS = ±5 V, TA = +25°C, RL = 1 kΩ, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth 200 mV p-p, RL = 150 Ω 150/125 225/200 MHz
2 V p-p, RL = 150 Ω 100/125 MHz
Gain Flatness 0.1 dB, 200 mV p-p, RL = 150 Ω 25/40 MHz
0.1 dB, 2 V p-p, RL = 150 Ω 20/40 MHz
Propagation Delay 2 V p-p, RL = 150 Ω 5 ns
Settling Time 0.1%, 2 V step, RL = 150 Ω 40 ns
Slew Rate 2 V step, RL = 150 Ω 375/450 V/µs
NOISE/DISTORTION PERFORMANCE
Differential Gain Error NTSC or PAL, RL = 1 kΩ 0.05 %
NTSC or PAL, RL = 150 Ω 0.05 %
Differential Phase Error NTSC or PAL, RL = 1 kΩ 0.05 Degrees
NTSC or PAL, RL = 150 Ω 0.05 Degrees
Crosstalk, All Hostile f = 5 MHz −70/−64 dB
f = 10 MHz −60/−52 dB
Off Isolation, Input-Output f = 10 MHz, RL = 150 Ω, one channel −90 dB
Input Voltage Noise 0.01 MHz to 50 MHz 16/18 nV/√Hz
DC PERFORMANCE
Gain Error No load 0.05/0.2 0.08/0.6 %
R
L = 1 kΩ 0.05/0.2 %
R
L = 150 Ω 0.2/0.35 %
Gain Matching No load, channel-channel 0.01/0.5 0.04/1 %
R
L = 1 kΩ channel-channel 0.01/0.5 %
Gain Temperature Coefficient 0.75/1.5 ppm/°C
OUTPUT CHARACTERISTICS
Output Impedance DC, enabled 0.2 Ω
Disabled 10 MΩ
Output Disable Capacitance Disabled 5 pF
Output Leakage Current Disabled 1 µA
Output Voltage Range No load ±3.0 ±3.3 V
Voltage Range IOUT = 20 mA ±2.5 ±3 V
Short-Circuit Current 65 mA
INPUT CHARACTERISTICS
Input Offset Voltage Worst case (all configurations) 3 15 mV
Temperature coefficient 10 µV/°C
Input Voltage Range No load ±3/±1.5 ±3.5 V
Input Capacitance Any switch configuration 5 pF
Input Resistance 1 10 MΩ
Input Bias Current Per output selected 2 5 µA
SWITCHING CHARACTERISTICS
Enable On Time 60 ns
Switching Time, 2 V Step 50% UPDATE to 1% settling 50 ns
Switching Transient (Glitch) 20/30 mV p-p
AD8114/AD8115
Rev. B | Page 4 of 32
Parameter Conditions Min Typ Max Unit
POWER SUPPLIES
Supply Current AVCC, outputs enabled, no load 70/80 mA
AVCC, outputs disabled 27/30 mA
AVEE, outputs enabled, no load 70/80 mA
AVEE, outputs disabled 27/30 mA
DVCC, outputs enabled, no load 16 mA
Supply Voltage Range ±4.5 to ±5.5 V
PSRR DC 64 80 dB
f = 100 kHz 66 dB
f = 1 MHz 46 dB
OPERATING TEMPERATURE RANGE
Temperature Range Operating (still air) −40 to +85 °C
θJA Operating (still air) 40 °C/W
AD8114/AD8115
Rev. B | Page 5 of 32
TIMING CHARACTERISTICS (SERIAL)
Table 2. Timing Characteristics
Parameter Symbol Min Typ Max Unit
Serial Data Setup Time t120 ns
CLK Pulse Width t2100 ns
Serial Data Hold Time t320 ns
CLK Pulse Separation, Serial Mode t4100 ns
CLK to UPDATE Delay t50 ns
UPDATE Pulse Width t650 ns
CLK to DATA OUT Valid, Serial Mode t7 200 ns
Propagation Delay, UPDATE to Switch On or Off – 50 ns
Data Load Time, CLK = 5 MHz, Serial Mode – 16 µs
CLK, UPDATE Rise and Fall Times – 100 ns
RESET Time – 200 ns
Table 3. Logic Levels
VIH VIL VOH VOL IIH IIL IOH IOL
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
DATA OUT
DATA OUT
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
DATA OUT
DATA OUT
2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max −400 µA min −400 µA max 3.0 mA min
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
1
0
1
0
DATA IN
CLK
1 = LATCHED
0 = TRANSPAREN
T
DATA OUT
OUT7 (D4) OUT7 (D3) OUT00 (D0)
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t
7
t
1
t
3
t
6
t
2
t
4
t
5
UPDATE
01070-002
Figure 2. Timing Diagram, Serial Mode
AD8114/AD8115
Rev. B | Page 6 of 32
TIMING CHARACTERISTICS (PARALLEL)
Table 4. Timing Characteristics
Parameter Symbol Min Typ Max Unit
Data Setup Time t120 ns
CLK Pulse Width t2100 ns
Data Hold Time t320 ns
CLK Pulse Separation t4100 ns
CLK to UPDATE Delay t50 ns
UPDATE Pulse Width t650 ns
Propagation Delay, UPDATE to Switch On or Off – 50 ns
CLK, UPDATE Rise and Fall Times – 100 ns
RESET Time – 200 ns
Table 5. Logic Levels
VIH VIL VOH VOL IIH IIL IOH IOL
RESET, SER/PAR,
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
RESET, SER/PAR,
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
DATA OUT DATA OUT RESET, SER/PAR,
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
RESET, SER/PAR,
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
DATA
OUT
DATA
OUT
2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max −400 µA min −400 µA
max 3.0 mA
min
1
0
1
0
D0–D3
A0–A2
CLK
1 = LATCHED
UPDATE
0 = TRANSPARENT
t
2
t
1
t
5
t
6
t
3
t
4
01070-003
Figure 3. Timing Diagram, Parallel Mode
AD8114/AD8115
Rev. B | Page 7 of 32
Table 6. Operation Truth Table
CE UPDATE CLK DATA IN DATA OUT RESET
SER/
PAR Operation/Comment
1 X X X X X X No change in logic.
0 1 f DataiDatai-80 1 0
The data on the serial DATA IN line is loaded into
serial register. The first bit clocked into the serial register
appears at DATA OUT 80 clocks later.
0 1 f D0…D4,
A0… A3
NA in parallel mode 1 1 The data on the parallel data lines, D0 to D4, are
loaded into the 80 bit serial shift register location
addressed by A0 to A3.
0 0 X X X 1 X Data in the 80-bit shift register transfers into the
parallel latches that control the switch array.
Latches are transparent.
X X X X X 0 X Asynchronous operation. All outputs are disabled.
Remainder of logic is unchanged.
D
CLK
Q
4 TO 16 DECODER
A0
A1
A2
CLK
16
256
DATA IN
(SERIAL)
(OUTPUT
ENABLE)
SER/PAR
CE
UPDATE
OUT0 EN
DATA
OUT
PARALLEL
DATA
DQ
CLK
DQ
CLK
DQ
CLK
DQ
CLK
D1
D2
D3
DQ
CLK
DQ
CLK
DQ
CLK
DQ
CLK
DQ
CLK
OUT1 EN
OUT2 EN
OUT3 EN
OUT4 EN
OUT5 EN
OUT6 EN
OUT7 EN
D
LE
QCLR
OUT15
EN
OUTPUT ENABLESWITCH MATRIX
S
D1
Q
D0
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0 DQ
CLK
S
D1
Q
D0
D4
DECODE
D
LE
QCLR
OUT0
EN
D
LE
OUT0
B0
Q
D
LE
Q
OUT0
B1
D
LE
Q
OUT0
B2
D
LE
Q
OUT0
B3
D
LE
OUT1
B0
Q
D
LE
QCLR
OUT14
EN
D
LE
OUT15
B0
Q
D
LE
OUT15
B1
Q
D
LE
OUT15
B2
Q
DQ
CLK
S
D1
Q
D0
S
D1
Q
D0
D
LE
OUT15
B3
Q
S
D1
Q
D0
OUT8 EN
OUT9 EN
OUT10 EN
OUT11 EN
OUT12 EN
OUT13 EN
OUT14 EN
OUT15 EN
A3
OUTPUT
ADDRESS
RESET
(OUTPUT ENABLE)
01070-011
Figure 4. Logic Diagram
AD8114/AD8115
Rev. B | Page 8 of 32
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Rating
Supply Voltage 12.0 V
Internal Power Dissipation1
AD8114/AD8115 100-Lead
Plastic LQFP (ST)
2.6 W
Input Voltage ±VS
Output Short-Circuit Duration Observe power
derating curves
Storage Temperature Range2−65°C to +125°C
1 Specification is for device in free air (TA = 25°C):
100-lead plastic LQFP (ST): θJA = 40°C/W.
2 Maximum reflow temperatures are to JEDEC industry standard J-STD-020.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8114/AD8115 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for
plastic encapsulated devices is determined by the glass transition
temperature of the plastic, approximately 125°C. Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 125°C for an extended
period can result in device failure.
While the AD8114/AD8115 are internally short-circuit
protected, this may not be sufficient to guarantee that the
maximum junction temperature (125°C) is not exceeded under
all conditions. To ensure proper operation, it is necessary to
observe the maximum power derating curves shown in Figure 5.
TJ = 125°C
AMBIENT TEMPERATURE (°C)
MAXIMUM POWER DISSIPATION (Ω)
5
4
3
2
1
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
01070-004
Figure 5. Maximum Power Dissipation vs. Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD8114/AD8115
Rev. B | Page 9 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
01070-005
NC = NO CONNECT
RESET
CE
DATA OUT
CLK
DATA IN
UPDATE
SER/PAR
NC
NC
NC
NC
NC
NC
NC
NC
NC
A0
A1
A2
A3
D0
D1
D2
D3
D4
26
AVCC13/14
27
OUT13
28
AVEE12/13
29
OUT12
30
AVCC11/12
31
OUT11
32
AVEE10/11
33
OUT10
34
AVCC09/10
35
OUT09
36
AVEE08/09
37
OUT08
38
AVCC07/08
39
OUT07
2
DGND
3
AGND
4
IN08
7
AGND
6
IN09
5
AGND
1
DVCC
8
IN10
9
AGND
10
IN11
12
IN12
13
AGND
14
IN13
15
AGND
16
IN14
17
AGND
18
IN15
19
AGND
20
AVEE
21
AVCC
22
AVCC15
23
OUT15
24
AVEE14/15
25
OUT14
11
AGND
74
DGND
DVCC
73
AGND
72
IN07
69
AGND
70
IN06
71
AGND
75
68
IN05
67
AGND
66
IN04
64
IN03
63
AGND
62
IN02
61
AGND
60
IN01
59
AGND
58
IN00
57
AGND
56
AVEE
55
AVCC
54
AVCC00
53
OUT00
52
AVEE00/01
51
OUT01
65
AGND
40
AVEE06/07
41
OUT06
42
AVCC05/06
43
OUT05
44
AVEE04/05
45
OUT04
46
AVCC03/04
47
OUT03
48
AVEE02/03
49
OUT02
50
AVCC01/02
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PIN 1
AD8114/AD8115
TOP VIEW
(Not to Scale)
Figure 6. Pin Configuration
AD8114/AD8115
Rev. B | Page 10 of 32
Table 8. Pin Function Descriptions
Pin No. Mnemonic Pin Description
58, 60, 62, 64, 66, 68, 70, 72,
4, 6, 8, 10, 12, 14, 16, 18
INxx Analog Inputs. xx = Channels 00 through 15.
96 DATA IN Serial Data Input, TTL Compatible.
97 CLK Clock, TTL Compatible. Falling edge triggered.
98 DATA OUT Serial Data Out, TTL Compatible.
95 UPDATE Enable (Transparent) Low. Allows serial register to connect directly to switch matrix.
Data latched when high.
100 RESET Disable Outputs, Active Low.
99 CE Chip Enable, Enable Low. Must be low to clock in and latch data.
94 SER/PAR Selects Serial Data Mode, Low or Parallel Data Mode, High. Must be connected.
53, 51, 49, 47, 45, 43, 41, 39,
37, 35, 33, 31, 29, 27, 25, 23
OUTyy Analog Outputs. yy = Channels 00 through 15.
3, 5, 7, 9, 11, 13, 15, 17, 19, 57,
59, 61, 63, 65, 67, 69, 71, 73
AGND Analog Ground for Inputs and Switch Matrix. Must be connected.
1, 75 DVCC +5 V for Digital Circuitry.
2, 74 DGND Ground for Digital Circuitry.
20, 56 AVEE −5 V for Inputs and Switch Matrix.
21, 55 AVCC +5 V for Inputs and Switch Matrix.
54, 50, 46, 42, 38, 34, 30, 26, 22 AVCCxx/yy +5 V for Output Amplifier that is Shared by Channels xx and yy. Must be connected.
52, 48, 44, 40, 36, 32, 28, 24 AVEExx/yy –5 V for Output Amplifier that is Shared by Channels xx and yy. Must be connected.
84 A0 Parallel Data Input, TTL Compatible (output select LSB).
83 A1 Parallel Data Input, TTL Compatible (output select).
82 A2 Parallel Data Input, TTL Compatible (output select).
81 A3 Parallel Data Input, TTL Compatible (output select MSB).
80 D0 Parallel Data Input, TTL Compatible (input select LSB)
79 D1 Parallel Data Input, TTL Compatible (input select).
78 D2 Parallel Data Input, TTL Compatible (input select).
77 D3 Parallel Data Input, TTL Compatible (input select MSB).
76 D4 Parallel Data Input, TTL Compatible (output enable).
85 to 93 NC No Connect.
AD8114/AD8115
Rev. B | Page 11 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (MHz)
1
0.1
GAIN (dB)
1 10 100 1000
–1
0
–2
–3
–4
–5
–6
–7
V
O
AS SHOWN
R
L
= 150Ω
GAIN
FLATNESS
2V p-p
200mV p-p
–0.2
0.2
0.1
0
–0.1
–0.3
–0.4
–0.5
FLATNESS (dB)
–0.6
01070-012
Figure 7. AD8114 Frequency Response, RL = 150 Ω
FREQUENCY (MHz)
GAIN (dB)
–7
–3
1
0
–1
–2
–4
–5
–6
–0.6
–0.2
0.2
0.1
0
–0.1
–0.3
–0.4
–0.5
FLATNESS (dB)
2
3
0.1 1 10 100 1000
0.3
0.4
GAIN
FLATNESS
2V p-p
200mV p-p
V
O
AS SHOWN
R
L
= 1kΩ
01070-013
Figure 8. AD8114 Frequency Response, RL = 1 kΩ
FREQUENCY (MHz)
GAIN (dB)
–3
1
0
–1
–2
–4
–5
–6
2
3
0.1 1 10 100 1000
4
R
L
= 1kΩ
R
L
= 150Ω
V
O
= 200mV p-p
R
L
AS SHOWN
C
L
= 18pF
01070-014
Figure 9. AD8114 Frequency Response vs. Load Impedance
FREQUENCY (MHz)
2
0.1
GAIN (dB)
1 10 100 1000
0
1
–1
–2
–3
–4
–5
–6
–8
–7 VO AS SHOWN
RL = 150Ω
GAIN
FLATNESS
200mV p-p
2V p-p
2V p-p
200mV p-p
0
0.5
0.4
0.3
0.2
0.1
–0.1
–0.2
–0.3
–0.4
FLATNESS (dB)
–0.5
01070-015
Figure 10. AD8115 Frequency Response, RL = 150 Ω
FREQUENCY (MHz)
3
0.1
GAIN (dB)
1 10 100 1000
1
2
0
–1
–2
–3
–4
–5
–7
–6 VO AS SHOWN
RL = 1kΩ
GAIN
FLATNESS
200mV p-p
2V p-p
2V p-p
200mV p-p
0
0.5
0.4
0.3
0.2
0.1
–0.1
–0.2
–0.3
–0.4
FLATNESS (dB)
–0.5
01070-016
Figure 11. AD8115 Frequency Response, RL = 1 kΩ
FREQUENCY (MHz)
GAIN (dB)
–4
4
2
0
–2
–6
–8
–10
6
8
0.1 1 10 100 1000
10
RL = 1kΩ
RL = 150Ω
VO = 200mV p-p
RL AS SHOWN
CL = 18pF
01070-017
Figure 12. AD8115 Frequency Response vs. Load Impedance
AD8114/AD8115
Rev. B | Page 12 of 32
FREQUENCY (MHz)
CROSSTALK (dB)
–70
–50
–60
–80
–90
–1000.1 1 10 100 1000
ALL HOSTILE
0
–40
–30
–20
–10
ADJACENT
R
L
= 1kΩ
R
T
= 37.5Ω
01070-018
Figure 13. AD8114 Crosstalk vs. Frequency
FUNDAMENTAL FREQUENCY (MHz)
DISTORTION (dBc)
–50
–30
–60
–80
–100 110
2ND HARMONIC
0
50
3RD HARMONIC
–20
–40
–70
–90
–10 V
O
= 2V p-p
R
L
= 150Ω
01070-019
Figure 14. AD8114 Distortion vs. Frequency
0 5 10 15 20 25 30 35 40 45
5ns/DIV
0.1%/DIV
01070-020
V
O
= 2V STEP
R
L
= 150Ω
Figure 15. AD8114 Settling Time
FREQUENCY (MHz)
CROSSTALK (dB)
–70
–50
–60
–80
–90
–1000.1 1 10 100 1000
ALL HOSTILE
0
–40
–30
–20
–10
ADJACENT
R
L
= 1kΩ
R
T
= 37.5Ω
01070-021
Figure 16. AD8115 Crosstalk vs. Frequency
FUNDAMENTAL FREQUENCY (MHz)
DISTORTION (dBC)
–50
–30
–60
–80
–100110
2ND HARMONIC
0
50
3RD HARMONIC
–20
–40
–70
–90
–10 V
O
= 2V p-p
R
L
= 150Ω
01070-022
Figure 17. AD8115 Distortion vs. Frequency
5ns/DIV
0 5 10 15 20 25 30 35 40 45
0.1%/DIV
01070-023
V
O
= 2V STEP
R
L
= 150Ω
Figure 18. AD8115 Settling Time
AD8114/AD8115
Rev. B | Page 13 of 32
FREQUENCY (MHz)
INPUT IMPEDANCE (Ω)
100k
1M
10k
1k
100 10 5000.1 1100
01070-024
Figure 19. AD8114 Input Impedance vs. Frequency
FREQUENCY (MHz)
1
0.1
OUTPUT IMPEDANCE (
Ω
)
1 10 100 1000
0.1
10
100
1000
01070-025
Figure 20. AD8114 Output Impedance, Enabled vs. Frequency
FREQUENCY (MHz)
0.1
OUTPUT IMPEDANCE (Ω)
1 10 100 1000
10
100
1M
1k
10k
100k
01070-026
Figure 21. AD8114 Output Impedance, Disabled vs. Frequency
FREQUENCY (MHz)
0.1
INPUT IMPEDANCE (Ω)
1 10 100 500
100
1k
10k
100k
1M
01070-027
Figure 22. AD8115 Input Impedance vs. Frequency
FREQUENCY (MHz)
0.1
OUTPUT IMPEDANCE (Ω)
1 10 100 1000
10
100
1000
1
0.1
01070-028
Figure 23. AD8115 Output Impedance, Enabled vs. Frequency
FREQUENCY (MHz)
0.1
OUTPUT IMPEDANCE (Ω)
1 10 100 1000
10
100
1k
10k
100k
1M
01070-029
Figure 24. AD8115 Output Impedance, Disabled vs. Frequency
AD8114/AD8115
Rev. B | Page 14 of 32
FREQUENCY (MHz)
OFF ISOLATION (dB)
–110
–90
–100
–120
–130
–1400.1 1 10
–80
100 500
–70
–60
–50
–40
01070-030
Figure 25. AD8114 Off Isolation, Input-Output
FREQUENCY (MHz)
PSRR (dB)
–100
0.03 100.1 1
–90
–80
–70
–60
–50
–40
–30
–20
–PSRR
+PSRR
01070-031
Figure 26. AD8114 PSRR vs. Frequency
FREQUENCY (Hz)
170
1010 100
VOLTAGE NOISE (nV/√Hz)
30
1k 10k 100k 1M 10M
16nV/√Hz
50
70
90
110
130
150
01070-032
Figure 27. AD8114 Voltage Noise vs. Frequency
FREQUENCY (MHz)
OFF ISOLATION (dB)
–110
–90
–100
–120
–130
–1400.1 1 10
–80
100 500
–70
–60
–50
–40
01070-033
Figure 28. AD8115 Off Isolation, Input-Output
FREQUENCY (MHz)
PSRR (dB)
–100
0.03 100.1 1
–90
–80
–70
–60
–50
–40
–30
–20
–PSRR
+PSRR
01070-034
Figure 29. AD8115 PSRR vs. Frequency
FREQUENCY (Hz)
170
1010 100
VOLTAGE NOISE (nV/√Hz)
30
1k 10k 100k 1M 10M
50
70
90
110
130
150
01070-035
18nV/√Hz
Figure 30. AD8115 Voltage Noise vs. Frequency
AD8114/AD8115
Rev. B | Page 15 of 32
01070-036
0.10V
0.05V
0V
–
0.05V
–
0.10V
–
0.15V
0.15V V
O
= 200mV STEP
R
L
= 150Ω
50mV 25ns
Figure 31. AD8114 Pulse Response, Small Signal
01070-037
1.0V
0.5V
0V
–0.5V
–1.0V
–1.5V
1.5V V
O
= 2V STEP
R
L
= 150Ω
500mV 25ns
Figure 32. AD8114 Pulse Response, Large Signal
01070-038
0V
+5V
–1V
–0V
+1V
INPUT 1
AT +1V
INPUT 0
AT –1V VOUT
UPDATE
10ns
Figure 33. AD8114 Switching Time
01070-039
0.10V
0.05V
0V
–
0.05V
–
0.10V
–
0.15V
0.15V VO = 200mV STEP
RL = 150
Ω
50mV 25ns
Figure 34. AD8115 Pulse Response, Small Signal
01070-040
1.0V
0.5V
0V
–0.5V
–1.0V
–1.5V
1.5V V
O
= 200mV STEP
R
L
= 150Ω
500mV 20ns
Figure 35. AD8115 Pulse Response, Large Signal
01070-041
0V
+5V
–2V
–0V
+2V
INPUT 1
AT +1V
INPUT 0
AT –1V
VOUT
UPDATE
10ns
Figure 36. AD8115 Switching Time
AD8114/AD8115
Rev. B | Page 16 of 32
01070-042
0V
0.05V
0V
–
0.05V
5V
UPDATE
50ns
Figure 37. AD8114 Switching Transient (Glitch)
OFFSET VOLTAGE (mV)
0
–12 –10
FREQUENCY
20
40
60
80
100
120
140
160
180
200
220
240
260
–8 –6 –4 –2 0246810
01070-043
Figure 38. AD8114 Offset Voltage Distribution
OFFSET VOLTAGE DRIFT (µV/°C)
0
–20
FREQUENCY
4
8
12
16
20
24
28
32
36
40
44
–16 –12 –8 –4 0 4 8 12 16 20
01070-044
Figure 39. AD8114 Offset Voltage Drift Distribution (−40°C to +85°C)
01070-045
0V
0.05V
0V
–
0.05V
5V
UPDATE
50ns
Figure 40. AD8115 Switching Transient (Glitch)
OFFSET VOLTAGE (mV)
0
–14 –10–12
FREQUENCY
20
40
60
80
100
120
140
160
180
200
220
240
–8 –6 –4 –2 0 2410 12 14 166 818
01070-046
Figure 41. AD8115 Offset Voltage Distribution
OFFSET VOLTAGE DRIFT (µV/°C)
0
FREQUENCY
4
8
12
16
20
24
28
32
36
40
44
–12 –8 –4 0 4 8 12 16 20
01070-047
Figure 42. AD8115 Offset Voltage Drift Distribution (−40°C to +85°C)
AD8114/AD8115
Rev. B | Page 17 of 32
I/O SCHEMATICS
ESD
ESD
INPUT
VCC
AVEE
01070-006
Figure 43. Analog Input
ESD
ESD
OUTPUT
V
CC
AVEE
01070-007
Figure 44. Analog Output
ESD
ESD
V
CC
RESET
20kΩ
DGND
01070-008
Figure 45. Reset Input
ESD
ESD
INPUT
V
CC
DGND
01070-009
Figure 46. Logic Input
ESD
ESD
OUTPUT
V
CC
DGND
2kΩ
01070-010
Figure 47. Logic Output
AD8114/AD8115
Rev. B | Page 18 of 32
THEORY OF OPERATION
The AD8114 (G = 1) and AD8115 (G = 2) are crosspoint arrays
with 16 outputs, each of which can be connected to any one of
16 inputs. Organized by output row, 16 switchable
transconductance stages are connected to each output buffer in
the form of a 16-to-1 multiplexer. Each of the 16 rows of
transconductance stages are wired in parallel to the 16 input
pins, for a total array of 256 transconductance stages. Decoding
logic for each output selects one (or none) of the
transconductance stages to drive the output stage. The
transconductance stages are NPN-input differential pairs,
sourcing current into the folded cascode output stage. The
compensation network and emitter follower output buffer are in
the output stage. Voltage feedback sets the gain, with the
AD8114 configured as a unity gain follower, and the AD8115
configured as a gain-of-2 amplifier with a feedback network.
This architecture provides drive for a reverse-terminated video
load (150 Ω), with low differential gain and phase error for
relatively low power consumption. Power consumption is
further reduced by disabling outputs and transconductance
stages that are not in use. The user will notice a small increase
in input bias current as each transconductance stage is enabled.
Features of the AD8114 and AD8115 simplify the construction
of larger switch matrices. The unused outputs of both devices
can be disabled to a high impedance state, allowing the outputs
of multiple ICs to be bused together. In the case of the AD8115,
a feedback isolation scheme is used so that the impedance of the
gain-of-2 feedback network does not load the output. Because
no additional input buffering is necessary, high input resistance
and low input capacitance are easily achieved without
additional signal degradation. To control enable glitches, it is
recommended that the disabled output voltage be maintained
within its normal enabled voltage range (±3.3 V). If necessary,
the disabled output can be kept from drifting out of range by
applying an output load resistor to ground.
A flexible TTL-compatible logic interface simplifies the
programming of the matrix. Both parallel and serial loading
into a first rank of latches programs each output. A global latch
simultaneously updates all outputs. A power-on reset pin is
available to avoid bus conflicts by disabling all outputs.
APPLICATIONS
The AD8114/AD8115 have two options for changing the
programming of the crosspoint matrix. In the first option a
serial word of 80 bits can be provided that will update the entire
matrix each time. The second option allows for changing a
single output’s programming via a parallel interface. The serial
option requires fewer signals, but more time (clock cycles) for
changing the programming, while the parallel programming
technique requires more signals, but can change a single output
at a time and requires fewer clock cycles to complete
programming.
Serial Programming
The serial programming mode uses the device pins CE, CLK,
DATA IN, UPDATE, and SER/PAR. The first step is to assert a
low on SER/PAR to enable the serial programming mode. CE
for the chip must be low to allow data to be clocked into the
device. The CE signal can be used to address an individual
device when devices are connected in parallel.
The UPDATE signal should be high during the time that data is
shifted into the device’s serial port. Although the data will still
shift in when UPDATE is low, the transparent, asynchronous
latches will allow the shifting data to reach the matrix. This will
cause the matrix to try to update to every intermediate state as
defined by the shifting data.
The data at DATA IN is clocked in at every down edge of CLK.
A total of 80 bits must be shifted in to complete the
programming. For each of the 16 outputs, there are four bits
(D0 to D3) that determine the source of its input followed by
one bit (D4) that determines the enabled state of the output. If
D4 is low (output disabled), the four associated bits (D0 to D3)
do not matter because no input will be switched to that output.
The most significant output address data is shifted in first, and
then following in sequence until the least significant output
address data is shifted in. At this point UPDATE can be taken
low, which will cause the programming of the device according
to the data that was just shifted in. The UPDATE registers are
asynchronous, and when UPDATE is low (and CE is low), they
are transparent.
AD8114/AD8115
Rev. B | Page 19 of 32
If more than one AD8114/AD8115 device is to be serially
programmed in a system, the DATA OUT signal from one
device can be connected to the DATA IN of the next device to
form a serial chain. All of the CLK, CE, UPDATE, and SER
/PAR pins should be connected in parallel and operated as
described above. The serial data is input to the DATA IN pin of
the first device of the chain, and it will ripple on through to the
last. Therefore, the data for the last device in the chain should
come at the beginning of the programming sequence. The
length of the programming sequence (80 bits) will be multiplied
by the number of devices in the chain.
Parallel Programming
While using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the
matrix. In fact, parallel programming allows the modification of
a single output at a time. Since this takes only one
CLK/UPDATE cycle, significant time savings can be realized by
using parallel programming.
One important consideration in using parallel programming is
that the RESET signal does not reset all registers in the
AD8114/AD8115. When taken low, the RESET signal will only
set each output to the disabled state. This is helpful during
power-up to ensure that two parallel outputs will not be active
at the same time.
After initial power-up, the internal registers in the device will
generally have random data, even though the RESET signal was
asserted. If parallel programming is used to program one
output, then that output will be properly programmed, but the
rest of the device will have a random program state depending
on the internal register content at power-up. Therefore, when
using parallel programming, it is essential that all outputs be
programmed to a desired state after power-up. This will ensure
that the programming matrix is always in a known state. From
then on, parallel programming can be used to modify a single
output or more at a time.
In similar fashion, if both CE and UPDATE are taken low after
initial power-up, the random power-up data in the shift register
will be programmed into the matrix. Therefore, to prevent the
crosspoint from being programmed into an unknown state, do
not apply low logic levels to both CE and UPDATE after power
is initially applied. Programming the full shift register one time
to a desired state by either serial or parallel programming after
initial power-up will eliminate the possibility of programming
the matrix to an unknown state.
To change an output’s programming via parallel programming,
SER/PAR and UPDATE should be taken high and CE should be
taken low. The CLK signal should be in the high state. The 4-bit
address of the output to be programmed should be put on A0 to
A3. The first four data bits (D0 to D3) should contain the
information that identifies the input that gets programmed to
the output that is addressed. The fourth data bit (D4) will
determine the enabled state of the output. If D4 is low (output
disabled), then the data on D0 to D3 does not matter.
After the desired address and data signals have been established,
they can be latched into the shift register by a high to low
transition of the CLK signal. The matrix will not be
programmed, however, until the UPDATE signal is taken low. It
is thus possible to latch in new data for several or all of the
outputs first via successive negative transitions of CLK while
UPDATE is held high, and then have all the new data take effect
when UPDATE goes low. This technique should be used when
programming the device for the first time after power-up when
using parallel programming.
POWER-ON RESET
When powering up the AD8114/AD8115, it is usually desirable
to have the outputs come up in the disabled state. When taken
low, the RESET pin will cause all outputs to be in the disabled
state. However, the RESET signal does not reset all registers in
the AD8114/AD8115. This is important when operating in the
parallel programming mode. Please refer to that section for
information about programming internal registers after power-
up. Serial programming will program the entire matrix each
time, so no special considerations apply.
Since the data in the shift register is random after power-up, it
should not be used to program the matrix, or the matrix can
enter unknown states. To prevent this, do not apply logic low
signals to both CE and UPDATE initially after power-up. The
shift register should first be loaded with the desired data, and
then UPDATE can be taken low to program the device.
The RESET pin has a 20 kΩ pull-up resistor to DVDD that can
be used to create a simple power-up reset circuit. A capacitor
from RESET to ground will hold RESET low for some time
while the rest of the device stabilizes. The low condition will
cause all the outputs to be disabled. The capacitor will then
charge through the pull-up resistor to the high state, thus
allowing full programming capability of the device.
GAIN SELECTION
The 16 × 16 crosspoints come in two versions, depending on
the gain of the analog circuit paths that is desired. The AD8114
device is unity gain and can be used for analog logic switching
and other applications where unity gain is desired. The AD8114
can also be used for the input and interior sections of larger
crosspoint arrays where termination of output signals is not
usually used. The AD8114 outputs have very high impedance
when their outputs are disabled.
The AD8115 can be used for devices that will be used to drive a
terminated cable with its outputs. This device has a built-in gain
AD8114/AD8115
Rev. B | Page 20 of 32
of 2 that eliminates the need for a gain-of-2 buffer to drive a
video line. Its high output disabled impedance minimizes signal
degradation when paralleling additional outputs.
CREATING LARGER CROSSPOINT ARRAYS
The AD8114/AD8115 are high density building blocks for
creating crosspoint arrays of dimensions larger than 16 × 16.
Various features, such as output disable, chip enable, and gain-
of-1 and gain-of-2 options, are useful for creating larger arrays.
When required for customizing a crosspoint array size, they can
be used with the AD8108 and AD8109, a pair of (unity gain and
gain-of-2) 8 × 8 video crosspoint switches, or with the AD8110
and AD8111, a pair of (unity gain and gain-of-2) 16 × 8 video
crosspoint switches.
The first consideration in constructing a larger crosspoint is to
determine the minimum number of devices required. The 16 ×
16 architecture of the AD8114/AD8115 contains 256 points,
which is a factor of 64 greater than a 4 × 1 crosspoint (or
multiplexer). The PC board area, power consumption, and
design effort savings are readily apparent when compared to
using these smaller devices.
For a nonblocking crosspoint, the number of points required is
the product of the number of inputs multiplied by the number
of outputs. Nonblocking requires that the programming of a
given input to one or more outputs does not restrict the
availability of that input to be a source for any other outputs.
Some nonblocking crosspoint architectures will require more
than this minimum as calculated above. Also, there are blocking
architectures that can be constructed with fewer devices than
this minimum. These systems have connectivity available on a
statistical basis that is determined when designing the overall
system.
The basic concept in constructing larger crosspoint arrays is to
connect inputs in parallel in a horizontal direction and to wire-
OR the outputs together in the vertical direction. The meaning
of horizontal and vertical can best be understood by looking at
a diagram. Figure 48 illustrates this concept for a 32 × 32
crosspoint array that uses four AD8114s or AD8115s.
AD8114
OR
AD8115
AD8114
OR
AD8115
AD8114
OR
AD8115
AD8114
OR
AD8115
16
16
16
16
R
TERM
IN 00–15
16
16
R
TERM
IN 16–31
16
16
16
16
01070-048
Figure 48. 32 × 32 Crosspoint Array Using AD8114 or Four AD8115s
The inputs are each uniquely assigned to each of the 32 inputs
of the two devices and terminated appropriately. The outputs
are wired-OR’ed together in pairs. The output from only one of
a wire-OR’ed pair should be enabled at any given time. The
device programming software must be properly written to cause
this to happen.
AD8114/AD8115
Rev. B | Page 21 of 32
16 R
TERM
IN 00–15 8
8
IN 16–31
IN 32–47
IN 48–63
IN 64–79
IN 80–95
IN 96–111
IN 112–127
8
8
8
8
RANK 2
32:16 NONBLOCKING
(32:32 BLOCKING)
RANK 1
(8 × AD8114)
128:32
16 R
TERM
8
8
16 R
TERM
8
8
16 R
TERM
8
8
16 R
TERM
8
8
16 R
TERM
8
8
16 R
TERM
8
8
16 R
TERM
8
8
AD8115
8
1kΩ
8
1kΩ
8
1kΩ
8
1k
Ω
AD8115
OUT 00Ð15
NONBLOCKING
ADDITIONAL
16 OUTPUTS
(SUBJECT
TO BLOCKING)
AD8114
AD8114
AD8114
AD8114
AD8114
AD8114
AD8114
AD8114
01070-049
Figure 49. Nonblocking 128 × 16 Array (128 × 32 Blocking)
Using additional crosspoint devices in the design can lower the
number of outputs that must be wire-OR’ed together. Figure 49
shows a block diagram of a system using eight AD8114s and
two AD8115s to create a nonblocking, gain-of-2, 128 × 16
crosspoint that restricts the wire-OR’ing at the output to only
four outputs.
Additionally, by using the lower eight outputs from each of the
two Rank 2 AD8115s, a blocking 128 × 32 crosspoint array can
be realized. There are, however, some drawbacks to this
technique. The offset voltages of the various cascaded devices
will accumulate, and the bandwidth limitations of the devices
will compound. In addition, the extra devices will consume
more current and take up more board space. Once again, the
overall system design specifications will determine how to make
the various tradeoffs.
MULTICHANNEL VIDEO
The excellent video specifications of the AD8114/AD8115 make
them ideal candidates for creating composite video crosspoint
switches. These can be made quite dense by taking advantage of
the AD8114/AD8115’s high level of integration and the fact that
composite video requires only one crosspoint channel per
system video channel. There are, however, other video formats
that can be routed with the AD8114/AD8115 requiring more
than one crosspoint channel per video channel.
Some systems use twisted-pair wiring to carry video signals.
These systems utilize differential signals and can lower costs
because they use lower cost cables, connectors and termination
methods. They also have the ability to lower crosstalk and reject
common-mode signals, which can be important for equipment
that operates in noisy environments or where common-mode
voltages are present between transmitting and receiving
equipment.
In such systems, the video signals are differential; there is a
positive and negative (or inverted) version of the signals. These
complementary signals are transmitted onto each of the two
wires of the twisted pair, yielding a first-order zero common-
mode voltage. At the receive end, the signals are differentially
received and converted back into a single-ended signal.
When switching these differential signals, two channels are
required in the switching element to handle the two differential
AD8114/AD8115
Rev. B | Page 22 of 32
signals that make up the video channel. Thus, one differential
video channel is assigned to a pair of crosspoint channels, both
input and output. For a single AD8114/AD8115, eight
differential video channels can be assigned to the 16 inputs and
16 outputs. This will effectively form an 8 × 8 differential
crosspoint switch.
Programming such a device will require that inputs and outputs
be programmed in pairs. This information can be deduced by
inspection of the programming format of the AD8114/AD8115
and the requirements of the system.
There are other analog video formats requiring more than one
analog circuit per video channel. One 2-circuit format that is
commonly being used in systems such as satellite TV, digital
cable boxes, and higher quality VCRs is called S-video or Y/C
video. This format carries the brightness (luminance or Y)
portion of the video signal on one channel and the color
(chrominance, chroma, or C) on a second channel.
Since S-video also uses two separate circuits for one video
channel, creating a crosspoint system requires assigning one
video channel to two crosspoint channels, as in the case of a
differential video system. Aside from the nature of the video
format, other aspects of these two systems will be the same.
There are yet other video formats using three channels to carry
the video information. Video cameras produce RGB (red, green,
blue) directly from the image sensors. RGB is also the usual
format used by computers internally for graphics. RGB can be
converted to Y, R-Y, B-Y format, sometimes called YUV format.
These 3-circuit video standards are referred to as component
analog video.
The component video standards require three crosspoint
channels per video channel to handle the switching function. In
a fashion similar to the 2-circuit video formats, the inputs and
outputs are assigned in groups of three, and the appropriate
logic programming is performed to route the video signals.
CROSSTALK
Many systems, such as broadcast video, that handle numerous
analog signal channels have strict requirements for keeping the
various signals from influencing any of the others in the system.
Crosstalk is the term used to describe the coupling of the
signals of other nearby channels to a given channel.
When there are many signals in close proximity in a system, as
will undoubtedly be the case in a system that uses the
AD8114/AD8115, the crosstalk issues can be quite complex. A
good understanding of the nature of crosstalk and some
definition of terms is required to specify a system that uses one
or more AD8114/AD8115s.
Types of Crosstalk
Crosstalk can be propagated by means of any of three methods.
These fall into the categories of electric field, magnetic field,
and sharing of common impedances. This section will explain
these effects.
Every conductor can be both a radiator of electric fields and a
receiver of electric fields. The electric field crosstalk mechanism
occurs when the electric field created by the transmitter
propagates across a stray capacitance (e.g., free space) and
couples with the receiver and induces a voltage. This voltage is
an unwanted crosstalk signal in any channel that receives it.
Currents flowing in conductors create magnetic fields that
circulate around the currents. These magnetic fields will then
generate voltages in any other conductors whose paths they
link. The undesired induced voltages in these other channels are
crosstalk signals. The channels that crosstalk can be said to have
a mutual inductance that couples signals from one channel to
another.
The power supplies, grounds, and other signal return paths of a
multichannel system are generally shared by the various
channels. When a current from one channel flows in one of
these paths, a voltage that is developed across the impedance
becomes an input crosstalk signal for other channels that share
the common impedance.
All these sources of crosstalk are vector quantities, so the
magnitudes cannot simply be added together to obtain the total
crosstalk. In fact, there are conditions where driving additional
circuits in parallel in a given configuration can actually reduce
the crosstalk.
Areas of Crosstalk
For a practical AD8114/AD8115 circuit, it is required that it be
mounted to some sort of circuit board to connect it to power
supplies and measurement equipment. Great care has been
taken to create a characterization board (also available as an
evaluation board) that adds minimum crosstalk to the intrinsic
device. This, however, raises the issue that a system’s crosstalk is
a combination of the intrinsic crosstalk of the devices in
addition to the circuit board to which they are mounted. It is
important to try to separate these two areas of crosstalk when
attempting to minimize its effect.
In addition, crosstalk can occur among the inputs to a
crosspoint and among the output. It can also occur from input
to output. Techniques will be discussed for diagnosing which
part of a system is contributing to crosstalk.
AD8114/AD8115
Rev. B | Page 23 of 32
Measuring Crosstalk
Crosstalk is measured by applying a signal to one or more
channels and measuring the relative strength of that signal on a
desired selected channel. The measurement is usually expressed
as dB down from the magnitude of the test signal. The crosstalk
is expressed by
() ()
(
)
sAtestsAselXT 10
log20=
where s = jω is the Laplace transform variable, Asel(s) is the
amplitude of the crosstalk-induced signal in the selected
channel, and Atest(s) is the amplitude of the test signal. It can be
seen that crosstalk is a function of frequency, but not a function
of the magnitude of the test signal (to first order). In addition,
the crosstalk signal will have a phase relative to the test signal
associated with it.
A network analyzer is most commonly used to measure
crosstalk over a frequency range of interest. It can provide both
magnitude and phase information about the crosstalk signal.
As a crosspoint system or device grows larger, the number of
theoretical crosstalk combinations and permutations can
become extremely large. For example, in the case of the 16 × 16
matrix of the AD8114/AD8115, we can examine the number of
crosstalk terms that can be considered for a single channel, say
IN00 input. IN00 is programmed to connect to one of the
AD8114/AD8115 outputs where the measurement can be made.
First, we can measure the crosstalk terms associated with
driving a test signal into each of the other 15 inputs one at a
time while applying no signal to IN00. We can then measure the
crosstalk terms associated with driving a parallel test signal into
all 15 other inputs taken two at a time in all possible
combinations, then three at a time, etc., until there is only one
way to drive a test signal into all 15 other inputs in parallel.
Each of these cases is legitimately different from the others and
might yield a unique value depending on the resolution of the
measurement system, but it is hardly practical to measure all
these terms and then to specify them. In addition, this describes
the crosstalk matrix for just one input channel. A similar
crosstalk matrix can be proposed for every other input. In
addition, if the possible combinations and permutations for
connecting inputs to the other (not used for measurement)
outputs are taken into consideration, the numbers rather
quickly grow to astronomical proportions. If a larger crosspoint
array of multiple AD8114/AD8115s is constructed, the numbers
grow larger still.
Obviously, some subset of all these cases must be selected to be
used as a guide for a practical measure of crosstalk. One
common method is to measure all hostile crosstalk. This term
means that the crosstalk to the selected channel is measured
while all other system channels are driven in parallel. In general,
this will yield the worst crosstalk number, but this is not always
the case due to the vector nature of the crosstalk signal.
Other useful crosstalk measurements are those created by one
nearest neighbor or by the two nearest neighbors on either side.
These crosstalk measurements will generally be higher than
those of more distant channels, so they can serve as a worst-case
measure for any other 1-channel or 2-channel crosstalk
measurements.
Input and Output Crosstalk
The flexible programming capability of the AD8114/AD8115
can be used to diagnose whether crosstalk is occurring more on
the input side or the output side. Some examples are illustrative.
A given input channel (IN07 in the middle for this example)
can be programmed to drive OUT07 (also in the middle). The
input to IN07 is just terminated to ground (via 50 Ω or 75 Ω)
and no signal is applied.
All the other inputs are driven in parallel with the same test
signal (practically that is provided by a distribution amplifier),
with all other outputs except OUT07 disabled. Since grounded
IN07 is programmed to drive OUT07, no signal should be
present. Any signal that is present can be attributed to the other
15 hostile input signals because no other outputs are driven.
(They are all disabled.) Thus, this method measures the all-
hostile input contribution to crosstalk into IN07. Of course, the
method can be used for other input channels and combinations
of hostile inputs.
For output crosstalk measurement, a single input channel is
driven (IN00, for example) and all outputs other than a given
output (IN07 in the middle) are programmed to connect to
IN00. OUT07 is programmed to connect to IN15 (far away
from IN00), which is terminated to ground. Thus OUT07
should not have a signal present since it is listening to a quiet
input. Any signal measured at the OUT07 can be attributed to
the output crosstalk of the other 16 hostile outputs. Again, this
method can be modified to measure other channels and other
crosspoint matrix combinations.
AD8114/AD8115
Rev. B | Page 24 of 32
Effect of Impedances on Crosstalk
The input side crosstalk can be influenced by the output
impedance of the sources that drive the inputs. The lower the
impedance of the drive source, the lower the magnitude of the
crosstalk. The dominant crosstalk mechanism on the input side
is capacitive coupling. The high impedance inputs do not have
significant current flow to create magnetically induced
crosstalk. However, significant current can flow through the
input termination resistors and the loops that drive them. Thus,
the PC board on the input side can contribute to magnetically
coupled crosstalk.
From a circuit standpoint, the input crosstalk mechanism looks
like a capacitor coupling to a resistive load. For low frequencies,
the magnitude of the crosstalk will be given by
(
)
[
]
sCRXT M
S×= 10
log20
where RS is the source resistance, CM is the mutual capacitance
between the test signal circuit and the selected circuit, and s is
the Laplace transform variable.
From the equation, it can be observed that this crosstalk
mechanism has a high-pass nature; it can be minimized by
reducing the coupling capacitance of the input circuits and
lowering the output impedance of the drivers. If the input is
driven from a 75 Ω terminated cable, the input crosstalk can be
reduced by buffering this signal with a low output impedance
buffer.
On the output side, the crosstalk can be reduced by driving a
lighter load. Although the AD8114/AD8115 is specified with
excellent differential gain and phase when driving a standard
150 Ω video load, the crosstalk will be higher than the
minimum obtainable due to the high output currents. These
currents will induce crosstalk via the mutual inductance of the
output pins and bond wires of the AD8114/AD8115.
From a circuit standpoint, this output crosstalk mechanism
looks like a transformer, with a mutual inductance between the
windings, that drives a load resistor. For low frequencies, the
magnitude of the crosstalk is given by
)/(log20 10 L
RsMxyXT ×=
where Mxy is the mutual inductance of Output X to Output Y,
and RL is the load resistance on the measured output. This
crosstalk mechanism can be minimized by keeping the mutual
inductance low and increasing RL. The mutual inductance can
be kept low by increasing the spacing of the conductors and
minimizing their parallel length.
AD8114/AD8115
Rev. B | Page 25 of 32
PCB LAYOUT
Extreme care must be exercised to minimize additional
crosstalk generated by the system circuit board(s). The areas
that must be carefully detailed are grounding, shielding, signal
routing, and supply bypassing.
The packaging of the AD8114/AD8115 is designed to help keep
the crosstalk to a minimum. Each input is separated from each
other input by an analog ground pin. All of these AGNDs
should be directly connected to the ground plane of the circuit
board. These ground pins provide shielding, low impedance
return paths, and physical separation for the inputs. All of these
help to reduce crosstalk.
Each output is separated from its two neighboring outputs by an
analog supply pin of one polarity or the other. Each of these
analog supply pins provides power to the output stages of only
the two nearest outputs. These supply pins provide shielding,
physical separation, and a low impedance supply for the
outputs. Individual bypassing of each of these supply pins with a
0.01 µF chip capacitor directly to the ground plane minimizes
high frequency output crosstalk via the mechanism of sharing
common impedances.
Each output also has an on-chip compensation capacitor that is
individually tied to the nearby analog ground pins AGND00
through AGND07. This technique reduces crosstalk by
preventing the currents that flow in these paths from sharing a
common impedance on the IC and in the package pins. These
AGNDxx signals should all be connected directly to the ground
plane.
The input and output signals will have minimum crosstalk if
they are located between ground planes on layers above and
below, and separated by ground in between. Vias should be
located as close to the IC as possible to carry the inputs and
outputs to the inner layer. The only place the input and output
signals surface is at the input termination resistors and the
output series back-termination resistors. These signals should
also be separated, to the extent possible, as soon as they emerge
from the IC package.
Optimized for video applications, all signal inputs and outputs
are terminated with 75 Ω resistors. Stripline techniques are used
to achieve a characteristic impedance of 75 Ω on the signal
input and output lines. Figure 50 shows a cross section of one of
the input or output tracks along with the arrangement of the
PCB layers. It should be noted that unused regions of the four
layers are filled up with ground planes. As a result, the input
and output traces, in addition to having controlled impedances,
are well shielded.
01070-057
w = 0.008"
(0.2mm)
a = 0.008"
(0.2mm)
b = 0.0514"
(1.3mm)
h = 0.025"
(0.63mm)
t = 0.00135" (0.0343mm) TOP LAYER
SIGNAL LAYER
POWER LAYER
BOTTOM LAYER
Figure 50. Cross Section of Input and Output Traces
The board has 32 BNC type connectors: 16 inputs and 16 outputs.
The connectors are arranged in a crescent around the device. As
can be seen from Figure 53, this results in all 16 input signal
traces and all 16 signal output traces having the same length.
This is useful in tests such as all-hostile crosstalk where the
phase relationship and delay between signals needs to be
maintained from input to output.
The three power supply pins AVCC, DVCC and AVEE should
be connected to good quality, low noise, ±5 V supplies. Where
the same ±5 V power supplies are used for analog and digital,
separate cables should be run for the power supply to the
evaluation board’s analog and digital power supply pins.
As a general rule, each power supply pin (or group of adjacent
power supply pins) should be locally decoupled with a 0.01 µF
capacitor. If there is a space constraint, it is more important to
decouple analog power supply pins before digital power supply
pins. A 0.1 µF capacitor, located reasonably close to the pins,
can be used to decouple a number of power supply pins. Finally
a 10 µF capacitor should be used to decouple power supplies as
they come onto the board.
AD8114/AD8115
Rev. B | Page 26 of 32
01070-051
Figure 51. Component Side Silkscreen
01070-052
Figure 52. Board Layout (Component Side)
AD8114/AD8115
Rev. B | Page 27 of 32
01070-053
Figure 53. Board Layout (Signal Layer)
01070-054
Figure 54. Board Layout (Ground Plane)
AD8114/AD8115
Rev. B | Page 28 of 32
01070-055
Figure 55. Board Layout (Circuit Side)
01070-056
Figure 56. Circuit Side Silkscreen
AD8114/AD8115
Rev. B | Page 29 of 32
EVALUATION BOARD
57,59
58
75Ω
INPUT 00 INPUT 00
AGND 75Ω
54
0.01µF
61
60
75Ω
INPUT 01 INPUT 01
AGND
63
62
75Ω
INPUT 02 INPUT 02
AGND
65
64
75Ω
INPUT 03 INPUT 03
AGND
67
66
75Ω
INPUT 04 INPUT 04
AGND
69
68
75Ω
INPUT 05 INPUT 05
AGND
71
70
75Ω
INPUT 06 INPUT 06
AGND
72
75Ω
INPUT 07 INPUT 07
5
4
75Ω
INPUT 08 INPUT 08
AGND
7
6
75Ω
INPUT 09 INPUT 09
AGND
9
8
75Ω
INPUT 10 INPUT 10
AGND
11
10
75Ω
INPUT 11 INPUT 11
AGND
13
12
75Ω
INPUT 12 INPUT 12
AGND
15
14
75Ω
INPUT 13 INPUT 13
AGND
17
16
75Ω
INPUT 14 INPUT 14
AGND
19
18
75Ω
INPUT 15 INPUT 15
AGND
98 DATA OUT
96 DATA IN
P2-5
P2-4
P2-2
P2-3
P2-1
P2-6
DGND
RESET
CE
CLK
/PAR
SER
A0
A1
A2
D0
D1
D2
D3
D4
P3-1
P3-2
P3-3
P3-4
P3-5
P3-6
P3-7
P3-8
P3-9
P3-10
P3-11
P3-12
P3-13
P3-14
2,74 100 99 97 95 84 83 82 81 80 79 78 77 76
SERIAL MODE
JUMP
R33
20kΩDVCC
OUTPUT 00
20, 56
AVEE
AVEE
21, 55
AVCC
AVCC
1, 75
DVCC
AD8114/AD8115
DVCC DGND NCAVEE AGND AVCCNC
P1-1 +
+
+
P1-2 P1-3 P1-4 P1-5 P1-6 P1-7
0.1µF10µF
0.1µF
0.01µF 0.01µF 0.01µF
10µF
0.1µF10µF
JUMPER
3,73 AGND
R
R
R
NOTES
R = OPTIONAL 50
Ω
TERMINATOR RESISTORS
C = OPTIONAL SMOOTHING CAPACITOR
RRC
R
R
A3
R R R R R R R R R
94
NO CONNECT:
85–93
AVCC AVCC
OUTPUT 00
53
75Ω
52
0.01µF
OUTPUT 01
AVEE AV
EE
OUTPUT 01
51
75Ω
50
0.01µF
OUTPUT 02
AVCC AVCC
OUTPUT 02
49
75Ω
48
0.01µF
OUTPUT 03
AVEE AV
EE
OUTPUT 03
47
75Ω
46
0.01µF
OUTPUT 04
AVCC AVCC
OUTPUT 04
45
75Ω
44
0.01µF
OUTPUT 05
AVEE AV
EE
OUTPUT 05
43
75Ω
42
0.01µF
OUTPUT 06
AVCC AVCC
OUTPUT 06
41
75Ω
40
0.01µF
OUTPUT 07
AVEE AV
EE
OUTPUT 07
39
75Ω
38
0.01µF
OUTPUT 08
AVCC AVCC
OUTPUT 08
37
75Ω
36
0.01µF
OUTPUT 09
AVEE AV
EE
OUTPUT 09
35
75Ω
34
0.01µF
OUTPUT 10
AVCC AVCC
OUTPUT 10
33
75Ω
32
0.01µF
OUTPUT 11
AVEE AV
EE
OUTPUT 11
31
75Ω
30
0.01µF
OUTPUT 12
AVCC AVCC
OUTPUT 12
29
75Ω
28
0.01µF
OUTPUT 13
AVEE AV
EE
OUTPUT 13
27
75Ω
26
0.01µF
OUTPUT 14
AVCC AVCC
OUTPUT 14
25
75Ω
24
0.01µF
OUTPUT 15
AVEE AV
EE
OUTPUT 15
23
22
AVCC
DVCC
01070-050
Figure 57. Evaluation Board Schematic
AD8114/AD8115
Rev. B | Page 30 of 32
CONTROL THE EVALUATION BOARD FROM A PC
CLK
DATA IN
RESET
UPDATE
CE
DGND
MOLEX 0.100" CENTER
CRIMP TERMINAL HOUSING
1
6
D-SUB 25 PIN (MALE)
14 1
25 13
EVALUATION BOARD PC
2
3
4
5
6
25
3
1
4
5
2
6
SIGNAL
DATA IN
CE
RESET
UPDATE
CLK
DGND
MOLEX
TERMINAL HOUSING
D-SUB-25
01070-058
The evaluation board includes Windows®-based control
software and a custom cable that connects the board’s digital
interface to the printer port of the PC. The wiring of this cable
is shown in Figure 58. The software requires Windows 3.1 or
later to operate. To install the software, insert the disk labeled
Disk 1 of 2 into the PC and run the file called SETUP.EXE.
Additional installation instructions will be given on-screen.
Before beginning installation, it is important to terminate any
other Windows applications that are running.
When you launch the crosspoint control software, you will be
asked to select the printer port. Most modern PCs have only
one printer port, usually called LPT1. However some laptop
computers use the PRN port.
Figure 58. Evaluation Board-PC Connection Cable
Figure 59 shows the main screen of the control software in its
initial reset state (all outputs off). Using the mouse, any input
can be connected with one or more outputs by simply clicking
on the appropriate radio buttons in the 16 × 16 on-screen array.
Each time a button is clicked on, the software automatically
sends and latches the required 80-bit data stream to the
evaluation board. An output can be turned off by clicking the
appropriate button in the off column. To turn off all outputs,
click on RESET.
OVERSHOOT OF PC PRINTER PORTS’ DATA LINES
The data lines on some printer ports have excessive overshoot.
Overshoot on the pin that is used as the serial clock (Pin 6 on
the D-Sub-25 connector) can cause communication problems.
This overshoot can be eliminated by connecting a capacitor
from the CLK line on the evaluation board to ground. A pad
has been provided on the circuit side (C33) of the evaluation
board to allow this capacitor to be soldered into place.
Depending on the overshoot from the printer port, this
capacitor may need to be as large as 0.01 µF.
While the computer software only supports serial programming
via a PC’s parallel port and the provided cable, the evaluation
board has a connector that can be used for parallel
programming. The SER/PAR signal should be at a logic high to
use parallel programming. There is no cable or software
provided with the evaluation board for parallel programming.
These are left to the user to provide.
AD8114/AD8115
Parallel Port Selection
01070-059
The software offers volatile and nonvolatile storage of
configurations. For volatile storage, up to two configurations
can be stored and recalled using the Memory 1 and Memory 2
buffers. These function in a fashion identical to the memory on
a pocket calculator. For nonvolatile storage of a configuration,
the save setup and load setup functions can be used. This stores
the configuration as a data file on disk.
Figure 59. Screen Display and Control Software
AD8114/AD8115
Rev. B | Page 31 of 32
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-026-BED
TOP VIEW
(PINS DOWN)
1
2526 51
50
75
76100
0.50
BSC
LEAD PITCH
0.27
0.22
0.17
1.60 MAX
0.75
0.60
0.45
VIEW A
16.00
BSC SQ
14.00
BSC SQ
PIN 1
1.45
1.40
1.35
0.15
0.05
0.20
0.09
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90° CCW
SEATING
PLANE
7°
3.5°
0°
Figure 60. 100-Lead Low Profile Quad Flat Package [LQFP]
(ST-100)
Dimension shown in millimeters
ORDERING GUIDE1
Model Temperature Range Package Description Package Option
AD8114AST −40°C to +85°C 100-Lead Low Profile Quad Flat Package [LQFP] ST-100
AD8114ASTZ2−40°C to +85°C 100-Lead Low Profile Quad Flat Package [LQFP] ST-100
AD8115AST −40°C to +85°C 100-Lead Low Profile Quad Flat Package [LQFP] ST-100
AD8115ASTZ2 −40°C to +85°C 100-Lead Low Profile Quad Flat Package [LQFP] ST-100
AD8114-EVAL Evaluation Board
AD8115-EVAL Evaluation Board
1 Details of the lead finish composition can be found on the ADI website at www.analog.com by reviewing the Material Description of each relevant package.
2 Z = Pb-free part.
AD8114/AD8115
Rev. B | Page 32 of 32
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01070–0–9/05(B)
