Am9150 1024x4 High-Speed Static RAW RAM DISTINCTIVE CHARACTERISTICS 1024 x 4 organization High speed - 20 ns Max. access time Separate data inputs and outputs Memory reset function @ High density SLIM 24-pin 300-MiL package Three-state output buffers @ Single +5 V power supply +10% @ Low-power version GENERAL DESCRIPTION The Am9150 is a high-performance, static, n-channel, read/write, random-access memory organized as 1024 x 4, It features single 5 V supply operation, TTL-compatible input and output levels, and separate input and output pins for improved system performance and ease of use. The Am9150 also incorporates a reset feature which will reset the entire contents of the memory to logical LOW in two cycle times by contralling R (RESET) and S (CS). The Am9150 has four contro! signals A, 5, W and G. The $ input controls read, write and reset operations of the device and provides for easy selection of an individual device when the outputs are tied together. The W (WE) input controls the normal read and write operations, and the G (OE) controls the state of the outputs. BLOCK DIAGRAM MODE SELECT TABLE q So] os ata Inputs 2 J Outputs Mode By aed $s Ww G R Ag nd now Ont ert ex ain Ayo] DECODERS H x x x Hi-Z Not Selected L H x L |HiZ Reset" L L x HJ HEZ Write L H L H {Q9-Qg3 Read L x kK H Hi-Z, Output Disable H=High *See Reset cycle description. L=Low %~1 avons X= Don't Care ay .-| BUFFERS. Apel + SELECT y=] cecooens ry Live TH sc + = iv | aurea earse (08) ~] PrP add gd ono By Op % G OC, G 0 BDO05261 PRODUCT SELECTOR GUIDE Part Number Am9150-20 | Am9150-25 | Am9150-35 | Am9150-45 | Am91L50-25 | Am91L50-35 | Am91L50-45 Maximum Access Time (ns) 20 26 35 45 25 36 45 0C to +70C 180 180 180 180 130 130 130 Ico Max. (mA) -55C to + 125C N/A 180 180 180 N/A N/A N/A www.DataSheet.in 4-53CONNECTION DIAGRAMS Top View ADDRESS 3 1 aooness 4 (| aporess 5 (1) aponess 6 (| appngss 7 (_]5 avoness 8 [_}6 aponess []7 n ~ DATAINPUT 0(Do) [_| 8 DATAINPUT1 (04) (_] 9 DATA OUTPUT 0(Q) [~~] 10 DATA OUTPUT? (04) Ol " Gno (_]12 2417] Veg (+5 ) 23[_]) aconess 2 221} aDoness 1 21{] ADORESS 0 20 (7) RESET (A) 19 ] HIP SELECT (5) 187) WRITE ENABLE (W) 17} GUTPUT ENABLE (3) 16{_] OATA INPUT 3(D3) 15 7) DATA INPUT 2(02) 14 [) data ouTPUT 3(Qy) 13 [_) OaTa OuTPuT 210.) LOGIC SYMBOL (DIP ONLY) 19 8 9 1516 17 18 R(RESET) Op 040203 10141314 LS001821 CDO05963 Note: Pin 1 is marked for orientation. Address Designators External Internal Ag AXo Ay AX Ag AXg Ag AXg Ag AX4 As AXS Aa AYo Az AY; Ag AY2 Ag AY3 Cp005931 METALLIZATION AND PAD LAYOUT Die Size: 0.99 x 0.163 www.DataSheet.in 4-54 Am9150ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a. Device Number b. Speed Option (if applicable) c. Package Type d. Temperature Range @. Optional Processing OPTIONAL PROCESSING Blank = Standard processing B = Burn-in . TEMPERATURE RANGE C= Commercial (0 to + 70C) PACKAGE TYPE D = 24-Pin (300-Mil) Ceramic DiP (CD3024) L = 28-Pin Rectangular Ceramic Leadless Chip Carrier (CLRO28) SPEED OPTION -20 = 20 ns -25 = 25 ns ~35 = 35 ns -45 = 45 ns Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult MSIS sales department to confirm availability of specific valid combinations, and to obtain additional data on MSIS's AM9150 =20 DBD & B | e 4. c b. a. DEVICE NUMBER/DESCRIPTION Am9150/Am91L50 1024 x 4 High-Speed Static R/W RAM Am91L50 = Low-Power Version Valid Combinations AM9150-20 AM9150-25 AM9150-35 DC, DCB, AM9150-45 LC, LOB AM91L50-25 AM91L50-35 standard military grade products. AM91L50-45 www.DataSheet.inMILITARY. ORDERING INFORMATION APL Products AMD products for Aerospace and Defense applications are available in several Packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-883C requirements. The order number (Valid Cambination) for APL products is formed by a combination of: a. Device Number b. Speed Option (if applicable) c. Device Class d. Package Type e. Lead Finish APL Products -AM9150_ =25 LB 4 A [| LEAD FINISH A= Hot Solder Dip C=Gold I d. PACKAGE TYPE L = 24-Pin (300-Mil} Ceramic DIP (CO9024) U = 28-Pin Rectangular Ceramic Leadless Chip Carrier (CLRO28) K = 24-Pin CERPACK (CFM024) . DEVICE CLASS /B = Class 6 b. SPEED OPTION -25 = 25 ns ~36 = 35 ns -45=45 ns a, DEVICE NUMBER/DESCRIPTION Am9150 1024 x 4 High-Spaed Static R/W RAM Valid Combinations Valid Combinations AM9150-25 /BLA Valid Combinations list configurations planned to be supported in volume AM9150-35 | 7BUG for this device. Consult MSIS sales department to confirm availability of /BKA specific valid combinations, and to obtain additional data on MSIS's AM91&0-45 standard military grade products. Group A Tests Group A tests consist of Subgroups 1, 2, 3, 7, 8, 9, 10, 11. PIN DESCRIPTION Ag~-Ag Address (Inputs) R RESET (Input; Active LOW) The 10 address inputs select one-of the 1024 4-bit words in An active-Low puise on R while Ap~Ag are stable, S$ is the RAM. LOW, and W and G are HIGH resets the whole memory. S Chip Select (Input; Active LOW) G_ Output Enabie (input; Active LOW) An active-LOW input which selects the device for operation. G controls the state of the data outputs in conjunction with S When & is HIGH, the device is deselected and the outputs - and W. will be in a high-impedance state. Do-D3 Data Input W = Write Enable (input; Active LOW) _ Data inputs to the RAM. W controls read and write operations. When W is HIGH and Qo-@3 Data Output G is LOW, data will be present at the data outputs. When W Data outputs from the RAM. The data outputs will be in a is LOW, data present on the data inputs will be written into high-impedance state when either 5 or G are HIGH or Wis the selected memory location. The data outputs will be ina LOW. high-impedance state. Vcc Power Supply +5 Volts Vss Ground www.DataSheet.in ied mnigiuyABSOLUTE MAXIMUM RATINGS (Note 1) OPERATING RANGES (note 2) Storage Temperature ..........0000ec -65 to + 150C Commercial (C) Devices Ambient Temperature with Ambient Temperature (Ta) ..........00.c0ccc000. 0 to +70C Power Applied ........ 0... cccecccccseeeeeene ee -55 to +125C Supply Voltage (Vcc) ... +5.0 Vt10% Supply Voltage with . Milita : ry (M} Devices Signal Vattages wih Trereeeeee sees neceecee es 0.5 V to +70 Ambient Temperature (Ta) .........000.... ~55 to +125C +109 Respect to Ground.......00000...c00 eee -3.5 V to +7.0 V Supply Voltage (Vcc) +5.0 V #10% Power Dissipation (Package Limitation) .................. 2W . . Berean ater actage Laon Zina QP8tting ranges deine those Its between whch te functionality of the device is guaranteed. The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations of static charge. It is suggested nevertheless, that conventional precautions be observed during storage, handling and use in order to avoid exposure to excessive voltages. DC CHARACTERISTICS over operating ranges unless otherwise specified (for APL Products, Group A, Subgroups 1, 2, 3 are tested unless otherwise noted) Am9150 Am91L50 Parameter Parameter Symbol Description Test Conditions Min. Max. Min. Max. Unit OH Output HIGH Current Vou = 2.4 V ~4 -4 mA tol Output LOW Current Vo. =0.4 V 12 12 mA Vin Input HIGH Voltage 22 6.0 2.2 6.0 Vv Vit Input LOW Voltage -2.5 0.8 -2.5 0.8 v hx Input Load Current GNO <Vi <Voc -10 10 -10 10 uA loz Output Leakage Current GND <Vo <Vcc Output Disabled -10 10 ~10 10 BA C Input Capacitance Test Frequency = 1.0 MHz 5 5 Ta = 25C, All Pins at 0 V, pF Co Output Capacitance Voc =5 V {Note 8) 7 7 . COM'L. 180 130 Ioc Voc Operating Supply Max Voc $< Vi, Output ui 80 wT mA Current Open L. 1 A los Output Short Circuit Current | GND <Vo <Voc (Notes 7, B) +50 +300 +50 +300 mA Notes: 1. Absolute Maximum Ratings are intended for user guidelines and are not tested. 2. For test and correlation purposes, ambient temperature is defined as the 'instant-ON" casa temperature. 3. Test conditions assume signal transition times of 10 ns or less, timing reference levels of 1.5 V, input pulse fevets of 0 to 3.0 V and output loading of the specified Io,/loH and 30 pF load capacitance. Output timing reference is 1.5 V. 4. The internal write time of the memory is defined by the overlap of 5 LOW and LOW. Both signais must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing is referenced to the rising edge of the signal that terminates the write. R must be HIGH. . Transition is measured at 1.5 V on the inputs to Voy-500 mV and Vo, + 500 mV on the outputs using the load shown in B. under Switching Test Circuits. W and R are HIGH for read cycle. - For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. . This parameter is not tested, but guaranteed by characterization. PND www.DataSheet.in AIL LOU: SDFSWITCHING CHARACTERISTICS over operating ranges unless otherwise specified (for APL Products, Group A, Subgroups 9, 10, 11 are tested unless otherwise noted) Parameter Am9150-25 | Am9150-35 | Am9150-45 Symbol Am9$150-20 | Am91L50-25 | Am91L50-35 | Am91L.50-45 Parameter No. |Standard | Alternate Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit READ CYCLE 1 TAVAYV irc Read Cycle Time (Note 6) 20 25 36 45 ns 2 TAVQV taA Address Access Time 20 26 35 45 ns 3 TSLQV tacs Chip Select Access Time 10 18 20 25 ns 4 TGLOQV toe Output Enable Access Time 10 16 20 25 ns 5 TSLOX tcLz Chip Select LOW to Output in 0 0 0 0 ns Low-Z (Notas 5, 8) 6 |TSHQZ toHz Chip Select HIGH to Output in 0 15 0 20 0 25 0 30 ns Hi-Z (Notes 5, 8) 7 |TGLOX toLz Output Enable LOW to Output in 0 0 0 Q ns Low-Z (Note 5, 8} 8 TGHQZ toHz Output Enable HIGH to Output in 0 15 0 20 0 25 0 30 ns Hi-Z (Notes 5, 8) g TAXOX tOHA Output Hold after COM'L. 3 3 3 3 ns Address Change MIL. 1 1 1 1 WRITE CYCLE 10 TAVAV two Write Cycle Time (Note 4) 20 26 36 45 ns WW TSLWH tow Chip Select LOW to Write Enable 10 15 20 30 ns HIGH 12 TAVWH taAw Address Valid to End of Write 15 20 30 40 ns 13 TAVWL tas Address Valid to Beginning of 5 5 5 5 ns Write 14 TWLWH twp Write Pulse Width 10 15 20 30 ns 15 TWHAX twR Address Hold after End of Write 5 5 5 5 ns 16 TDVWH tpve Data in Valid to Write Enable 10 15 20 30 ns HIGH 17, | TWHDX tou Data Hold after End of Write 5 5 5 5 ns 18 TWLOQZ twz Write Enable LOW to Output in 0 15 0 20 0 25 0 30 ns Hi-Z (Notes 5, 8) 19 TWHOX tow Writa Enable HIGH to Output in 0 0 9 0 ns Low-Z (Notes 5, 8) RESET CYCLE 20 | TAVAV tRRC Reset Cycle Time 40 50 70 90 ns 21 TAVRL tASA Address Valid to Beginning of 9 0 0 0 ns Reset 22 TWHRL tasw Write Enable HIGH to Beginning 0 0 0 0 ns of Reset 23 TSLRL trscs Chip Select LOW to Beginning of 0 0 0 0 ns Reset 24 TRLRH trp Reset Pulse Width 20 20 30 40 as 25 TRHSX tRHCS Chip Select Hold after End of 0 0 0 0 ns Reset 26 TRHWL tRHW Write Enable Hold after End of 20 30 40 50 ns Reset 27 TRHAX tRHA Address Hold after End of Reset 20 30 40 50 ns 28 | TALOZ tRHZ Reset LOW to Output in Hi-Z 9 15 0 20 0 26 0 35 ns (Notes 5, 8) 29 TRHQX trALz Reset HIGH to Output in Low-Z 0 0 0 0 ns (Notas 5, 8) 4-96 Nates: See notes following DC Characteristics table. www.DataSheet.in ALOURESET CYCLE The reset cycle is initiated by R going LOW for a time = tap, and is terminated by hoiding R HIGH for a time = tRHa. The addresses to the device must be stable during the RESET cycle time. The entire contents of the RAM will be reset to ZERO regardless of the address chosen during the cycle. The control must be <Vi_ maximum, and W must be > Vin minimum and it is recommended that G be > Viy minimum. The reset cycle is normally associated with current spikes, both at Vcc and GND as shown in the graph. To attenuate the current spikes, an external bypass capacitor (high frequency, 0.1 wF) for each Am9150 socket is recommended. Typical Icc and Ignp During a Reset Cycle Ty = 25 Veo = 5.5V es 24 Fy (a1) wma ~ - -_ ,; FS Sice 4 ma 4- -+ at SN leno L 1 1 1 1 L 1 1 pa o 1 2 3% 4 5 6 7 89 7 TIME - na WFO009920 SWITCHING TEST CIRCUITS Vec Voc 3300 200 Dour Sour 30 pF (INCLUDING a000 SCOPE AND 2000 5 oF WG) TC002350 TC002360 A. B. www.DataSheet.in Am9150 4-59SWITCHING WAVEFORMS KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS: OUTPUTS MUST AE WIL BE STEADY STEADY WILL BE MAY CH FROMATOL CHANGING FROM H TOL may cHance WILL BE FROML TOH CHANGING FROM L TOH DONT CARE; CHANGING: ANY CHANGE STATE PERMITTED UNKNOWN CENTER DOES NOT LINE IS HiGH APPLY \ E OFF STATE KS000010 ZA d 3 4-60 Read Cycle www.DataSheet.in Am9150 WF009890SWITCHING WAVEFORMS (Cont'd.) 5 (cB) W (WE) Og-D3 (DATA INPUT) a - Xx @ 5c \\ i) OW/LLLLLLLLLz Pe i (REGET) WW y @ ) HIGH 9-3 LXER RRNA MPEDANCE KORTA OUTPUT) RX RA RAX KX OKNY \ OUTPUT VALID ZERO WF009810 Reset Cycle www.DataSheet.in Am9150 4-61