1
®
FN9263.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL97645
Boost + VON Slice + VCOM
The ISL97645 represents an integrated DC/DC regulator for
monitor and notebook applications with screen sizes up to
20”. The device integrates a boost converter for generating
AVDD, a VON slice circuit, and a high performance VCOM
amplifier.
The boost converter features a 2.6A FET and has user
programmable soft-start and compensation. With efficiencies
up to 92%, the AVDD is user selectable from 7V to 20V.
The VON slice circuit can control gate voltages up to 30V.
High and low levels are programmable, as well as discharge
rate and timing.
The integrated VCOM features high speed and drive
capability. With 30MHz bandwidth and 50V/µs slew rate, the
VCOM amplifier is capable of driving 400mA peaks, and
100mA continuous output curren t.
Pinout
ISL97645
(24 LD 4x4 QFN)
TOP VIEW
Features
2.7V to 5.5V Input
2.6A Integrated Boost for Up to 20V AVDD
Integrated VON Slice
600kHz/1.2MHz fS
•V
COM Amplifier
-30MHz BW
-50V/µs SR
- 400mA Peak Output Current
UV and OT Protection
24 Ld 4x4 QFN
Pb-Free (RoHS Compliant)
Applications
LCD Monitors (15”+)
Notebook Display (up to 16”)
VGH
RE
CE
PGND
FB
ENABLE
OUT
NEG
POS
AGND
NC
NC
GND
VGH_M
VFLK
VDPM
VDD_1
VDD_2
LX
VIN
FREQ
COMP
SS
NC
1
2
3
4
5
6
18
17
16
15
14
13
24 23 22 21 20 19
789101112
Ordering Information
PART NUMBER
(Note) PART
MARKING
TEMP.
RANGE
(°C) PACKAGE
(Pb-Free) PKG.
DWG. #
ISL97645IRZ 97645IRZ -40 to +85 24 Ld 4x4 QFN L24. 4x4D
ISL97645IRZ-T* 97645IRZ -40 to +85 24 Ld 4x4 QFN
6k pc Tape & Reel L24.4x4D
ISL97645IRZ-TK* 97645IRZ -40 to +85 24 Ld 4x4 QFN
1k pc Tape & Reel L24.4x4D
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach materials
and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which
is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
Data Sheet December 14, 2007
2FN9263.1
December 14, 2007
Pin Descriptions
PIN NUMBER PIN NAME FUNCTION
1 GND Ground
2 VGH_M Gate Pulse Modulation Output
3 VFLK Gate Pulse Modulation Control Input
4 VDPM Gate Pulse Modulation Enable
5 VDD_1 Gate Pulse Modulation Lower Voltage Input
6VDD_2V
COM Amplifier Supply
7OUTV
COM Amplifier Output
8NEGV
COM Amplifier Inverting Input
9POSV
COM Amplifier Noninverting Input
10 AGND VCOM Amplifier Ground
11 NC
12 NC
13 NC
14 SS Boost Converter Soft-start. Connect a capacitor between this pin and GND to set the soft-start
time.
15 COMP Boost Converter Compensation Pin. Connect a series resistor and capacitor between this pin and
GND to optimize transient response.
16 FREQ Boost Converter Frequency Select.
17 VIN Boost Converter Power Supply
18 LX Boost Converter Switching Node
19 ENABLE Chip Enable Pin. Connect to Vin for normal operation, GND for shutdown.
20 FB Boost Converter Feedback
21 PGND Boost Converter Power Ground
22 CE Gate Pulse Modulator Delay Control. Connect a capacitor between this pin and GND to set the
delay time.
23 RE Gate Pulse Modulator Slew Control. Connect a resistor between this pin and GND to set the falling
slew rate.
24 VGH Gate Pulse Modulator High Voltage Input
ISL97645
3FN9263.1
December 14, 2007
Absolute Maximum Ratings Thermal Information
Lx to GND, AGND and PGND . . . . . . . . . . . . . . . . . . . . -0.5 to +25V
VDD2, OUT, NEG and POS
to GND, AGND and PGND. . . . . . . . . . . . . . . . . . . . . -0.5 to +25V
VDD1, VGH and VGH_M
to GND, AGND and PGND. . . . . . . . . . . . . . . . . . . . . -0.5 to +32V
Differential Voltage Between POS and NEG . . . . . . . . . . . . . . . ±6V
Voltage Between GND, AGND and PGND . . . . . . . . . . . . . . . ±0.5V
All Other Pins to GND, AGND and PGND. . . . . . . . . . -0.5 to +6.5V
Input, Output, or I/O Voltage . . . . . . . . . . .GND -0.3V to VIN + 0.3V
Recommended Operating Conditions
Input Voltage Range, VS . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Boost Output Voltage Range, AVDD . . . . . . . . . . . . . . . . .8V to 20V
Input Capacitance, CIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22µF
Boost Inductor, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH to 10µH
Output Capacitance, COUT. . . . . . . . . . . . . . . . . . . . . . . . . .2x22µF
Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C
Thermal Resistance θJA (°C/W) θJC (°C/W)
4x4 QFN Package (Notes 1, 2) . . . . . . 39 2.5
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Maximum Continuous Junction Temperature . . . . . . . . . . . +125°C
Power Dissipation
TA ≤ +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.44W
TA = +70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.34W
TA = +85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.98W
TA = +100°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.61W
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications VIN = ENABLE = 5V, VDD1 = VDD2 = 14V, VGH = 25V, AVDD = 10V, TA= -40°C to +85°C
Unless Otherwise Noted.
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
GENERAL
VSVINInput Voltage Range 2.7 3.3 5.5 V
IS_DIS VIN Supply Currents when Disabled ENABLE = 0V 0.2 2 µA
IS VIN Supply Currents ENABLE = 5V, LX not switching 1 mA
UVLO Undervoltage Lockout Threshold VIN2 Rising 2.3 2.45 2.6 V
VIN2 Falling 2.2 2.35 2.5 V
OTRThermal Shutdown Temperature Temperature Rising 140 °C
OTFTemperature Falling 100 °C
LOGIC INPUT CHARACTERISTICS - ENABLE, VFLK, FREQ, VDPM
VIL Low Voltage Threshold 0.8 V
VIH High Voltage Threshold 2.2 V
RIL Pull-Down Resistor Enabled, Input at Vin 150 250 400 kΩ
STEP-UP SWITCHING REGULATOR
AVDD Output Voltage Range VIN*1.25 20 V
ΔAVDD/ΔIOUT Load Regulation 50mA < ILOAD < 250mA 0.2 %
ΔAVDD/ΔVIN Line Regulation ILOAD = 150mA, 3.0 < VIN < 5.5V 0.15 0.25 %/V
ACCAVDD Overall Accuracy (Line, Load,
Temperature) 10mA < ILOAD < 300mA,
3.0 < Vin < 5.5V, 0°C < TA < +85°C -3 3 %
VFB Feedback Voltage (VFB)I
LOAD = 100mA, TA = +25°C 1.20 1.21 1.22 V
ILOAD = 100mA, TA = -40°C to +85°C 1.19 1.21 1.23 V
ISL97645
4FN9263.1
December 14, 2007
IFB FB Input Bias Current 250 500 nA
RDS(ON) Switch On Resistance 150 300 mΩ
EFF Peak Efficiency 92 %
ILIM Switch Current Limit 2.1 2.6 A
DMAX Max Duty Cycle 85 90 %
FOSC Oscillator Frequency FREQ = 0V 550 650 800 kHz
FREQ = VIN2 1.0 1.2 1.4 MHz
ISS Soft-Start Slew Current SS < 1V, TA = +25°C 2.75 µA
VCOM AMPLIFIER RLOAD = 10k, CLOAD = 10pF, Unless Otherwise Stated
VSAMP Supply Voltage 4.5 20 V
ISAMP Supply Current 3mA
VOS Offset Voltage 320mV
IBNoninverting Input Bias Current 0 100 nA
CMIR Common Mode Input Voltage
Range 0VDD2V
CMRR Common-Mode Rejection Ratio 50 70 dB
PSRR Power Supply Rejection Ratio 70 85 dB
VOH Output Voltage Swing High Iout(source) = 5mA VDD2 - 50 mV
VOH Output Voltage Swing High Iout(source) = 50mA VDD2 - 450 mV
VOL Output Voltage Swing Low Iout(sink) = 5mA 50 mV
VOL Output Voltage Swing Low Iout(sink) = 50mA 450 mV
ISC Output Short Circuit Current 250 400 mA
SR Slew Rate 50 V/µs
BW Gain Bandwidth -3dB gain point 30 MHz
GATE PULSE MODULATOR
VGH VGH Voltage 7 30 V
IVGH VGH Input Current VFLK = 0 260 µA
RE = 33kΩ, VFLK = VDD1 40 µA
VDD1 VDD1 Voltage 3 VGH - 2 V
IVDD1 VDD1 Input Current -2 0.1 2 µA
RONVGH VGH to VGH_M On Resistance 70 Ω
IDIS_VGH VGH_M Discharge Current (Note 1) RE = 33kΩ8mA
TDEL DELAY Time (Note 2) CE = 470pF, RE = 33kΩ1.9 µs
NOTES:
1. Nominal discharge current = 300/(RE+5kΩ).
2. Nominal delay time = 4000*CE.
Electrical Specifications VIN = ENABLE = 5V, VDD1 = VDD2 = 14V, VGH = 25V, AVDD = 10V, TA= -40°C to +85°C
Unless Otherwise Noted. (Continued)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
ISL97645
5FN9263.1
December 14, 2007
I
Typical Performance Curves
FIGURE 1. AVDD EFFICIENCY vs IAVDD FIGURE 2. AVDD LOAD REGULATION vs IAVDD
FIGURE 3. LINE REGULATION AVDD vs VIN FIGURE 4. BOOST CONVERTER TRANSIENT RESPONSE
FIGURE 5. GPM CIRCUIT WAVEFORM FIGURE 6. GPM CIRCUIT WAVEFORM
0
10
20
30
40
50
60
70
80
90
100
0 200 400 600 800 1000 1200
IAVDD (mA )
EFFICIENCY (%)
FOSC = 1.2MHz
FOSC = 650kHz
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0 200 400 600 800 1000 1200
IAVDD (mA)
LOAD REGULATION (%)
FOSC = 1.2MHz
FOSC = 650kHz
10.15
10.2
10.25
10.3
10.35
10.4
10.45
10.5
3 3.5 4.0 4.5 5.0 5.5 6.0
VIN (V)
AVDD (V)
AVDD 500mA
AVDD 150mA IAVDD
AVDD (AC COUPLED)
L = 10µH, COUT = 40µF, CCOMP = 2.2nF, RCOMP = 10k
VGH_M
VFLK
CE = 1pF, RE = 100k
VGH_M
VFLK
CE = 1000pF, RE = 100k
ISL97645
6FN9263.1
December 14, 2007
FIGURE 7. GPM CIRCUIT WAVEFORM FIGURE 8. GPM CIRCUIT WAVEFORM
FIGURE 9. VCOM RISING SLEW RATE FIGURE 10. VCOM BANDWIDTH MEASUREMENT
Typical Performance Curves (Continued)
VGH_M
VFLK
CE = 10pF, RE = 100k
VGH_M
VFLK
CE = 10pF, RE = 150k
INPUT SIGNAL
OUTPUT SIGNAL
INPUT
OUTPUT
SIGNAL
SIGNAL
(-3dB ATTENTUATION
FROM INPUT SIGNAL)
ISL97645
7FN9263.1
December 14, 2007
Block Diagram
FIGURE 11. ISL97645 BLOCK DIAGRAM
+
-
VFLK VGH CE REVGH_M
LX
PGND
ENABLE
FB
COMP
FREQ
OSCILLATION
SLOPE
COMPENSATION
GENERATOR
REFERENCE
GENERATOR
SUMMING
AMPLIFIER
START-UP AND
FAULT CONTROL
+
-
PWM
LOGIC
SS
2.5µA
OUT
VIN
VDPM
NC
NC
VDD2
POS
NEG
GND
VDD1
+
-
GPM
CIRCUIT
ISL97645
8FN9263.1
December 14, 2007
Typical Application Diagram
Applications Information
The ISL97645 provides a complete power solution for TFT
LCD applications. The system consists of one boost
converter to generate A VDD voltage for column drivers, one
integrat ed VCOM buffer which can provide up to 400mA peak
current. This part also integrates Gate Pulse Modulator
circuit that can help to optimize the picture quality.
Enable Control
When enable pin is pulling down, the ISL97645 is shut down
reducing the supply current to <10µA. When the voltage at
enable pin reaches 2.2V, the ISL97645 is on.
Boost Converter
Frequency Selection
The ISL97645 switching frequency can be user selected to
operate at eit h er co nstant 650kHz or 1.2MHz. Lo w er
switching frequency can save power dissipation, while
higher switching frequency can allow smalle r external
components like inductor and output capacitors, etc.
Connecting FREQ pin to ground sets the PWM switching
frequency to 650MHz, or connecting FREQ pin to VIN for
1.2MHz.
Soft-Start
The soft-start is provided by an internal 2.5µA current source
to charge the external soft start capacitor. The ISL97645
ramps up current limit from 0A up to full value, as the voltage
at SS pin ramps from 0 to 1.2V. Hence the soft-start time is
4.8ms when the soft-start cap acitor is 10nF, 22.6ms for 47nF
and 48ms for 100nF.
Operation
The boost converter is a current mode PWM converter
operating at either a 650kHz or 1.2MHz. It can operate in
both discontinuous conduction mode (DCM) at light load and
FIGURE 12. TYPICAL APPLICATION DIAGRAM
BOOST
GPM
CIRCUIT
VON
AVDD
ENABLE
VGH
VDD_1
VGH_M
LX
FB
VFLK
COMP
SS
POS
TO ROW DRIVER
NC
NC
VIN
GND
VDPM
FREQ-
CE
RE
PGND
VDD2
AGND
VIN
C1
22µF C3
2.2nF
C4
10nF
S1
S2
S3
C5
470P
R3
2K
C6
0.1µF
0.47µF
R2
1.3K
R1
10K
C2
47µF
L1
10µH D1
NEG-
OUT
VCOM
+4.0V
AVDD
R7
80k
C11
1µF
R6
130k
ISL97645
9FN9263.1
December 14, 2007
continuous mode (CCM). In continuous current mode,
current flows continuously in the inductor during the entire
switching cycle in steady state operation. The voltage
conversion ratio in continuous current mode is given by:
Where D is the duty cycle of the switching MOSFET.
Figure 11 sho ws the block diagra m of the boost regulator. It
uses a summing amplifier architecture consisting of gm
stages for voltage feedback, current feedback and slope
compensation. A comparator looks at the peak inductor
current cycle by cycle and terminates the PWM cycle if the
current limit is reached.
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network in the order of 60kΩ is recommended.
The boost converter output voltage is determined by the
following equation:
The current through the MOSFET is limited to 2.6APEAK.
This restricts the maximum output current (average) based
on the following equation:
Where ΔIL is peak to peak inductor ripple current, and is set
by:
where fS is the switching frequency (650kHz or 1.2MHz).
The Table 2 gives typical values (margins are considered
10%, 3%, 20%, 10% and 15% on VIN, VO, L, fS and IOMAX).
Capacitor
An input capa ci to r is used to suppress the voltage ripple
injected into the boost converter. The ceramic capacitor with
capacitance larger than 10µF is recommended. The voltage
rating of input capacitor should be larger than the maximum
input voltage. Some capacitors are recommended in Table 1
for input capacitor.
VBoost
VIN
-------------------1
1D
-------------
=(EQ. 1)
VBoost R1R2
+
R2
---------------------VFB
×=(EQ. 2)
T ABLE 1. BOOST CONVERTER INPUT CAP ACITOR
RECOMMENDATION
CAPACITOR SIZE MFG PART NUMBER
10µF/16V 1206 TDK C3216X7R1C106M
10µF/10V 0805 Murata GRM21BR61A106K
22µF/10V 1210 Murata GRB32ER61A226K
IOMAX ILMT
ΔIL
2
--------
⎝⎠
⎛⎞
VIN
VO
---------
×=(EQ. 3)
ΔILVIN
L
--------- D
fs
----
×=(EQ. 4)
TABLE 2. MAXIMUM OUTPUT CURRENT CALCULATION
VIN (V) VO (V) L (µH) Fs (MHz) IOMAX (mA)
3 9 10 0.65 636
3 12 10 0.65 419
3 15 10 0.65 289
5 9 10 0.65 1060
5 12 10 0.65 699
5 15 10 0.65 482
5 18 10 0.65 338
3 9 10 1.2 742
3 12 10 1.2 525
3 15 10 1.2 395
5 9 10 1.2 1236
5 12 10 1.2 875
5 15 10 1.2 658
5 18 10 1.2 514
ISL97645
10 FN9263.1
December 14, 2007
Inductor
The boost inductor is a critical part which influences the
output voltage ripple, transient response, and efficiency.
Values of 3.3µH to 10µ H are used to match the internal
slope compensation. The inductor must be able to handl e
the following average and peak current:
Some inductors are recommended in Table 3.
Rectifier Diode
A high-speed diode is necessary due to the high switching
frequency. Schottky diodes are recommended because of
their fast recovery time and low forward voltage. The reverse
voltage rating of this diode should be higher than the
maximum output voltage. The rectifier diode must meet the
output current and peak inductor current requirements. The
following table is some recommendations for boost converter
diode.
Output Capacitor
The output capacitor supplies the load directly and reduces
the ripple voltage at the output. Output ripple voltage
consists of two components: the voltage drop due to the
inductor ripple current flowing through the ESR of output
capacitor, and the charging an d discharg ing of the output
capacitor.
For low ESR ceramic capacitors, the output ripple is
dominated by the charging and discharging of the output
capacitor. The voltage rating of the output capacitor should
be greater than the maximum output voltage.
Note: Capacitors have a voltage coefficient that makes their
effective capacitance drop as the voltage across then
increases. COUT in the equation above assumes the
effective value of the cap acitor at a particular voltage and not
the manufacturer’s stated value, measured at zero volts.
The following table shows some selections of output
capacitors.
Compensation
The boost converter of ISL97645 can be compensated by a
RC network connected from CM1 pin to ground. 4.7nF and
10k RC network is used in the demo board. The larger value
resistor and lower value capacitor can lower the transient
overshoot, however, at the expense of stability of the loop.
Cascaded MOSFET Application
An 20V N-channel MOSFET is integrated in the boo st
regulator. For the applications where the output voltage is
greater than 20V, an external cascaded MOSFET is needed
as shown in Figure 13. The voltage rating of the external
MOSFET should be greater than AVDD.
TABLE 3. BOOST INDUCTOR RECOMMENDATION
INDUCTOR DIMENSIONS
(mm) MFG PART NUMBER
6.8µH/3APEAK 7.3x6.8x3.2 TDK RLF7030T-6R8N3R0
10µH/4APEAK 8.3x8.3x4.5 Sumida CDR8D43-100NC
5.2µH/4.55APEAK 10x10.1x3.8 Cooper
Bussmann CD1-5R2
T ABLE 4. BOOST CONVERTER RECTIFIER DIODE
RECOMMENDATION
DIODE VR/IAVG RATING PACKAGE MFG
SS23 30V/2A SMB Fairchild
Semiconductor
MBRS340 40V/3A SMC International
Rectifier
SL23 30V/2A SMB Vishay
Semiconductor
ILAVG IO
1D
-------------
=
ILPK ILAVG
ΔIL
2
--------
+= (EQ. 5)
VRIPPLE ILPK ESR VOVIN
VO
------------------------IO
COUT
----------------1
fs
----
××+×=(EQ. 6)
TABLE 5. BOOST OUTPUT CAPACITOR RECOMMENDATION
CAPACITOR SIZE MFG PART NUMBER
10µF/25V 1210 TDK C3225X7R1E106M
10µF/25V 1210 Murata GRM32DR61E106K
FIGURE 13. CASCADED MOSFET TOPOLOGY FOR HIGH
OUTPUT VOLTAGE APPLICATIONS
Intersil
ISL97645
LX
FB
AVDD
VIN
ISL97645
11 FN9263.1
December 14, 2007
Gate Pulse Modulator Circuit
The gate pulse modulator circuit functions as a three way
multiplexer, switching VGHM betwee n gr ound, VDD1 and
VGH. Voltage selection is provided by digital inputs VDPM
(enable) and VFLK (control). High to low delay and slew
control is provided by external components on pins CE and
RE, respectively. A block diagram of the gate pulse
modulator circuit is shown in Figure 14.
When VDPM is LOW, the block is disabled and VGHM is
grounded. When VDPM is HIGH, the output is determined
by VFLK. When VFLK goes high, VGHM is pulled to VGH by
a 70Ω switch. When VFLK goes low, there is a delay
controlled by capacitor CE, following which VGHM is driven
to VDD1, with a slew rate controlled by resistor RE. Note
that VDD1 is used only as a reference voltage for an
amplifier, thus does not have to source or sink a signific ant
DC current.
FIGURE 14. GATE PULSE MODULATOR CIRCUIT BLOCK DIAGRAM
+
-
+
-
+
-
VGH
VGH_M
VDD1
RE
CE
VFLK
EnGPM1
VREF
200µA
x240
CONTROL AND
TIMING
ISL97645
12 FN9263.1
December 14, 2007
Low to high transition is determine d primarily by the switch
resistance and the external capacitive load. High to low
transition is more complex. Take the case where the block is
already enabled (VDPM is H). When VFLK is H, pin CE is
grounded. On the falling edge of VFLK, a current is passed
into pin CE, to charge an external capacitor to 1.2V. This
creates a delay, equal to CE*4200. At this point, the output
begins to pull down from VGH to VDD1. The slew curre nt is
equal to 300/(RE+5000)*Load Capacitance.
S tart-Up Sequence
Figure 16 shows a detailed start-up sequence waveform.
When VIN exceeds 2.5V and ENABLE reaches the VIH
threshold value, Boost co nverter starts up, and gate pulse
modulator circuit output holds until VDPM goes to high. Note
that there is a DC path in the boost converter from the input
to the output through the inductor and diode, hence the input
voltage will be seen at output with a forward voltage drop of
diode before the part is enabled. If this voltage is not desired,
the following circuit can be inserted betwee n input and
inductor to disconnect the DC path when the part is disabled.
VCOM Amplifier
The VCOM amplifier is designed to control the voltage on the
back plate of an LCD display. This plate is capacitively
coupled to the pixel drive voltage which alternately cycles
positive and negative at the line rate for the display . Thus the
amplifier must be capable of sourcing and sinking capacitive
pulses of current, which can occasionally be quite large (a
few 100mA for typical applications).
The ISL97645 VCOM amplifier's output current is limited to
400mA. This limit level, which is roughly the same for
sourcing and sinking, is included to maintain reliable
operation of the part. It does not necessarily prevent a large
temperature rise if the current is maintained. (In this case the
whole chip may be shut down by the thermal trip to protect
functionality.) If the displ ay occasionally demands current
pulses higher than this limit, the reservoir capacitor will
provide the excess and the amplifier will top the reservoir
capacitor back up once the pulse has stopped. This will
happen on the µs time scale in practica l systems and for
pulses 2 or 3 times the current limit, the V COM voltage will
have settled again before the next line is processed.
Fault Protection
ISL97645 provides the overall fault protections including
over current protection and over-temperature protection.
An internal temperature sensor continuously monitors the
die temperature. In the event that die temp erature exceeds
the thermal trip point, the device will shut down and disable
itself. The upper and lower trip points are typically set to
+140°C and +100°C respectively.
FIGURE 15. GATE PULSE MODULATOR TIMING DIAGRAM
DELAY TIME
CONTROLLED BY CE
SLOPE CONTROLLED
BY RE AND LOAD
CAPACITANCE
VGH
VDD_1
VDPM
VFLK
VGH_M
0
0
0
FIGURE 16. START-UP SEQUENCE
VIN
VDPM
AVDD
0
0
0
ENABLE
0
VGH_M
VIN THRESHOLD
FIGURE 17. CIRCUIT TO DISCONNECT THE DC PATH OF
BOOST CONVERTER
INPUT
ENABLE
TO INDUCTOR
ISL97645
13
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FN9263.1
December 14, 2007
Layout Recommendation
The device’s performance including efficiency, output noise ,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
There are some general guidelines for layout:
1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
2. Place VIN and VDD bypass capacitors close to the pins.
3. Reduce the loop area with large AC amplitudes and fast
slew rate.
4. The feedback network should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.
5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point.
6. The exposed die pla te , on the underneath of the
package, should be soldered to an equivalent area of
metal on the PCB. This contact area should have multiple
via connections to the back of the PCB as well as
connections to intermediate PCB layers, if available, to
maximize thermal dissipation away from the IC.
7. To minimize the thermal resistance of the package when
soldered to a multi-layer PCB, the amount of copper track
and ground plane area connected to the exposed die
plate should be maximized and spread out as far as
possible from the IC. The bottom and top PCB areas
especially should be maximized to allow thermal
dissipation to the surrounding air.
8. A signal ground plane, separate from the power ground
plane and connected to the power ground pins only at the
exposed die plate, should be used for ground return
connections for control circuit.
9. Minimize feedback input track lengths to avoid switching
noise pick-up.
A demo board is available to illustrate the proper layout
implementation.
ISL97645
14 FN9263.1
December 14, 2007
ISL97645
Package Outline Drawing
L24.4x4D
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/06
0 . 90 ± 0 . 1
5
C0 . 2 REF
TYPICAL RECOMMENDED LAND PATTERN
0 . 05 MAX.
( 24X 0 . 6 )
DETAIL "X"
( 24X 0 . 25 )
0 . 00 MIN.
( 20X 0 . 5 )
( 2 . 50 )
SIDE VIEW
( 3 . 8 TYP )
BASE PLANE
4
TOP VIEW
BOTTOM VIEW
712
24X 0 . 4 ± 0 . 1
13
4.00
PIN 1 18
INDEX AREA
24
19
4.00 2.5
0.50
20X
4X
SEE DETAIL "X"
- 0 . 05
+ 0 . 07
24X 0 . 23
2 . 50 ± 0 . 15
PIN #1 CORNER
(C 0 . 25)
1
SEATING PL AN E
0.08 C
0.10 C
C
0.10 M C A B
AB
(4X) 0.15
located within the zone indicated. The pin #1 indentifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
between 0.15mm and 0.30mm from the terminal tip.
Dimension b applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES: