CY7C056V
CY7C057V
3.3 V 16K/32K x 36
FLEx36™ Asynchronous Dual-Port Static
RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-06055 Rev. *E Revised March 30, 2011
Features
■True dual-ported memory cells that allow simultaneous
access of the same memory location
■16K x 36 organization (CY7C056V)
■32K x 36 organization (CY7C057V)
■0.25-micron Complimentary metal oxide semiconductor
(CMOS) for optimum speed/power
■High-speed access: 12/15 ns
■Low operating power
❐Active: ICC = 250 mA (typical)
❐Standby: ISB3 = 10 A (typical)
■Fully asynchronous operation
■Automatic power-down
■Expandable data bus to 72 bits or more using Master/Slave
Chip Select when using more than one device
■On-chip arbitration logic
■Semaphores included to permit software handshaking
between ports
■INT flag for port-to-port communication
■Byte select on left port
■Bus matching on right port
■Depth expansion via dual chip enables
■Pin select for Master or Slave
■Commercial and Industrial temperature ranges
■Available in 144-Pin Thin quad plastic flatpack (TQFP) or
172-Ball ball grid array (BGA)
■Pb-free packages available
■Compact packages:
❐144-Pin TQFP (20 x 20 x 1.4 mm)
❐172-Ball BGA (1.0-mm pitch) (15 x 15 x.51 mm)
Notes
1. A0–A13 for 16K; A0–A14 for 32K devices.
2. BUSY is an output in Master mode and an input in Slave mode.
R/WL
CE0L
CE1L
OEL
I/O
Control
Address
Decode
BUSYL
CEL
Interrupt
Semaphore
Arbitration
SEML
INTL
M/S
R/WR
CE0R
CE1R
OER
CER
Logic Block Diagram
A0L–A13/14L
True Dual-Ported
RAM Array
BUSYR
SEMR
INTR
Address
Decode A0R–A13/14R
[2] [2]
[1] [1]
14/15 14/15
14/15 14/15
Left
Port
Control
Logic
I/O18L–I/O26L
9
I/O27L–I/O35L
9
I/O0L–I/O8L
9
I/O9L–I/O17L
9
Right
Port
Control
Logic
I/O
Control
9
9
I/OR
9
9
Bus
Match
9/18/36
BA
BM
SIZE
WA
B0–B3
CY7C056V CY7C057V CY7C037V CY7C038V3.3 V 16K/32K x 36
FLEx36™ Asynchronous Dual-Port Static RAM
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CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E Page 2 of 26
Contents
Pin Configurations ...........................................................4
Pin Configurations ...........................................................5
Selection Guide ................................................................5
Pin Definitions ..................................................................6
Maximum Ratings............................................................. 7
Operating Range ............................................................... 7
Electrical Characteristics..................................................8
Capacitance ...................................................................... 8
AC Test Load and Waveforms ......................................... 9
Switching Characteristics ..............................................10
Data Retention Mode ...................................................... 11
Timing .............................................................................. 11
Read Cycle No. 1 (Either Port Address Access) ........ 12
Read Cycle No. 2 (Either Port CE/OE Access) ..........12
Read Cycle No. 3 (Either Port)...................................12
Switching Waveforms ....................................................12
Write Cycle No. 1: R/W Controlled Timing ................. 13
Write Cycle No. 2: CE Controlled Timing ...................13
Semaphore Read After Write Timing, Either Side......14
Timing Diagram of Semaphore Contention ................ 14
Timing Diagram of Write with BUSY (M/S = HIGH).... 15
Write Timing with Busy Input (M/S = LOW) ............... 15
Busy Timing Diagram No. 1 (CE Arbitration).............. 16
Busy Timing Diagram No. 2 (Address Arbitration) ..... 16
Architecture ....................................................................18
Functional Description ................................................... 18
Write Operation ......................................................... 18
Read Operation ......................................................... 18
Interrupts ................................................................... 18
Busy .......................................................................... 18
Master/Slave ............................................................. 18
Semaphore Operation ............................................... 18
Right Port Configuration................................................. 20
Right Port Operation ...................................................... 20
Left Port Operation ......................................................... 20
Bus Match Operation ..................................................... 20
Long-Word (36-bit) Operation ................................... 21
Word (18-bit) Operation ............................................. 21
Byte (9-bit) Operation ................................................ 21
Ordering Information ...................................................... 22
Ordering Code Definition ........................................... 22
Package Diagrams .......................................................... 23
Acronyms ........................................................................ 24
Document Conventions ................................................. 24
Units of Measure ....................................................... 24
Sales, Solutions, and Legal Information ...................... 26
Worldwide Sales and Design Support ....................... 26
Products .................................................................... 26
PSoC Solutions ......................................................... 26
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CY7C057V
Document #: 38-06055 Rev. *E Page 3 of 26
Functional Description
The CY7C056V and CY7C057V are low-power CMOS 16K and
32K x 36 dual-port static RAMs. Various arbitration schemes are
included on the devices to handle situations when multiple
processors access the same piece of data. Two ports are
provided, permitting independent, asynchronous access for
reads and writes to any location in memory. The devices can be
utilized as standalone 36-bit dual-port static RAMs or multiple
devices can be combined in order to function as a 72-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 72-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete logic. Application areas include
interprocessor/multiprocessor designs, communications status
buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE)[3],
Read or Write Enable (R/W), and Output Enable (OE). Two flags
are provided on each port (BUSY and INT). BUSY signals that
the port is trying to access the same location currently being
accessed by the other port. The Interrupt Flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic Power-down feature is controlled independently on
each port by Chip Select (CE0 and CE1) pins.
The CY7C056V and CY7C057V are available in 144-Pin Thin
quad plastic flatpack (TQFP) and 172-Ball ball grid array (BGA)
packages.
Note
3. CE is LOW when CE0 VIL and CE1 VIH.
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CY7C057V
Document #: 38-06055 Rev. *E Page 4 of 26
Pin Configurations
Notes
4. This pin is A14L for CY7C057V.
5. This pin is A14R for CY7C057V
I/O32L
I/O33R
I/O23L
I/O33L
2
3
4
I/O34L I/O34R
5
I/O35L I/O35R
6
A0L A0R
7
A1L A1R
8
A2L A2R
9
A3L A3R
10
A4L A4R
11
A5L A5R
12
A6L A6R
13
A7L
108
A7R
14
B0
107
BM
15
B1
106
SIZE
16
B2
105
WA
17
B3
104
BA
18
OEL
103
OER
19
R/WL
102
R/WR
20
VDD
101
VDD
21
VSS
100
VSS
22
VSS
99
VDD
23
CE0L
98
CE0R
24
CE1L
97
CE1R
25
M/S
96
VDD
26
SEML
95
SEMR
27
INTL
94
INTR
28
BUSYL
93
BUSYR
29
A8L
92
A8R
30
A9L
91
A9R
31
A10L
90
A10R
32
A11L
89
A11R
33
A12L
88
A12R
34
A13L
87
A13R
35
NC
86
NC
36
I/O26L
85
I/O26R
I/O25L
84
I/O25R
I/O24L
83
I/O24R
82
81
41
42
43
44
I/O22L I/O31L
45
VSS VSS
46
I/O21L I/O30L
47
I/O20L I/O29L
48
I/O19L I/O28L
49
I/O18L I/O27L
50
VDD VDD
51
I/O8L I/O17L
52
I/O7L I/O16L
53
I/O6L I/O15L
54
I/O5L I/O14L
55
VSS VSS
56
I/O4L I/O13L
57
I/O3L I/O12L
58
I/O2L
143
I/O11L
59
I/O1L
142
I/O10L
60
I/O0L
141
I/O9L
61
I/O0R
140
I/O9R
62
I/O1R
139
I/O10R
63
I/O2R
138
I/O11R
64
I/O3R
137
I/O12R
65
I/O4R
136
I/O13R
66
VSS
135
VSS
67
I/O5R
134
I/O14R
68
I/O6R
133
I/O15R
69
I/O7R
132
I/O16R
70
I/O8R
131
I/O17R
71
VDD
130
VDD
72
I/O18R
129
I/O27R
123
I/O19R
128
I/O28R
122
I/O20R
127
I/O29R
121
I/O21R
126
I/O30R
120
VSS
125
VSS
119
I/O22R
124
I/O31R
118
I/O23R I/O32R
117
116
37
38
39
40
80
79
78
77
76
75
74
73
115
114
113
112
111
110
109
144
1
CY7C056V (16K x 36)
CY7C057V (32K x 36)
[4] [5]
Figure 1. 144-Pin Thin Quad Flatpack (TQFP) Top View
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CY7C057V
Document #: 38-06055 Rev. *E Page 5 of 26
Pin Configurations (continued)
Figure 2. 172-Ball Ball Grid Array (BGA)
Top View
1 2 3 4567891011121314
AI/O32L I/O30L NC VSS I/O13L VDD I/O11L I/O11R VDD I/O13R VSS NC I/O30R I/O32R
BA0L I/O33L I/O29 I/O17L I/O14L I/O12L I/O9L I/O9R I/O12R I/O14R I/O17R I/O29R I/O33R A0R
CNC A1L I/O31L I/O27L NC I/O15L I/O10L I/O10R I/O15R NC I/O27R I/O31R A1R NC
DA2L A3L I/O35L I/O34L I/O28L I/O16L VSS VSS I/O16R I/O28R I/O34R I/O35R A3R A2R
EA4L A5L NC B0L NC NC NC NC BM NC A5R A4R
FVDD A6L A7L B1L NC NC SIZE A7R A6R VDD
GOEL B2L B3L CE0L CE0R BA WA OER
HVSS R/WLA8LCE1L CE1R A8R R/WRVSS
JA9L A10L VSS M/S NC NC VDD VDD A10R A9R
KA11L A12L NC SEML NC NC NC NC SEMR NC A12R A11R
LBUSYL A13L INTL I/O26L I/O25L I/O19L VSS VSS I/O19R I/O25R I/O26R INTR A13R BUSYR
MNC NC[4] I/O22L I/O18L NC I/O7L I/O2L I/O2R I/O7R NC I/O18R I/O22R NC[5] NC
NI/O24L I/O20L I/O8L I/O6L I/O5L I/O3L I/O0L I/O0R I/O3R I/O5R I/O6R I/O8R I/O20R I/O24R
PI/O23L I/O21L NC VSS I/O4L VDD I/O1L I/O1R VDD I/O4R VSS NC I/O21R I/O23R
Selection Guide
CY7C056V
CY7C057V
-12
CY7C056V
CY7C057V
-15
Unit
Maximum access time 12 15 ns
Typical operating current 250 240 mA
Typical standby current for ISB1 (Both ports TTL level) 55 50 mA
Typical standby current for ISB3 (Both ports CMOS level) 10 A10 AA
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CY7C057V
Document #: 38-06055 Rev. *E Page 6 of 26
Pin Definitions
Left Port Right Port Description
A0L–A13/14L A0R–A13/14R Address (A0–A13 for 16K; A0–A14 for 32K devices)
SEML SEMRSemaphore Enable
CE0L, CE1L CE0R, CE1R Chip Enable (CE is LOW when CE0 VIL and CE1 VIH)
INTLINTRInterrupt flag
BUSYLBUSYRBusy flag
I/O0L–I/O35L I/O0R–I/O35R Data bus input/output
OELOEROutput Enable
R/WLR/WRRead/Write Enable
B0–B3Byte select inputs. Asserting these signals enables read and write operations
to the corresponding bytes of the memory array.
BM, SIZE See bus matching for details.
WA, BA See bus matching for details.
M/S Master or Slave select
VSS Ground
VDD Power
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CY7C057V
Document #: 38-06055 Rev. *E Page 7 of 26
Maximum Ratings[6]
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................–65 C to +150 C
Ambient temperature with
power applied ........................................... –55C to +125 C
Supply voltage to ground potential ...............–0.5 V to +4.6 V
DC voltage applied to
outputs in High Z state........................... –0.5 V to VDD+0.5 V
DC input voltage .................................–0.5 V to VDD+0.5 V[7]
Output current into outputs (LOW) .............................. 20 mA
Static discharge voltage........................................... >2001 V
Latch-up current ..................................................... >200 mA
Notes
6. The voltage on any input or I/O pin can not exceed the power pin during power-up.
7. Pulse width < 20 ns.
Operating Range
Range
Ambient
Temperature VDD
Commercial 0 C to +70 C 3.3 V ± 165 mV
Industrial –40 C to +85 C 3.3 V ± 165 mV
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CY7C057V
Document #: 38-06055 Rev. *E Page 8 of 26
Notes
8. Deselection for a port occurs if CE0 is HIGH or if CE1 is LOW.
9. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
10. Tested initially and after any design or process changes that may affect these parameters.
Electrical Characteristics Over the Operating Range[8]
Parameter Description
CY7C056V
CY7C057V
Unit
-12 -15
Min Typ Max Min Typ Max
VOH Output HIGH voltage
(VDD = Min., IOH = –4.0 mA) 2.4 – 2.4
–
–V
VOL Output LOW voltage
(VDD = Min., IOL = +4.0 mA) –0.4– 0.4V
VIH Input HIGH voltage 2.0 – 2.0 – V
VIL Input LOW voltage – 0.8 – 0.8 V
IOZ Output leakage current –10 10 –10 10 A
ICC Operating current (VDD = Max.,
IOUT = 0 mA) output disabled
Commercial
–
250 385
–
240 360 mA
Industrial – 265 385 mA
ISB1 Standby current (Both ports TTL level
and deselected)
f = fMAX
Commercial 55 75 50 70 mA
Industrial –6595mA
ISB2 Standby current (One port TTL
level and deselected)
f = fMAX
Commercial 180 240 175 230 mA
Industrial – 190 255 mA
ISB3 Standby current (Both ports CMOS
level and deselected) f =0
Commercial 0.01 1 0.01 1 mA
Industrial – 0.01 1 mA
ISB4 Standby current (One Port CMOS
level and deselected) f = fMAX[9] Commercial 160 210 155 200 mA
Industrial – 170 215 mA
Capacitance[10]
Parameter Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz,
VDD = 3.3 V
10 pF
COUT Output capacitance 10 pF
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CY7C057V
Document #: 38-06055 Rev. *E Page 9 of 26
Notes
11. External AC Test Load Capacitance = 10 pF.
12. (Internal I/O pad Capacitance = 10 pF) + AC Test Load.
AC Test Load and Waveforms
VTH = 1.5 V
OUTPUT
C
(a) Normal Load (Load 1)
R = 50
Z0 = 50
[11]
3.0 V
VSS
90% 90%
10%
3ns 3ns
10%
ALL INPUT PULSES
3.3 V
OUTPUT
C = 5 pF
(b) Three-State Delay (Load 2)
R2 = 435
R1 = 590
(b) Load Derating Curve
1
2
3
4
5
6
7
30 60 80 100 200
for access time (ns)
Capacitance (pF)
20[12]
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CY7C057V
Document #: 38-06055 Rev. *E Page 10 of 26
Switching Characteristics Over the Operating Range[13]
Parameter Description
CY7C056V
CY7C057V
Unit
-12 -15
Min Max Min Max
Read Cycle
tRC Read cycle time 12 – 15 –ns
tAA Address to data valid – 12 –15 ns
tOHA Output hold from address change 3 – 3 – ns
tACE[14, 15] CE LOW to data valid – 12 –15 ns
tDOE OE LOW to data valid – 8 –10 ns
tLZOE[14, 16, 17, 18] OE Low to low Z 0 – 0 – ns
tHZOE[14, 16, 17, 18] OE HIGH to High Z – 10 –10 ns
tLZCE[14, 13, 17, 18] CE LOW to Low Z 3 – 3 – ns
tHZCE[14, 16, 17, 18] CE HIGH to High Z – 10 –10 ns
tLZBE Byte Enable to Low Z 3 – 3 – ns
tHZBE Byte Enable to High Z – 10 –10 ns
tPU[14, 18] CE LOW to power-up 0 – 0 – ns
tPD[14, 18] CE HIGH to power-down – 12 –15 ns
tABE[15] Byte Enable access time – 12 –15 ns
Write Cycle
tWC Write cycle time 12 – 15 –ns
tSCE[14, 15] CE LOW to write end 10 – 12 –ns
tAW Address valid to write end 10 – 12 –ns
tHA Address hold from write end 0 – 0 – ns
tSA[15] Address set-up to write start 0 – 0 – ns
tPWE Write pulse width 10 – 12 –ns
tSD Data set-up to write end 10 – 10 –ns
tHD Data hold from write end 0 – 0 – ns
tHZWE[17, 18] R/W LOW to High Z – 10 – – ns
tLZWE[17, 18] R/W HIGH to Low Z 3 – 3 – ns
tWDD[19] Write pulse to data delay – 25 – – ns
tDDD[19] Write data valid to read data valid – 20 –25 ns
Busy Timing[20]
tBLA BUSY LOW from address match – 12 –15 ns
tBHA BUSY HIGH from address mismatch – 12 –15 ns
tBLC BUSY LOW from CE LOW – 12 –15 ns
Notes
13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOI/IOH
and 10-pF load capacitance.
14. CE is LOW when CE0 VIL and CE1 VIH
15. To access RAM, CE = L and SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
16. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
17. Test conditions used are Load 2.
18. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer
to Read Timing with Busy waveform.
19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
20. Test conditions used are Load 1.
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Document #: 38-06055 Rev. *E Page 11 of 26
Data Retention Mode
The CY7C056V and CY7C057V are designed with battery
backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules ensure data
retention:
1. Chip Enable (CE)[23] must be held HIGH during data retention,
within VDD to VDD – 0.2 V.
2. CE must be kept between VDD – 0.2 V and 70% of VDD during
the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VDD reaches the
minimum operating voltage (3.15 volts).
Notes
21. Test conditions used are Load 1.
22. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
23. CE is LOW when CE0 VIL and CE1 VIH.
24. CE = VDD, Vin = VSS to VDD, TA = 25 C. This parameter is guaranteed but not tested.
Busy Timing[21]
tBHC BUSY HIGH from CE HIGH – 12 –15 ns
tPS Port set-up for priority 5 – 5 – ns
tWB R/W LOW after BUSY (Slave) 0 – 0 – ns
tWH R/W HIGH after BUSY HIGH (Slave) 11 – 13 –ns
tBDD[22] BUSY HIGH to data valid – 12 –15 ns
Interrupt Timing[21]–
tINS INT set time – 12 –15 ns
tINR INT reset time – 12 –15 ns
Semaphore Timing
tSOP SEM flag update pulse (OE or SEM)10–10 –ns
tSWRD SEM flag write to read time 5 – 5 – ns
tSPS SEM flag contention window 5 – 5 – ns
tSAA SEM address access time – 12 –15 ns
Switching Characteristics Over the Operating Range[13] (continued)
Parameter Description
CY7C056V
CY7C057V
Unit
-12 -15
Min Max Min Max
Timing
Parameter Test Conditions[24] Max Unit
ICCDR1 @ VDDDR = 2 V 50 A
Data Retention Mode
3.15 V 3.15 V
VCC 2.0 V
VCC to VCC –0.2 V
VCC
CE
tRC
VIH
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CY7C057V
Document #: 38-06055 Rev. *E Page 12 of 26
Switching Waveforms
Notes
25. R/W is HIGH for read cycles.
26. Device is continuously selected. CE0 = VIL, CE1=VIH, and B0, B1, B2, B3, WA, BA are valid. This waveform cannot be used for semaphore reads.
27. OE = VIL.
28. Address valid prior to or coinciding with CE0 transition LOW and CE1 transition HIGH.
29. To access RAM, CE0 = VIL, CE1=VIH, B0, B1, B2, B3, WA, BA are valid, and SEM = VIH. To access semaphore, CE0 = VIH, CE1=VIL and SEM = VIL or CE0
and SEM=VIL, and CE1= B0 = B1 = B2 = B3, =VIH.
tRC
tAA
tOHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
tOHA
Read Cycle No. 1 (Either Port Address Access)[25, 26, 27]
tACE
tLZOE
tDOE
tHZOE
tHZCE
DATA VALID
tLZCE
tPU tPD
ISB
ICC
DATA OUT
B2, B3, WA, BA
CE0, CE1, B0, B1,
CURRENT
Read Cycle No. 2 (Either Port CE/OE Access)[25, 28, 29]
SELECT VALID
OE
DATA OUT
tRC
ADDRESS
tAA tOHA
CE0, CE1
tLZCE
tABE
tHZCE
tHZCE
tACE
tLZCE
Read Cycle No. 3 (Either Port)[25, 27, 28, 29]
B0, B1, B2,
B3, WA, BA BYTE SELECT VALID
CHIP SELECT VALID
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CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E Page 13 of 26
Notes
30. R/W must be HIGH during all address transitions.
31. A write occurs during the overlap (tSCE or tPWE) of CE0=VIL and CE1=VIH or SEM=VIL and B0–3 LOW.
32. tHA is measured from the earlier of CE0/CE1 or R/W or (SEM or R/W) going HIGH at the end of Write Cycle.
33. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified tPWE.
34. To access RAM, CE0 = VIL, CE1=SEM = VIH.
35. To access byte B0, CE0 = VIL, B0 = VIL, CE1=SEM = VIH.
To access byte B1, CE0 = VIL, B1 = VIL, CE1=SEM = VIH.
To access byte B2, CE0 = VIL, B2 = VIL, CE1=SEM = VIH.
To access byte B3, CE0 = VIL, B3 = VIL, CE1=SEM = VIH.
36. Transition is measured ±150 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
37. During this period, the I/O pins are in the output state, and input signals must not be applied.
38. If the CE0 LOW and CE1 HIGH or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance
state.
Switching Waveforms (continued)
tAW
tWC
tPWE
tHD
tSD
tHA
CE0, CE1
R/W
OE
DATAOUT
DATA IN
ADDRESS
tHZOE
tSA
tHZWE tLZWE
Write Cycle No. 1: R/W Controlled Timing[30, 31, 32, 33]
[36]
[36]
[33]
[34, 35]
NOTE 37 NOTE 37
CHIP SELECT VALID
tAW
tWC
tSCE
tHD
tSD
tHA
R/W
DATA IN
ADDRESS
tSA
Write Cycle No. 2: CE Controlled Timing[30, 31, 32, 38]
CE0, CE1
[34, 35] CHIP SELECT VALID
[+] Feedback
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E Page 14 of 26
Notes
39. CE0 = HIGH and CE1 = LOW for the duration of the above timing (both write and read cycle).
40. I/O0R = I/O0L = LOW (request semaphore); CE0R = CE0L = HIGH and CE1R = CE1L=LOW.
41. Semaphores are reset (available to both ports) at cycle start.
42. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
Switching Waveforms (continued)
tSOP
tSAA
VALID ADRESS VALID ADRESS
tHD
DATAIN VALID DATAOUT VALID
tOHA
tAW
tHA
tACE
tSOP
tSCE
tSD
tSA tPWE
tSWRD tDOE
WRITE CYCLE READ CYCLE
OE
R/W
I/O0
SEM
A0–A2
Semaphore Read After Write Timing, Either Side[39]
MATCH
tSPS
MATCH
R/WL
SEM L
R/WR
SEMR
Timing Diagram of Semaphore Contention[40, 41, 42]
A0L–A2L
A0R–A2R
[+] Feedback
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E Page 15 of 26
Note
43. CE0L = CE0R = LOW; CE1L = CE1R = HIGH.
Switching Waveforms (continued)
VALID
tDDD
tWDD
MATCH
MATCH
R/WR
DATA IN R
DATAOUTL
tWC
ADDRESSR
tPWE
VALID
tSD tHD
ADDRESSL
tPS
tBLA tBHA
tBDD
BUSYL
Timing Diagram of Write with BUSY (M/S = HIGH)[43]
tPWE
R/W
BUSY
tWB tWH
Write Timing with Busy Input (M/S = LOW)
[+] Feedback
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E Page 16 of 26
Note
44. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
Switching Waveforms (continued)
ADDRESS MATCH
tPS
ADDRESSL
BUSYR
ADDRESS MISMATCH
tRC or tWC
tBLA tBHA
ADDRESSR
ADDRESS MATCH ADDRESS MISMATCH
tPS
ADDRESSL
BUSR
tRC or tWC
tBLA tBHA
ADDRESSR
Right Address Valid First:
Busy Timing Diagram No. 2 (Address Arbitration)[44]
Left Address Valid First:
[+] Feedback
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E Page 17 of 26
Notes
45. tHA depends on which enable pin (CE0L/CE1L or R/WL) is deasserted first.
46. tINS or tINR depends on which enable pin (CE0L/CE1L or R/WL) is asserted last.
Switching Waveforms (continued)
Interrupt Timing Diagrams
WRITE 3FFF (7FFF for CY7C057V)
tWC
tHA
READ 3FFF
tRC
tINR
WRITE 3FFE (7FFE for CY7C057V)
tWC
Right Side Sets INTL:
Left Side Sets INTR:
Left Side Clears INTL:
READ 3FFE
tINR
tRC
ADDRESSL
R/WL
INTL
OEL
ADDRESSR
R/WR
INTR
ADDRESSR
R/W
R
INTR
OER
ADDRESSL
R/WL
INTR
tINS
tHA
tINS
(7FFF for CY7C057V)
(7FFE for CY7C057V)
[45]
[46]
[46]
[46]
[45]
[46]
CE0L, CE1L
CE0R, CE1R
CE0R, CE1R
CE0L, CE1L
CHIP SELECT VALID
CHIP SELECT VALID
CHIP SELECT VALID
CHIP SELECT VALID
Right Side Clears INTR:
[+] Feedback
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E Page 18 of 26
Architecture
The CY7C056V and CY7C057V consist of an array of 16K and
32K words of 36 bits each of dual-port RAM cells, I/O and
address lines, and control signals (CE0/CE1, OE, R/W). These
control pins permit independent access for reads or writes to any
location in memory. To handle simultaneous writes/reads to the
same location, a BUSY pin is provided on each port. Two
Interrupt (INT) pins can be utilized for port-to-port
communication. Two Semaphore (SEM) control pins are used for
allocating shared resources. With the M/S pin, the devices can
function as a master (BUSY pins are outputs) or as a slave
(BUSY pins are inputs). The devices also have an automatic
power-down feature controlled by CE0/CE1. Each port is
provided with its own Output Enable control (OE), which allows
data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE0 and CE1 pins (see Write Cycle No. 2
waveform). Required inputs for non-contention operations are
summarized in Table 1. If a location is being written to by one port
and the opposite port attempts to read that location, a port-to-port
flowthrough delay must occur before the data is read on the
output; otherwise the data read is not deterministic. Data will be
valid on the port tDDD after the data is presented on the other
port.
Read Operation
When reading the device, the user must assert both the OE and
CE[3] pins. Data will be available tACE after CE or tDOE after OE
is asserted. If the user wishes to access a semaphore flag, then
the SEM pin must be asserted instead of the CE[3] pin, and OE
must also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (3FFF for the CY7C056V,
7FFF for the CY7C057V) is the mailbox for the right port and the
second-highest memory location (3FFE for the CY7C056V,
7FFE for the CY7C057V) is the mailbox for the left port. When
one port writes to the other port’s mailbox, an interrupt is
generated to the owner. The interrupt is reset when the owner
reads the contents of the mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.The operation of the interrupts and their interaction with
Busy are summarized in Tabl e 2 .
Busy
The CY7C056V and CY7C057V provide on-chip arbitration to
resolve simultaneous memory location access (contention). If
both ports’ Chip Enables are asserted and an address match
occurs within tPS of each other, the busy logic will determine
which port has access. If tPS is violated, one port will definitely
gain permission to the location, but it is not predictable which port
will get that permission. BUSY will be asserted tBLA after an
address match or tBLC after CE is taken LOW.
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the slave.
This will allow the device to interface to a master device with no
external components. Writing to slave devices must be delayed
until after the BUSY input has settled (tBLC or tBLA), otherwise,
the slave chip may begin a write cycle during a contention
situation. When tied HIGH, the M/S pin allows the device to be
used as a master and, therefore, the BUSY line is an output.
BUSY can then be used to send the arbitration outcome to a
slave.
Semaphore Operation
The CY7C056V and CY7C057V provide eight semaphore
latches, which are separate from the dual-port memory locations.
Semaphores are used to reserve resources that are shared
between the two ports. The state of the semaphore indicates that
a resource is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a zero to a semaphore
location. The left port then verifies its success in setting the latch
by reading it. After writing to the semaphore, SEM or OE must
be deasserted for tSOP before attempting to read the semaphore.
The semaphore value will be available tSWRD + tDOE after the
rising edge of the semaphore write. If the left port was successful
(reads a 0), it assumes control of the shared resource, otherwise
(reads a 1) it assumes the right port has control and continues to
poll the semaphore. When the right side has relinquished control
of the semaphore (by writing a 1), the left side will succeed in
gaining control of the semaphore. If the left side no longer
requires the semaphore, a one is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches. For
normal semaphore access, CE[3] must remain HIGH during SEM
LOW. A CE active semaphore access is also available. The
semaphore may be accessed through the right port with
CE0R/CE1R active by asserting the Bus Match Select (BM) pin
LOW and asserting the Bus Size Select (SIZE) pin HIGH. The
semaphore may be accessed through the left port with
CE0L/CE1L active by asserting all B0–3 Byte Select pins HIGH.
A0–2 represents the semaphore address. OE and R/W are used
in the same manner as a normal memory access. When writing
or reading a semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a 1 will appear
at the same semaphore address on the right port. That
semaphore can now only be modified by the port showing 0 (the
left port in this case). If the left port now relinquishes control by
writing a 1 to the semaphore, the semaphore will be set to 1 for
both ports. However, if the right port had requested the
semaphore (written a 0) while the left port had control, the right
port would immediately own the semaphore as soon as the left
port released it. Ta bl e 3 shows sample semaphore operations.
[+] Feedback
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E Page 19 of 26
Table 1. Non-Contending Read/Write[47]
Inputs Outputs
CE R/W OE B0, B1, B2, B3SEM I/O0–I/O35 Operation
H X X X H High Z Deselected: Power-down
X X X All H HHigh Z Deselected: Power-down
L L X H/L H Data in and High Z Write to selected bytes only
L L X All L HData in Write to all bytes
L H L H/L H Data out and High Z Read selected bytes only
L H L All L HData out Read all bytes
X X H X X High Z Outputs disabled
H H L X L Data out Read data in semaphore flag
X H L All H LData out Read data in semaphore flag
H X X L Data in Write DIN0 into semaphore flag
X X All H LData in Write DIN0 into semaphore flag
L X X Any L LNot allowed
Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH)[47, 48]
Left Port Right Port
Function R/WLCELOELA0L–13L INTLR/WRCEROERA0R–13R INTR
Set right INTR flag L L X 3FFF X X X X X L[50]
Reset right INTR flag X X X X X X L L 3FFF H[49]
Set left INTL flag X X X X L[49] L L X 3FFE X
Reset left INTL flag X L L 3FFE H[50] X X X X X
Table 3. Semaphore Operation Example
Function I/O0–I/O8 Left I/O0–I/O8 Right Status
No action 1 1 Semaphore free
Left port writes 0 to Semaphore 0 1 Left port has semaphore token
Right port writes 0 to Semaphore 0 1 No change. Right side has no write access to
Semaphore
Left port writes 1 to Semaphore 1 0 Right port obtains semaphore token
Left port writes 0 to Semaphore 1 0 No change. Left port has no write access to semaphore
Right port writes 1 to Semaphore 0 1 Left port obtains semaphore token
Left port writes 1 to Semaphore 1 1 Semaphore free
Right port writes 0 to Semaphore 1 0 Right port has semaphore token
Right port writes 1 to Semaphore 1 1 Semaphore free
Left port writes 0 to Semaphore 0 1 Left port has semaphore token
Left port writes 1 to Semaphore 1 1 Semaphore free
Notes
47. CE is LOW when CE0 VIL and CE1 VIH.
48. A0L–14L and A0R–14R, 7FFF/7FFE for the CY7C057V.
49. If BUSYR=L, then no change.
50. If BUSYL=L, then no change.
[+] Feedback
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E Page 20 of 26
When reading a semaphore, data lines 0 through 8 output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore will definitely be
obtained by one side or the other, but there is no guarantee which
side will control the semaphore.
When reading a semaphore, data lines 0 through 8 output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore will definitely be
obtained by one side or the other, but there is no guarantee which
side will control the semaphore.
When reading a semaphore, data lines 0 through 8 output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore will definitely be
obtained by one side or the other, but there is no guarantee which
side will control the semaphore.
Bus Match Operation
The right port of the CY7C057V 32Kx36 dual-port SRAM can be
configured in a 36-bit long-word, 18-bit word, or 9-bit byte format
for data I/O. The data lines are divided into four lanes, each
consisting of 9 bits (byte-size data lines).
The bus match select (BM) pin works with bus size select (SIZE)
to select bus width (long-word, word, or byte) for the right port of
the dual-port device. The data sequencing arrangement is
selected using the word address (WA) and byte address (BA)
input pins. A logic “0” applied to both the bus match select (BM)
Notes
51. BM and SIZE must be configured one clock cycle before operation is guaranteed.
52. In x36 mode WA and BA pins are “Don’t Care.”
53. In x18 mode BA pin is a “Don’t Care.”
54. DQ represents data output of the chip.
Right Port Configuration[51, 52, 53]
BM SIZE Configuration I/O Pins Used
0 0 x36 (standard) I/O0–35
0 1 x36 (CE active SEM mode) I/O0–35
1 0 x18 I/O0–17
1 1 x9 I/O0–8
Right Port Operation
Configuration WA BA Data Accessed[54] I/O Pins Used
x36 X X DQ0–35 I/O0–35
x18 0 X DQ0–17 I/O0–17
x18 1 X DQ18–35 I/O0–17
x9 0 0 DQ0–8 I/O0–8
x9 0 1 DQ9–17 I/O0–8
x9 1 0 DQ18–26 I/O0–8
x9 1 1 DQ27–35 I/O0–8
Left Port Operation
Control Pin Effect
B0 I/O0–8 Byte control
B1 I/O9–17 Byte control
B2 I/O18–26 Byte control
B3 I/O27–35 Byte control
9
/
BA WA
CY7C056V
CY7C057V
16K/32Kx36
Dual Port
BM SIZE
9
/
9
/
9
/x9, x18, x36
/
BUS MODE
x36
/
[+] Feedback
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E Page 21 of 26
pin and to the bus size select (SIZE) pin will select long-word
(36-bit) operation. A logic “1” level applied to the bus match
select (BM) pin will enable either byte or word bus width
operation on the right port I/Os depending on the logic level
applied to the SIZE pin. The level of bus match select (BM) must
be static throughout device operation.
Normally, the bus size select (SIZE) pin would have no
standard-cycle application when BM = LOW and the device is in
long-word (36-bit) operation. A “special” mode has been added
however to disable ALL right port I/Os while the chip is active.
This I/O disable mode is implemented when SIZE is forced to a
logic “1” while BM is at a logic “0”. It allows the bus-matched port
to support a chip enable “Don’t care” semaphore read/write
access similar to that provided on the left port of the device when
all Byte Select (B0–3) control inputs are deselected.
The bus size select (SIZE) pin selects either a byte or word data
arrangement on the right port when the bus match select (BM)
pin is HIGH. A logic “1” on the SIZE pin when the BM pin is HIGH
selects a byte bus (9-bit) data arrangement). A logic “0” on the
SIZE pin when the BM pin is HIGH selects a word bus (18-bit)
data arrangement. The level of the bus size select (SIZE) must
also be static throughout normal device operation.
Long-Word (36-bit) Operation
Bus match select (BM) and bus size select (SIZE) set to a logic
“0” will enable standard cycle long-word (36-bit) operation. In this
mode, the right port’s I/O operates essentially in an identical
fashion as does the left port of the dual-port SRAM. However no
byte select control is available. All 36 bits of the long-word are
shifted into and out of the right port’s I/O buffer stages. All read
and write timing parameters may be identical with respect to the
two data ports. When the right port is configured for a long-word
size, word address (WA), and byte Address (BA) pins have no
application and their inputs are “Don’t Care”[55] for the external
user.
Word (18-bit) Operation
Word (18-bit) bus sizing operation is enabled when bus match
select (BM) is set to a logic “1” and the bus sze select (SIZE) pin
is set to a logic “0.” In this mode, 18 bits of data are ported
through I/O0R–17R. The level applied to the word address (WA)
pin during word bus size operation determines whether the
most-significant or least-significant data bits are ported through
the I/O0R–17R pins in an Upper word/Lower word select fashion
(note that when the right port is configured for word size
operation, the Byte Address pin has no application and its input
is “Don’t care”[55]).
Device operation is accomplished by treating the WA pin as an
additional address input and using standard cycle address and
data setup/hold times. When transferring data in word (18-bit)
bus match format, the unused I/O18R–35R pins are three-stated.
Byte (9-bit) Operation
Byte (9-bit) bus sizing operation is enabled when bus match
select (BM) is set to a logic “1” and the bus size select (SIZE) pin
is set to a logic “1.” In this mode, data is ported through I/O0R–8R
in four groups of 9-bit bytes. A particular 9-bit byte group is
selected according to the levels applied to the word address
(WA) and byte address (BA) input pins.
Device operation is accomplished by treating the word address
(WA) pin and the byte address (BA) pins as additional address
inputs having standard cycle address and data set-up/hold
times. When transferring data in byte (9-bit) bus match format,
the unused I/O9R–35R pins are three-stated.
Note
55. Even though a logic level applied to a “Don’t Care” input will not change the logical operation of the dual-port, inputs that are temporarily a “Don’t Care” (along with
unused inputs) must not be allowed to float. They must be forced either HIGH or LOW.
I/Os Rank WA BA
I/O27R–35R Upper-MSB 1 1
I/O18R–26R Lower-MSB 1 0
I/O9R–17R Upper-MSB 0 1
I/O0R–8R Lower-MSB 0 0
[+] Feedback
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E Page 22 of 26
Ordering Information
16K x 36 3.3 V Asynchronous Dual Port SRAM
32K x 36 3.3 V Asynchronous Dual Port SRAM
Ordering Code Definition
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
15 CY7C056V-15AXC A144 144-Pin Pb-free Thin Quad Flat Pack Commercial
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
12 CY7C057V-12AC A144 144-Pin Thin Quad Flat Pack Commercial
CY7C057V-12AXC A144 144-Pin Pb-free Thin Quad Flat Pack
15 CY7C057V-15AXC A144 144-Pin Pb-free Thin Quad Flat Pack Commercial
CY7C057V-15AXI A144 144-Pin Pb-free Thin Quad Flat Pack Industrial
CY7C057V-15BBI BB172 172-Ball Ball Grid Array (BGA) Industrial
CY7C057V-15BBXC BB172 172-Ball Ball Grid Array (BGA)
CY 7C XXX
Company ID: CY = Cypress
7C = Dual Port SRAM
Width: 05=x36
Operating Range
C = Commercial I = Industrial
X
Depth: 6=16K or 7=32K
XX X
Package: A=TQFP or BB=FBGA
0
Speed Grade : 12ns/15ns
X
X : Pb free (RoHS Compliant)
X
X = V: 3.3 V
[+] Feedback
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E Page 23 of 26
Package Diagrams
Figure 3. 144-Pin Plastic Thin Quad Flat Pack (TQFP) A144
51-85047 *C
[+] Feedback
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E Page 24 of 26
FLEx36 is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
Acronyms Document Conventions
Units of Measure
Package Diagrams (continued)
Figure 4. 172-Ball FBGA (15 x 15 x 1.25 mm) BB172
51-85114 *C
Acronym Description
CMOS complementary metal oxide semiconductor
TQFP thin quad plastic flatpack
I/O input/output
SRAM static random access memory
BGA ball grid array
Symbol Unit of Measure
ns nano seconds
VVolts
µA micro Amperes
mA milli Amperes
Ohms
mV milli Volts
MHz Mega Hertz
pF pico Farad
WWatts
°C degree Celcius
[+] Feedback
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E Page 25 of 26
Document History Page
Document Title: CY7C056V/CY7C057V 3.3 V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static RAM
Document Number: 38-06055
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 110214 12/16/01 SZV Change from Spec number: 38-00742 to 38-06055
*A 122305 12/27/02 RBI Power up requirements added to Maximum Ratings Information
*B 393770 See ECN YIM Added Pb-Free Logo
Added Pb-Free parts to ordering information:
CY7C056V-12AXC, CY7C056V-15AXC, CY7C057V-12AXC,
CY7C057V-15AXC, CY7CO57V-15AXI
*C 2897217 03/22/2010 RAME Updated Ordering Information
Updated Package Diagrams
*D 3093365 11/25/2010 ADMU Removed part CY7C057V-15BBC
Added part CY7C057V-15AXI
Updated datasheet as per new template
Added Acronyms and Units of Measure table
Added Ordering Code Definition
Updated all footnotes.
*E 3210221 03/30/2011 ADMU Removed parts CY7C056V-15AC and CY7C057V-12BBC from the Ordering
Information table.
[+] Feedback
Document #: 38-06055 Rev. *E Revised March 30, 2011 Page 26 of 26
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C056V
CY7C057V
© Cypress Semiconductor Corporation, 2008-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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