March 2007 Rev 4 1/39
39
L6563
L6563A
Advanced transition-mode PFC controller
Features
■Very precise adjustable output overvoltage
protection
■Tracking boost function
■Protection against feedback loop failure
(Latched shutdown)
■Interface for cascaded converter's PWM
controller
■Input voltage feedforward (1/V
2
)
■Inductor saturation detection (L6563 only)
■Remote ON/OFF control
■Low (≤90µA) start-up current
■5mA max. quiescent current
■1.5% (@ T
J
= 25°C) internal reference voltage
■-600/+800 mA totem pole gate driver with
active pull-down during UVLO
■SO14 package
Applications
PFC pre-regulators for:
■HI-END AC-DC adapter/charger
■Desktop PC, server, WEB server
■IEC61000-3-2 OR JEIDA-MITI compliant
SMPS, in excess of 350W
Table 1. Device summary
Part number Package Packaging
L6563 SO-14 Tube
L6563TR SO-14 Tape & Reel
L6563A SO-14 Tube
L6563ATR SO-14 Tape & Reel
SO-14
www.st.com
Figure 1. Block diagram
+
-
VREF2
Vb i a s
( INTERNA L SUPPLY BUS)
+
-
2.5V
R1
R2
+-
-
+
ZERO CURRENT
DETECTOR
VCC
14
123
4
ZCD
V
CC
INV COMP MULT
CS
GD
13
11
G
ND 12
MULTIP LIE R
R
S
Q
STARTER
1.7V
+-
6
TBO
+
-
2.5V
PFC_OK
7
1:1
CURRENT
MIRROR
+
-
RUN
10
0.52V
0.6V
PWM_LATCH
8
5
VFF
LEADING-EDGE
BLANKING
1:1
BUFFER from
VFF
1.4V
0.7V
PWM_STOP
9
Vbi a s
UVLO
COMP AR ATOR
+
-
0.2V
0.26V
15 V
SAT
DISABLE LATCH
UVLO
3V
SAT
Ideal diode
1 / V 2
Starter
OFF
Driver
Q
TRACKING
BOOST
ON/OFF CONTROL
(BROWNOUT DETECTION)
LIN E VOLTAGE
FEEDFORWARD
INDUCTOR
SATURATION
DETECTION
( not in L6563A )
FEEDBACK
FAILURE
PROTECTION
VOLTAGE
REGULATOR
Voltage
references
Contents L6563 - L6563A
2/39
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Feedback Failure Protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Voltage Feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5 Tracking Boost function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.6 Inductor saturation detection (L6563 only) . . . . . . . . . . . . . . . . . . . . . . . . 27
6.7 Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . . 28
6.8 Summary of L6563/A idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7 Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
L6563 - L6563A Description
3/39
1 Description
The device is a current-mode PFC controller operating in Transition Mode (TM). Based on
the core of a standard TM PFC controller, it offers improved performance and additional
functions.
The highly linear multiplier, along with a special correction circuit that reduces crossover
distortion of the mains current, allows wide-range-mains operation with an extremely low
THD even over a large load range.
The output voltage is controlled by means of a voltage-mode error amplifier and a precise
(1.5% @T
J
= 25°C) internal voltage reference. The stability of the loop and the transient
response to sudden mains voltage changes are improved by the voltage feedforward
function (1/V
2
correction).
Additionally, the IC provides the option for tracking boost operation (where the output
voltage is changed tracking the mains voltage). The device features extremely low
consumption (≤ 90 µA before start-up and ≤ 5 mA running).
In addition to an effective two-step OVP that handles normal operation overvoltages, the IC
provides also a protection against feedback loop failures or erroneous output voltage
setting.
In the L6563 a protection is added to stop the PFC stage in case the boost inductor
saturates. This function is not included in the L6563A. This is the only difference between
the two part numbers.
An interface with the PWM controller of the DC-DC converter supplied by the PFC pre-
regulator is provided: the purpose is to stop the operation of the converter in case of
anomalous conditions for the PFC stage (feedback loop failure, boost inductor's core
saturation) in the L6563 only and to disable the PFC stage in case of light load for the DC-
DC converter, so as to make it easier to comply with energy saving norms (Blue Angel,
EnergyStar, Energy2000, etc.). The device includes disable functions suitable for remote
ON/OFF control both in systems where the PFC pre-regulator works as a master and in
those where it works as a slave.
The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable
to drive high current MOSFETs or IGBTs. This, combined with the other features and the
possibility to operate with the proprietary Fixed-Off-Time control, makes the device an
excellent low-cost solution for EN61000-3-2 compliant SMPS in excess of 350W.
Figure 2. Typical system block diagram
V
inac
V
outdc
PWM is turned off in case of PFC’s
anomalous operation for safety
PFC can be turned off at light
load to ease compliance with
energy saving regulations.
L6563
L6563A
PWM or
Resonant
CONTROLLER
PFC PRE-REGULATOR DC-DC CONVERTER
Description L6563 - L6563A
4/39
1.1 Pin connection
Figure 3. Pin connection (top view)
1.2 Pin description
INV
COMP
MULT
CS
VFF
TBO
PFC_OK
Vcc
GD
GND
ZCD
RUN
PWM_STOP
PWM_LATCH
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Table 2. Pin description
Pin N° Name Description
1INV
Inverting input of the error amplifier. The information on the output voltage of the PFC pre-
regulator is fed into the pin through a resistor divider.
The pin normally features high impedance but, if the tracking boost function is used, an
internal current generator programmed by TBO (pin 6) is activated. It sinks current from the
pin to change the output voltage so that it tracks the mains voltage.
2COMP
Output of the error amplifier. A compensation network is placed between this pin and INV
(pin 1) to achieve stability of the voltage control loop and ensure high power factor and low
THD.
3MULT
Main input to the multiplier. This pin is connected to the rectified mains voltage via a
resistor divider and provides the sinusoidal reference to the current loop. The voltage on
this pin is used also to derive the information on the RMS mains voltage.
4CS
Input to the PWM comparator. The current flowing in the MOSFET is sensed through a
resistor, the resulting voltage is applied to this pin and compared with an internal reference
to determine MOSFET’s turn-off.
A second comparison level at 1.7V detects abnormal currents (e.g. due to boost inductor
saturation) and, on this occurrence, shuts down the IC, reduces its consumption almost to
the start-up level and asserts PWM_LATCH (pin 8) high. This function is not present in the
L6563A.
5VFF
Second input to the multiplier for 1/V2 function. A capacitor and a parallel resistor must be
connected from the pin to GND. They complete the internal peak-holding circuit that
derives the information on the RMS mains voltage. The voltage at this pin, a DC level equal
to the peak voltage at pin MULT (pin 3), compensates the control loop gain dependence on
the mains voltage. Never connect the pin directly to GND.
L6563 - L6563A Description
5/39
6TBO
Tracking Boost function. This pin provides a buffered VFF voltage. A resistor connected
between this pin and GND defines a current that is sunk from pin INV (pin 1). In this way,
the output voltage is changed proportionally to the mains voltage (tracking boost). If this
function is not used leave this pin open.
7PFC_OK
PFC pre-regulator output voltage monitoring/disable function. This pin senses the output
voltage of the PFC pre-regulator through a resistor divider and is used for protection
purposes. If the voltage at the pin exceeds 2.5V the IC is shut down, its consumption goes
almost to the start-up level and this condition is latched. PWM_LATCH pin is asserted high.
Normal operation can be resumed only by cycling the Vcc. This function is used for
protection in case the feedback loop fails.
If the voltage on this pin is brought below 0.2V the IC is shut down and its consumption is
considerably reduced. To restart the IC the voltage on the pin must go above 0.26V. If these
functions are not needed, tie the pin to a voltage between 0.26 and 2.5 V.
8PWM_LATCH
Output pin for fault signaling. During normal operation this pin features high impedance. If
either a voltage above 2.5V at PFC_OK (pin 7) or a voltage above 1.7V on CS (pin 4) of
L6563 is detected the pin is asserted high. Normally, this pin is used to stop the operation
of the DC-DC converter supplied by the PFC pre-regulator by invoking a latched disable of
its PWM controller. If not used, the pin will be left floating.
9PWM_STOP
Output pin for fault signaling. During normal operation this pin features high impedance. If
the IC is disabled by a voltage below 0.5V on RUN (pin 10) the voltage at the pin is pulled
to ground. Normally, this pin is used to temporarily stop the operation of the DC-DC
converter supplied by the PFC pre-regulator by disabling its PWM controller. If not used,
the pin will be left floating.
10 RUN
Remote ON/OFF control. A voltage below 0.52V shuts down (not latched) the IC and
brings its consumption to a considerably lower level. PWM_STOP is asserted low. The IC
restarts as the voltage at the pin goes above 0.6V. Connect this pin to VFF (pin 5) either
directly or through a resistor divider to use this function as brownout (AC mains
undervoltage) protection, tie to INV (pin 1) if the function is not used.
11 ZCD Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-
going edge triggers MOSFET’s turn-on.
12 GND Ground. Current return for both the signal part of the IC and the gate driver.
13 GD
Gate driver output. The totem pole output stage is able to drive power MOSFET’s and
IGBT’s with a peak current of 600 mA source and 800 mA sink. The high-level voltage of
this pin is clamped at about 12V to avoid excessive gate voltages.
14 VCC Supply Voltage of both the signal part of the IC and the gate driver.
Table 2. Pin description (continued)
Pin N° Name Description
Absolute maximum ratings L6563 - L6563A
6/39
2 Absolute maximum ratings
3 Thermal data
Table 3. Absolute maximum ratings
Symbol Pin Parameter Value Unit
VCC 14 IC supply voltage (Icc = 20mA) self-limited V
--- 2, 4 to 6, 8
to 10 Analog inputs & outputs -0.3 to 8 V
--- 1, 3, 7 Max. pin voltage (Ipin = 1 mA) Self-limited V
IPWM_STOP 10 Max. sink current 3 mA
I
ZCD
9 Zero current detector max. current -10 (source)
10 (sink) mA
PTOT Power dissipation @TA = 50°C 0.75 W
TJJunction temperature operating range -25 to 150 °C
TSTG Storage temperature -55 to 150 °C
Table 4. Thermal data
Symbol Parameter Value Unit
RthJA Maximum thermal resistance junction-ambient 120 °C/W
L6563 - L6563A Electrical characteristics
7/39
4 Electrical characteristics
Table 5. Electrical characteristics
( -25°C < T
J
< +125°C, V
CC
= 12V, C
o
= 1nF between pin GD and GND, C
FF
=1µF between pin V
FF
and GND; unless otherwise specified)
Symbol Parameter Test condition Min Typ Max Unit
Supply voltage
Vcc Operating range After turn-on 10.3 22 V
VccOn Turn-on threshold (1) 11 12 13 V
VccOff Turn-off threshold (1) 8.7 9.5 10.3 V
Hys Hysteresis 2.3 2.7 V
VZZener Voltage Icc = 20 mA 22 25 28 V
Supply current
Istart-up Start-up current Before turn-on, Vcc = 10V 50 90 µA
IqQuiescent current After turn-on 3 5 mA
ICC Operating supply current @ 70kHz 3.8 5.5 mA
I
qdis
Idle state quiescent
Current
Latched by PFC_OK > Vthl or
Vcs > VCSdis 180 250 µA
Disabled by PFC_OK < Vth or
RUN < V
DIS
1.5 2.2 mA
IqQuiescent current During static/dynamic OVP 2 3 mA
Multiplier input
IMULT Input bias current VMULT = 0 to 3 V -0.2 -1 µA
VMULT Linear operation range 0 to 3 V
VCLAMP Internal clamp level IMULT = 1 mA 99.5 V
Output max. slope VMULT=0 to 0.5V, VFF=0.8V
VCOMP = Upper clamp 2.2 2.34 V/V
KMGain (3) VMULT = 1 V, VCOMP= 4 V,
VVFF = VMULT
0.375 0.45 0.525 V
Error amplifier
VINV Voltage feedback input
threshold
T
J
= 25 °C 2.465 2.5 2.535
V
10.3 V < Vcc < 22 V (2) 2.44 2.56
Line regulation Vcc = 10.3 V to 22V 2 5 mV
IINV Input bias current TBO open, VINV = 0 to 4 V -0.2 -1 µA
Vcs
∆
VMULT
∆
---------------------
Electrical characteristics L6563 - L6563A
8/39
Symbol Parameter Test condition Min Typ Max Unit
VINVCLAMP Internal clamp level IINV = 1 mA 99.5 V
Gv Voltage gain Open loop 60 80 dB
GB Gain-bandwidth product 1 MHz
ICOMP
Source current VCOMP = 4V, VINV = 2.4 V -2 -3.5 -5 mA
Sink current VCOMP = 4V, VINV = 2.6 V 2.5 4.5 mA
VCOMP
Upper clamp voltage ISOURCE = 0.5 mA 5.7 6.2 6.7 V
Lower clamp voltage I
SINK
= 0.5 mA (2) 2.12.252.4 V
Current sense comparator
ICS Input bias current VCS = 0 -1 µA
t
LEB
Leading edge blanking 100 200 300 ns
td
(H-L)
Delay to output 120 ns
VCSclamp Current sense reference
clamp
VCOMP = Upper clamp,
VVFF = VMULT =0.5V 1.0 1.08 1.16 V
Vcsoffset Current sense offset
VMULT = 0, VVFF = 3V 25
mV
VMULT = 3V, VVFF = 3V 5
VCSdis Ic latch-off level (L6563
only) (2) 1.6 1.7 1.8 V
Output overvoltage
IOVP Dynamic OVP triggering
current 17 20 23 µA
Hys Hysteresis (4) 15 µA
Static OVP threshold (2) 2 2.15 2.3 V
Voltage feedforward
VVFF Linear operation range RFF = 47 kΩ to GND 0.5 3 V
∆VDropout
V
MULTpk
-V
VFF
20 mV
Table 5. Electrical characteristics (continued)
( -25°C < T
J
< +125°C, V
CC
= 12V, C
o
= 1nF between pin GD and GND, C
FF
=1µF between pin V
FF
and GND; unless otherwise specified)
L6563 - L6563A Electrical characteristics
9/39
Symbol Parameter Test condition Min Typ Max Unit
Zero current detector
VZCDH Upper clamp voltage IZCD = 2.5 mA 5.0 5.7 V
VZCDL Lower clamp voltage IZCD = - 2.5 mA -0.3 0 0.3 V
VZCDA Arming voltage
(positive-going edge) (4) 1.4 V
VZCDT Triggering voltage
(negative-going edge) (4) 0.7 V
IZCDb Input bias current VZCD = 1 to 4.5 V 1µA
IZCDsrc Source current capability -2.5 mA
IZCDsnk Sink current capability 2.5 mA
Tracking boost function
∆VDropout voltage
V
VFF
- V
TBO
ITBO = 0.25 mA 20 mV
ITBO Linear operation 0 0.25 mA
IINV - ITBO current
mismatch ITBO = 25 µA to 0.25 mA -3.5 3.5 %
VTBOclamp Clamp voltage VVFF = 4V (2) 2.9 3 3.1 V
PFC_OK
V
thl
Latch-off threshold Voltage rising (2) 2.4 2.5 2.6 V
V
th
Disable threshold Voltage falling (2) 0.2 V
VEN Enable threshold Voltage rising (2) 0.26 V
IPFC_OK Input bias current VPFC_OK = 0 to 2.5V -0.1 -1 µA
Vclamp Clamp voltage IPFC_OK = 1 mA 99.5 V
PWM_LATCH
I
leak
Low level leakage
current VPWM_LATCH=0 -1 µA
VHHigh level IPWM_LATCH = -0.5 mA 3.7 V
PWM_STOP
I
leak
High level leakage
current VPWM_STOP = 6V 1µA
VLLow level IPWM_STOP = 0.5 mA 1V
Vclamp Clamp voltage IPFC_OK = 2 mA 99.5 V
Table 5. Electrical characteristics (continued)
( -25°C < T
J
< +125°C, V
CC
= 12V, C
o
= 1nF between pin GD and GND, C
FF
=1µF between pin V
FF
and GND; unless otherwise specified)
Electrical characteristics L6563 - L6563A
10/39
(1), (2) Parameters tracking each other
(3) The multiplier output is given by:
(4) Parameters guaranteed by design, functionality tested in production.
Symbol Parameter Test condition Min Typ Max Unit
Run function
IRUN Input bias current VRUN = 0 to 3 V -1 µA
VDIS Disable threshold Voltage falling (2) 0.5 0.52 0.54 V
VEN Enable threshold Voltage rising (2) 0.56 0.6 0.64 V
Start timer
tSTART Start timer period 75 150 300 µs
Gate driver
VOHdrop Dropout voltage
IGDsource = 20 mA 22.6V
IGDsource = 200 mA 2.5 3 V
VOLdrop IGDsink = 200 mA 12V
tfCurrent fall time 30 70 ns
trCurrent rise time 40 80 ns
VOclamp Output clamp voltage IGDsource = 5mA; Vcc = 20V 10 12 15 V
UVLO saturation Vcc=0 to VccOn, Isink=10mA 1.1 V
Table 5. Electrical characteristics (continued)
( -25°C < T
J
< +125°C, V
CC
= 12V, C
o
= 1nF between pin GD and GND, C
FF
=1µF between pin V
FF
and GND; unless otherwise specified)
VCS KM
VMULT VCOMP 2.5–()⋅
VVFF
2
-------------------------------------------------------------
⋅=
L6563 - L6563A Typical electrical performance
11/39
5 Typical electrical performance
Figure 4. Supply current vs supply voltage Figure 5. VCC Zener voltage vs TJ
Figure 6. IC consumption vs TJFigure 7. Feedback reference vs TJ
Figure 8. Start-up & UVLO vs TJFigure 9. E/A output clamp levels vs TJ
Vcc(V)
0
0.005
0.01
0.05
0.1
0.5
1
5
10
Icc
(mA)
0 5 10 15 20
Co = 1nF
f = 70 kHz
Tj= 25°C
25
Vcc(V)
0
0.005
0.01
0.05
0.1
0.5
1
5
10
Icc
(mA)
0 5 10 15 20
Co = 1nF
f = 70 kHz
Tj= 25°C
25
Tj (°C)
Vccz(pin 14)
(V)
-50 0 50 100 150
22
23
24
25
26
27
28
Tj (°C)
Vccz(pin 14)
(V)
-50 0 50 100 150
22
23
24
25
26
27
28
-50 0 50 100 150
0.02
0.05
0.1
0.2
0.5
1
2
5
10
Icc
(mA)
Operating
Quiescent
Disabled or
during OVP
Before start-up
Vcc = 12 V
Co = 1 nF
f = 70 kHz
Tj (°C)
Latched off
-50 0 50 100 150
0.02
0.05
0.1
0.2
0.5
1
2
5
10
Icc
(mA)
Operating
Quiescent
Disabled or
during OVP
Before start-up
Vcc = 12 V
Co = 1 nF
f = 70 kHz
Tj (°C)
Latched off
VREF
(V)
-50 0 50 100 150
2.4
2.45
2.5
2.55
2.6
Vcc = 12 V
Tj (°C)
(pin 1)
VREF
(V)
-50 0 50 100 150
2.4
2.45
2.5
2.55
2.6
Vcc = 12 V
Tj (°C)
(pin 1)
Tj (°C)
VCC-ON
(V)
VCC-OFF
(V)
-50 0 50 100 150
9
9.5
10
10.5
11
11.5
12
12.5
Tj (°C)
VCC-ON
(V)
VCC-OFF
(V)
-50 0 50 100 150
9
9.5
10
10.5
11
11.5
12
12.5
Tj (°C)
VCOMP (pin 2)
(V)
-50 0 50 100 150
1
2
3
4
5
6
7
Upper clamp
Lower clamp
Vcc = 12 V
Tj (°C)
VCOMP (pin 2)
(V)
-50 0 50 100 150
1
2
3
4
5
6
7
Upper clamp
Lower clamp
Vcc = 12 V
Typical electrical performance L6563 - L6563A
12/39
Figure 10. Static OVP level vs TJFigure 11. Vcs clamp vs TJ
Figure 12. Dynamic OVP current vs TJ
(normalized value)
Figure 13. Current-sense offset vs
mains voltage phase angle
Figure 14. Delay-to-output vs TJFigure 15. Ic latch-off level on current sense vs
TJ (L6563 only)
Tj (°C)
VCOMP (pin 2)
(V)
-50 0 50 100 150
2
2.1
2.2
2.3
2.4
2.5
Vcc = 12 V
Tj (°C)
VCOMP (pin 2)
(V)
-50 0 50 100 150
2
2.1
2.2
2.3
2.4
2.5
Vcc = 12 V
Tj (°C)
VCSx (pin 4)
(V)
-50 0 50 100 150
1
1.1
1.2
1.3
1.4
1.5
Vcc = 12 V
VCOMP = Upper clamp
Tj (°C)
VCSx (pin 4)
(V)
-50 0 50 100 150
1
1.1
1.2
1.3
1.4
1.5
Vcc = 12 V
VCOMP = Upper clamp
IOVP
-50 0 50 100 150
80%
90%
100%
110%
120%
Vcc = 12 V
Tj (°C)
IOVP
-50 0 50 100 150
80%
90%
100%
110%
120%
Vcc = 12 V
Tj (°C) θ(
°)
VCSoffset (pin 4)
(mV)
0 0.628 1.256 1.884 2.512 3.14
0
5
10
15
20
25
30
Vcc = 12 V
Tj = 25 °
VMULT = 0 to 3V
VFF = 3V
VMULT = 0 to 0.7V
VFF = 0.7V
θ(
°)
VCSoffset (pin 4)
(mV)
0 0.628 1.256 1.884 2.512 3.14
0
5
10
15
20
25
30
Vcc = 12 V
Tj = 25 °
VMULT = 0 to 3V
VFF = 3V
VMULT = 0 to 0.7V
VFF = 0.7V
Tj (°C)
tD(H-L)
(ns)
-50 0 50 100 150
50
100
150
200
250
300
Vcc = 12 V
Tj (°C)
tD(H-L)
(ns)
-50 0 50 100 150
50
100
150
200
250
300
Vcc = 12 V
Tj (°C)
Vpin4
(V)
-50 0 50 100 150
1.0
1.2
1.4
1.6
1.8
2.0
Vcc = 12 V
Tj (°C)
Vpin4
(V)
-50 0 50 100 150
1.0
1.2
1.4
1.6
1.8
2.0
Vcc = 12 V
L6563 - L6563A Typical electrical performance
13/39
Figure 16. Multiplier characteristics @ VFF = 1V Figure 17. ZCD clamp levels vs TJ
Figure 18. Multiplier characteristics @ VFF = 3V Figure 19. ZCD source capability vs TJ
Figure 20. Multiplier gain vs TJFigure 21. VFF & TBO dropouts vs TJ
VMULT (pin 3) (V)
VCOMP (pin 2)
(V)
0 0.2 0.4 0.6 0.8 1 1.2
0
0.2
0.4
0.6
0.8
1
2.6
3.0
3.5
4.0
4.5
upper voltage
clamp
5.0
5.5
VCS (pin 4)
(V)
Vcc = 12 V
Tj = 25 °C
VMULT (pin 3) (V)
VCOMP (pin 2)
(V)
0 0.2 0.4 0.6 0.8 1 1.2
0
0.2
0.4
0.6
0.8
1
2.6
3.0
3.5
4.0
4.5
upper voltage
clamp
5.0
5.5
VCS (pin 4)
(V)
Vcc = 12 V
Tj = 25 °C
Tj (°C)
VZCD (pin 11)
(V)
-50 0 50 100 150
-1
0
1
2
3
4
5
6
7
Vcc = 12 V
IZCD= ±2.5 mA
Upper clamp
Lower clamp
Tj (°C)
VZCD (pin 11)
(V)
-50 0 50 100 150
-1
0
1
2
3
4
5
6
7
Vcc = 12 V
IZCD= ±2.5 mA
Upper clamp
Lower clamp
VMULT (pin 3) (V)
VCOMP (pin 2)
(V)
0 0.5 1 1.5 2 2.5 3 3.5
0
0.1
0.2
0.3
0.4
0.5
2.6
3.0
3.5
4.0
4.5
upper voltage
clamp
5.0
5.5
VCS (pin 4)
(V)
Vcc = 12 V
Tj = 25 °C
VMULT (pin 3) (V)
VCOMP (pin 2)
(V)
0 0.5 1 1.5 2 2.5 3 3.5
0
0.1
0.2
0.3
0.4
0.5
2.6
3.0
3.5
4.0
4.5
upper voltage
clamp
5.0
5.5
VCS (pin 4)
(V)
Vcc = 12 V
Tj = 25 °C
Tj (°C)
IZCDsrc
(mA)
-50 0 50 100 150
-8
-6
-4
-2
0
Vcc = 12 V
VZCD= lower clamp
Tj (°C)
IZCDsrc
(mA)
-50 0 50 100 150
-8
-6
-4
-2
0
Vcc = 12 V
VZCD= lower clamp
KM
Tj (°C)
-50 0 50 100 150
0
0.2
0.4
0.6
0.8
1
Vcc = 12 V
VCOMP =4 V
VMULT = VFF =1V
KM
Tj (°C)
-50 0 50 100 150
0
0.2
0.4
0.6
0.8
1
Vcc = 12 V
VCOMP =4 V
VMULT = VFF =1V
Tj (°C)
-50 0 50 100 150
-2
0
2
4
6
(mV)
Vpin5 - Vpin3
Vpin6 - Vpin5
Vcc = 12 V
Vpin3 = 2.9 V
Tj (°C)
-50 0 50 100 150
-2
0
2
4
6
(mV)
Vpin5 - Vpin3
Vpin6 - Vpin5
Vcc = 12 V
Vpin3 = 2.9 V
Typical electrical performance L6563 - L6563A
14/39
Figure 22. TBO current mismatch vs TJFigure 23. RUN thresholds vs TJ
Figure 24. TBO-INV current mismatch vs
TBO currents
Figure 25. PWM_LATCH high saturation vs TJ
Figure 26. TBO clamp vs TJFigure 27. PWM_STOP low saturation vs TJ
Tj (°C)
-50 0 50 100 150
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
I(INV)-I(TBO)
I(INV)
100·
ITBO = 25 µA
ITBO = 250 µA
Vcc = 12 V
Tj (°C)
-50 0 50 100 150
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
I(INV)-I(TBO)
I(INV)
100·
ITBO = 25 µA
ITBO = 250 µA
Vcc = 12 V
Tj (°C)
Vpin10
(V)
-50 0 50 100 150
0.0
0.2
0.4
0.6
0.8
1.0
Vcc = 12 V
ON
OFF
Tj (°C)
Vpin10
(V)
-50 0 50 100 150
0.0
0.2
0.4
0.6
0.8
1.0
Vcc = 12 V
ON
OFF
I(TBO)
0 100 200 300 400 500 600
-2.3
-2.2
-2.1
-2.0
-1.9
-1.8
-1.7
-1.6
Vcc = 12 V
Tj = 25 °C
I(INV)-I(TBO)
I(INV)
100·
I(TBO)
0 100 200 300 400 500 600
-2.3
-2.2
-2.1
-2.0
-1.9
-1.8
-1.7
-1.6
Vcc = 12 V
Tj = 25 °C
I(INV)-I(TBO)
I(INV)
100·
Tj (°C)
Vpin8
(V)
-50 0 50 100 150
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
Vcc = 12 V
Isource = 50 µA
Isource = 500 µA
Tj (°C)
Vpin8
(V)
-50 0 50 100 150
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
Vcc = 12 V
Isource = 50 µA
Isource = 500 µA
Tj (°C)
-50 0 50 100 150
2.5
2.75
3
3.25
3.5
Vcc = 12 V
Vpin3= 4 V
(V)
Vpin6
Tj (°C)
-50 0 50 100 150
2.5
2.75
3
3.25
3.5
Vcc = 12 V
Vpin3= 4 V
(V)
Vpin6
Tj (°C)
Vpin9
(V)
-50 0 50 100 150
0.0
1.0
2.0
3.0
4.0
5.0
Vcc = 12 V
Isink = 0.5 mA
0.50
0.40
0.30
0.20
0.10
0
Tj (°C)
Vpin9
(V)
-50 0 50 100 150
0.0
1.0
2.0
3.0
4.0
5.0
Vcc = 12 V
Isink = 0.5 mA
0.50
0.40
0.30
0.20
0.10
0
L6563 - L6563A Typical electrical performance
15/39
Figure 28. PFC_OK thresholds vs TJFigure 29. UVLO saturation vs TJ
Figure 30. Start-up timer vs TJFigure 31. Gate-drive output low saturation
Figure 32. Gate-drive clamp vs TJFigure 33. Gate-drive output high saturation
Tj (°C)
Vpin7
(V)
-50 0 50 100 150
0.1
0.2
0.3
0.5
1.0
2.0
3.0
Vcc = 12 V
ON
OFF
Latch-off
Tj (°C)
Vpin7
(V)
-50 0 50 100 150
0.1
0.2
0.3
0.5
1.0
2.0
3.0
Vcc = 12 V
ON
OFF
Latch-off
Tj (°C)
-50 0 50 100 150
0.5
0.6
0.7
0.8
0.9
1
1.1
Vcc = 0 V
Vpin15
(V)
Tj (°C)
-50 0 50 100 150
0.5
0.6
0.7
0.8
0.9
1
1.1
Vcc = 0 V
Vpin15
(V)
Tj (°C)
Tstart
(µs)
-50 0 50 100 150
100
110
120
130
140
150
Vcc = 12 V
Tj (°C)
Tstart
(µs)
-50 0 50 100 150
100
110
120
130
140
150
Vcc = 12 V
Vpin15 (V)
0 200 400 600 800 1,000
0
1
2
3
4
IGD(mA)
Tj = 25 °C
Vcc = 11 V
SINK
Vpin15 (V)
0 200 400 600 800 1,000
0
1
2
3
4
IGD(mA)
Tj = 25 °C
Vcc = 11 V
SINK
Tj (°C)
Vpin15clamp
(V)
-50 0 50 100 150
10
10.5
11
11.5
12
Vcc = 20 V
Tj (°C)
Vpin15clamp
(V)
-50 0 50 100 150
10
10.5
11
11.5
12
Vcc = 20 V
0 100 200 300 400 500 600 700
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
IGD (mA)
Tj = 25 °C
Vcc = 11 V
SOURCE
Vcc - 2.0
Vcc - 2.5
Vcc - 3.0
Vcc - 3.5
Vcc - 4.0
V
pin15 (V)
0 100 200 300 400 500 600 700
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
IGD (mA)
Tj = 25 °C
Vcc = 11 V
SOURCE
Vcc - 2.0
Vcc - 2.5
Vcc - 3.0
Vcc - 3.5
Vcc - 4.0
V
pin15 (V)
Application information L6563 - L6563A
16/39
6 Application information
6.1 Overvoltage protection
Normally, the voltage control loop keeps the output voltage VO of the PFC pre-regulator
close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider.
Neglecting the ripple components, under steady state conditions the current through R1
equals that through R2. Considering that the non-inverting input of the error amplifier is
internally biased at 2.5V, the voltage at pin INV will be 2.5V as well, then:
Equation 1
If the output voltage experiences an abrupt change ∆Vo the voltage at pin INV is kept at 2.5V
by the local feedback of the error amplifier, a network connected between pins INV and
COMP that introduces a long time constant. Then the current through R2 remains equal to
2.5/R2 but that through R1 becomes:
Equation 2
The difference current ∆I
R1
= I’
R1
- I’
R1
= ∆V
O
/R1 will flow through the compensation network
and enter the error amplifier (pin COMP). This current is monitored inside the IC and when it
reaches about 18 µA the output voltage of the multiplier is forced to decrease, thus reducing
the energy drawn from the mains. If the current exceeds 20 µA, the OVP is triggered
(Dynamic OVP), and the external power transistor is switched off until the current falls
approximately below 5 µA. However, if the overvoltage persists (e.g. in case the load is
completely disconnected), the error amplifier will eventually saturate low hence triggering an
internal comparator (Static OVP) that will keep the external power switch turned off until the
output voltage comes back close to the regulated value. The output overvoltage that is able
to trigger the OVP function is then:
Equation 3
∆
V
O
= R1 · 20 · 10
-6
IR2 IR1
2.5
R2
--------VO2.5–
R1
----------------------===
I'R1
VO2.5–VO
∆+
R1
----------------------------------------=
L6563 - L6563A Application information
17/39
An important advantage of this technique is that the overvoltage level can be set
independently of the regulated output voltage: the latter depends on the ratio of R1 to R2,
the former on the individual value of R1. Another advantage is the precision: the tolerance of
the detection current is 15%, which means 15% tolerance on the ∆VO. Since it is usually
much smaller than Vo, the tolerance on the absolute value will be proportionally reduced.
Example: VO = 400V, ∆VO = 40V.
Then: R1 = 40V/20µA = 2MΩ ; R2 = 2.5·2MΩ·/(400-2.5) = 12.58kΩ.
The tolerance on the OVP level due to the L6563/A will be 40·0.15 = 6 V, that is ± 1.36%.
When either OVP is activated the quiescent consumption is reduced to minimize the
discharge of the Vcc capacitor.
Figure 34. Output voltage setting, OVP and FFP functions: internal block diagram
-
+
2.5V
L6563
L6563A
1
2
INV
COMP
E/A
+
-
Frequency
Compensation
+
-
R2
7
PFC_OK
ITBO
2.25V Static OVP
Dynamic OVP
20 µA
Vout
{
R1a
R1b
R1
9.5V
FAULT (latched)
TBO
FUNCTION
R4
{
R3a
R3b
R3
+
-
FAULT (not latched)
0.26V
9.5V
Application information L6563 - L6563A
18/39
6.2 Feedback Failure Protection (FFP)
The OVP function above described is able to handle "normal" overvoltage conditions, i.e.
those resulting from an abrupt load/line change or occurring at start-up. It cannot handle the
overvoltage generated, for instance, when the upper resistor of the output divider (R1) fails
open: the voltage loop can no longer read the information on the output voltage and will
force the PFC pre-regulator to work at maximum ON-time, causing the output voltage to rise
with no control.
A pin of the device (PFC_OK) has been dedicated to provide an additional monitoring of the
output voltage with a separate resistor divider (R3 high, R4 low, see Figure 34). This divider
is selected so that the voltage at the pin reaches 2.5V if the output voltage exceeds a preset
value, usually larger than the maximum Vo that can be expected, also including worst-case
load/line transients.
Example: VO = 400 V, Vox = 475V. Select: R3 = 3MΩ;
then: R4 = 3MΩ ·2.5/(475-2.5) = 15.87kΩ.
When this function is triggered, the gate drive activity is immediately stopped, the device is
shut down, its quiescent consumption is reduced below 250 µA and the condition is latched
as long as the supply voltage of the IC is above the UVLO threshold. At the same time the
pin PWM_LATCH is asserted high. PWM_LATCH is an open source output able to deliver
3.7V min. with 0.5 mA load, intended for tripping a latched shutdown function of the PWM
controller IC in the cascaded DC-DC converter, so that the entire unit is latched off. To
restart the system it is necessary to recycle the input power, so that the Vcc voltages of both
the L6563/A and the PWM controller go below their respective UVLO thresholds.
The PFC_OK pin doubles its function as a not-latched IC disable: a voltage below 0.2V will
shut down the IC, reducing its consumption below 1 mA. In this case both PWM_STOP and
PWM_LATCH keep their high impedance status. To restart the IC simply let the voltage at
the pin go above 0.26 V.
Note that this function offers a complete protection against not only feedback loop failures or
erroneous settings, but also against a failure of the protection itself. Either resistor of the
PFC_OK divider failing short or open or a PFC_OK pin floating will result in shutting down
the IC and stopping the pre-regulator.
6.3 Voltage Feedforward
The power stage gain of PFC pre-regulators varies with the square of the RMS input
voltage. So does the crossover frequency f
c
of the overall open-loop gain because the gain
has a single pole characteristic. This leads to large trade-offs in the design.
For example, setting the gain of the error amplifier to get f
c
= 20 Hz @ 264 Vac means
having f
c
≅ 4 Hz @ 88 Vac, resulting in a sluggish control dynamics. Additionally, the slow
control loop causes large transient current flow during rapid line or load changes that are
limited by the dynamics of the multiplier output. This limit is considered when selecting the
sense resistor to let the full load power pass under minimum line voltage conditions, with
some margin. But a fixed current limit allows excessive power input at high line, whereas a
fixed power limit requires the current limit to vary inversely with the line voltage.
Voltage Feedforward can compensate for the gain variation with the line voltage and allow
overcoming all of the above-mentioned issues. It consists of deriving a voltage proportional
to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V
2
corrector)
and providing the resulting signal to the multiplier that generates the current reference for
the inner current control loop (see Figure 35).
L6563 - L6563A Application information
19/39
Figure 35. Voltage feedforward: squarer-divider (1/V
2
) block diagram and transfer
characteristic
In this way a change of the line voltage will cause an inversely proportional change of the
half sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of
the multiplier output will be halved and vice versa) so that the current reference is adapted to
the new operating conditions with (ideally) no need for invoking the slow dynamics of the
error amplifier. Additionally, the loop gain will be constant throughout the input voltage
range, which improves significantly dynamic behavior at low line and simplifies loop design.
Actually, deriving a voltage proportional to the RMS line voltage implies a form of integration,
which has its own time constant. If it is too small the voltage generated will be affected by a
considerable amount of ripple at twice the mains frequency that will cause distortion of the
current reference (resulting in high THD and poor PF); if it is too large there will be a
considerable delay in setting the right amount of feedforward, resulting in excessive
overshoot and undershoot of the pre-regulator's output voltage in response to large line
voltage changes. Clearly a trade-off is required.
The device realizes Voltage Feedforward with a technique that makes use of just two
external parts and that limits the feedforward time constant trade-off issue to only one
direction. A capacitor C
FF
and a resistor R
FF
, both connected from the VFF (pin 5) pin to
ground, complete an internal peak-holding circuit that provides a DC voltage equal to the
peak of the rectified sine wave applied on pin MULT (pin 3). R
FF
provides a means to
discharge C
FF
when the line voltage decreases (see Figure 35). In this way, in case of
sudden line voltage rise, C
FF
will be rapidly charged through the low impedance of the
internal diode and no appreciable overshoot will be visible at the pre-regulator's output; in
case of line voltage drop C
FF
will be discharged with the time constant R
FF
·C
FF
, which can
be in the hundred ms to achieve an acceptably low steady-state ripple and have low current
distortion; consequently the output voltage can experience a considerable undershoot, like
in systems with no feedforward compensation.
01234
0
0.5
1
1.5
2
V
FF
=V
MULT
Vcsx
0.5
V
COMP
=4V
Actual
Ideal
5
MULT
3
R5
Rectif ied mains
R6
"ideal" diode
current
reference
(Vcsx)
9.5V
VFF
C
FF
R
FF
E/ A o ut p u t
(V
COMP
)
-
+
1/V
2
MULTIPLIER
L6563
L6563A
Application information L6563 - L6563A
20/39
The twice-mains-frequency (2·f
L
) ripple appearing across C
FF
is triangular with a peak-to-
peak amplitude that, with good approximation, is given by:
Equation 4
where f
L
is the line frequency. The amount of 3
rd
harmonic distortion introduced by this
ripple, related to the amplitude of its 2·f
L
component, will be:
Equation 5
Figure 36 shows a diagram that helps choose the time constant R
FF
·C
FF
based on the
amount of maximum desired 3
rd
harmonic distortion. Always connect R
FF
and C
FF
to the
pin, the IC will not work properly if the pin is either left floating or connected directly to
ground.
Figure 36. R
FF
·C
FF
as a function of 3
rd
harmonic distortion introduced in the input
current
The dynamics of the voltage feedforward input is limited downwards at 0.5V (see Figure 35),
that is the output of the multiplier will not increase any more if the voltage on the V
FF
pin is
below 0.5V. This helps to prevent excessive power flow when the line voltage is lower than
the minimum specified value (brownout conditions).
VFF
∆2VMULTpk
14f
LRFFCFF
+
---------------------------------------=
D3%100
2πfLRFFCFF
---------------------------------=
D %
3
0.1 1 10
0.01
0.1
1
10
f = 50 Hz
L
f = 60 Hz
L
R · C [s]
FFFF
L6563 - L6563A Application information
21/39
6.4 THD optimizer circuit
The L6563/A is provided with a special circuit that reduces the conduction dead-angle
occurring to the AC input current near the zero-crossings of the line voltage (crossover
distortion). In this way the THD (Total Harmonic Distortion) of the current is considerably
reduced.
A major cause of this distortion is the inability of the system to transfer energy effectively
when the instantaneous line voltage is very low. This effect is magnified by the high-
frequency filter capacitor placed after the bridge rectifier, which retains some residual
voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input
current flow to temporarily stop.
To overcome this issue the device forces the PFC pre-regulator to process more energy
near the line voltage zero-crossings as compared to that commanded by the control loop.
This will result in both minimizing the time interval where energy transfer is lacking and fully
discharging the high-frequency filter capacitor after the bridge.
Figure 37 shows the internal block diagram of the THD optimizer circuit.
Figure 37. THD optimizer circuit
+
+
MULT
COMP
t
@ Vac1
@ Vac2 > Vac1
t
t
to PWM
comparator
MULTIPLIER
OFFSET
GENERATOR
t
VFF
1 / V2
t
t
+
+
MULT
COMP
t
@ Vac1
@ Vac2 > Vac1
t
t
to PWM
comparator
MULTIPLIERMULTIPLIER
OFFSET
GENERATOR
OFFSET
GENERATOR
t
VFF
1 / V2
1 / V2
t
t
Application information L6563 - L6563A
22/39
Figure 38. THD optimization: standard TM PFC controller (left side) and L6563/A
(right side)
Essentially, the circuit artificially increases the ON-time of the power switch with a positive
offset added to the output of the multiplier in the proximity of the line voltage zero-crossings.
This offset is reduced as the instantaneous line voltage increases, so that it becomes
negligible as the line voltage moves toward the top of the sinusoid. Furthermore the offset is
modulated by the voltage on the V
FF
pin (see Section 6.3 on page 18 section) so as to have
little offset at low line, where energy transfer at zero crossings is typically quite good, and a
larger offset at high line where the energy transfer gets worse.
The effect of the circuit is shown in Figure 38, where the key waveforms of a standard TM
PFC controller are compared to those of this chip.
To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitor
after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large
capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself -
even with an ideal energy transfer by the PFC pre-regulator - thus reducing the effectiveness
of the optimizer circuit.
Imains
Vdrain
Imains
Vdrain
Input current Input current
MOSFET's drain voltage MOSFET's drain voltage
Rectified mains voltage Rectified mains voltage
Input current Input current
L6563 - L6563A Application information
23/39
6.5 Tracking Boost function
In some applications it may be advantageous to regulate the output voltage of the PFC pre-
regulator so that it tracks the RMS input voltage rather than at a fixed value like in
conventional boost pre-regulators. This is commonly referred to as "tracking boost" or
"follower boost" approach.
With this IC the function can be realized by connecting a resistor (R
T
) between the TBO pin
and ground. The TBO pin presents a DC level equal to the peak of the MULT pin voltage and
is then representative of the mains RMS voltage. The resistor defines a current, equal to
V(TBO)/R
T
, that is internally 1:1 mirrored and sunk from pin INV (pin 1) input of the error
amplifier. In this way, when the mains voltage increases the voltage at TBO pin will increase
as well and so will do the current flowing through the resistor connected between TBO and
GND. Then a larger current will be sunk by INV pin and the output voltage of the PFC pre-
regulator will be forced to get higher. Obviously, the output voltage will move in the opposite
direction if the input voltage decreases.
To avoid undesired output voltage rise should the mains voltage exceed the maximum
specified value, the voltage at the TBO pin is clamped at 3V. By properly selecting the
multiplier bias it is possible to set the maximum input voltage above which input-to-output
tracking ends and the output voltage becomes constant. If this function is not used, leave
the pin open: the device will regulate a fixed output voltage.
Starting from the following data:
●Vin
1
= minimum specified input RMS voltage;
●Vin
2
= maximum specified input RMS voltage;
●Vo
1
= regulated output voltage @ Vin = Vin1;
●Vo
2
= regulated output voltage @ Vin = Vin2;
●Vox = absolute maximum limit for the regulated output voltage;
●∆Vo = OVP threshold,
Application information L6563 - L6563A
24/39
to set the output voltage at the desired values use the following design procedure:
1. Determine the input RMS voltage Vinclamp that produces Vo = Vox:
Equation 6
and choose a value Vin
x
such that Vin
2
= Vin
x
< Vin
clamp
. This will result in a limitation of the
output voltage range below Vox (it will equal Vox if one chooses Vin
x
= Vin
clamp
)
2. Determine the divider ratio of the MULT pin (pin 3) bias:
Equation 7
and check that at minimum mains voltage Vin
1
the peak voltage on pin 3 is greater than
0.65V.
3. Determine R1, the upper resistor of the output divider:
Equation 8
4. Calculate the lower resistor R2 of the output divider and the adjustment resistor RT:
Equation 9
Vinclamp
Vox Vo1
–
Vo2Vo1
–
--------------------------- Vin2
Vox Vo2
–
Vo2Vo1
–
--------------------------- Vin1
⋅–⋅=
k3
2Vin
x
⋅
-----------------------=
R1 Vo∆
20
-----------106
⋅=
R2 2.5 R1 Vin2Vin1
–
Vo12.5–()Vin2Vo22.5–()Vin1
⋅–⋅
--------------------------------------------------------------------------------------------------
⋅⋅=
RT2kR1Vin2Vin1
–
Vo2Vo1
–
------------------------------
⋅⋅ ⋅=
L6563 - L6563A Application information
25/39
5. Check that the maximum current sourced by the TBO pin (pin 6) does not exceed the
maximum specified (0.25mA):
Equation 10
In the following Mathcad® sheet, as an example, the calculation is shown for the circuit
illustrated in Figure 40. Figure 41 shows the internal block diagram of the tracking boost
function.
Design data
Vin
1
:= 88V Vo
1
:= 200V
Vin
2
:= 264V Vo
2
:= 385V
Vox ;= 400V
∆Vo ;= 40V
Step 1
choose: Vin
x
: = 270V
Step 2
Step 3
ITBOmax
3
RT
-------0.25 10 3–
⋅≤=
Vinclamp:Vox Vo1
–
Vo2Vo1
–
--------------------------- Vin2
⋅=Vox Vo2
–
Vo2Vo1
–
--------------------------- Vin1
⋅–Vinclamp = 278.27V
k: 3
2Vin
x
⋅
-----------------------=k = 7.857 x 10
-3
R1: Vo∆
20
-----------106
⋅=R1 = 2 x 10
6
Ω
Application information L6563 - L6563A
26/39
Step 4
Step 5
Figure 39. Output voltage vs. input voltage characteristic with TBO
R2: 2.5 R1 Vin2Vin1
–
Vo12.5–()Vin2Vo22.5–()Vin1
⋅–⋅
--------------------------------------------------------------------------------------------------
⋅⋅=R2 = 4.762 x 10
4
Ω
RT:k2R1
Vin2Vin1
–
Vo2Vo1
–
------------------------------
⋅⋅⋅=R
T
= 2.114 x 10
4
Ω
ITBOmax:3
RT
-------103
⋅=I
TBOmax
= 0.142 mA
VMULTpk k2Vi⋅⋅←Vo(Vin
1
) = 200V
Vo(Vi): =
VTBO if VMULTpk 3,VMULTpk,3<()←Vo(Vin
2
) = 385V
2.5 1 R1
R2
--------+
⎝⎠
⎛⎞
VTBO
R1
RT
--------
⋅+⋅Vo(Vin
X
) = 391.307V
100 150 200 250 300
200
250
300
350
400 Vo 2
Vo Vin
()
Vin 2
Vin x
Vin
L6563 - L6563A Application information
27/39
6.6 Inductor saturation detection (L6563 only)
Boost inductor's hard saturation may be a fatal event for a PFC pre-regulator: the current
upslope becomes so large (50-100 times steeper, see Figure 42) that during the current
sense propagation delay the current may reach abnormally high values. The voltage drop
caused by this abnormal current on the sense resistor reduces the gate-to-source voltage,
so that the MOSFET may work in the active region and dissipate a huge amount of power,
which leads to a catastrophic failure after few switching cycles.
However, in some applications such as ac-dc adapters, where the PFC pre-regulator is
turned off at light load for energy saving reasons, even a well-designed boost inductor may
occasionally slightly saturate when the PFC stage is restarted because of a larger load
demand. This happens when the restart occurs at an unfavorable line voltage phase, so that
the output voltage may drop significantly below the rectified peak voltage. As a result, in the
Figure 40. 80W, wide-range-mains PFC pre-regulator with tracking boost function active
14
3
BRIDGE
4 x 1N4007
C1
0.22 µF
400V
C3
22
m
F
25V
FUSE
4A/250V
R3
68 kΩ
T
11
12
L6563
13
21
C6 100 nF
R6
10
Ω
MOS
STP8NM50
4
C6
56 µF
400V
Vo=200 to 385 V
Po=80W
Vac
(88V to 264V)
R7a,b
0.68 Ω
1/4 W
R9
47.5 kΩ
+
-
C2
2.2nF
D1
STTH1L06 NTC
R5
62 kΩ
C5
1 µF
5
C4
470 nF
67
10
89
R4
21 kΩ
R8b
1 MΩ
Supply Voltage
10.3 to 22V
R8a
1 MΩ
C7
10 nF
R10b
3.3 MΩ
R10a
3.3 MΩ
R11
34.8 kΩ
R1b
3.3 MΩ
R1a
3.3 MΩ
R2
51.1 kΩR10
390 kΩ
Figure 41. Tracking boost and voltage feedforward blocks
R1
L6563
L6563A
INV 1
Vout
TBO
6
1:1 CURRENT
MIRROR
R
T
2.5V
E/A
+
-
COMP
2
3V
-
+
5
I
TBO
I
R1
MULT
3
R5
Rectified mains
R6
"ideal"
diode
MULTIPLIER 1/V
2
current
reference
R2
I
R2
I
TBO
9.5V
9.5V
VFF
C
FF
R
FF
Application information L6563 - L6563A
28/39
boost inductor the inrush current coming from the bridge rectifier adds up to the switched
current and, furthermore, there is little or no voltage available for demagnetization.
To cope with a saturated inductor, the L6563 is provided with a second comparator on the
current sense pin (CS, pin 4) that stops and latches off the IC if the voltage, normally limited
within 1.1V, exceeds 1.7V. Also the cascaded DC-DC converter can be stopped via the
PWM_LATCH pin that is asserted high. In this way the entire system is stopped and enabled
to restart only after recycling the input power, that is when the Vcc voltages of the L6563
and the PWM controller go below their respective UVLO thresholds. System safety will be
considerably increased.
To better suit the applications where a certain level of saturation of the boost inductor needs
to be tolerated, the L6563A does not support this protection function.
6.7 Power management/housekeeping functions
A special feature of this IC is that it facilitates the implementation of the "housekeeping"
circuitry needed to coordinate the operation of the PFC stage to that of the cascaded DC-
DC converter. The functions realized by the housekeeping circuitry ensure that transient
conditions like power-up or power down sequencing or failures of either power stage be
properly handled.
This device provides some pins to do that. As already mentioned, one communication line
between the IC and the PWM controller of the cascaded DC-DC converter is the
PWM_LATCH pin, which is normally open when the PFC works properly and goes high if it
loses control of the output voltage (because of a failure of the control loop) or if the boost
inductor saturates, with the aim of latching off the PWM controller of the cascaded DC-DC
converter as well (Section 6.2: Feedback Failure Protection (FFP) on page 18 for more
details).
A second communication line can be established via the disable function included in the
PFC_OK pin (Section 6.2 on page 18 for more details ). Typically this line is used to allow
the PWM controller of the cascaded DC-DC converter to shut down the L6563/A in case of
light load, to minimize the no-load input consumption. Should the residual consumption of
the chip be an issue, it is also possible to cut down the supply voltage. Interface circuits like
those shown in Figure 43, where the L6563/A works along with the L5991, PWM controller
with standby function, can be used. Needless to say, this operation assumes that the
cascaded DC-DC converter stage works as the master and the PFC stage as the slave or, in
other words, that the DC-DC stage starts first, it powers both controllers and
enables/disables the operation of the PFC stage.
Figure 42. Effect of boost inductor saturation on the MOSFET current and detection method
L6563 - L6563A Application information
29/39
The third communication line is the PWM_STOP pin (pin 9), which works in conjunction with
the RUN pin (pin 10). The purpose of the PWM_STOP pin is to inhibit the PWM activity of
both the PFC stage and the cascaded DC-DC converter. The pin is an open collector,
normally open, that goes low if the device is disabled by a voltage lower than 0.52V on the
RUN pin. It is important to point out that this function works correctly in systems where the
PFC stage is the master and the cascaded DC-DC converter is the slave or, in other words,
where the PFC stage starts first, powers both controllers and enables/disables the operation
of the DC-DC stage.
This function is quite flexible and can be used in different ways. In systems comprising an
auxiliary converter and a main converter (e.g. desktop PC's silver box or hi-end LCD-TV),
where the auxiliary converter also powers the controllers of the main converter, the pin RUN
can be used to start and stop the main converter. In the simplest case, to enable/disable the
PWM controller the PWM_STOP pin can be connected to either the output of the error
amplifier (Figure 44 a) or, if the chip is provided with it, to its soft-start pin (Figure 44 b). The
use of the soft-start pin allows the designer to delay the start-up of the DC-DC stage with
respect to that of the PFC stage, which is often desired. An underlying assumption in order
for that to work properly is that the UVLO thresholds of the PWM controller are certainly
higher than those of the L6563/A.
Figure 43. Interface circuits that let DC-DC converter’s controller IC disable the L6563/A at light
load
L5991/A
ST-BY
4
16
27
kΩ
Vref
L6563
PFC_OK
7
100
kΩ
150
kΩ
150
kΩ
47
kΩ
100 nF
BC547
BC547
BC557
L5991/A
ST-BY
4
16
27
kΩ
Vref
L6563
Vcc
14
100
kΩ
150
kΩ
150
kΩ
15
kΩ
100 nF
BC557
BC547
BC557 100 nF
Supply_Bus
L6668
PFC_STOP
14
16
Vcc
10 k
Ω
BC557
2.2 k
Ω
L6563
L6563A
Vcc
14
8.2 V
L6563
L6563A
(RUN)
PFC_OK
BC547
L6668
14 PFC_STOP
7
(10)
2.2 k
Ω
8
VREF
100 k
Ω
L6599
PFC_STOP
14
L6563
L6563A
(RUN)
PFC_OK 7
(10)
Application information L6563 - L6563A
30/39
Figure 44. Interface circuits that let the L6563/A switch on or off a PWM controller
If this is not the case or it is not possible to achieve a start-up delay long enough (because
this prevents the DC-DC stage from starting up correctly) or, simply, the PWM controller is
devoid of soft start, the arrangement of Figure 45 lets the DC-DC converter start-up when
the voltage generated by the PFC stage reaches a preset value. The technique relies on the
UVLO thresholds of the PWM controller.
Figure 45. Interface circuits for actual power-up sequencing (master PFC)
Another possible use of the RUN and PWM_STOP pins (again, in systems where the PFC
stage is the master) is brownout protection, thanks to the hysteresis provided.
Brownout protection is basically a not-latched device shutdown function that must be
activated when a condition of mains undervoltage is detected. This condition may cause
overheating of the primary power section due to an excess of RMS current. Brownout can
also cause the PFC pre-regulator to work open loop and this could be dangerous to the PFC
stage itself and the downstream converter, should the input voltage return abruptly to its
rated value. Another problem is the spurious restarts that may occur during converter power
down and that cause the output voltage of the converter not to decay to zero monotonically.
For these reasons it is usually preferable to shutdown the unit in case of brownout.
L6563 - L6563A Application information
31/39
IC shutdown upon brownout can be easily realized as shown in Figure 46 The scheme on
the left is of general use, the one on the right can be used if the bias levels of the multiplier
and the R
FF
·C
FF
time constant are compatible with the specified brownout level and with the
specified holdup time respectively.
In Ta bl e 6 it is possible to find a summary of all of the above mentioned working conditions
that cause the device to stop operating.
Figure 46. Brownout protection (master PFC)
6.8 Summary of L6563/A idle states
.
10
RUN
AC mains
L6563
L6563A
VFF
L6563
L6563A
5
RUN
10
RFF CFF
Table 6. Summary of L6563/A idle states
Condition Caused or
revealed by
PWM_LATCH
(pin 8)
PWM_STOP
(pin 9)
Typical IC
consumption IC behavior
UVLO Vcc < 8.7 V Open Open 50 µA Auto-restart
Feedback
disconnected
PFC_OK > 2.5 V Active (high) Open 180 µA Latched
Saturated
Boost Inductor
Vcs > 1.7 V
(L6563 only)
Active (high)
(L6563 only)
Open 180 µA
(L6563 only)
Latched
(L6563 only)
AC Brownout RUN < 0.52 V Open Active (low) 1.5 mA Auto-restart
Standby PFC_OK < 0.2 V Open Open 1.5 mA Auto-restart
Application examples and ideas L6563 - L6563A
32/39
7 Application examples and ideas
Figure 47. Demo board (EVAL6563-80W) 80W, Wide-range, Tracking Boost: Electrical schematic
Boost inductor spec:
E25x13x7 core, 3C85 ferrite or equivalent
1.6 mm gap for 0.43 mH primary inductance
Primary: 80 turns 20 x 0.1 mm
Secondary: 9 turns 0.1 mm
14
3
P1
1W08G
R11A
1 MΩ
C1
0.47 µF
400V
C2
33 µF
25V
FUSE
4A/250V
R3A
120 kΩ
D3
1N4148
D2
20 V
R2
33 Ω
15 nF
C6
R1
47 kΩ
T
11
12
L6563 13
21
C12 220 nF
R6
22
Ω
Q1
STP8NM50
4
C5
56 µF
400 V
Vo=220 to 390 V
Po = 80 W
Vac
(88V to 264V)
R8
37.4 kΩ
+
-
C7
4.7 nF
D1
STTH2L06
NTC
2.5 Ω
R4
39 kΩ
C8
1 µF
5
C9
470 nF
6
7
10
89
R14
22.1 kΩ
R13
10.5 kΩ
R3B
120 kΩ
R11B
1 MΩ
R10
15.8 kΩ
R9A
1 MΩ
R9B
1 MΩ
R12A
1 MΩ
R12A
1 MΩ
R7A
0.68 Ω
1/2 W
R7B
0.68 Ω
1/2 W
R15
0 Ω
C10
N.A.
R17
390 kΩ
C11
4.7 nF
R18
47 kΩ
R20
47 kΩ
TP1
TP2
Daux
1N4007
C4
100 nF
Figure 48. EVAL6563-80W: PCB and component layout (Top view, real size: 64 x 94 mm)
L6563 - L6563A Application examples and ideas
33/39
Figure 49. EVAL6563-80W: PCB layout, soldering side (Top view)
Note: Measurements done with the line filter shown in Figure 51.
Note: Measurements done with the line filter shown in Figure 51.
Table 7. EVAL6563-80W: Evaluation results at full load
Vin (VAC)Pin (W) Vo (VDC)∆Vo
(Vpk-pk)Po (W) η (%) PF THD (%)
90 85.3 219.4 16.6 79.64 93.4 0.999 3.7
115 84.9 244.1 15.0 80.80 95.2 0.998 4.3
135 83.7 263.7 13.9 80.16 95.8 0.997 4.8
180 83.5 307.6 14.5 80.28 96.1 0.993 6.0
230 85.2 356.7 13.0 81.33 95.5 0.984 7.7
265 85.0 390.6 12.1 80.85 95.1 0.974 9.5
Table 8. EVAL6563-80W: Evaluation results at half load
Vin (VAC)Pin (W) Vo (VDC)∆Vo
(Vpk-pk)Po (W) η (%) PF THD (%)
90 43.4 219.9 8.6 40.90 94.2 0.997 4.8
115 42.6 244.5 7.7 40.10 94.1 0.994 5.7
135 43.1 264.0 7.3 40.39 93.7 0.989 6.5
180 43.8 307.7 7.7 40.31 92.0 0.978 8.4
230 45.6 356.8 6.8 41.03 90.0 0.951 9.6
265 46.0 390.7 6.7 40.63 88.3 0.920 14.2
Application examples and ideas L6563 - L6563A
34/39
Figure 50. EVAL6563-80W: Vout vs. Vin relationship (tracking boost)
Figure 51. Line filter (not tested for EMI compliance) used for EVAL6563-80W
evaluation
L6563 - L6563A Application examples and ideas
35/39
Figure 52. 250W, wide-range-mains PFC pre-regulator with fixed output voltage
14
3
B1
KBU8M
R1A
820 k
C1
1 µF
400V C2
1 µF
FUSE
8A/250V
R3
47 k
11
12
L6563
13
21
M1
STP12NM50
4
R9A
1 M
C8
150 µF
450 V
Vout = 400V
Pout = 250 W
Vac
88V
to
264V
R8A,B
0.22
1 W
R10
12.7 k
+
-
C3
10nF
D2
STTH5L06
R6 33
C4
1 µF
R1B
820 k
R2
10 k
D3 1N4148
R9B
1 M
NTC1
2.5
D1
1N5406
C6
470 nF
630 V
R5
6.8 k
L1
R4
1 M
Vcc
10.3 to 22 V
R11A
1.87 M
R12
20 k
R11B
1.87 M
6
7
5
R7
390 k
C5
470nF
8 9
C7
10 nF
10
Boost Inductor (L1) Spec
ETD29x16x10 core, 3C85 ferrite or equivalent
1.5 mm gap for 150 µH primary inductance
Primary: 74 turns 20xAWG30 ( 0.3 mm)
Secondar
y
: 8 turns 0.1 mm
Figure 53. 350W, wide-range-mains PFC pre-regulator with fixed output voltage and FOT control
14
3
B1
KBU8M
R1A
620 k
C1
1 µF
400V C2
1 µF
FUSE
8A/250V
R8
1.5 k
11 12
L6563
13
21
M1A
STP12NM50
4
C11
220 µF
450 V
Vout = 400V
Pout = 350W
Vac
88V
to
264V
R12A,B,C
0.33
1 W
+
-
C3
10nF
D2
STTH806DTI
R9 6.8
C5
1 µF
R1B
620 k
R2
10 k
D3 1N4148
D5
1N4148
R7
12 k
C7
560 pF
C6 330 pF
NTC1
2.5
D1
1N5406
C9
470 nF
630 V
R5
6.8 k
R10 6.8
D4
1N4148 M1B
STP12NM50
R6
1.5 k
TR1
BC557
L1
R15A
1.87 M
R16
20 k
R15B
1.87 M
6
7
5
R3
390 k
C4
470nF
98 9
C10
10 nF
10
C8
330 pF
R11 330
R13A
1 M
R14
12.7 k
R13B
1 M
R4
1 M
Vcc
10.3 to 22 V
L1: core E42*21*15, B2 material
1.9 mm air gap on centre leg, main winding
inductance 0.55 mH
58 T of 20 x AWG32 ( 0.2 mm)
Application examples and ideas L6563 - L6563A
36/39
Figure 54. Demagnetization sensing without auxiliary winding
Figure 55. Enhanced turn-off for big MOSFET driving
V
inac
L6563
L6563A
V
out
C
ZCD
R
ZCD
R
load
9
ZCD
13
12
14
GD
GND
DRIVER
Vcc
Q
L6563
L6563A Rs
BC327
L6563 - L6563A Package mechanical data
37/39
8 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
Table 9. SO-14 Mechanical data
Dim. mm. inch
Min Typ Max Min Typ Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.30 0.004 0.012
A2 1.10 1.65 0.043 0.065
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.01
D (1) 8.55 8.75 0.337 0.344
E 3.80 4.0 0.150 0.157
e 1.27 0.050
H 5.8 6.20 0.228 0.244
h 0.25 0.50 0.01 0.02
L 0.40 1.27 0.016 0.050
k 0° (min.), 8° (max.)
ddd 0.10 0.004
Figure 56. Package dimensions
0016019D
Revision history L6563 - L6563A
38/39
9 Revision history
Table 10. Revision history
Date Revision Changes
13-Nov-2004 1 First issue
24-Sep-2005 2 Changed the maturity from “Preliminary data” to “Datasheet”
17-Nov-2006 3
Added new part number L6563A (Table 2)
Updated the Section 4 on page 7 & Section 7 on page 32 the
document has been reformatted
12-Mar-2007 4 Replaced block diagram, added Figure 37 on page 21 and minor
editor changes.
L6563 - L6563A
39/39
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