HSP45102SC-33Z - Intersil Corporation

®HSP45102

12-Bit Numerically Controlled Oscillator

The Intersil HSP45102 is Numerically Controlled Oscillator

(NCO12) with 32-bit frequency resolution and 12-bit output.

With over 69dB of spurious free dynamic range and worst

case frequency resolution of 0.009Hz, the NCO12 provides

significant accuracy for frequency synthesis solutions at a

competitive price.

The frequency to be generated is sel ected from two frequency

control words. A single control pin select s which word is used

to determine the output frequency. Switching from one

frequency to another occurs in one clock cycl e, with a 6 cl ock

pipeline delay from the time that the new control word i s

loaded until t 4-he new frequency appears on th e output.

T wo pins, P0-1, are provided for phase modulation. They are

encoded and added to the top two bits of the phase

accumulator to offset the phase in 90° increments.

The 13-bit output of the Phase Offset Adder is mapped to the

sine wave amplitude via the Sine ROM. The output data

format is offset binary to simplify interfacing to D/A

converters. Spurious frequency components in the output

sinusoid are less than -69dBc.

The NCO12 has applications as a Direct Digital Synthesizer

and modulator in low cost digital radios, satellite terminals,

and function generators.

Features

• 33MHz, 40MHz Versions

• 32-Bit Frequency Control

• BFSK, QPSK Modulation

• Serial Frequency Load

• 12-Bit Sine Output

• Offset Binary Output Format

• 0.009Hz T uning Resolution at 40MHz

• Spurious Freq uency Components <-69dBc

• Fully Static CMOS

•Low Cost

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Direct Digital Synthesis

• Modulation

• PSK Communications

• Related Products

- HI5731 12-Bit, 10 0MHz D/A Con ver ter

Ordering Information

PART NUMBER PART MARKING TEMP.

RANGE (°C) PACKAGE PKG.

DWG. #

HSP45102SC-33 HSP45102SC-33 0 to +70 28 Ld SOIC (300 mil) M28.3

HSP45102SC-33Z (Note) HSP45102SC-33Z 0 to +70 28 Ld SOIC (300 mil) (Pb-free) M28.3

HSP45102SC-40 HSP45102SC -40 0 to +70 28 Ld SOIC (300 mil) M28.3

HSP45102SC-40Z (Note) HSP45102SC-40Z 0 to +70 28 Ld SOIC (300 mil)(Pb-free) M28.3

HSP45102SI-3396 HSP45102SI -33 0 to +70 28 Ld SOIC (300 mil) (Tape and Reel) M28.3

HSP45102SI-33Z (Note) HSP45102SI-33Z 0 to +70 28 Ld SOIC (300 mil) (Pb-free) M28.3

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Data Sheet April 25, 2007 FN2810.9

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

2FN2810.9

April 25, 2007

Block Diagram

Pinout HSP45102

(28 LEAD SOIC)

TOP VIEW

PHASE

ACCUMULATOR

FREQUENCY

CONTROL

SECTION

PHASE

OFFSET

ADDER

SINE

ROM

CLK

PO-1

13 OUT0-11

MSB/LSB

SFTEN

SCLK

LOAD

TXFR

SEL_L/M

ENPHAC

13 12

OUT6

OUT7

OUT8

OUT9

OUT10

OUT11

GND

VCC

SEL_L/M

SFTEN

MSB/LSB

ENPHAC

SCLK

OUT5

OUT3

OUT2

OUT1

OUT0

GND

LOAD

TXFR

CLK

GND

OUT4

VCC

HSP45102

3FN2810.9

April 25, 2007

Pin Description

NAME TYPE DESCRIPTION

VCC +5V power supply pin.

GND Ground

P0-1 I Phase modulation inputs (become active after a pipeline delay of four clocks). A phase shift of 0°, 90°,

180°, or 270° can be selected as shown in Table 1.

CLK I NCO clock. (CMOS level)

SCLK I This pin clocks the frequency control shift register.

SEL_L/M I A high on this input selects the least sign ificant 32 bits of the 64-bit frequency register as the input to

the phase accumulator; a low selects the most significant 32 bits.

SFTEN I The active low input enables the shifting of the frequency register.

MSB/LSB I This input selects the shift direction of the frequency register. A low on this input shifts in the data LSB

first; a high shifts in the data MSB first.

ENPHAC I This pin, when low, enables the clocking of the Phase Accumulator. This input has a pipeline delay of

four clocks.

SD I Dat a on this p in is shif ted into the fr eque ncy re gister by th e risin g edge of SCL K when SFTEN is low.

TXFR I This active low input is clocked onto the chip by CLK and becomes active after a pipeline delay of four

clocks. When low, the frequency control word selected by SEL_L/M is transferred from the freq uency

LOAD I This input becomes active after a pipeline dela y of five clocks. When low, the feedba ck in the phase

accumulator is zeroed.

OUT0-11 O Output data. OUT0 is LSB. Unsigned.

All inputs are TTL level, with the exception of CLK.

Overline designates active low signals.

HSP45102

4FN2810.9

April 25, 2007

Functional Description

The NCO12 produces a 12-bit sinusoid whose frequency

and phase are digitally controlled. The frequency of the sine

wave is determined by one of two 32-bit words. Selection of

the active word is made by SEL_L/M. The pha se of the

output is controlled by the two-bit input P0-1, which is used

to select a phase offset of 0°, 90°, 180°, or 270°.

As shown in the Block Diagram, the NCO12 consists of a

Frequency Control Section, a Phase Accumulator, a Phase

Offset Adder and a Sine ROM. The Frequency Control

section serially loads the frequency control word into the

frequency register. The Phase Accumulator and Phase

Offset Adder compute the phase angle using the frequency

control word and the two phase modulation inputs. The Sine

ROM generates the sine of the computed phase angle. The

format of the 12-bit output is offset binary.

Frequency Control Section

The Frequency Control Section shown in Figure 1 serially

loads the frequency data into a 64-bit, bidirectional shift

input. When this input is high, the frequency control word on

the SD input is shifted into the register MSB first. When

MSB/LSB is low the dat a is shifted in LSB first. The register

shifts on the rising edge of SCLK when SFTEN is low. The

timing of these si gnals is shown in Figures 2A and 2B.

The 64 bits of the frequency register are sent to the Phase

Accumulator Section where 32 bits are selected to control

the frequency of the sinusoidal output.

Phase Accumulator Section

The phase accumulator and phase offset adder compute the

phase of the sine wave from the frequency control word and

the phase modulation bits P0-1. The architecture is shown in

Figure 1. The most significant 13 bits of the 32-bit phase

accumulator are summed with the two-bit phase offset to

generate the 13-bit phase input to the Sine Rom. A value of

0 corresponds to 0°, a value of 1000 hexa decimal

corresponds to a value of 180°.

The phase accumulator advances the phase by the amount

programmed into the frequency control register. The output

frequency is equal to:

where N is the 32 bit s of fr equency control wo rd that is

programmed. INT[•] is the integer of the comput ation. For

example, if the control word is 200 00000 hexadecimal and the

clock frequency is 30MHz, then the output frequen cy wou ld

be fCLK/8, or 3.75MHz.

The frequency control multiplexer selects the least

significant 32 bits from the 64-bit frequency control register

when SEL_L/M is high, and the most significant 32 bits

when SEL_L/M is low. When only one frequency word is

desired, SEL_L/M and MSB/LSB must be either both high or

both low. Th is i s due to the fact that when a freque ncy

control word is loaded into the sh ift register LSB first, it

enters through the most significant bit of the register. After

32 bits have been shifted in, they will reside in the 32 most

significant bits of the 64-bit register.

When TXFR is asserted, the 32 bit s selected by the frequency

control multiplexer are clocked into the phase accumulator

/13 MSBs

R.P0-1

CLK

P0-1

CLK

/32

ACCUMULATOR

INPUT

R.TXFR /32

CLK

/32

‘0’ /32

64-BIT

SHIFT

REG

/32

PHASE ACCUMULATOR

2-DLY

R.P0-1

PHASE OFFSET ADDER

/13

R/13 R

SINE

ROM /12

CLK

FRCTRL

SCLK

FREQUENCY

CONTROL

SECTION

R.LOAD

SFTEN

MSB/LSB

R.ENPHAC

R.TXFR

R.LOAD

TXFR

LOAD

SEL_L/M

R.ENPHAC

0-31

32-63

(HIGH SELECTS FRCTRL0-31, LOW SELECTS FRCTRL32-63)

OUT0-11

4-DLY

ENPHAC

FIGURE 1. NCO-12 FUNCTIONAL BLOCK DIAGRAM

CLK

0 1

MUX

0 1

MUX

fLO Nf

CLK

×232

⁄(), or=(EQ. 1)

N INT fOUT

fCLK

-------------

⎝⎠

⎜⎟

⎛⎞

232 ,=(EQ. 2)

HSP45102

5FN2810.9

April 25, 2007

input register. At each clock, the contents of this register are

summed with the current contents of the accumulator to step to

the new phase. The phase accumulator stepping may be

inhibi ted by hold ing ENPHAC high. The phase accumulator

may be loaded with the value in the input register by asserting

LOAD, which zeroes the feedback to the phase accumulator .

The phase adder sums the encoded phase modula t ion bi ts

P0-1 and the output of the phase accumulator to offset the

phase by 0°, 90°, 180° or 270°. The tw o bits are encoded to

produce the phase mapping shown in Table 1. This phase

mapping is provided for direct connection to the in-phase

and quadrature data bits for QPSK modulation. ROM Section

The ROM section generates the 12-bit sine value from the

13-bit output of the phase adder. The output format is offset

binary and ranges from 001 to FFF hexadecimal, cente red

around 800 hexadecimal.

TABLE 1. PHASE MAPPING

P0-1 CODING

P1 P0 PHASE SHIFT (DEGREES)

00 0

01 90

1 0 270

1 1 180

FIGURE 2A. FREQUENCY LOADING ENABLED BY SFTEN

FIGURE 2B. FREQUENCY LOADING CONTROLLED BY SCLK

FIGURE 3. I/O TI MING

SCLK

SFTEN

MSB/LSB

01263

SCLK

SFTEN

MSB/LSB

01263

CLK

LOAD

TXFR

OUT0-11

1 34 6789101152

NEW

DATA

ENPHAC

SEL_L/M

HSP45102

6FN2810.9

April 25, 2007

Absolute Maximum Ratings TA= +25°C Thermal Information

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V

Input, Output or I/O Voltage Applied . . . . . GND -0.5V to VCC +0.5V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Operating Conditions

Operating Voltage Range (Commercial, Industrial) . . +4.75V to +5.25V

Operating Temperature Range (Commercial) . . . . . . . 0°C to +70°C

Operating Temperature Range (Industrial) . . . . . . . .-40°C to +85°C

Thermal Resistance (Typical, Note 1) θJA (°C/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Die Characteristics

Backside Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS

Logical One Input Voltage VIH VCC = 5.25V 2.0 - V

Logical Zero Input Voltage VIL VCC = 4.75V - 0.8 V

High Level Clock Input VIHC VCC = 5.25V 3.0 - V

Low Level Clock Input VILC VCC = 4.75V - 0.8 V

Output HIGH Voltage VOH IOH = -400μA, VCC = 4.75V 2.6 - V

Output LOW Voltage VOL IOL = +2.0mA, VCC = 4.75V - 0.4 V

Input Leakage Current IIVIN = VCC or GND, VCC = 5.25V -10 10 μA

Standby Power Supply Current ICCSB VIN = VCC or GND, VCC = 5.25V, Note 4 - 500 μA

Operating Power Supply Current ICCOP f = 33MHz, VIN = VCC or GND

VCC = 5.25V, Notes 2 and 4 -99 mA

Capacitance TA = +25°C, Note 3

PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS

Input Capacitance CIN FREQ = 1MHz, VCC = Open. All

measurements are referenced to device

ground

-10 pF

Output Capacitance CO-10 pF

NOTES:

2. Power supply current is proportional to operating frequency. Typical rating for ICCOP is 3mA/MHz.

3. Not tested, but characterized at initial design and at major process/design changes.

4. Output load per test load circuit with switch open and CL = 40pF.

HSP45102

7FN2810.9

April 25, 2007

AC Test Load Circuit

AC Electrical Specifications VCC = 5.0V ±5%, TA = 0°C to +70°C, TA = -40°C to +85°C (Note 5)

PARAMETER SYMBOL NOTES

-33 (33MHz) -40 (40MHz)

UNITSMIN MAX MIN MAX

Clock Period tCP 30 - 25 - ns

Clock High tCH 12 - 10 - ns

Clock Low tCL 12 - 10 - ns

SCLK High/Low tSW 12 - 10 - ns

Setup Time SD to SCLK Going High tDS 12 - 12 - ns

Hold Time SD from SCLK Going High tDH 0-0- ns

Setup Time SFTEN, MSB/LSB to SCLK Going High tMS 15 - 12 - ns

Hold Time SFTEN, MSB/LSB from SCLK Go in g High tMH 0-0- ns

Setup Time SCLK High to CLK Going High tSS Note 6 16 - 15 - ns

Setup Time P0-1 to CLK Going High tPS 15 - 12 - ns

Hold Time P0-1 from CLK Going High tPH 1-1- ns

Setup Time LOAD, TXFR, ENPHAC, SEL_L/M

to CLK Going High tES 15 - 13 - ns

Hold Time LOAD, TXFR, ENPHAC, SEL_L/M

from CLK Going High tEH 1-1- ns

CLK to Output Delay tOH 215213 ns

Output Rise, Fall Time tRF Note 7 8 - 8 - ns

NOTES:

5. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; Input levels (all other inputs) 0V and 3.0V; T iming reference levels

(CLK) 2.0V ; All others 1.5V. Output load per test load circuit with switch closed and CL = 40pF. Output transition is measured at VOH > 1.5V and

VOL < 1.5V.

6. If TXFR is active, care must be taken to not violate setup and hold times as data from the shift registers may not have settled before CLK occur s.

7. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design

changes.

EQUIVALENT CIRCUIT

CL (NOTE)

IOH 1.5V IOL

DUT

SWITCH S1 OPEN FOR ICCSB AND ICCOP

NOTE: Test head capacitance.

HSP45102

8FN2810.9

April 25, 2007

Waveforms

FIGURE 4.

tCP

tCL

tCH

tPS tPH

tES tEH

tOH tRF

tSW tSS

tDS tDH

tMH

tMS

tSW

CLK

SCLK

MSB/LSB,

P0-1

OUT0-11

ENPHAC, SEL_L/M

LOAD, TXFR,

SFTEN

HSP45102

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersi l or it s sub sidi ari es.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN2810.9

April 25, 2007

HSP45102

Small Outline Plastic Packages (SOIC)

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2

of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. In-

terlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact.

INDEX

AREA

123

-B-

0.25(0.010) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45o

H0.25(0.010) BM M

M28.3 (JEDEC MS-013-AE ISSUE C)

28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.0200 0.33 0.51 9

C 0.0091 0.0125 0.23 0.32 -

D 0.6969 0.7125 17.70 18.10 3

E 0.2914 0.2992 7.40 7.60 4

e 0.05 BSC 1.27 BSC -

H 0.394 0.419 10.00 10.65 -

h 0.01 0.029 0.25 0.75 5

L 0.016 0.050 0.40 1.27 6

N28 287

α0o8o0o8o-

Rev. 0 12/93