ADC0844,ADC0848 ADC0844/ADC0848 8-Bit P Compatible A/D Converters with Multiplexer Options Literature Number: SNAS523C ADC0844/ADC0848 8-Bit P Compatible A/D Converters with Multiplexer Options General Description Features The ADC0844 and ADC0848 are CMOS 8-bit successive approximation A/D converters with versatile analog input multiplexers. The 4-channel or 8-channel multiplexers can be software configured for single-ended, differential or pseudodifferential modes of operation. The differential mode provides low frequency input common mode rejection and allows offsetting the analog range of the converter. In addition, the A/D's reference can be adjusted enabling the conversion of reduced analog ranges with 8-bit resolution. The A/Ds are designed to operate from the control bus of a wide variety of microprocessors. TRI-STATE output latches that directly drive the data bus permit the A/Ds to be configured as memory locations or I/O devices to the microprocessor with no interface logic necessary. Easy interface to all microprocessors Operates ratiometrically or with 5 VDC voltage reference No zero or full-scale adjust required 4-channel or 8-channel multiplexer with address logic Internal clock 0V to 5V input range with single 5V power supply 0.3 standard width 20-pin or 24-pin DIP 28 Pin Molded Chip Carrier Package Key Specifications Resolution Total Unadjusted Error Single Supply Low Power Conversion Time 8 Bits 1/2 LSB and 1 LSB 5 VDC 15 mW 40 s Block Diagram 501601 * ADC0848 shown in DIP Package CH5-CH8 not included on the ADC0844 (c) 2008 National Semiconductor Corporation 5016 www.national.com ADC0844/ADC0848 8-Bit P Compatible A/D Converters with Multiplexer Options December 2, 2008 ADC0844/ADC0848 Connection Diagrams Molded Chip Carrier Package Dual-In-Line Package 501602 Top View 501629 Top View See Ordering Information Dual-In-Line Package 501630 Top View Ordering Information Temperature Range Total Unadjusted Error 1 LSB MUX Channels Package Outline ADC0844CCN 4 N20A Molded Dip ADC0848BCN ADC0848CCN 8 N24D Molded Dip ADC0844BCJ* ADC0844CCJ* 4 J20A Cerdip ADC0848BCV ADC0848CCV 8 V28A Molded Chip Carrier 8 V28A Molded Chip Carrier in Tape and Reel 1/2 LSB 0C to +70C -40C to +85C ADC0848BCVX ADC0848CCVX * Product/package combination obsolete; shown for reference only www.national.com 2 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Voltage Logic Control Inputs At Other Inputs and Outputs Input Current at Any Pin (Note 3) Package Input Current (Note 3) Storage Temperature Package Dissipation at TA=25C ESD Susceptibility (Note 4) Lead Temperature (Soldering, 10 seconds) Dual-In-Line Package (Plastic) 6.5V 300C 215C 220C Operating Conditions (Notes 1, 2) -0.3V to +15V -0.3V to VCC+0.3V 5 mA 20 mA -65C to +150C 875 mW 800V Supply Voltage (VCC) Temperature Range 4.5 VDC to 6.0 VDC TMINTATMAX ADC0844CCN, ADC0848BCN, 0CTA70C ADC0848CCN ADC0844BCJ *, ADC0844CCJ -40CTA85C *, ADC0848BCV, ADC0848CCV * Product/package combination obsolete; shown for reference only. 260C Electrical Characteristics The following specifications apply for VCC = 5 VDC unless otherwise specified.Boldface limits apply from TMIN to TMAX; all other limits TA = Tj = 25C. ADC0844CCN ADC0848BCN, ADC0848CCN ADC0848BCV, ADC0848CCV Limit Design Tested Design Units Typ Limit Limit Limit (Note 5) (Note 7) (Note 6) (Note 7) ADC0844BCJ (Note 12) ADC0844CCJ (Note 12) Parameter Conditions Typ (Note 5) Tested Limit (Note 6) CONVERTER AND MULTIPLEXER CHARACTERISTICS Maximum Total VREF=5.00 VDC Unadjusted Error (Note 8) ADC0844BCN, ADC0848BCN, BCV ADC0844CCN, ADC0848CCN, CCV ADC0844CCJ (Note 12) 1/2 1 1/2 1 LSB 1 LSB LSB Minimum Reference Input Resistance 2.4 1.1 2.4 1.2 1.1 k Maximum Reference Input Resistance 2.4 5.9 2.4 5.4 5.9 k (Note 9) VCC+0.05 Minimum Common-Mode Input Voltage (Note 9) GND -0.05 DC Common-Mode Error Differential Mode 1/16 1/4 Power Supply Sensitivity VCC=5V5% 1/16 Maximum Common-Mode Input Voltage VCC+0.05 VCC+0.05 V GND -0.05 GND -0.05 V 1/16 1/4 1/4 LSB 1/16 LSB -1 -0.1 -1 A 1 0.1 1 A 2.0 2.0 2.0 V 0.8 (Note 10) On Channel=5V, Off Channel Leakage Current Off Channel=0V On Channel=0V, Off Channel=5V DIGITAL AND DC CHARACTERISTICS VIN(1), Logical "1" Input Voltage (Min) VCC=5.25V VIN(0), Logical "0" Input Voltage (Max) VCC=4.75V 0.8 V IIN(1), Logical "1" Input Current (Max) VIN=5.0V 0.005 1 0.005 1 A IIN(0), Logical "0" Input Current (Max) VIN=0V -0.005 -1 -0.005 -1 A 0.8 VCC=4.75V, VOUT(1), Logical "1" Output Voltage (Min) IOUT=-360 A 2.4 2.8 2.4 V IOUT=-10 A 4.5 4.6 4.5 V 3 www.national.com ADC0844/ADC0848 Dual-In-Line Package (Ceramic) Molded Chip Carrier Package Vapor Phase (60 seconds) Infrared (15 seconds) Absolute Maximum Ratings (Notes 1, 2) ADC0844/ADC0848 ADC0844CCN ADC0848BCN, ADC0848CCN ADC0848BCV, ADC0848CCV Limit Design Tested Design Units Typ Limit Limit Limit (Note 5) (Note 7) (Note 6) (Note 7) ADC0844BCJ (Note 12) ADC0844CCJ (Note 12) Parameter Conditions Typ (Note 5) Tested Limit (Note 6) V V =4.75V, VOUT(0), Logical "0" Output Voltage (Max) CC IOUT=1.6 mA 0.4 0.34 0.4 V A VOUT=0V -0.01 -3 -0.01 -0.3 -3 VOUT=5V 0.01 3 0.01 0.3 3 A ISOURCE, Output Source Current (Min) VOUT=0V -14 -6.5 -14 -7.5 -6.5 mA ISINK, Output Sink Current (Min) VOUT=VCC 16 8.0 16 9.0 8.0 mA ICC, Supply Current (Max) CS =1, VREF Open 1 2.5 1 2.3 2.5 mA IOUT, TRI-STATE Output Current (Max) AC Electrical Characteristics The following specifications apply for VCC = 5VDC, tr = tf = 10 ns unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA = Tj = 25C. Parameter Conditions tC, Maximum Conversion Time (See Graph) tW(WR), Minimum WR Pulse Width (Note 11) Typ (Note 5) Tested Limit (Note 6) Design Limit (Note 7) Units 30 40 60 s 50 150 ns tACC, Maximum Access Time (Delay from Falling Edge of RD to CL = 100 pF (Note 11) Output Data Valid) 145 225 ns t1H, t0H, TRI-STATE Control (Maximum Delay from Rising Edge of RD to Hi-Z State) 125 200 ns CL = 10 pF, RL = 10k (Note 11) tWI, tRI, Maximum Delay from Falling Edge of WR or RD to Reset (Note 11) of INTR 200 400 tDS, Minimum Data Set-Up Time (Note 11) 50 100 tDH, Minimum Data Hold Time (Note 11) 0 50 ns ns ns CIN, Capacitance of Logic Inputs 5 pF COUT, Capacitance of Logic Outputs 5 pF Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to the ground pins. Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V-or VIN > V+) the absolute value of the current at that pin should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four. Note 4: Human body model, 100 pF discharged through a 1.5 k resistor. Note 5: Typical figures are at 25C and represent most likely parametric norm. Note 6: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 7: Design limits are guaranteed by not 100% tested. These limits are not used to calculate outgoing quality levels. Note 8: Total unadjusted error includes offset, full-scale, linearity, and multiplexer error. Note 9: For VIN (-) VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input, which will forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than VCC supply. Be careful during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading. Note 10: Off channel leakage current is measured after the channel selection. Note 11: The temperature coefficient is 0.3%/C. Note 12: This product/package combination is obsolete. Shown for reference only. www.national.com 4 ADC0844/ADC0848 Typical Performance Characteristics Logic Input Threshold Voltage vs. Supply Voltage Output Current vs. Temperature 501632 501631 Power Supply Current vs. Temperature Linearity Error vs. VREF 501634 501633 Conversion Time vs. VSUPPLY Conversion Time vs. Temperature 501635 501636 5 www.national.com ADC0844/ADC0848 Unadjusted Offset Error vs. VREF Voltage 501637 TRI-STATE Test Circuits and Waveforms t1H t1H, CL = 10 pF 501604 501605 tr = 20 ns t0H t0H, CL = 10 pF 501607 501606 www.national.com tr = 20 ns 6 ADC0844/ADC0848 Leakage Current Test Circuit 501608 Timing Diagrams Programming New Channel Configuration and Starting a Conversion 501609 Note 13: Read strobe must occur at least 600 ns after the assertion of interrupt to guarantee reset of INTR . Note 14: MA stands for MUX address. Using the Previously Selected Channel Configuration and Starting a Conversion 7 www.national.com ADC0844/ADC0848 501610 www.national.com 8 www.national.com ADC0848 Functional Block Diagram 501611 ADC0844/ADC0848 9 ADC0844/ADC0848 The actual voltage converted is always the difference between an assigned "+" input terminal and a "-" input terminal. The polarity of each input terminal of the pair being converted indicates which line the converter expects to be the most positive. If the assigned "+" input is less than the "-" input the converter responds with an all zeros output code. A unique input multiplexing scheme has been utilized to provide multiple analog channels. The input channels can be software configured into three modes: differential, single ended, or pseudo-differential. Figure 1 shows the three modes using the 4-channel MUX ADC0844. The eight inputs of the ADC0848 can also be configured in any of the three modes. In the differential mode, the ADC0844 channel inputs are grouped in pairs, CH1 with CH2 and CH3 with CH4. The polarity assignment of each channel in the pair is interchangeable. The single-ended mode has CH1-CH4 assigned as the positive input with the negative input being the analog ground (AGND) of the device. Finally, in the pseudo-differential mode CH1-CH3 are positive inputs referenced to CH4 which is now a pseudo-ground. This pseudo-ground input can be set to any potential within the input common-mode range of the converter. The analog signal conditioning required in transducerbased data acquisition systems is significantly simplified with this type of input flexibility. One converter package can now handle ground referenced inputs and true differential inputs as well as signals with some arbitrary reference voltage. The analog input voltages for each channel can range from 50 mV below ground to 50 mV above VCC (typically 5V) without degrading conversion accuracy. Functional Description The ADC0844 and ADC0848 contain a 4-channel and 8channel analog input multiplexer (MUX) respectively. Each MUX can be configured into one of three modes of operation differential, pseudo-differential, and single ended. These modes are discussed in the Applications Information Section. The specific mode is selected by loading the MUX address latch with the proper address (see Table 1 and Table 2). Inputs to the MUX address latch (MA0-MA4) are common with data bus lines (DB0-DB4) and are enabled when the RD line is high. A conversion is initiated via the CS and WR lines. If the data from a previous conversion is not read, the INTR line will be low. The falling edge of WR will reset the INTR line high and ready the A/D for a conversion cycle. The rising edge of WR, with RD high, strobes the data on the MA0/DB0-MA4/ DB4 inputs into the MUX address latch to select a new input configuration and start a conversion. If the RD line is held low during the entire low period of WR the previous MUX configuration is retained, and the data of the previous conversion is the output on lines DB0-DB7. After the conversion cycle (tC 40 s), which is set by the internal clock frequency, the digital data is transferred to the output latch and the INTR is asserted low. Taking CS and RD low resets INTR output high and outputs the conversion result on the data lines (DB0DB7). Applications Information 1.0 MULTIPLEXER CONFIGURATION The design of these converters utilizes a sampled-data comparator structure which allows a differential analog input to be converted by a successive approximation routine. TABLE 1. ADC0844 MUX ADDRESSING MUX Address CS WR RD MA3 MA2 MA1 MA0 X L L L L X L L H L X L H L L H X L H H L H L H L L L H L H L H L L H H L L H L H H H L H H H L L L H H L H L H H H L L X X X X L NP NP Channel# CH1 CH2 H + H - - + H - + - + - + + - Previous Channel Configuration 10 Single-Ended - - + L MUX Mode Differential - + H AGND - + X = don't care, NP = negative pulse www.national.com + - H NP CH4 + H NP CH3 PseudoDifferential ADC0844/ADC0848 4 Single-Ended 501612 2 Differential 501613 3 Pseudo-Differential 501614 Combined 501615 FIGURE 1. Analog Input Multiplexer Options code for a given input condition. For absolute accuracy (Figure 2b), where the analog input varies between very specific voltage limits, the reference pin can be biased with a time and temperature stable voltage source. The LM385 and LM336 reference diodes are good low current devices to use with these converters. The maximum value of the reference is limited to the VCC supply voltage. The minimum value, however, can be quite small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing less than a 5V output span. Particular care must be taken with regard to noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 LSB equals VREF/256). 2.0 REFERENCE CONSIDERATIONS The voltage applied to the reference input of these converters defines the voltage span of the analog input (the difference between VIN(MAX) and VIN(MIN)) over which the 256 possible output codes apply. The devices can be used in either ratiometric applications or in systems requiring absolute accuracy. The reference pin must be connected to a voltage source capable of driving the minimum reference input resistance of 1.1 k. This pin is the top of a resistor divider string used for the successive approximation conversion. In a ratiometric system (Figure 2a), the analog input voltage is proportional to the voltage used for the A/D reference. This voltage is typically the system power supply, so the VREF pin can be tied to VCC. This technique relaxes the stability requirements of the system reference as the analog input and A/D reference move together maintaining the same output 11 www.national.com ADC0844/ADC0848 3.0 THE ANALOG INPUTS 3.1 Analog Differential Voltage Inputs and CommonMode Rejection The differential input of these converters actually reduces the effects of common-mode input noise, a signal common to both selected "+" and "-" inputs for a conversion (60 Hz is most typical). The time interval between sampling the "+" input and then the "-" inputs is 1/2 of a clock period. The change in the common-mode voltage during this short time interval can cause conversion errors. For a sinusoidal common-mode signal this error is: 501638 where fCM is the frequency of the common-mode signal, Vpeak is its peak voltage value and tC is the conversion time. For a 60 Hz common-mode signal to generate a 1/4 LSB error (5 mV) with the converter running at 40 S, its peak value would have to be 5.43V. This large a common-mode signal is much greater than that generally found in a well designed data acquisition system. TABLE 2. ADC0848 MUX Addressing MUX Address MA4 MA3 MA2 MA1 MA0 CS WR RD Channel CH1 CH2 - + CH3 CH4 - + CH5 CH6 - + CH7 X L L L L L H + X L L L H L H - X L L H L L H + X L L H H L H - X L H L L L H + X L H L H L H - X L H H L L H + X L H H H L H - L H L L L L H L H L L H L H L H L H L L L H L H H L L H H L L L H L H H L H L H L H H H L L H L H H H H L H H H L L L L H H H L L H L H H H L H L L H H L H H L H H H L L L H H H H L H L H H H H H L L H X X X X X L L NP - + - - + - + H - + - + Single-Ended - + - + + - - + - + H NP MUX Mode Differential + H NP CH8 AGND - + H - + - + PseudoDifferential - + + - Previous Channel Configuration X = don't care, NP = negative pulse RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance signal source be required. 3.2 Input Current Due to the sampling nature of the analog inputs, short duration spikes of current enter the "+" input and exit the "-" input at the clock edges during the actual conversion. These currents decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period. Bypass capacitors at the inputs will average these currents and cause an effective DC current to flow through the output resistance of the analog signal source. Bypass capacitors should not be used if the source resistance is greater than 1 k. 4.0 OPTIONAL ADJUSTMENTS 4.1 Zero Error The zero of the A/D does not require adjustment. If the minimum analog input voltage value, VIN(MIN), is not ground, a zero offset can be done. The converter can be made to output 0000 0000 digital code for this minimum input voltage by biasing any VIN (-) input at this VIN(MIN) value. This is useful for either differential or pseudo-differential modes of input channel configuration. The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be measured by 3.3 Input Source Resistance The limitation of the input source resistance due to the DC leakage currents of the input multiplexer is important. A worstcase leakage current of 1 A over temperature will create a 1 mV input error with a 1 k source resistance. An op amp www.national.com 12 4.3 Adjusting for an Arbitrary Analog Input Voltage Range If the analog zero voltage of the A/D is shifted away from ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference should be properly adjusted first. A VIN (+) voltage which equals this desired zero reference plus 1/2 LSB (where the LSB is calculated for the desired analog span, 1 LSB = analog span/256) is applied to selected "+" input and the zero reference voltage at the corresponding "-" input should then be adjusted to just obtain the 00HEX to 01HEX code transition. 4.2 Full-Scale The full-scale adjustment can be made by applying a differential input voltage which is 1 1/2 LSB down from the desired analog full-scale voltage range and then adjusting the magnitude of the VREF input for a digital output code changing from 1111 1110 to 1111 1111. 501616 a) Ratiometric 501617 b) Absolute with a Reduced Span FIGURE 2. Referencing Examples The full-scale adjustment should be made [with the proper VIN (-) voltage applied] by forcing a voltage to the VIN (+) input which is given by: where VMAX=the high end of the analog input range and VMIN=the low end (the offset zero) of the analog range. (Both are ground referenced.) The VREF (or VCC) voltage is then adjusted to provide a code change from FEHEX to FFHEX. This completes the adjustment procedure. 13 www.national.com ADC0844/ADC0848 grounding the V - input and applying a small magnitude positive voltage to the V+ input. Zero error is the difference between actual DC input voltage which is necessary to just cause an output digital code transition from 0000 0000 to 0000 0001 and the ideal 1/2 LSB value (1/2 LSB=9.8 mV for VREF=5.000 VDC). ADC0844/ADC0848 For an example see the Zero-Shift and Span Adjust circuit below. Zero-Shift and Span Adjust (2VVIN5V) 501618 Differential Voltage Input 9-Bit A/D 501619 www.national.com 14 ADC0844/ADC0848 Span Adjust (0VVIN3V) 501620 Protecting the Input 501621 Diodes are 1N914 High Accuracy Comparators 501622 DO = all 1s if VIN(+)>VIN(-) DO = all 0s if VIN(+)<VIN(-) 15 www.national.com ADC0844/ADC0848 Operating with Automotive Ratiometric Transducers 501623 * VIN(-)=0.15 VCC 15% of VCCVXDR85% of VCC www.national.com 16 ADC0844/ADC0848 A Stand Alone Circuit 501625 Note: DUT pin numbers in parentheses are for ADC0844, others are for ADC0848. Start a Conversion without Updating the Channel Configuration 501626 CS *WR will update the channel configuration and start a conversion. CS *RD will read the conversion data and start a new conversion without updating the channel configuration. Waiting for the end of this conversion is not necessary. A CS *WR can immediately follow the CS*RD . 17 www.national.com ADC0844/ADC0848 ADC0844--INS8039 Interface 501627 SAMPLE PROGRAM FOR ADC0844--INS8039 INTERFACE CONVERTING TWO RATIOMETRIC, DIFFERENTIAL SIGNALS ORG JMP ORG MOV 0H BEGIN 10H R1,#0FFH B8 20 89 FF 23 00 MOV ORL MOV R0,#20H P1,#0FFH A,00H 0018 001A 14 50 23 02 CALL MOV CONV A,#02H 001C 001D 18 14 50 INC CALL R0 CONV 0000 04 10 0010 B9 FF 0012 0014 0016 BEGIN: ;START PROGRAM AT ADDR 10 ;MAIN PROGRAM ;LOAD R1 WITH A UNUSED ADDR ;LOCATION ;A/D DATA ADDRESS ;SET PORT 1 OUTPUTS HIGH ;LOAD THE ACC WITH A/D MUX DATA ;CH1 AND CH2 DIFFERENTIAL ;CALL THE CONVERSION SUBROUTINE ;LOAD THE ACC WITH A/D MUX DATA ;CH3 AND CH4 DIFFERENTIAL ;INCREMENT THE A/D DATA ADDRESS ;CALL THE CONVERSION SUBROUTINE ;CONTINUE MAIN PROGRAM ;CONVERSION SUBROUTINE ;ENTRY:ACC--A/D MUX DATA ;EXIT: ACC--CONVERTED DATA 0050 0052 0053 0054 0056 0057 0059 005A 99 FE 91 09 32 53 81 89 01 A0 83 www.national.com CONV: LOOP: ORG ANL MOVX IN JB1 MOVX ORL MOV RET 50H P1,#0FEH @R1,A A,P1 LOOP A,@R1 P1,&01H @R0,A 18 ;CHIP SELECT THE A/D ;LOAD A/D MUX & START CONVERSION ;INPUT INTR STATE ;IF INTR = 1 GOTO LOOP ;IF INTR = 0 INPUT A/D DATA ;CLEAR THE A/D CHIP SELECT ;STORE THE A/D DATA ;RETURN TO MAIN PROGRAM ADC0844/ADC0848 I/O Interface to NSC800 501628 SAMPLE PROGRAM FOR ADC0848--NSC800 INTERFACE 0008 000F NCONV DEL EQU EQU 16 15 001F 3C00 CS ADDTA EQU EQU 1FH 003CH MUXDTA: DB 08H,09H,0AH,0BH DB 0CH,0DH,0EH,0FH LD C,CS ;DELAY 50 sec CONVERSION ;THE BOARD ADDRESS ;START OF RAM FOR A/D ;DATA ;MUX DATA 0000 08 09 0A 0B 0004 0C 0D 0E 0F 0008 0E 1F 000A 06 16 LD B,NCONV 000C HL,MUXDTA 000F 21 0000 11 003C LD LD DE,ADDTA 0012 ED A3 0014 EB EX DE,HL 0015 3E 0F LD A,DEL 0017 3D DEC A ;WAIT 50 sec FOR THE 0018 NZ,WAIT ;CONVERSION TO FINISH 001B C2 0013 ED A2 JP 001D EB EX DE,HL 001E C2 000E JP NZ,STCONV START: STCONV: OUTI ;LOAD A/D'S MUX DATA ;AND START A CONVERSION ;HL=RAM ADDRESS FOR THE ;A/D DATA WAIT: INI ;STORE THE A/D'S DATA ;CONVERTED ALL INPUTS? ;IF NOT GOTO STCONV END Note 15: This routine sequentially programs the MUX data latch in the signal-ended mode. For CH1-CH8 a conversion is started, then a 50 s wait for the A/D to complete a conversion and the data is stored at address ADDTA for CH1, ADDTA + 1 for CH2, etc. 19 www.national.com ADC0844/ADC0848 Physical Dimensions inches (millimeters) unless otherwise noted Ceramic Dual-In-Line Package (J) (product obsolete in this package) NS Package Number J20A Molded Dual-In-Line Package (N) NS Package Number N20A www.national.com 20 ADC0844/ADC0848 Molded Dual-In-Line Package (N) NS Package Number N24D 21 www.national.com ADC0844/ADC0848 Molded Chip Carrier Package (V) NS Package Number V28A www.national.com 22 ADC0844/ADC0848 Notes 23 www.national.com ADC0844/ADC0848 8-Bit P Compatible A/D Converters with Multiplexer Options Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH(R) Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage Reference www.national.com/vref Design Made Easy www.national.com/easy PowerWise(R) Solutions www.national.com/powerwise Solutions www.national.com/solutions Serial Digital Interface (SDI) www.national.com/sdi Mil/Aero www.national.com/milaero Temperature Sensors www.national.com/tempsensors Solar Magic(R) www.national.com/solarmagic Wireless (PLL/VCO) www.national.com/wireless Analog University(R) www.national.com/AU THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION ("NATIONAL") PRODUCTS. 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