Integrated
Circuit
Systems, Inc.
ICS950813
Advance Information
0708—10/10/02
Block Diagram
Recommended Application:
CK-408 clock for Brookdale/Odem/Montara-GM for P4/Banias
processor.
Output Features:
• 3 Differential CPU Clock Pairs @ 3.3V
• 7 PCI (3.3V) @ 33.3MHz including 2 early PCI clocks
• 3 PCI_F (3.3V) @ 33.3MHz
• 1 USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz
• 1 REF (3.3V) @ 14.318MHz
• 5 3V66 (3.3V) @ 66.6MHz
• 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features:
• Provides standard frequencies and additional 3%, 5%
and 10% over-clocked frequencies
• Supports spread spectrum modulation:
No spread, Center Spread (±0.3%, ±0.55%), or Down
Spread (-0.5%, -0.75%)
• Offers adjustable PCI early clock via latch inputs
• Selectable 1X or 2X strength for REF via I2C interface
• Programmable group to group skew
• Linear programmable frequency and spreading %
• Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
• Uses external 14.318MHz crystal
• Stop clocks and functional control available through
I2C interface.
Key Specifications:
•CPU Output Jitter <150ps
• 3V66 Output Jitter <250ps
• CPU Output Skew <100ps
Pin Configuration
Frequency Generator with 200MHz Differential CPU Clocks
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
VDDREF 1 56 REF
X1 2 55 FS1
X2 3 54 FS0
GND 4 53 CPU_STOP#*
PCICLK_F0 5 52 CPUCLKT0
PCICLK_F1 651
CPUCLKC0
*ASEL/PCICLK_F2 7 50 VDDCPU
VDDPCI 8 49 CPUCLKT1
GND 9 48 CPUCLKC1
PCICLK0 10 47 GND
**E_PCICLK1/PCICLK1 11 46 VDDCPU
PCICLK2 12 45 CPUCLKT2
**E_PCICLK3/PCICLK3 13 44 CPUCLKC2
VDDPCI 14 43 MULTSEL*
GND 15 42 IREF
PCICLK4 16 41 GND
PCICLK5 17 40 PWRSAVE#*
PCICLK6 18 39 48MHz_USB/FS2**
VDD3V66 19 38 48MHz_DOT
GND 20 37 VDD48
3V66_2 21 36 GND
3V66_3 22 35 3V66_1/VCH_CLK/FS3**
3V66_4 23 34 PCI_STOP#*
3V66_5 24 33 3V66_0/FS4**
*PD# 25 32 VDD3V66
VDDA 26 31 GND
GND 27 30 SCLK
Vtt_PWRGD# 28 29 SDATA
56-P in 300mi l S SO P
56-P in 240mil T S S O P
*These inputs have 120K internal pull-up resistors to VDD.
**Internal pull-down resistors to ground.
ICS950813
Func t ionali t y Ta ble
CPU AGP PCI
MHz MHz MHz
0 0 100.00 66.67 33.33
0 1 133.33 66.67 33.33
10
200.00 66.67 33.33
11
166.66 66.66 33.33
FS1 FS0
PLL2
PLL1
Spread
Spectrum
3V66 (5:2)
48MHz_USB
48MHz_DOT
X1
X2 XTAL
OSC
3V66
DIVDER
PD#
Vtt_PWRGD#
PWRSAVE#
CPU_STOP#
PCI_STOP#
MULTSEL
SDATA
SCLK
FS (4:0)
I REF
Control
Logic
Config.
Reg.
REF
3V66_0
CPU
DIVDER 3
3
CPUCLKT (2:0)
CPUCLKC (2:0)
Stop
3V66_1/VCH_CLK
PCICLK (6:0)
PCI
DIVDER
3
7
PCICLK_F (2:0)
Stop
Asynchronous AGP/ P CI Frequency Selection Tabl
e
Byte7 Bit5 Byte7 Bit4 AGP Frequency PCI Frequency
0 0 66.00 33.00
0 1 75.43 37.72
1 0 88.00 44.00
1
1
--
--
2
ICS950813
Advance Information
0708—10/10/02
Pin Description
PIN # PIN NAME PIN TYPE DESCRIPTION
1 V DDREF PWR Ref, XTAL po we r supp ly, nominal 3.3 V
2 X1 IN Crystal input,nominally 14.318MHz.
3 X2 OUT Crystal output, Nominally 14 .318MHz
4 GND PWR Ground pin.
5 PCICLK_F0 OUT Free running P CI clock not affected by PCI_STOP# .
6 PCICLK_F1 OUT Free running P CI clock not affected by PCI_STOP# .
7 *ASEL/PCICLK_F2 I/O Asynchro nous AGP/PCI frequency latch input pin / 3.3V PCI free running
clock put. Pull-Up = Main PLL / Pull-Down = Async Fix PLL
8 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V
9 GND PWR Ground pin.
10 PCICLK0 OUT PCI clock output.
11 **E_PCICLK1/PCICLK1 I/O Early/Normal PCI clock output latched at power up.
12 PCICLK2 OUT PCI clock output.
13 **E_PCICLK3/PCICLK3 I/O Early/Normal PCI clock output latched at power up.
14 VDDPCI PWR Power supply for PCI clo cks, nominal 3.3V
15 GND PWR Ground pin.
16 PCICLK4 OUT PCI clock output.
17 PCICLK5 OUT PCI clock output.
18 PCICLK6 OUT PCI clock output.
19 VDD3V66 PWR Power pin for the 3V66 clocks.
20 GND PWR Ground pin.
21 3V66_2 OUT 3.3 V 66.6 6MHz clock output
22 3V66_3 OUT 3.3 V 66.6 6MHz clock output
23 3V66_4 OUT 3.3 V 66.6 6MHz clock output
24 3V66_5 OUT 3.3 V 66.6 6MHz clock output
25 *PD# IN
A
synchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal
are stopped. The latency of the power down will not be greater than 3ms.
26 VDDA PWR 3.3V power for the PLL core.
27 GND PWR Ground pin.
28 Vtt_PWRGD# IN This 3.3V LVTTL input is a level sensitive strobe used to determine when
latch inputs are valid and are ready to be sampled. This is an active low
input.
3
ICS950813
Advance Information
0708—10/10/02
Pin Description (Continued)
PIN # P IN NAME PIN TYPE DESCRIPTION
29 SDATA I/O Da ta pi n for I2C circui try 5V tolerant
30 SCLK IN Clock pin of I2C circuitry 5V tol erant
31 GND PWR Ground pin.
32 VDD3V66 PWR Power pin for the 3V66 clocks.
33 3V66_0/FS4** I/O Frequency select latch input pin / 3.3V 66.66MHz clock output.
34 PCI_STOP#* IN
Stops all PCICLKs besides the PCICLK_F clocks at logi c 0 level, when input
low
35 3V66_1/VCH_CLK/FS3** I/O Frequency select latch input pin / 3. 3V 66.66MHz cl ock output / 48MHz
VCH clock output.
36 GND PWR Ground pin.
37 VDD48 PWR Power for 24 & 48MHz outpu t buffers and fixed PLL core.
38 48MHz_DOT OUT 48MHz clock output.
39 48MHz_USB/FS2** I/O Frequency select latch input pin / 3.3V 48MHz clock output.
40 PWRSAVE#* IN Real Time input pin to change frequency to under-clock entries located in
FS 4:2 = '100'. Clock groups gear ratio will n ot be change during this
operation.
41 GND PWR Ground pin.
42 IREF OUT This pin establishes the reference current for the CPUCLK pairs. This pin
re quires a fixed precisi on resistor tied to ground in order to establish the
appropriate current.
43 MULTSEL* IN 3.3V LVTTL input for selection the current multiplier for CPU outputs
44 CPUCLKC2 OUT
"Complementary" cl ocks of differential pai r CPU outputs. These are current
mo de outputs. External resistors are required for voltage bi as.
45 CPUCLKT2 OUT "True" cl ocks of di fferential pai r CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
46 VDDCPU PWR Supply for CP U clocks, 3.3V nominal
47 GND PWR Ground pin.
48 CPUCLKC1 OUT
"Complementary" cl ocks of differential pai r CPU outputs. These are current
mo de outputs. External resistors are required for voltage bi as.
49 CPUCLKT1 OUT "True" cl ocks of di fferential pai r CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
50 VDDCPU PWR Supply for CP U clocks, 3.3V nominal
51 CPUCLKC0 OUT
"Complementary" cl ocks of differential pai r CPU outputs. These are current
mo de outputs. External resistors are required for voltage bi as.
52 CPUCLKT0 OUT "True" cl ocks of di fferential pai r CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
53 CPU_STOP#* IN Stops all CPUCLK besides the free runni ng cl ocks
54 FS0 IN Frequency select pin.
55 FS1 IN Frequency select pin.
56 REF OUT 14.318 MHz reference clock.
Power Supply
VDD GND
1 4 Xtal, Ref, CPU PLL, digital
37 36 48M Hz, Fix Digital, Fix Analog
46 47 Master clock, CP U An alog
Pin Number Description
4
ICS950813
Advance Information
0708—10/10/02
Frequency Sel ect Table 1
Bit4 Bit3 Bit2 Bit1 Bit0 CPU AGP PCI Spread
FS4 FS3 FS2 FS1 FS0 MHz MHz MHz %
0 0 0 0 0 100.00 66.67 33.33 0.3% Center
0 0 0 0 1 133.33 66.67 33.33 0.3% Center
0 0 0 1 0 200.00 66.67 33.33 0.3% Center
00011
166.66 66.66 33.33 0.3% Center
0 0 1 0 0 100.00 66.67 33.33 0 - 0.5% down
0 0 1 0 1 133.33 66.67 33.33 0 - 0.5% down
0 0 1 1 0 200.00 66.67 33.33 0 - 0.5% down
00111
166.66 66.66 33.33 0 - 0.5% down
0 1 1 0 0 100.00 66.67 33.33 0.55% Center
0 1 1 0 1 133.33 66.67 33.33 0.55% Center
01110
200.00 66.67 33.33 0.55% Center
01111
166.66 66.66 33.33 0.55% Center
0 1 0 0 0 100.00 66.67 33.33 0 - 0.75% down
0 1 0 0 1 133.33 66.67 33.33 0 - 0.75% down
0 1 0 1 0 200.00 66.67 33.33 0 - 0.75% down
01011
166.66 66.66 33.33 0 - 0.75% down
1 0 0 0 0 80.00 53.33 26.67 Spread Off
1 0 0 0 1 106.66 53.33 26.67 Spread Off
1 0 0 1 0 160.00 53.33 26.67 Spread Off
10011
133.33 53.33 26.67 Spread Off
1 0 1 0 0 103.00 68.67 34.33 0.3% Center
1 0 1 0 1 137.33 68.66 34.33 0.3% Center
1 0 1 1 0 206.00 68.67 34.33 0.3% Center
10111
171.66 68.66 34.33 0.3% Center
1 1 0 0 0 105.00 70.00 35.00 0.3% Center
1 1 0 0 1 140.00 70.00 35.00 0.3% Center
1 1 0 1 0 Tristate Tristate Tristate N/A
11011
174.99 70.00 35.00 0.3% Center
1 1 1 0 0 110.00 73.33 36.67 0.3% Center
1 1 1 0 1 146.66 73.33 36.67 0.3% Center
1 1 1 1 0 Test/2 Test/4 Test/8 N/A
11111
183.33 73.33 36.67 0.3% Center
5
ICS950813
Advance Information
0708—10/10/02
Host Swi ng S elect Functi ons
MULTSEL
0
1
Output
Ioh = 4 * I REF
Ioh = 6 * I REF
1.0V @ 50 ohm
0.7V @ 50 ohm
Voh @ Z
Board Target
Reference R,
Rr = 221 1%,
Iref = 5.00mA
Rr = 475 1%,
Iref = 2.32mA
50 ohms
50 ohms
PCI S elect Functions
1 0 1.0ns
1
1
1.5ns
0
0
0ns
0
1
0.5ns
E_PCICLK1 E_PCICLK3 E_PCICLK(3,1)*
Note:
* Approximate values
E_PCICLK3 = 10Kohm resistor.
0 = No resistor
1 = 10Kohm pull-up to V
DD
.
E_PCICLK1 = 10Kohm resistor.
Frequency Select Tabl e 2
FS4 FS3 FS2
000
001
010
011
100
101
110
111
Freqency Select CP U, 3 V66, PCI
Standard Clocking
10% Overclocking
Clocking Mode
Standard Clocking 0.3% Center Spread
Standard Clocking 0 to -0.5%, Down Spread
0.3% Center Spread
Standard Clocking 0 to - 0.75%, Down
Pwr Save Clocking Spread Off
0.3% Center Spread
3% Overclocking 0.3% Center Spread
5% Overclocking 0.3% Center Spread
PWRSAVE# Usage Illustration
Bit4 Bit3 Bit2 Bit1 Bit0 CPU AGP PCI
FS4 FS3 FS2 FS1 FS0 MHz MHz MHz
X X X 0 0 XXX XXX XXX
X X X 0 1 XXX XXX XXX
X X X 1 0 XXX XXX XXX
XXX11XXX XXX XXX
1 0 0 0 0 80.00 53.33 26.67
1 0 0 0 1 106.66 53.33 26.67
1 0 0 1 0 160.00 53.33 26.67
10011
133.33 53.33 26.67
PWRSAVE# = '0'. as
PWRSAV E# is driven to low '0'.
The out put f requenci es of the
CPU, A G P and PCI cl ock wil l
smoothly switch to frequencies
indicat ed by F S (4: 2) = 100. The
f requenci es gear rati o wil l be kept
the same. Notice that the 48MH
z
& REF frequencies will not be
changed. T hi s f unction can be
us ed wit h as ynchronous
A GP / PCI f requenc ies.
PWRSAVE# = '1'. as
P WRSA VE # i s driven bac k to
high '1'. T he output frequenci es
will be driv en bac k t o the
ori ginal p rogra m m ed
f requenci es sm oot hl y . Noti ce
that this operation will only
happen aft er t he PWRS A VE #
has been driv en to '0'. This will
not aff ect power up or I2C
program m ed f requenci es i f t he
P WRSA F E # has been t ied t o a
'1'.
6
ICS950813
Advance Information
0708—10/10/02
Pin # Name 0 1 PWD
Bit 7 - Spread Enabled Spread Spectrum Control RW OFF ON 0
Bi t 6 - CPUCLKT(2:0) Power down mode output level
0= CPU driven in power down
1= undriven RW HIGH LOW 0
Bit 5 35 3V66_1/VCH_CLK/FS3** VCH/66.66 Select RW 66.66 48.00 0
Bit 4 53 CPU_STOP#* Reflects value of pin R Stop Active X
Bit 3 34 PCI_STOP#* Reflects value of pin at power up.
Also can be set . RW Stop Active X
Bit 2 39 FS3 Frequency Selection RW - - X
Bit 1 55 FS1 Frequency Selection R - - X
Bit 0 54 FS0 Frequency Selection R - - X
Note:
Pin #
Name
0
1
PWD
Bit 7 43 MULTSEL* Reflects value of pin R - - x
Bi t 6 - CPUCLKT(2:0) CPU_Stop mode outpu t level
0= CPU driven when stopped
1 = undriven RW HIGH LOW 0
Bit 5 45, 44
CPUCLKT2, CPUCLKC2
(see note) Allow control of output with
assertion of CPU_STOP#. RW Not
Freerun Freerun 0
Bit 4 49, 48
CPUCLKT1, CPUCLKC1
(see note) Allow control of output with
assertion of CPU_STOP#. RW Not
Freerun Freerun 0
Bit 3 52, 51
CPUCLKT0, CPUCLKC0
(see note) Allow control of output with
assertion of CPU_STOP#. RW Not
Freerun Freerun 0
Bit 2 45, 44 CP UCLKT2, CPUCLKC2 Output control RW Disable E nable 1
Bit 1 49, 48 CP UCLKT1, CPUCLKC1 Output control RW Disable E nable 1
Bit 0 52, 51 CP UCLKT0, CPUCLKC0 Output control RW Disable E nable 1
Note:
Pin #
Name
0
1
PWD
Bit 7 56 REF 1X or 2X Strength control RW 1X 2X 0
Bit 6 18 PCICLK6 Output control RW Disable Enable 1
Bit 5 17 PCICLK5 Output control RW Disable Enable 1
Bit 4 16 PCICLK4 Output control RW Disable Enable 1
Bit 3 13 **E _PCICLK3/PCICLK3 Output control RW Disable Enable 1
Bit 2 12 PCICLK2 Output control RW Disable Enable 1
Bit 1 11 **E _PCICLK1/PCICLK1 Output control RW Disable Enable 1
Bit 0 10 PCICLK0 Output control RW Disable Enable 1
Note:
CPUCLK(2:0) can be turned on/off by CPU_STOP#. Refer to table 4.
PCI CLK(6:0) can be turned on/off by PCI_STOP#. Refer to table 3.
Affecte d Pin
TypeCo ntrol Functi on
Bit Control
BYTE
0
BYTE
1
BYTE
2
For PCI_STOP# function, refer to table 3.
Type
Bit Control
Type
Co ntrol Functi on
Affecte d Pin
Bit Control
Co ntrol Functi on
Affecte d Pin
7
ICS950813
Advance Information
0708—10/10/02
Pin #
Name
0
1
PWD
Bit 7 38 48MHz_DOT Output control RW Disable Enable 1
Bit 6 39 48MHz_USB/FS2** Output control RW Disable Enable 1
Bit 5 7 *ASEL/PCICLK_F2 (see note) Allow control of output with
assertion of PCI_STOP#. RW Freerun Not
Freerun 0
Bit 4 6 PCICLK_F1 (see note) Allow control of output with
assertion of PCI_STOP#. RW Freerun Not
Freerun 0
Bit 3 5 PCICLK_F0 (see note) Allow control of output with
assertion of PCI_STOP#. RW Freerun Not
Freerun 0
Bit 2 7 *ASEL/PCICLK_F2 Output control RW Disable Enable 1
Bit 1 6 PCICLK_F1 Output control RW Disable Enable 1
Bit 0 5 PCICLK_F0 Output control RW Disable Enable 1
Note:
Pin #
Name
0
1
PWD
Bit 7 35 FS3 Frequency Selection RW - - X
Bit 6 33 FS4 Frequency Selection RW - - X
Bit 5 33 3V66_0/FS4** Output control RW Disable Enable 1
Bit 4 35 3V66_1/VCH_CLK/FS3** Output control RW Disable Enable 1
Bit 3 24 3V66_5 Output control RW Disable Enable 1
Bit 2 23 3V66_4 Output control RW Disable Enable 1
Bit 1 22 3V66_3 Output control RW Disable Enable 1
Bit 0 21 3V66_2 Output control RW Disable Enable 1
Pin #
Name
0
1
PWD
Bit 7 X PD Mode Iref Mirror Enable Al lo w Iref Mirror to be ON during
Power Down Mod e RW OFF ON 0
Bi t 6 X Reserved Reserved X - - 0
Bit 5 X 3V66(5:2) (See table 6) Allow control of output with
assertion of CPU_STOP#. XFreerunNot
Freerun 0
Bit 4 X 3V66(1:0) (See table 7) Allow control of output with
assertion of CPU_STOP#. XFreerunNot
Freerun 0
Bit 3 RW - - 0
Bit 2 RW - - 0
Bit 1 RW - - 0
Bit 0 RW - - 0
Note:
Pin #
Name
0
1
PWD
Bit 7 X Revision ID Bit 3 R - - 0
Bit 6 X Revision ID Bit 2 R - - 0
Bit 5 X Revision ID Bit 1 R - - 0
Bit 4 X Revision ID Bit 0 R - - 0
Bit 3 X Vendor ID Bit 3 (Reserved) R - - 0
Bit 2 X Vendor ID Bit 2 (Reserved) R - - 0
Bit 1 X Vendor ID Bit 1 (Reserved) R - - 0
Bit 0 X Vendor ID Bit 0 (Reserved) R - - 1
Affecte d Pin
BYTE
6
Functions in Byte 5 of CK408 were intended as a test and debug byte only.
00 = Medium (default), 01 = Low,
11,10 =High
Bit Control
Bit Control
Type
39 48MHz_USB Slew Control
48MHz_DOT Slew Control38
BYTE
4
Affecte d PinBYTE
5
Co ntrol Functi on
Affecte d Pin Bit Con trol
Type
BYTE
3
PCICLK_F(2:0) can be turned on/off by PCI_STOP#. Refer to table 5.
Co ntrol Functi on
Co ntrol Functi on
Type
Bit Control
00 = Medium (default), 01 = Low,
11,10 =High
TypeCo ntrol Functi on
Affecte d Pin
R evision ID Va lue Ba sed on
D evice Re vision
8
ICS950813
Advance Information
0708—10/10/02
Note: See table 8 for Byte 11-14 default information
Pin # Name 0 1 PWD
Bit 7 X (Reserved) (Reserved) RW - - 1
Bit 6 X AEN 3V66/PCI Freq Source Select RW Fix_PLL
Async CPU_PLL
Sync 1
Bit 5 X AFS1 Async Fr eq select bit 1 RW 0
Bit 4 X AFS0 Async Freq select bit 0 RW 0
Bit 3 X (Reserved) (Reserved) RW - - 1
Bit 2 X (Reserved) (Reserved) RW - - 1
Bit 1 X (Reserved) (Reserved) RW - - 1
Bit 0 X
(Reserved)
(Reserved)
RW
-
-
1
Pin #
Name
0
1
PWD
Bit 7 X - (Reserved) X - - 0
Bit 6 X - (Reserved) X - - 0
Bit 5 X - (Reserved) X - - 0
Bit 4 X - (Reserved) X - - 0
Bit 3 X - R - - 1
Bit 2 X - R - - 1
Bit 1 X - R - - 1
Bit 0 X - R - - 1
Note: Byte 8 is for ICS test onl y. Do not write as system damage may occur. Bit(2:0) con tain the readback Byte count.
Pin # Name 0 1 PWD
Bit 7 RW - - 0
Bit 6 RW - - 0
Bit 5 RW - - 0
Bit 4 RW - - 0
Bit 3 RW - - 0
Bit 2 RW - - 0
Bit 1 RW - - 0
Bit 0 RW - - 0
Pin #
Name
0
1
PWD
Bit 7 X - M/N E nab le (Enable access to
Byte 11 - 14) RW HW/B0 Byte
(11-14) 0
Bit 6 X - Unused - - - 0
Bit 5 X RW - - 0
Bit 4 X RW - - 0
Bit 3 X - Unused - - - 1
Bit 2 X - Unused - - - 0
Bit 1 X - Unused - - - 1
Bit 0 X - Unused - - - 0
13, 1 2 ,
11, 10 PCICLK (3:0) Slew Contol
18 , 17 , 16 PCICLK (6:4) Slew Contol
BYTE
8
BYTE
7
BYTE
9Affecte d Pin
7, 6, 5 PCICLK_F (2:0) Slew Con tol
Bit Control
Type
Affecte d Pin
Type
Affecte d Pin
Co ntrol Functi on
Readback Byte Count
Co ntrol Functi on
BYTE
10
Affecte d Pin
Bit Control
Bit Control
Co ntrol Functi on Type
Co ntrol Functi on
35
3V66 (5:2) Skew Approx 250ps per bit (Ref to PCI)
Type
VCHCLK Slew Control 00 = High(default), 01 = Low,
11,10 = Medium
Bit Control
00 (default), 11 = Medium
01 = Low, 10 =High
00 (default), 11 = Medium
10 = Low, 01 =High
00 (default), 11 = Medium
10 = Low, 01 =High
See Async Freq
Selection Table
9
ICS950813
Advance Information
0708—10/10/02
Pin # Name 0 1 PWD
Bi t 7 X - VCO Divider Bit8 RW - - X
Bit 6 X - REF Divider Bit6 RW - - X
Bit 5 X - REF Divider Bit5 RW - - X
Bit 4 X - REF Divider Bit4 RW - - X
Bit 3 X - REF Divider Bit3 RW - - X
Bit 2 X - REF Divider Bit2 RW - - X
Bit 1 X - REF Divider Bit1 RW - - X
Bit 0 X - REF Divider Bit0 RW - - X
Pin # Name 0 1 PWD
Bi t 7 X - VCO Divider Bit7 RW - - X
Bi t 6 X - VCO Divider Bit6 RW - - X
Bi t 5 X - VCO Divider Bit5 RW - - X
Bi t 4 X - VCO Divider Bit4 RW - - X
Bi t 3 X - VCO Divider Bit3 RW - - X
Bi t 2 X - VCO Divider Bit2 RW - - X
Bi t 1 X - VCO Divider Bit1 RW - - X
Bi t 0 X - VCO Divider Bit0 RW - - X
Pin #
Name
0
1
PWD
Bit 7 X - Spread Spectrum Bit7 RW - - X
Bit 6 X - Spread Spectrum Bit6 RW - - X
Bit 5 X - Spread Spectrum Bit5 RW - - X
Bit 4 X - Spread Spectrum Bit4 RW - - X
Bit 3 X - Spread Spectrum Bit3 RW - - X
Bit 2 X - Spread Spectrum Bit2 RW - - X
Bit 1 X - Spread Spectrum Bit1 RW - - X
Bit 0 X - Spread Spectrum Bit0 RW - - X
Pin #
Name
0
1
PWD
Bit 7 X - (Reserved) RW - - X
Bit 6 X - (Reserved) RW - - X
Bit 5 X - Spread Spectrum Bit13 RW - - X
Bit 4 X - Spread Spectrum Bit12 RW - - X
Bit 3 X - Spread Spectrum Bit11 RW - - X
Bit 2 X - Spread Spectrum Bit10 RW - - X
Bit 1 X - Spread Spectrum Bit9 RW - - X
Bit 0 X - Spread Spectrum Bit8 RW - - X
Bit Control
Affecte d Pin Co ntrol Functi on Type
Co ntrol Functi on Type
BYTE
12
Note: Please utilize software utility provi ded by ICS Applicatio n Engineering to configure spread spectrum. Incorrect spread
percen ta ge may ca use system failure.
Affecte d Pin
Bit Control
Note: Please utilize software utility provi ded by ICS Applicatio n Engineering to configure spread spectrum. Incorrect spread
percen ta ge may ca use system failure.
BYTE
13
Type
Co ntrol Functi on Type Bit Control
Note: The decimal representation of these 9 bits (Byte 12 bit[7:0]) and Byte 11 bit [7]) + 8 is equal to the VCO divider value.
BYTE
14 Affecte d Pin Co ntrol Functi on
Bit Control
Note: The decimal representation of these 7 bits (Byte 11 bit[6:0]) + 2 is equal to the RE F divider value.
BYTE
11
Affecte d Pin
10
ICS950813
Advance Information
0708—10/10/02
Table 3
PCI_STOP# I2C Control Table
Note:
When this Byte 0, Bit 3 i s low (0), all PCI clocks are stopped.
Table 4
CPUCLKT/C (2:0) Outputs I2C Control Table
Note: Individual CPUCLK outputs are controlled by Byte 1, Bit 3, 4, and 5.
Table 5
PCICLK_F (2:0) Outputs I2C Control Table
Note:
Individual PCICLK outputs are controlled by Byte 3, Bit 3, 4, and 5.
Table 6
3V66 (5:2) I2C Control Table
Note: Activating Byte 5, Bit 5 will allow CPU_STOP# to control stop of pins 21, 22, 23, and 24.
Table 7
3V66 (1:0) I2C Control Table
Note:
Activating Byte 5, Bi t 4 will al low CPU_STOP# to control sto p of pins 33 and 35.
1
1
Running
0
1
Stopped
1
0
Running
3V66 (1:0)
0
0
Running
1
1
CPU_STOP#
(Pi n 53) Byte 5
Bit 4
Running
Running
0
0
0
1
Running
Stopped
1
0
1
0
Running
1
1
Running
0
0
Stop
0
1
Running
1
1
Running
PCI_STOP#
(Pi n 34) Byte 3
Bit 3, 4, 5 PCICLK (2:0) Outputs
0
1
Running
1
0
Running
CPUCLKT/C (2:0) Outputs
0
0
Stop
1
PCI_STOP#
(Pi n 34)
CPU_STOP#
(Pi n 53) Byte 1
Bit 3, 4, 5
Byte 0 Bit 3
Write Bit
0
0
Byte 0, Bit 3 Read Bit
(I nternal Status)
0
0
0
CPU_STOP#
(Pi n 53) Byte 5
Bit 5 3V6 6 (5:2)
0
1
1
0
1`
1
11
ICS950813
Advance Information
0708—10/10/02
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD + 0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +90°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended per iods may affect product reliability.
El ec t r i c al Char ac t er ist i cs - I nput/ Suppl y/Com m on O utput Par a m et er s
TA = 0 - 70°C; Suppl y Vol tage VDD = 3.3 V + /-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I nput Hi gh V ol tage V
IH
2V
DD
+ 0.3 V
I nput Low V ol tage V
IL
V
SS
- 0.3 0.8 V
I nput Hi gh Current I
IH
V
IN
= V
DD
-5 5 mA
I
IL1
V
IN
= 0 V; Inputs wi t h no pul l -up res i st ors -5 m A
I
IL2
V
IN
= 0 V; Inputs wi t h pul l -up res i st ors -200
Operat i ng Suppl y
Current IDD3.3OP C
L
= F ul l l oad; Sel ect @ 100 MHz 229 280 mA
IDD3.3OP C
L
= F ul l l oad; Sel ect @ 133 MHz 220 280 mA
P owerdown Current I
DD3.3PD
IREF=5 mA 45 mA
I nput F requency F
i
V
DD
= 3.3 V M Hz
P i n Inductanc e L
pin
7nH
C
IN
Logic I nputs 5 pF
C
OUT
Out put pin capac i tance 6 pF
C
INX
X 1 & X2 pi ns 27 30 33 pF
PWRSAVE
Stabilization1,2 TPWRSV From Assertion of PWRSAVE# to 1st
clock. 1.8 ms
Clk St abiliz ation1,2 TSTAB From PowerUp or deas sert i on of
P owerDown to 1st clock . 1.8 ms
t
PZH
,t
PZL
Out put enable del ay (all outputs) 1 10 ns
tPHZ,tPLZ O ut put di sable del ay (all out puts ) 1 10 ns
1Guarant eed by des i gn, not 100% t est ed i n producti on.
2S ee ti m i ng di agram s for buf f ered and un-buf fered t i m i ng requirem ent s.
Delay1
I nput Capaci tance1
I nput Low Current
12
ICS950813
Advance Information
0708—10/10/02
El ectr i ca l Charac t er i stic s - CPUCLKT/C
TA = 0 - 70°C; VDD = 3. 3 V +/-5% ; CL = 10-20 pF (unle s s ot herwi se s p ec i fi ed)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Current S ource Output
Impedance Zo1 VO = Vx3000 Ω
Output Hi gh Vol tage V
OH3
I
OH
= -1 mA 2.4 V
Out pu t Low V ol tage V
OL3
I
OL
= 1 m A 0.4
V ol ta ge High V Hi gh 660 850
V ol tage Lo w V Low -150 150
Ma x Vol tage V ovs 1150
Mi n Volt age V uds -450
Cros si ng V ol tag e (abs) Vcros s(abs) 250 550 mV
Cros sing V ol t a ge (v ar) d-V cross V ari ati on of c ross i ng over al l edges 140 mV
Ri se T i me t
r
V
OL
= 0.175V, V
OH
= 0.525V 175 700 ps
Fall Time t
f
V
OH
= 0.525 V V
OL
= 0 .175V 175 700 ps
Ri se T i me Va ri a ti o n d- t
r
125 ps
F al l Ti m e V ariation d-t
f
125 ps
Duty Cycle dt3 M easurem ent f rom di f ferent i al wavefrom 4 5 55 %
Skew t
sk3
V
T
= 50% 100 ps
Jitter, Cycle to cycle t
jcyc-cyc
1VT = 50 % 150 ps
1Guaranteed by de s i gn, not 100% t est ed i n product i on.
2 I
OWT
can be vari ed and i s se l ect a bl e thru the M ULT SEL pi n.
mV
S tati st ical m e asurem ent on si ng l e end ed
s i gnal usi ng os ci l l oscope m at h func ti on.
M easurem ent on sing l e ended si gnal
us i ng absol ute val ue. mV
El ectri c al Character ist i c s - 3V66
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unl es s ot herwi se specifi ed)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Out pu t Frequ enc y F
O1
MHz
Output I m pedance R
DSP1
1V
O
= V
DD
*(0.5) 12 55 Ω
Out pu t High Voltage V
OH
1I
OH
= -1 mA 2.4 V
Out p ut Low V ol t age V
OL
1I
OL
= 1 m A 0.55 V
Out p ut Hi gh Current I
OH
1V
OH@MIN
= 1.0 V, V
OH@MAX
= 3.135 V -33 -33 m A
Outp ut Lo w Current I
OL
1V
OL @MIN
= 1.95 V, V
OL @MAX
= 0.4 V 30 38 m A
Ris e Time t
r1
1V
OL
= 0.4 V, V
OH
= 2.4 V 0.5 2 ns
Fall Time t
f1
1V
OH
= 2.4 V, V
OL
= 0.4 V 0.5 2 ns
Duty Cy cle dt11V
T
= 1.5 V 45 55 %
Skew t
sk1
1V
T
= 1.5 V 250 ps
Jitter tjcyc-cyc1VT = 1.5 V 3V66 250 ps
1Guarant ee d by desi gn, not 100% test ed in product i on.
13
ICS950813
Advance Information
0708—10/10/02
El ect r i ca l Characteri stics - PCI CLK
TA = 0 - 70°C; VDD = 3.3 V +/-5% ; CL = 1 0-30 pF (unl ess otherwise speci fi ed)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output F requency F
O1
MHz
Output Im pedance R
DSP1
1V
O
= V
DD
*(0.5) 12 55 Ω
Out put High Vol t age V
OH
1I
OH
= -1 mA 2.4 V
Output Low Voltage V
OL
1I
OL
= 1 mA 0. 55 V
Output High Current I
OH
1V
OH@MIN
= 1.0 V, V
OH@MAX
= 3.135 V -3 3 -33 m A
Ou tput Low Current I
OL
1V
OL @MI N
= 1.95 V, V
OL @MAX
= 0. 4 V 30 38 mA
Ri se T i m e t
r1
1V
OL
= 0. 4 V, V
OH
= 2.4 V 0. 5 2 ns
Fall Tim e t
f1
1V
OH
= 2.4 V, V
OL
= 0.4 V 0. 5 2 ns
Du ty Cycle dt11V
T
= 1.5 V 45 55 %
Skew t
sk1
1V
T
= 1.5 V 500 ps
Jitter,cycle to cyc tjcyc-cyc1VT = 1.5 V 250 ps
1Guarante ed by des i gn , not 100% tested in productio n.
El ect r ical Char ac t er i stics - VCH, 48M Hz DO T, 48M Hz, USB
TA = 0 - 70°C; VDD = 3. 3 V +/ -5 % ; CL = 10 -20 pF (unle ss ot h erwise speci fi ed)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output F requency F
O1
MHz
Output Im pedance R
DSP1
1VO = VDD*(0.5) 20 60 Ω
Output Hi gh Vo ltage V
OH
1IOH = -1 mA 2.4 V
Out put Low V ol t age V
OL
1IOL = 1 m A 0. 4 V
Out put High Current I
OH
1V OH@MIN = 1.0 V , V OH@MAX = 3. 1 35 V -29 -23 m A
Ou tput Low Current I
OL
1VOL @MI N = 1. 95 V , V OL @MAX = 0.4 V 29 27 mA
48 DO T Rise Ti me t
r1
1VOL = 0.4 V , V OH = 2.4 V 0.5 1 ns
48DOT Fall Time t
f1
1VOH = 2. 4 V , V OL = 0.4 V 0 . 5 1 ns
VCH 48 USB Rise
Time tr11VOL = 0.4 V , VOH = 2.4 V 1 2 ns
VCH 48 USB Fall Time t
f1
1VOH = 2. 4 V , V OL = 0.4 V 1 2 ns
48 DOT Duty Cycl e d t11VT = 1.5 V 45 55 %
V CH 48 US B Dut y
Cycle dt11VT = 1.5 V 45 55 %
48 DOT Jit t er t
jcyc-cyc
1VT = 1.5 V 350 p s
USB to DOT Skew t
sk1
1VT = 1.5 V (0 OR 180 degrees) 1 ns
VCH Jitter tjcyc-cyc1VT = 1. 5 V 350 ps
1Guarante ed by des i gn , not 100% tested in productio n.
14
ICS950813
Advance Information
0708—10/10/02
Elect r i cal Charact er i stics - REF
TA = 0 - 70°C; V DD = 3. 3 V +/-5%; CL = 10-20 pF (unless ot herwise spec i fi ed)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
S
Out put F requenc y F
O1
MHz
Out put Im pedance R
DSP1
1V
O
= V
DD
*(0.5) 20 60 Ω
Output High Vol t age V
OH
1I
OH
= -1 mA 2.4 V
Out put Low V oltage V
OL
1I
OL
= 1 m A 0. 4 V
Output Hi gh Cu rrent I
OH
1V
OH@MIN
= 1.0 V, V
OH@MAX
= 3.135 V -29 -23 m A
Out put Low Current I
OL
1V
OL @MI N
= 1.95 V , V
OL @MAX
= 0.4 V 29 27 mA
Ri se Time t
r1
1V
OL
= 0.4 V , V
OH
= 2.4 V 1 2 ns
Fall Time t
f1
1V
OH
= 2.4 V, V
OL
= 0.4 V 1 2 ns
Duty Cyc le dt11V
T
= 1.5 V 45 55 %
Jitter tjcyc-cyc1VT = 1.5 V 1000 ps
1Guarant eed by desi gn, not 100% test ed in produc tion.
15
ICS950813
Advance Information
0708—10/10/02
General I2C serial interface information
How to Write:
•Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) star ts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate star t bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) will need to acknowledge each
byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byte
Index Bloc k Write Oper ation
Slave Address D2(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address D3(H)
Index Block Read Operation
Slave Address D2(H)
Beginning Byte = N ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
16
ICS950813
Advance Information
0708—10/10/02
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock,
there is no defined phase relationship between 3V66_1_VCH and other 3V66 clocks. The PCI group should lag 3V66
by the standard skew described below as Tpci.
Un-Buffered Mode 3V66 & PCI Phase Relationship
G r o up t o Gr oup Sk ews at Com mon Tr ans i ti on Edg es: Unb uf f e r ed Mode
GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS
3V 66 t o P CI 1,2 S3V66-PCI 3V66 (5: 0) leads 33MHz PCI 1. 5 2. 55 3.5 ns
1Guarent eed by desi gn, not 100% tested in produc t i on.
2500ps T oleranc e
E_PCICLK to PCICLK Ske w s
GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS
TE_PCI-PCI1 E _P CI CLK 1 (pin 11)= 0
E _PCI CLK 3 (pin 13)= 1 0.3 0.5 0.7 ns
TE_PCI-PCI2 E _P CI CLK 1 (pin 11)= 1
E _PCI CLK 3 (pin 13)= 0 0.8 1.0 1.2 ns
TE_PCI-PCI3 E _P CI CLK 1 (pin 11)= 1
E _PCI CLK 3 (pin 13)= 1 1.3 1.5 1.7 ns
1Guarant eed by desi gn, not 100% tes t ed i n produc t i on.
E_PCICLK to PCICLK1
3V66 (1:0)
3V66 (4:2)
3V66_5
E_PCICLK (3,1)
PCICLK_F (2:0) PCICLK (6:0) Tpci
Tepci
17
ICS950813
Advance Information
0708—10/10/02
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch
low in their ne xt high to low tr ansition. The PCI_ST OP# setup time tsu is 10 ns, f or transitions to be recognized b y the next
rising edge.
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
Asser tion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
CPU_STOP# - Asser tion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
CPU_STOP# Functionality
#POTS_UPCTUPCCUPC
1lamroNlamroN
0tluM*feritaolF
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next tr ansition. When the I 2C Bit 6 of Byte 1 is prog rammed to '0'
the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output drive
current v alues. The CPU will be driv en high with a current value equal to (Mult 0 'select') x (Iref), the CPU# signal will not
be driven . When the I2C Bit 6 of Byte 1 is programmed to '1' then final state of the stopped CPU signals is Low, both CPU
and CPU# outputs will not be driven.
CPU_STOP#
CPUCLKT
CPUCLKC
18
ICS950813
Advance Information
0708—10/10/02
PD# Functionality
#DPTKLCUPCCKLCUPC66V3 F_KLCICP KLCICP TOD/BSU zHM84
1lamroNlamroNzHM66
zHM33
zHM84
0tluM*feritaolFwoLwoLwoL
CPU_STOP# - De-asser tion (transition from logic "0" to logic "1")
De-assertion of CPU_STOP# Waveforms
All CPU outputs that were stopped are to resume normal operation in a glitch free manner . The maximum latency from the
de-asser tion to active outputs is to be defined to be between 2 - 6 CPU clock periods (2 clocks are shown). If the I2C
Bit 6 of Byte 1 is programmed to "1" then the stopped CPU outputs will be driven High within 10 nS of CPU_Stop# de-
assertion.
When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU clocks
must be held lo w on their ne xt high to low transitions . When the I2C Bit 6 of Byte 0 is programmed to '0' CPU cloc ks must
be held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. If Bit 6 of Byte 0 is '1' then both
CPU and CPU# are undriven. Note the example below shows CPU = 133 MHz and Bit 6 of Byte 0 = '0', this diagram and
description is applicable for all valid CPU frequencies 66, 100, 133, 200 MHz.
Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than
one clock cycle to complete.
PD# - Assertion (transition from logic "1" to logic "0")
Power Down Asser tion of Waveforms
CPU_STOP#
CPUCLKT(2:0)
*
CPUCLKT(2:0)TS
CPUCLKC(2:0)
Tdrive_CPU_STOP# <10ns @ 200mV
*Signal TS is CPUCLKT in Tri-State mode
0ns
PD#
CPUCLKT 100MHz
CPUCLKC 100MHz
3V66MHz
PCICLK 33MHz
USB 48MHz
REF 14.318MHz
25ns 50ns
19
ICS950813
Advance Information
0708—10/10/02
Power Down De-Assertion Mode
The power-up latency needs to be less than 1.8mS. this is the time from the de-asseration of the powerdown of the ramping
of the pow er supply until the time that stable clocks are output from the cloc k chip . If the I2C Bit 6 of Byte 0 is programmed
to "1" then the stopped CPU outputs will be driven high within 3 nS of PD# de-asseration.
Test Configuration Diagram
CPU 0.7V Configuration test load board termination
TLA
TLB
MULTSEL Pin must be High
Rs=33 Ohms
5%
Rs=33 Ohms
5%
Rp=49.9 Ohms
1% Rp=49.9 Ohms
1%
Rset=475 Ohms
1% 2pF
5% 2pF
5%
CPUCLKT te
st
point
CPUCLKC tes
t
point
C
LK408
20
ICS950813
Advance Information
0708—10/10/02
Fig. 1
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up,
they act as input pins. The logic level (voltage) that is
present on these pins at this time is read and stored into
a 5-bit inter nal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device
changes the mode of operations for these pins to an
output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K
8.2K
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor .
21
ICS950813
Advance Information
0708—10/10/02
Ordering Information
ICS950813yFT
Designation for tape and reel packaging
Packag e Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit number s)
Prefix
ICS, AV = Standard Device
Example:
ICS95 XXXX y F - T
INDEX
AREA
INDEX
AREA
12
1 2
N
D
h x 45°
h x 45°
E1 E
SEATING
PLANE
SEATING
PLANE
A1
A
e
-C-
- C -
b
.10 (.004) C
.10 (.004) C
c
L
300 mil SSOP Package
MIN MAX MIN MAX
A 2.41 2.80 .095 .110
A1 0.20 0.40 .008 .016
b 0.20 0.34 .008 .0135
c 0.13 0.25 .005 .010
D
E 10.03 10.68 .395 .420
E1 7.40 7.60 .291 .299
e
h 0.38 0.64 .015 .025
L 0.50 1.02 .020 .040
N
α0° 8° 0° 8°
MIN MAX MIN MAX
56 18.31 18.55 .720 .730
10-0034
SYMBOL In Millimeters In Inches
COMM O N DIMENSIO NS COM M O N DIMENSIO NS
SEE VARIATIONS SEE VARIATIONS
0. 635 B A S I C 0. 025 BA S I C
Re fe re nce Doc. : JE DE C P ublication 95 , MO-118
VARIATIONS
SEE VARIATIONS SEE VARIATIONS
ND m m. D (in ch)
22
ICS950813
Advance Information
0708—10/10/02
Ordering Information
ICS950813yGT
Designation for tape and reel packaging
Packag e Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
Example:
ICS95 XXXX y G - T
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1 E
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
c
L
aaa
C
6.10 mm. Body, 0.50 mm. pitch TSSOP
(240 mil) (20 mil)
MIN MAX MIN MAX
A--1.20--.047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b0.170.27.007.011
c 0.09 0.20 .0035 .008
D
E
E1 6.00 6.20 .236 .244
e
L0.450.75.018.030
N
a0°8°0°8°
aaa -- 0.10 -- .004
VARIATIONS
MIN MAX MIN MAX
56 13.90 14.10 .547 .555
10-0039
ND m m . D ( in ch)
Reference Doc.: JEDEC Publication 95, MO-153
0.50 BASIC 0.020 BASIC
SEE VARIATIONS SEE VARIATIONS
SEE VARIATIONS SEE VARIATIONS
8.10 BASIC 0.319 BASIC
SYMBOL In Millimeters In Inches
COMMON DIMENSIONS COMMON DIME NSION
S
