ADUCM330WDCPZ-RL - ANALOG DEVICES

Integrated, Precision Battery Sensor for

Automotive Systems

Data Sheet

ADuCM330/ADuCM331

Rev. C Document Feedback

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FEATURES

High precision analog-to-digital converters (ADCs)

Dual channel, simultaneous sampling

I-ADC 20-bit Σ-Δ (minimizes range switching)

VADC/TADC 20-bit Σ-Δ

Programmable ADC conversion rate from 1 Hz to 8 kHz

On-chip ±5 ppm/°C voltage reference

Current channel

Fully differential, buffered input

Programmable gain (from 4 to 512)

ADC absolute input range: −200 mV to +300 mV

Digital comparator with current accumulator feature

Voltage channel

Buffered, on-chip attenuator for 12 V battery input

Temperature channel

External and on-chip temperature sensor options

Microcontroller

ARM Cortex-M3 32-bit processor

16.384 MHz precision oscillator with 1% accuracy

Serial wire download (SWD) port supporting code

download and debug

Automotive qualified integrated local interconnect network

(LIN) transceiver

LIN 2.2-compatible slave, 100 kb fast download option

SAE J-2602-compatible slave

Low electromagnetic emissions (EME)

High electromagnetic immunity (EMI)

Memory

96 kB (ADuCM330)/128 kB (ADuCM331) Flash/EE memory, ECC

6 kB SRAM, ECC

4 kB data Flash/EE memory, ECC

10,000 cycle Flash/EE endurance

20 year Flash/EE retention

In circuit download via SWD and LIN

On-chip peripherals

Serial port interface (SPI)

General-purpose input/output (GPIO) port

General-purpose timer

Wake-up timer

Watchdog timer

On-chip, power-on reset

Power

Operates directly from 12 V battery supply

Power consumption, 8 mA typical (16 MHz)

Low power monitor mode

Package and temperature range

32-lead, 6 mm × 6 mm LFCSP

Fully specified for −40°C to +115°C operation; additional

specifications for 115°C to 125°C

Qualified for automotive applications

APPLICATIONS

Battery sensing/management for automotive and light

mobility vehicles

Lead acid battery measurement for power supplies in

industrial and medical domains

FUNCTIONAL BLOCK DIAGRAM

20-BIT

ADC

PGA BUF

IIN+

IIN–

RESULT

ACCUMULATOR DIGITAL

COMPARATOR

20-BIT

ADC

MUX BUF

SWDIO SWCLK

VDD

33VDD

AVDD18

DVDD18

AGND

DGND

VSS

IO_VSS

GPIO5/LC_TX/LIN_TX

GPIO4/IRQ1/LC_RX/

ECLKIN/LIN_RX

GPIO3/IRQ0/MOSI/

LC_TX/LIN_TX

GPIO2/MISO

GPIO1/SCLK/LIN_TX

GPIO0/CS/LIN_RX

VBAT

VTEMP

GND_SW

PRECISION ANALOG ACQUISITION

CORTEX-M3

PROCESSOR 16MHz

PREC O S C 1%

LPM

1 × GP TIMER

WD TIMER

W/U TIMER

GPIO PORT

SPI PORT

LIN LIN

LDO

POR

MEMORY

96kB (ADuCM 330) /

128kB (ADuCM 331)

FLASH,

6kB SRAM,

4kB DATA

RESET

TEMPERATURE

SENSOR PRECISION

REFERENCE

ADuCM330/ADuCM331

11153-004

Figure 1.

ADuCM330/ADuCM331 Data Sheet

Rev. C | Page 2 of 16

TABLE OF CONTENTS

Features .............................................................................................. 1

Applicat ions ....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Specifications ..................................................................................... 4

Absolute Maximum Ratings .......................................................... 10

ESD Caution ................................................................................ 10

Pin Configuration and Function Descriptions ........................... 11

Terminology .................................................................................... 13

Applications Information .............................................................. 14

Design Guidelines ...................................................................... 14

Power and Ground Recommendations ................................... 14

Exposed Pad Thermal Recommendations .............................. 14

General Recommendations....................................................... 14

Recommended Schematic ............................................................. 15

Outline Dimensions ....................................................................... 16

Ordering Guide .......................................................................... 16

Automotive Products ................................................................. 16

REVISION HISTORY

10/15—Rev. B to Rev. C

Changes to Table 2 .......................................................................... 10

7/15—Revision B: Initial Version

Data Sheet ADuCM330/ADuCM331

Rev. C | Page 3 of 16

GENERAL DESCRIPTION

The ADuCM330/ADuCM331 are fully integrated, 8 kSPS, data

acquisition systems that incorporate dual, high performance

multichannel sigma-delta (Σ-Δ) ADCs, a 32-bit ARM® Cortex™-M3

processor, and flash. The ADuCM330 has 96 kB program flash

and the ADuCM331 has 128 kB program flash. Both devices

have 4 kB data flash.

The ADuCM330/ADuCM331 are complete system solutions

for battery monitoring in 12 V automotive applications. The

ADuCM330/ADuCM331 integrate all of the required features to

precisely and intelligently monitor, process, and diagnose 12 V

battery parameters including battery current, voltage, and

temperature over a wide range of operating conditions.

Minimizing external system components, the devices are

powered directly from a 12 V battery. On-chip, low dropout (LDO)

regulators generate the supply voltage for two integrated Σ-Δ

ADCs. The ADCs precisely measure battery current, voltage, and

temperature to characterize the state of the health and the charge

of the car battery.

The devices operate from an on-chip, 16.384 MHz high frequency

oscillator that supplies the system clock. This clock is routed

through a programmable clock divider from which the core clock

operating frequency is generated. The devices also contain a

32 kHz oscillator for low power operation.

The analog subsystem consists of an ADC with a programmable

gain amplifier (PGA) that allows the monitoring of various current

and voltage ranges. It also includes a precision reference on chip.

The ADuCM330/ADuCM331 integrate a range of on-chip

peripherals that can be configured under core software control

as required in the application. These peripherals include a SPI

serial input/output communication controller, six GPIO pins, one

general-purpose timer, a wake-up timer, and a watchdog timer.

The ADuCM330/ADuCM331 are specifically designed to operate

in battery-powered applications where low power operation is

critical. The microcontroller core can be configured in normal

operating mode, resulting in an overall system current con-

sumption of <18.5 mA when all peripherals are active. The

devices can also be configured in a number of low power operating

modes under direct program control, consuming <100 μA. The

ADuCM330/ADuCM331 also include a LIN physical interface

for single wire, high voltage communications in automotive

environments.

The devices operate from an external 3.6 V to 18 V (on VDD,

Pin 26) voltage supply and is specified over the −40°C to +115°C

temperature range, with additional typical specifications at +115°C

to +125°C.

The information in this data sheet is relevant for silicon

Revisions L6x, where x represents a number between 0 and 9.

For more information and register details for the ADuCM330/

ADuCM331, see the user guide ADuCM330/ADuCM331

Hardware Reference Manual, UG-716.

ADuCM330/ADuCM331 Data Sheet

Rev. C | Page 4 of 16

SPECIFICATIONS

VDD = 3.6 V to 18 V, fCORE = 16.384 MHz, CD = 0, normal mode, VREF = 1.2 V (internal), unless otherwise noted. Typical values noted

reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise stated.

Parameters not specified in the 115°C to 125°C temperature range of operation are functional within this range but with degraded performance

Table 1.

A = −40°C to +115°C

TA = +115°C to

+125°C1

Parameter Test Conditions/Comments Min Typ Max Typ Unit

ADC SPECIFICATIONS

Conversion Rate1 ADC normal operating mode 4 8000 Hz

ADC low power mode, chop on 1 656 Hz

Current Channel (IIN+/IIN− Only)

No Missing Codes1 Valid for all ADC update rates and

ADC modes

20 Bits

Integral Nonlinearity1, 2 ±10 ±200 ±80 ppm of FSR

Positive Integral

Nonlinearity (INL)1, 2, 3

±200 ±80 ppm of FSR

Negative INL1, 2, 3 ±200 ±80 ppm of FSR

Offset Error1, 4, 5 Chop off, gain = 4, 8, or 16, external

short, after user system calibration at

25°C, 1 LSB = (2.28/gain) μV

−100 ±24 +100 LSBs

Chop off, gain = 32 or 64, external

short, after user system calibration at

25°C, 1 LSB = (2.28/gain) μV

−160 ±48 +160 LSBs

Chop off, gain = 512, external short,

after user system calibration at 25°C,

1 LSB = (2.28/gain) μV

−1400 ±60 +1400 LSBs

Chop on, external short, low power

mode, gain = 64 or 512, processor

powered down

−300 ±50 +250 ±250 nV

Chop on, external short, after user

system calibration at 25°C, VDD = 18 V

−1.5 +1.5 ±0.1 μV

Offset Error Drift1, 2, 6 Chop off, gains of 4 to 64, normal mode ±0.48 LSB/°C

Chop on ±5 ±5 nV/°C

Total Gain Error1, 4, 5, 7 Factory calibrated at a gain of 8,

normal mode

−0.5 ±0.1 +0.5 ±0.15 %

Low power mode −1 ±0.2 +1 ±0.2 %

Gain Drift1, 8 ±3 ±3 ppm/°C

PGA Gain Mismatch Error ±0.1 ±0.1 %

Output Noise1 ADC0CON[11:10], PGASCALE = 0x3

Gain = 64, ADCFLT = 0x08101 0.80 1.3 1.2 μV rms

Gain = 64, ADCFLT = 0x00007 0.75 1.1 μV rms

Gain = 32, ADCFLT = 0x08101 1.00 1.5 1.3 μV rms

Gain = 32, ADCFLT = 0x00007 0.80 1.2 μV rms

Gain = 16, ADCFLT = 0x08101 1.50 2.6 2.0 μV rms

Gain = 16, ADCFLT = 0x00007 1.10 1.9 μV rms

Gain = 8, ADCFLT = 0x08101 2.10 4.1 2.5 μV rms

Gain = 8, ADCFLT = 0x00007 1.60 2.4 μV rms

Gain = 4, ADCFLT = 0x08101 3.40 5.1 4.0 μV rms

Gain = 4, ADCFLT = 0x00007 2.60 3.9 μV rms

Gain = 64, ADCFLT = 0x10001 1.60 3 2.0 μV rms

Gain = 32, ADCFLT = 0x10001 1.70 3.45 2.1 μV rms

Gain = 16, ADCFLT = 0x10001 2.00 4.2 2.2 μV rms

Gain = 8, ADCFLT = 0x10001 2.40 5.1 3.2 μV rms

Gain = 4, ADCFLT = 0x10001 4.35 9.6 5.5 μV rms

ADC low power mode, 221 Hz update

rate, chop enabled, gain = 64

0.6 0.9 0.8 μV rms

Data Sheet ADuCM330/ADuCM331

Rev. C | Page 5 of 16

A = −40°C to +115°C

TA = +115°C to

+125°C1

Parameter Test Conditions/Comments Min Typ Max Typ Unit

Voltage Channel1, 9

No Missing Codes Valid at all ADC update rates 20 Bits

INL From 6 V to 18 V ±10 ±350 ±150 ppm of FSR

Offset Error 4, 5 Chop off, 1 LSB = 27.4 µV, after two point

calibration

−160 ±16 +160 LSB

Chop on, after two-point calibration,

offset measured using 0 V differential

into voltage ADC (VADC) auxiliary pins

−16 ±4.8 +16 ±4.8 LSB

Offset Error Drift6 Chop off ±0.48 ±1 LSB/°C

Total Gain Error4, 5, 7 Includes resistor mismatch −0.25 ±0.06 +0.25 ±0.1 %

A = −25°C to +65°C −0.15 ±0.03 +0.15 %

Gain Drift8 Includes resistor mismatch drift ±3 ±3 ppm/°C

Output Noise10 10 Hz update rate, chop on 50 80 µV rms

ADCFLT = 0x00007 180 270 µV rms

ADCFLT = 0x08101 280 350 300 µV rms

ADCFLT = 0x10001 400 730 470 µV rms

Temperature Channel1

No Missing Codes Valid at all ADC update rates 20 Bits

INL ±10 ±60 ±15 ppm of FSR

Offset Error4, 11

Chop off, 1 LSB = 1.14 V (unipolar

mode), after two point calibration

−160 ±48 +160 LSB

Offset Error4 Chop on −80 +16 +80 ±16 LSB

Offset Error Drift Chop off ±0.48 ±0.48 LSB/°C

Total Gain Error4, 11 −0.25 ±0.06 +0.25 ±0.10 %

Gain Drift8 3 3 ppm/°C

Output Noise 1 kHz update rate, ADCFLT = 0x00007 7.5 11.25 10 µV rms

ADC SPECIFICATIONS, ANALOG

INPUT

PGASCALE[11:10] = 0x2

Current Channel1

Absolute Input Voltage

Range

Applies to both IIN+ and IIN− −200 +300 mV

Input Voltage Range12

Gain = 4, limited by absolute input

voltage range

±300 mV

Gain = 8 ±150 mV

Gain = 32 ±37.5 mV

Input Leakage Current13 −3 +3 ±0.2 nA

Input Offset Current13 0.2 0.6 0.4 nA

Voltage Channel

Absolute Input Voltage

Range1

Voltage ADC specifications are valid in

this range

6 18 V

Input Voltage Range1 0 to 28.8 V

VBAT Input Current VBAT = 18 V 5 9 13 11 µA

Temperature Channel VREF = (AVDD18, GND_SW)

Absolute Input Voltage

Range1, 14

100 1500 mV

Input Voltage Range1 0 to 1.4 V

VTEMP Input Current1 2.5 10 nA

VOLTAGE REFERENCE

Internal Reference 1.2 1.2 V

Power-Up Time1 0.5 0.5 ms

Initial Accuracy1 Measured at TA = 25°C −0.15 +0.15 %

Temperature Coefficient1, 15 −20 ±5 +20 ±8 ppm/°C

Long-Term Stability16 100 ppm/1000 hr

ADuCM330/ADuCM331 Data Sheet

Rev. C | Page 6 of 16

TA = −40°C to +115°C

TA = +115°C to

+125°C1

Parameter Test Conditions/Comments Min Typ Max Typ Unit

ADC DIAGNOSTICS

AVDD18/136 Accuracy1, 2, 17 At any gain setting 12 14 13 mV

Voltage Attenuator Current

Source Accuracy

Differential voltage increase on the

attenuator when current is on

2.4 3.2 2.8 V

RESISTIVE ATTENUATOR

Divider Ratio 24

Resistor Mismatch Drift Implicit in the voltage channel gain error

specification

±3 ppm/°C

ADC GROUND SWITCH

Resistor to Ground 45 60 75 kΩ

TEMPERATURE SENSOR1, 18 Processor in hibernate mode

Accuracy TA = 115°C to 125°C −3.5 ±1 +3.5 ±1 °C

TA = −40°C to +115°C −3 ±1 +3 °C

TA = −25°C to +85°C −2.5 ±0.5 +2.5 °C

TA = −10°C to +55°C −2 ±0.5 +2 °C

POWER-ON RESET (POR)1 Refers to voltage at the VDD pin

POR Trip Level 2.8 3.1 3.4 3.3 V

POR Hysteresis 0.1 V

LOW VOLTAGE FLAG (LVF)

LVF Level Refers to voltage at the VDD pin 2.6 2.75 3.00 V

WATCHDOG TIMER (WDT)

Shortest Timeout Period 32,768 Hz clock with a prescaler of 1 30.5 30.5 µs

Longest Timeout Period 32,768 Hz clock with a prescaler of 4096 8192 8192 sec

FLASH/EE MEMORY

Endurance19 10,000 Cycles

Data Retention20 20 Years

LOGIC INPUTS1

Input Voltage

Low, VINL 0.4 V

High, VINH 2.0 V

LOGIC OUTPUTS1 All logic outputs, measured with

±1 mA load

Output Voltage

High, VOH 33VDD −

0.4

Low, VOL 0.4 V

DIGITAL INPUTS1 All digital inputs except RESET,

SWDIO, and SWCLK

Logic 1 Input Current (Leakage

Current)

INH

= 3.3 V

±1

±10

µA

Logic 0 Input Current (Leakage

Current)

VINL = 0 V ±1 ±10 µA

Input Capacitance 10 pF

ON-CHIP OSCILLATORS

Low Frequency Oscillator

(LFOSC)

32,768 Hz

Accuracy ±5 %

After a calibration from HFOSC

−6

High Frequency Oscillator

(HFOSC)

16.384 MHz

Accuracy (LINCAL)1, 21 −0.75 ±0.5 +0.75 %

Accuracy (High Precision

Mode)

−1 +1 %

Accuracy (Low Precision

Mode)

−3 +3 %

Data Sheet ADuCM330/ADuCM331

Rev. C | Page 7 of 16

TA = −40°C to +115°C

TA = +115°C to

+125°C1

Parameter Test Conditions/Comments Min Typ Max Typ Unit

PROCESSOR START-UP TIME1

At Power-On Includes kernel power-on execution

time, VDD drops to < 0.8 V

18 ms

Brownout VDD drops below power on reset

voltage but not below 0.8 V

1.15 ms

After Reset Event Includes kernel power-on execution

time

1.25 ms

Wake-Up from LIN

0.15

LIN INPUT/OUTPUT GENERAL1

Baud Rate 1000 20,000 Bits/sec

VDD Supply voltage range for which the

LIN interface is functional

7 18 V

LIN Comparator Response

Time

38 90 µs

LIN DC PARAMETERS

ILIN_DOM_MAX Current limit for driver when LIN bus is

in dominant state, VBAT = VBAT

(maximum)

40 200 mA

ILIN_PAS_REC1 Driver off, 7.0 V < VBUS < 18 V, VDD =

VLIN − 0.7 V

20 µA

ILIN_PAS_DOM1 Input leakage, VLIN = 0 V, VBAT = 12 V,

driver off

−1 mA

ILIN_NO_GND1, 22 Control unit disconnected from

ground, GND = VDD, 0 V < VLIN <

18 V, VBAT = 12 V

−1 +1 mA

BUS_NO_BAT

VBAT disconnected, VDD = GND, 0 V <

VBUS < 18 V

µA

VLIN_DOM1 LIN receiver dominant state, VDD > 7.0 V 0.4 × VDD V

VLIN_REC1 LIN receiver recessive state, VDD > 7.0 V 0.6 VDD V

VLIN_CNT1 VLIN_CNT = (VTH_DOM + VTH_REC)/2, VDD > 7.0 V 0.475 ×

VDD

0.5 ×

VDD

0.525 ×

VDD

VHYS1 VHYS = VTH_REC − VTH_DOM 0.175 ×

VDD

VLIN_DOM_DRV_LOSUP1 LIN dominant output voltage, VDD =

7.0 V

RL = 500 Ω 1.2 V

RL = 1000 Ω 0.6 V

VLIN_DOM_DRV_HISUP1 LIN dominant output voltage, VDD =

18 V

RL = 500 Ω 2 V

RL = 1000 Ω 0.8 V

VLIN_RECESSIVE1 LIN recessive output voltage 0.8 × VDD V

VBAT Shift1, 22 0 0.115 ×

VDD

GND Shift1, 22 0 0.115 ×

VDD

RSLAVE Slave termination resistance 20 30 47 30 kΩ

VSERIAL_DIODE1 Voltage drop at the serial diode,

DSer_Int

0.4 0.7 1 V

ADuCM330/ADuCM331 Data Sheet

Rev. C | Page 8 of 16

TA = −40°C to +115°C

TA = +115°C to

+125°C1

Parameter Test Conditions/Comments Min Typ Max Typ Unit

LIN AC PARAMETERS1 Bus load conditions (CBUS||RBUS):

1 nF||1 kΩ, 6.8 nF||660 Ω, 10 nF||500 Ω

D1 Duty Cycle 1 0.396

THREC(MAX) = 0.744 × VBAT

THDOM(MAX) = 0.581 × VBAT

VSUP = 7.0 V to 18 V, tBIT = 50 µs

D1 = tBUS_REC(MIN)/(2 × tBIT)

D2 Duty Cycle 2 0.581

THREC(MIN) = 0.284 × VBAT

THDOM(MIN) = 0.422 × VBAT

VSUP = 7.0 V to 18 V, tBIT = 50 µs

D2 = tBUS_REC(MAX)/(2 × tBIT)

D322

THREC(MAX) = 0.778 × VBAT

0.417

THDOM(MAX) = 0.616 × VBAT

VDD = 7.0 V to 18 V

tBIT = 96 µs

D3 = tBUS_REC(MIN)/(2 × tBIT)

D422 THREC(MIN) = 0.389 × VBAT 0.590

THDOM(MIN) = 0.251 × VBAT

VDD = 7.0 V to 18 V

tBIT = 96 µs

D4 = tBUS_REC(MAX)/(2 × tBIT)

tRX_PDR22 Propagation delay of receiver 6 µs

tRX_SYM22 Symmetry of receiver propagation

delay rising edge, with respect to

falling edge (tRX_SYM = tRF_PDR − tRX_PDF)

−2 +2 µs

PACKAGE THERMAL

SPECIFICATIONS

Thermal Impedance (θJA)23 JEDEC 4-layer board 40 °C/W

POWER REQUIREMENTS

Power Supply Voltages

VDD (Pin 26) 3.6 18 V

DVDD33 (Pin 21) 3.3 3.3 V

AVDD18 (Pin 19) 1.88 1.88 V

DVDD18 (Pin 22) 1.88 1.88 V

POWER CONSUMPTION

IDD (Processor Normal

Mode)24

CD0 (PCLK = 16 MHz), 16 MHz 1% mode,

ADCs off, reference buffer off, executing

code from program flash

8 17 9 mA

CD1 (PCLK = 8 MHz), 16 MHz 1% mode,

ADCs off, reference buffer off, executing

code from program flash

CD0 (PCLK = 16 MHz), 16 MHz 1% mode,

ADCs on, reference buffer on, executing

code from program flash

9.5 18.5 10 mA

IDD (Processor Powered

Down)

Precision oscillator off, ADC off,

external LIN master pull-up resistor

present, measured with wake-up and

watchdog timers clocked from low

power oscillator, maximum value is at

105°C, and VDD = 18 V

60 100 µA

IDD LIN 500 µA

IDD IADC

Gain = 4, 8, or 16

700

µA

Gain = 32 or 64 800 µA

LPM, gain = 64 350 µA

Data Sheet ADuCM330/ADuCM331

Rev. C | Page 9 of 16

TA = −40°C to +115°C

TA = +115°C to

+125°C1

Parameter Test Conditions/Comments Min Typ Max Typ Unit

IDD ADC1 VADC 550 µA

IDD Internal Reference (1.2 V) 150 µA

IDD HFOSC Reduction from 1% to 3% mode 50 µA

1 Not guaranteed by production test, but by design and/or characterization data at production release.

2 Valid for PGA current ADC gain settings of 4, 8, 16, 32, and 64.

3 System chopping enabled.

4 These specifications include temperature drift.

5 A user system calibration removes this error at a given temperature (and at a given gain for the current channel).

6 The offset error drift is included in the offset error. This typical specification is an indicator of the offset error due to temperature drift. This typical value is the mean of

the temperature drift characterization data distribution.

7 Includes internal reference temperature drift.

8 The gain drift is included in the total gain error. This typical specification is an indicator of the gain error due to the temperature drift in the ADC. This typical value is

the mean of the temperature drift characterization data distribution.

9 Voltage channel specifications include resistive attenuator input stage, unless otherwise stated.

10 RMS noise is referred to voltage attenuator input; for example, at fADC = 1 kHz, the typical rms noise at the ADC input is 7.5 µV, scaling by the attenuator (24) yields

these input referred noise figures.

11 Valid after an initial self calibration.

12 It is possible to extend the ADC input range by up to 10% by modifying the factory set value of the gain calibration register or using system calibration. This approach

can also be used to reduce the ADC input range (LSB size).

13 Valid for a differential input less than 10 mV.

14 The absolute value of the voltage of VTEMP and GND_SW must be 100 mV (minimum) for accurate operation of the temperature analog-to-digital converter (T-ADC).

15 Measured using box method.

16 The long-term stability specification is accelerated and noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.

17 Valid after an initial self gain calibration.

18 Die temperature.

19 Endurance is qualified to 10,000 cycles, as per JEDEC Standard 22 Method A117 and measured at −40°C, +25 °C, and +115°C. Typical endurance at +25°C is 100k cycles.

20 Data retention lifetime equivalent at junction temperature (TJ) = 85°C, as per JEDEC Standard 22 Method A117. Data retention lifetime derates with junction temperature.

21 Measured with LIN communication active.

22 These specifications are not production tested but are supported by LIN compliance testing.

23 Thermal impedance can be used to calculate the thermal gradient from ambient to die temperature.

24 Typical additional supply current consumed during Flash/EE memory program and erase cycles is 3 mA and 1 mA, respectively.

ADuCM330/ADuCM331 Data Sheet

Rev. C | Page 10 of 16

ABSOLUTE MAXIMUM RATINGS

The ADuCM330/ADuCM331 operate directly from the 12 V

battery supply and is fully specified over the −40°C to +115°C

temperature range, unless otherwise noted.

Table 2.

Parameter Rating

AGND to DGND to VSS to IO_VSS −0.3 V to +0.3 V

VBAT to AGND −22 V to +40 V

VDD to VSS −0.3 V to +40 V

LIN to IO_VSS −18 V to +40 V

Digital Input/Output Voltage to DGND −0.3 V to DVDD33 + 0.3 V

ADC Inputs to AGND

−0.3 V to AVDD18 + 0.3 V

ESD (Human Body Model) Rating

HBM-ADI0082 (Based on ANSI/ ESD

STM5.1-2007)

All Pins Except LIN and VBAT ±2.0 kV

LIN

±6 kV

VBAT ±4 kV

IEC 61000-4-2

LIN and VBAT ±8 kV

Storage Temperature Range −55°C to +150°C

Junction Temperature

Transient

150°C

Continuous 130°C

Lead Temperature

Soldering Reflow1 260°C

Lifetime2

Normal Mode 480 hours at −40°C

1600 hours at +23°C

5200 hours at +60°C

640 hours at +85°C

80 hours at +105°C

Standby Mode 12,648 hours at −40°C

60,000 hours at +25°C

50,000 hours at +50°C

1 JEDEC standard J-STD-020.

2 Using an activation energy of 0.7 eV, verified using high temperature

operating life (HTOL) at 125°C for 1000 hours.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

ESD CAUTION

Data Sheet ADuCM330/ADuCM331

Rev. C | Page 11 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES

1. DNC = DO NOT CONNECT. DO NO T CO NNE CT THIS P IN.

2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE

SOLDERE D TO GROUND FO R THERM AL REAS O NS .

1DNC

2DGND

3DVDD18

4DVDD33

533VDD

6AVDD18

7AGND

8VREF

RESET

SWDIO

SWCLK

GPIO0/CS/LIN_RX

GPIO1/SCLK/LIN_TX

GPIO2/MISO

GPIO3/IRQ0/MOSI/LC_TX/LIN_TX

GPIO4/IRQ1/LC_RX/ECLKIN/LIN_RX

GND_SW

VTEMP

IIN+_AUX

IIN+

IIN–

IIN–_AUX

VINP_AUX

VINM_AUX

GPIO5/LC_TX/LIN_TX

DGND

VSS

IO_VSS

LIN

VBAT

VDD

DGND

TOP VIEW

(No t t o Scal e)

ADuCM330/

ADuCM331

11153-005

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Type 1 Description

1 RESET I Reset Input Pin. Active low. This pin has an internal pull-up resistor to 33VDD.

2 SWDIO I/O Cortex-M3 Debug Data Input and Output Channel. At power-on, this output is disabled and

pulled high via an internal pull-up resistor. This pin can be left unconnected when not in use.

3 SWCLK I Cortex-M3 Debug Clock Input. This is an input pin only and has an internal pull-up resistor. This

pin can be left unconnected when not in use.

4 GPIO0/CS/LIN_RX I/O General-Purpose Input/Output 0 (P0.0) (GPIO0). By default, this pin is configured as an input.

The pin has an internal 25 kΩ pull-up resistor to 33VDD and, when not in use, can be left

unconnected.

Chip Select (CS). When configured, this pin also operates the SPI chip select input.

Local Interconnect Network Receiver (Rx) (LIN_RX). This pin can be configured as the Rx pin for

LIN frames in external transceiver mode.

5 GPIO1/SCLK/LIN_TX I/O General-Purpose Input/Output 1 (P0.1) (GPIO1). By default, this pin is configured as an input.

This pin is used by the kernel in external mode. See the ADuCM330/ADuCM331 hardware

reference manual for more information. The pin has an internal 25 kΩ pull-up resistor to 33VDD

and, when not in use, can be left unconnected.

Serial Clock Input (SCLK). When configured, this pin operates the SPI serial clock input.

Local Interconnect Network Transmitter (Tx) (LIN_TX). This pin can be configured as the Tx pin

for LIN frames in external transceiver mode.

6 GPIO2/MISO I/O General-Purpose Input/Output 2 (P0.2) (GPIO2). By default, this pin is configured as an input. The pin

has an internal 25 kΩ pull-up resistor to 33VDD and, when not in use, can be left unconnected.

Master Input/Slave Output (MISO). When configured, this pin also operates the SPI master

input/slave output.

7 GPIO3/IRQ0/MOSI/

LC_TX/LIN_TX

I/O General-Purpose Input/Output 3 (P0.3) (GPIO3). By default, this pin is configured as an input.

This pin is used by the kernel in external mode. See the ADuCM330/ADuCM331 hardware

reference manual for more information. The pin has an internal 25 kΩ pull-up resistor to 33VDD

and, when not in use, can be left unconnected.

Interrupt Request (IRQ0). This pin can also be configured as External Interrupt Request 0.

Master Output/Slave Input (MOSI). This pin can be configured as an SPI master output/slave

input pin.

LIN Conformance Tx (LC_TX). This pin can be connected to the LIN physical Tx for LIN

conformance testing.

Local Interconnect Network Tx (LIN_TX). This pin can also be connected as the Tx pin for LIN

frames in external transceiver mode.

ADuCM330/ADuCM331 Data Sheet

Rev. C | Page 12 of 16

Pin No. Mnemonic Type 1 Description

8 GPIO4/IRQ1/LC_RX/

ECLKIN/LIN_RX

I/O General-Purpose Input/Output 4 (P0.4) (GPIO4). By default, this pin is configured as an input.

This pin is used by the kernel in external mode. See the ADuCM330/ADuCM331 hardware

reference manual for more information. The pin has an internal 25 kΩ pull-up resistor to 33VDD

and, when not in use, can be left unconnected.

Interrupt Request (IRQ1). This pin can be configured as External Interrupt Request 1.

LIN Conformance Rx (LC_RX). This pin can be connected to LIN physical RX for LIN conformance

testing.

External Clock (ECLKIN). This pin can be configured as the external clock input.

Local Interconnect Network Rx (LIN_RX). This pin can be configured as the receiving pin for LIN

frames in external transceiver mode.

9 GND_SW I Switch to Internal Analog Ground Reference. This pin is the negative input for the external

temperature channel.

10 VTEMP I External Pin for Negative Temperature Coefficient (NTC)/Positive Temperature Coefficient (PTC)

Temperature Measurement.

11 IIN+_AUX S Auxiliary IIN+ Pin. Connect this pin to AGND.

IIN+

Positive Differential Input for Current Channel.

13 IIN− I Negative Differential Input for Current Channel.

14 IIN−_AUX S Auxiliary IIN− Pin. Connect this pin to AGND.

15 VINP_AUX S Auxiliary Input Voltage Positive Channel. Connect this pin to AGND.

16 VINM_AUX S Auxiliary Input Voltage Negative Channel. Connect this pin to AGND.

17 VREF S Voltage Reference Pin. Connect this pin via a 470 nF capacitor to ground. This pin can also be

used to input an external voltage reference. This pin cannot be used to supply an external circuit.

18 AGND S Ground Reference for On-Chip Precision Analog Circuits.

19 AVDD18 S Supply from Analog LDO. Do not connect this pin to an external circuit.2

20 33VDD S 3.3 V Supply. Connect to Pin 21. Do not connect this pin to an external circuit.2

21 DVDD33 S 3.3 V Supply. Connect to Pin 20. Do not connect this pin to an external circuit.2

22 DVDD18 S 1.8 V Supply. Do not connect this pin to an external circuit.2

23 DGND S Ground Reference for On-Chip Digital Circuits.

24 DNC Do Not Connect. This pin is internally connected; therefore, do not externally connect to this pin.

25 DGND S Ground Reference for On-Chip Digital Circuits.

26 VDD S Battery Power Supply for On-Chip Regulator.

27 VBAT S Battery Voltage Input fo Resistor Divider.

28 LIN I/O Local Interconnect Network (LIN) Physical Interface Input/Output.

29 IO_VSS S Ground Reference for the LIN Pin.

30 VSS S Ground Reference. This is the ground reference for the internal voltage regulators.

31 DGND S Ground Reference for On-Chip Digital Circuits.

32 GPIO5/LC_TX/LIN_TX I/O General-Purpose Input/Output 5 (P0.5) (GPIO5). By default, this pin is configured as an input.

This pin is checked by the kernel on every reset. See the ADuCM330/ADuCM331 hardware

reference manual for further information. The pin has an internal 25 kΩ pull-up resistor to

33VDD and, when not in use, can be left unconnected.

LIN Conformance Tx (LC_TX). This pin can be connected to the LIN physical Tx for LIN

conformance testing.

Local Interconnect Network Tx (LIN_TX). This pin can be configured as the Tx pin for LIN frames

in external transceiver mode.

33 EPAD Exposed Pad. It is recommended that the exposed pad be soldered to ground for thermal reasons.

1 I is input, O is output, and S is supply.

2 Using the 1.8 V or 3.3 V supply to power an external circuit can have POR, EMC, and self heating implications. Device evaluation and testing completed without an

external load attached.

Data Sheet ADuCM330/ADuCM331

Rev. C | Page 13 of 16

TERMINOLOGY

Conversion Rate

The conversion rate specifies the rate at which an output result

is available from the ADC, after the ADC has settled.

The Σ-Δ conversion techniques used on this device means that

although the ADC front-end signal is oversampled at a relatively

high sample rate, a subsequent digital filter is used to decimate

the output, giving a valid 20-bit data conversion result at output

rates from 1 Hz to 8 kHz.

Note that, when software switches from one input to another

(on the same ADC), the digital filter must first be cleared and

then allowed to average a new result. Depending on the con-

figuration of the ADC and the type of filter, this averaging can

require multiple conversion cycles.

Integral Nonlinearity (INL)

INL is the maximum deviation of any code from a straight line

passing through the endpoints of the transfer function. The

endpoints of the transfer function are zero scale, a point ½ LSB

below the first code transition, and full scale, a point ½ LSB

above the last code transition (111…110 to 111…111). The

error is expressed as a percentage of full scale.

Positive INL is defined as the deviation from a straight line

through ½ LSB above midscale code transition to ½ LSB above

the last code transition.

Negative INL is defined as the deviation from a straight line

from a point ½ LSB below the first code transition to a point

½ LSB above the midscale code transition.

No Missing Codes

No missing codes is a measure of the differential nonlinearity of

the ADC. The error is expressed in bits and specifies the number

of codes (ADC results) as 2N bits, where N = no missing codes,

guaranteed to occur through the full ADC input range.

Offset Error

Offset error is the deviation of the first code transition ADC

input voltage from the ideal first code transition.

Offset Error Drift

Offset error drift is the variation in absolute offset error with

respect to temperature. This error is expressed as LSB/°C or nV/°C.

Gain Error

Gain error is a measure of the span error of the ADC. It is a

measure of the difference between the measured and the ideal

span between any two points in the transfer function.

Output Noise

The output noise is specified as the standard deviation (or 1 × Σ)

of ADC output codes distribution collected when the ADC

input voltage is at a dc voltage. It is expressed as μV rms or

nV rms. The output, or rms noise, is used to calculate the

effective resolution of the ADC as defined by the following

equation:

Effective Resolution = log2(Full-Scale Range/rms Noise) bits

The peak-to-peak noise is defined as the deviation of codes that fall

within 6.6 × Σ of the distribution of ADC output codes collected

when the ADC input voltage is at dc. The peak-to-peak noise is

therefore calculated as 6.6 × the rms noise.

The peak-to-peak noise can be used to calculate the ADC (noise

free, code) resolution for which there is no code flicker within a

6.6 × Σ limit as defined by the following equation:

Noise Free Code Resolution = log2(Full-Scale Range/Peak-

to-Peak Noise) bits

ADuCM330/ADuCM331 Data Sheet

Rev. C | Page 14 of 16

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting design and layout of the ADuCM330/ADuCM331

on a printed circuit board (PCB), it is recommended that the

designer become familiar with the following guidelines that

describe any special circuit considerations and layout

requirements needed.

POWER AND GROUND RECOMMENDATIONS

Place capacitors that are connecting to the ADuCM330/

ADuCM331 as close to the pins of the device as possible, with

minimal trace length.

Capacitors connected to the 33VDD, AVDD18, and DVDD18

pins must have a low equivalent series resistance (ESR) rating.

All components must be rated accordingly to the temperature

range expected by the application.

EXPOSED PAD THERMAL RECOMMENDATIONS

It is required that the exposed pad on the underside of the

ADuCM330/ADuCM331 be connected to ground to achieve

the best electrical and thermal performance. It is recommended

that the user connect an exposed continuous copper plane on

the PCB to the ADuCM330/ADuCM331 exposed pad, and that

the copper plane has several vias to achieve the lowest possible

resistive thermal path for heat dissipation to flow through the

bottom of the PCB. It is recommended that these vias be solder

filled or plugged.

GENERAL RECOMMENDATIONS

It is highly recommended to use the schematic given with

component values specified (see Figure 3). The component

values shown in Figure 3 are chosen from the characterization

tests and evaluated for optimum performance of the ADuCM330/

ADuCM331.

Configure the GPIOs as inputs with pull-up resistors enabled to

obtain the lowest possible current consumption in hibernate mode.

Set the Cortex-M3 core clock speed to the minimum required

to meet the application requirements.

Data Sheet ADuCM330/ADuCM331

Rev. C | Page 15 of 16

RECOMMENDED SCHEMATIC

Figure 3 shows external components recommended for proper operation of the ADuCM330/ADuCM331.

11153-003

*LIN 2.2 P HY S ICAL TEST PAS S E D WI TH 220pF CAPACIT OR.

DGND

EPAD

IO_VSS

VSS

DGND

AGND

DNC

DGND

10µF

10nF

100nF

10nF

1nF

10nF

IIN–

14 IIN–_AUX

11 IIN+_AUX

17 VREF

15 VINP_AUX

16 VINM_AUX

IIN+

100µΩ

SHUNT

VBAT VDD

VBAT 4 5

GPIO1/SCLK/LIN_TX

GPIO2/MISO

GPIO3/IRQ0/MOSI/LC_TX/LIN_TX

GPIO4/IRQ1/LC_RX/ECLKIN/LIN_RX

GPIO5/LC_TX/LIN_TX

SWDIO

SWCLK

AVDD18 VTEMP

9GND_SW

33VDD

DVDD33

LIN

RESET

DVDD33

1µF

DVDD18

0.47µF0.47µF

AVDD18

100nF

1kΩ

ECU

MASTER

PESD1LIN

(OPTIONAL)

LIN

220Ω

100kΩ

220Ω

1kΩ

10kΩ

NTC

0.47µF

ADuCM330/

ADuCM331

OPTIONAL

GPIO0/CS/LIN_RX

Figure 3. Recommended Schematic

ADuCM330/ADuCM331 Data Sheet

Rev. C | Page 16 of 16

OUTLINE DIMENSIONS

0.50

BSC

PIN 1

INDICATOR

916

2425

PIN 1

INDICATOR

SEATING

PLANE

0.05 MAX

0.02 NO M

0.15 REF

COPLANARITY

0.08

0.30

0.25

0.18

6.10

6.00 SQ

5.90

1.00

0.95

0.85

FOR PROP E R CO NN E CT ION OF

THE EXPOSED PAD, REF ER T O

TH E PI N CONFI GURATI ON A ND

FU NCT IO N DE S C RI P TI ONS

SECTION OF THIS DATA SHEET.

0.70

0.60

0.50

0.20 MIN

*3.90

3.80 SQ

3.70

*COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-7

WIT H T HE EX CEPT I ON OF THE EXPOSED PAD DIMENSION.

07-14-2014-D

TOP VIEW

EXPOSED

PAD

BOTTOM VIEW

PKG-003499/3916

Figure 4. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6 mm × 6 mm Body, Very Thin Quad

(CP-32-15)

Dimensions shown in millimeters

ORDERING GUIDE

Model1, 2

Temperature

Range3

Program Flash/

Data Flash/SRAM Package Description

Package

Option

ADuCM330WDCPZ −40°C to +115°C 96 kB/4 kB/6 kB 32-Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-15

ADuCM330WDCPZ-RL −40°C to +115°C 96 kB/4 kB/6 kB 32-Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-15

ADuCM331WDCPZ −40°C to +115°C 128 kB/4 kB/6 kB 32-Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-15

ADuCM331WDCPZ-RL −40°C to +115°C 128 kB/4 kB/6 kB 32-Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-15

EVAL-ADUCM331QSPZ Socketed Evaluation Board with Switches and LEDs

1 Z = RoHS Compliant Part.

2 W = Qualified for Automotive Applications.

3 The ADuCM330/ADuCM331 are functional but have degraded performance at temperatures from 115°C to 125°C.

AUTOMOTIVE PRODUCTS

The ADuCM330W/ADuCM331W models are available with controlled manufacturing to support the quality and reliability requirements

of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore,

designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for

use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and

to obtain the specific Automotive Reliability reports for these models.

registered trademarks are the property of their respective owners.

D11153-0-10/15(C)