LT6556
1
6556f
LT6556
V+
V–
RINA
GINA
BINA
RINB
GINB
BINB
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
VREF
6556 TA01
AGND
ENABLE
DGND
1k
ROUT
1k
GOUT
1k
BOUT
×1
×1
×1
SELECT A/B
TIME (ns)
OUTPUT (V)
1.5
1.0
0.5
0
–0.5
–1.0
–1.5 4 8 12 16
6556 TA02
2020 6 10 14 18
VIN = 2VP-P
VS = ±5V
RL = 1k
TA = 25°C
750MHz Gain of 1 Triple
2:1Video Multiplexer
The LT®6556 is a high speed triple 2:1 video multiplexer
with an internally fi xed gain of 1. The individual buffers
are optimized for performance with a 1k load and feature a
2VP-P –3dB bandwidth of 450MHz, making them ideal for
driving very high resolution video signals. Separate power
supply pins for each amplifi er boost channel separation
to 72dB, allowing the LT6556 to excel in many high speed
applications.
While the performance of the LT6556 is optimized for dual
supply operation, it can also be operated with a single sup-
ply as low as 4.5V. Using dual 5V supplies, each amplifi er
draws only 9.5mA. When disabled, the amplifi ers draw
less than 330µA and the outputs become high impedance.
For applications requiring a fi xed gain of 2, refer to the
LT6555 datasheet.
The LT6556 is available in 24-lead SSOP and ultra-compact
24-lead QFN packages.
■ RGB Buffers
■ UXGA Video Multiplexing
■ LCD Projectors
■ 750MHz –3dB Small Signal Bandwidth
■ 450MHz –3dB 2VP-P Large-Signal Bandwidth
■ 120MHz ±0.1dB Bandwidth
■ High Slew Rate: 2100V/µs
■ Fixed Gain of 1; No External Resistors Required
■ 72dB Channel Separation at 10MHz
■ 52dB Channel Separation at 100MHz
■ –84dBc 2nd Harmonic Distortion at 10MHz, 2VP-P
■ –87dBc 3rd Harmonic Distortion at 10MHz, 2VP-P
■ Low Supply Current: 9.5mA per Amplifi er
■ 6.5ns 0.1% Settling Time for 2V Step
■ I
SS ≤ 330µA per Amplifi er When Disabled
■
Differential Gain of 0.033%, Differential Phase of 0.022°
■ Wide Supply Range: ±2.25V (4.5V) to ±6V (12V)
■
Available in 24-Lead SSOP and 24-Lead QFN Packages
RGB Multiplexer and Line Driver
APPLICATIO S
U
FEATURES DESCRIPTIO
U
TYPICAL APPLICATIO
U
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Large-Signal Transient Response
LT6556
2
6556f
Total Supply Voltage (V+ to V–) .............................12.6V
Input Current (Note 2) .........................................±10mA
Output Current (Continuous) ..............................±70mA
⎯
E
⎯
N to DGND Voltage (Note 2) ..................................5.5V
SEL to DGND Voltage (Note 2) ....................................8V
Output Short-Circuit Duration (Note 3) ............ Indefi nite
Operating Temperature Range (Note 4) ... –40°C to 85°C
Specifi ed Temperature Range (Note 5) .... –40°C to 85°C
(Note 1)
The
denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VS = ±5V, RL = 1k, CL = 1.5pF, V
⎯
E
⎯
N = 0.4V, VAGND, VDGND, VVREF = 0V.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Offset Voltage VIN = 0V, VOS = VOUT ●
18 ±67
±75
mV
mV
IIN Input Current ●–12 ±45 µA
RIN Input Resistance VIN = ±1V ●100 500 kΩ
CIN Input Capacitance f = 100kHz ●1pF
PSRR Power Supply Rejection Ratio VS = ±2.25V to ±6V (Note 6) ●51 62 dB
ELECTRICAL CHARACTERISTICS
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
Junction Temperature
SSOP ................................................................ 150°C
QFN ................................................................... 125°C
Storage Temperature Range
SSOP ................................................. –65°C to 150°C
QFN .................................................... –65°C to 125°C
Soldering Temperature (10 sec) ............................ 300°C
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
GN PACKAGE
24-LEAD PLASTIC SSOP
24
23
22
21
20
19
18
17
16
15
14
13
IN1A
DGND
IN2A
VREF
IN3A
AGND1
IN1B
AGND2
IN2B
AGND3
IN3B
V–
V+
EN
SEL A/B
V+
OUT1
V–
OUT2
V+
OUT3
V–
V+
V+
G = +1
G = +1
G = +1
TJMAX = 150°C, θJA = 90°C/W
24 23 22 21 20 19
789
TOP VIEW
25
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
10 11 12
6
5
4
3
2
1
13
14
15
16
17
18VREF
IN3A
AGND1
V–
IN1B
AGND2
V+
OUT1
V–
OUT2
V+
OUT3
IN2A
DGND
IN1A
V+
EN
SEL A/B
IN2B
AGND3
IN3B
V+
V+
V–
TJMAX = 125°C, θJA = 37°C/W, θJC = 2.6°C/W
EXPOSED PAD (PIN 25) IS V–
MUST BE SOLDERED TO PCB
ORDER PART NUMBER GN PART MARKING ORDER PART NUMBER UF PART MARKING*
LT6556CGN
LT6556IGN
LT6556CGN
LT6556IGN
LT6556CUF
LT6556IUF
6556
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
LT6556
3
6556f
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: This parameter is guaranteed to meet specifi ed performance
through design and characterization. It is not production tested.
Note 3: As long as output current and junction temperature are kept
below the Absolute Maximum Ratings, no damage to the part will occur.
Depending on the supply voltage, a heat sink may be required.
Note 4: The LT6556C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 5: The LT6556C is guaranteed to meet specifi ed performance from
0°C to 70°C. The LT6556C is designed, characterized and expected to
meet specifi ed performance from –40°C and 85°C but is not tested or
QA sampled at these temperatures. The LT6556I is guaranteed to meet
specifi ed performance from –40°C to 85°C.
Note 6: In order to follow the constraints for 4.5V operation for PSRR
and IPSRR testing at ±2.25V, the DGND pin is set to V–, the
⎯
E
⎯
N pin is set
The
denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VS = ±5V, RL = 1k, CL = 1.5pF, VEN = 0.4V, VAGND, VDGND, VVREF = 0V.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IPSRR Input Current Power Supply Rejection VS = ±2.25V to ±6V (Note 6) ●1±3µA/V
AV ERR Gain Error VOUT = VREF = ±2V, Nominal Gain 1V/V ●–2.8 –1.15 0%
AV MATCH Gain Matching Any One Channel to Another ±0.05 %
VOUT Output Voltage Swing (Note 7) ●±3.65 ±3.85 V
ISSupply Current, Per Amplifi er RL = ∞
●
9.5 13
14.5
mA
mA
Supply Current, Disabled, Per Amplifi er V
⎯
E
⎯
N = 4V, RL = ∞
V
⎯
E
⎯
N = Open, RL = ∞
●
●
47
42
330
330
µA
µA
I
⎯
E
⎯
NEnable Pin Current V
⎯
E
⎯
N = 0.4V
V
⎯
E
⎯
N = 4V
●
●
–200
–75
–95
–21
µA
µA
ISEL Select Pin Current VSEL = 0.4V
VSEL = 4V
●
●
–50
–50
–5
–1
µA
µA
ISC Output Short-Circuit Current RL = 0Ω, VIN = ±2V, VREF = ±1V ●±50 ±105 mA
SR Slew Rate ±1V on ±2.2V Output Step (Note 8) 1200 2100 V/µs
–3dB BW Small-Signal –3dB Bandwidth VOUT = 200mVP-P 750 MHz
0.1dB BW Gain Flatness ±0.1dB Bandwidth VOUT = 200mVP-P 120 MHz
FPBW Full Power Bandwidth 2V VOUT = 2VP-P (Note 9) 190 335 MHz
Full Power Bandwidth 4V VOUT = 4VP-P (Note 9) 175 MHz
All-Hostile Crosstalk f = 10MHz, VIN = 2VP-P
f = 100MHz, VIN = 2VP-P
–72
–52
dB
dB
Selected Channel to Unselected
Channel Crosstalk
f = 10MHz, VIN = 2VP-P
f = 100MHz, VIN = 2VP-P
–85
–64
dB
dB
Channel Select Output Transient INA = INB = 0V 200 mVP-P
Channel-to-Channel Select Time INA = –1V, INB = 1V
from 50% SEL to VOUT = 0V
8ns
tSSettling Time 0.1% of VFINAL, VSTEP = 2V 6.5 ns
tR, tFSmall-Signal Rise and Fall Time 10% to 90%, VOUT = 200mVP-P 500 ps
dG Differential Gain (Note 10) 0.056 %
dP Differential Phase (Note 10) 0.028 Deg
HD2 2nd Harmonic Distortion f = 10MHz, VOUT = 2VP-P –84 dBc
HD3 3rd Harmonic Distortion f = 10MHz, VOUT = 2VP-P –87 dBc
to V– + 0.4V, and the SEL pin is set to either V– + 0.4V or V– + 4V. At ±6V
and all other cases, DGND is set to ground and the
⎯
E
⎯
N and SEL pins are
referenced from it.
Note 7: The VREF pin is set to 3V when testing positive swing and –3V
when testing negative swing to ensure that the internal input clamps do
not limit the output swing.
Note 8: Slew rate is 100% production tested using both inputs of
channel 2. Slew rates of channels 1 and 3 are guaranteed through
design and characterization.
Note 9: Full power bandwidth is calculated from the slew rate:
FPBW = SR/(π • V
P-P)
Note 10: Differential gain and phase are measured using a Tektronix
TSG120YC/NTSC signal generator and a Tektronix 1780R video
measurement set. The resolution of this equipment is better than 0.05%
and 0.05°. Nine identical amplifi er stages were cascaded giving an
effective resolution of better than 0.0056% and 0.0056°.
LT6556
4
6556f
TEMPERATURE (°C)
–55
INPUT BIAS CURRENT (A)
–20
–15
–10
105
6556 G05
–25
–30
–40 –15 25 65
–35 125
545 85
–35
0
–5
VS = ±5V
VIN = 1.5V
VIN = –1.5V
VIN = 0V
EN PIN VOLTAGE (V)
SUPPLY CURRENT (mA)
6556 G03
12
10
8
6
4
2
001.0 2.0 2.5
0.5 1.5 3.0 3.5 4.0
VS = ±5V
RL = ∞
VIN = 0V
TA = –55°C
TA = 125°C
TA = 25°C
TOTAL SUPPLY VOLTAGE (V)
04
6556 G02
12356789101112
SUPPLY CURRENT (mA)
12
10
8
6
4
2
0
VS = ±5V
VEN, VIN, VDGND, VSEL = 0V
TA = 25°C
TEMPERATURE (°C)
–55
SUPPLY CURRENT (mA)
–15 25 45 125
6556 G01
–35 5 65 85 105
12
10
8
6
4
2
0
VS = ±5V
RL = ∞
VIN = 0V
VEN = 0V
VEN = 4V
VEN = 0.4V
SINK CURRENT (mA)
0
OUTPUT VOLTAGE (V)
–2
–1
0
80
6556 G09
–3
–4
–5 10 20 30 40 50 60 70 90 100
VS = ±5V
VIN = –4V
VVREF = –3V TA = 125°C
TA = 25°C
TA = –55°C
SOURCE CURRENT (mA)
0
OUTPUT VOLTAGE (V)
3
4
5
80
6556 G08
2
1
010 20 30 40 50 60 70 90 100
VS = ±5V
VIN = 4V
VVREF = 3V
TA = 125°C
TA = 25°C
TA = –55°C
TEMPERATURE (°C)
–55
0
OFFSET VOLTAGE (mV)
10
20
–15 25 45 125
6556 G04
5
–35 5 65 85 105
15
25 VS = ±5V
VIN = 0V
VREF PIN VOLTAGE (V)
–2
OUTPUT VOLTAGE (V)
0
2
2
6556 G07
–2
–5
–4
–1 01
–1.5 –0.5 0.5 1.5
5
4
–1
1
–3
3
VS = ±5V
RL = 1k
HIGH SWING
LOW SWING
TA = 125°C
TA = 125°C
TA = 25°C
TA = –55°C
TA = –55°C
TA = 25°C
EN PIN VOLTAGE (V)
0
EN PIN CURRENT (μA)
0
–20
–40
–60
–80
–100
–120
–140
6556 G06
25
134
VS = ±5V
VDGND = 0V
TA = –55°C
TA = 25°C
TA = 125°C
Supply Current per Amplifi er
vs Temperature
Supply Current per Amplifi er
vs Supply Voltage
Supply Current per Amplifi er
vs
⎯
E
⎯
N Pin Voltage
Offset Voltage vs Temperature
Input Bias Current
vs Temperature
⎯
E
⎯
N Pin Current vs
⎯
E
⎯
N Pin Voltage
Maximum Output Voltage Swing
vs VREF Pin Voltage
Output Voltage Swing
vs ILOAD (Output High)
Output Voltage Swing
vs ILOAD (Output Low)
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LT6556
5
6556f
FREQUENCY (MHz)
–80
AMPLITUDE (dB)
–40
0
–100
–60
–20
0.1 10 100 1000
6556 G16
–120
1
VS = ±5V
VOUT = 2VP-P
RL = 1k
TA = 25°C
DRIVE IN A;
SELECT IN B
DRIVE IN B;
SELECT IN A
FREQUENCY (MHz)
–80
AMPLITUDE (dB)
–40
0
–100
–60
–20
0.1 10 100 1000
6556 G17
–120
1
VS = ±5V
VOUT = 2VP-P
RL = 1k
TA = 25°C
WORST
ADJACENT ALL CHANNELS
DRIVEN
FREQUENCY (MHz)
–3
AMPLITUDE (dB)
0
3
6
0.1 10 100 1000
6555 G15
–6
1
9VS = ±5V
VOUT = 200mVP-P
RL = 1k
TA = 25°CCL = 15pF
CL = 0pF
CL = 6.8pF
CL = 3.3pF
CL = 10pF
FREQUENCY (MHz)
–4
GAIN (dB)
–2
–1
1
3
2
0.1 10 100 1000
6556 G13
–6
1
0
–3
–5
VS = ±5V
RL = 1k
TA = 25°C
VOUT = 2VP-P
VOUT = 4VP-P
VOUT = 200mVP-P
FREQUENCY (MHz)
–0.05
GAIN (dB)
0.05
0.15
–0.10
0
0.10
0.1 10 100 1000
6556 G14
–0.15
1
IN3B
IN2B
IN3A
VS = ±5V
VOUT = 200mVP-P
RL = 1k
TA = 25°C
IN1A
IN1B
IN2A
FREQUENCY (MHz)
–100
DISTORTION (dBc)
–80
–60
–40
–20
0.01 1 10 100
6556 G18
–120
0.1
0
–110
–90
–70
–50
–30
–10 VS = ±5V
VOUT = 2VP-P
RL = 1k
TA = 25°C
HD2
HD3
FREQUENCY (MHz)
20
REJECTION RATIO (dB)
40
70
10
30
50
60
0.001 0.1 1 10 100
6556 G12
0
0.01
±PSRR
–PSRR
+PSRR
VS = ±5V
TA = 25°C
FREQUENCY (kHz)
INPUT NOISE (nV/√Hz OR pA/√Hz)
0.001 0.01 1 10 1000.1
1000
100
10
1
in
VS = ±5V
TA = 25°C
en
6556 G10
6556 G11
FREQUENCY (MHz)
INPUT IMPEDANCE (kΩ)
0.01 0.1 10 100 10001
1000
100
10
1
0.1
VS = ±5V
VIN = 0V
TA = 25°C
Input Noise Spectral Density Input Impedance vs Frequency
PSRR vs Frequency
Frequency Response
vs Output Amplitude Gain Flatness vs Frequency
Frequency Response with
Capacitive Loads
Crosstalk vs Frequency Crosstalk vs Frequency Harmonic Distortion vs Frequency
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LT6556
6
6556f
TIME (ns)
0
SEL A/B (V)
4
2
1
3
5
20 40 60 80
6556 G26
10010030507090
VS = ±5V
RL = 1k
INA = INB = 0V
TA = 25°C
OUTPUT (V)
–0.05
0.05
0.15
–0.10
0
0.10
FREQUENCY (MHz)
0.01
0.1
OUTPUT IMPEDANCE (Ω)
100
1000000
0.1 1 10 100 1000
6556 G19
1
10000
1000
10
100000 DISABLED
VEN = 4V
ENABLED
VEN = O.4V VS = ±5V
TA = 25°C
TIME (ns)
0
SEL A/B (V)
OUTPUT (V)
4
2
1
3
5
0
–1.5
1.5
1.0
0.5
–0.5
–1.0
20 40 60 80
6556 G27
10010030507090
VS = ±5V
RL = 1k
INB = 300MHz, 2VP-P SINE
TA = 25°C INA = 0V
GAIN ERROR—BETWEEN CHANNELS (%)
–0.1
PERCENT OF UNITS (%)
25
30
35
40
0.1
6556 G25
15
0
–0.075 –0.025–0.05
00.025 0.05 0.075
20
10
5
VS = ±5V
VOUT = ±2V
RL = 1k
TA = 25°C
GAIN ERROR—INDIVIDUAL CHANNEL (%)
–1.3
PERCENT OF UNITS (%)
25
30
35
–.90
6556 G24
15
0–1.25 –1.15–1.2 –1.1 –1.05 –1.0 –.95
20
10
5
VS = ±5V
VOUT = ±2V
RL = 1k
TA = 25°C
TIME (ns)
0
OUTPUT (V)
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.5
–2.5
–1.0
–2.0
16
6556 G23
4 8 12 20142 6 10 18
VIN = 4VP-P
VS = ±5V
RL = 1k
TA = 25°C
TIME (ns)
–0.2
OUTPUT (V)
0.2
0.5
0.9
0
0.4
0.7
–0.1
0.3
0.6
0.1
0.8
4 8 12 16
6556 G22
2020 6 10 14 18
VIN = 700mVP-P
VS = ±5V
RL = 1k
TA = 25°C
TIME (ns)
0
OUTPUT (V)
–0.10
0
0.10
0.20
0.15
16
6556 G21
–0.20
–0.15
–0.05
0.05
4812
218
610 14 20
VIN = 200mVP-P
VS = ±5V
RL = 1k
TA = 25°C
6556 G20
CAPACITIVE LOAD (pF)
1
OUTPUT SERIES RESISTANCE ()
35
30
25
20
15
10
5
0
10 100 1000
VOUT = 2VP–P
VS = ±5V
RL = 1k
TA = 25°C
AC PEAKING
>3dB
Output Impedance vs Frequency
Maximum Capacitive Load vs
Output Series Resistor Small-Signal Transient Response
Video Amplitude Transient
Response Large-Signal Transient Response Gain Error Distribution
Gain Error Matching Distribution Channel Switching Transient Channel Switching Transient
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LT6556
7
6556f
PI FU CTIO S
UUU
IN1A (Pin 1): Channel 1 Input A. This pin has a nominal
impedance of 500kΩ and does not have any internal
termination resistor.
DGND (Pin 2): Digital Ground Reference for Enable Pin.
This pin is normally connected to ground.
IN2A (Pin 3): Channel 2 Input A. This pin has a nominal
impedance of 500kΩ and does not have any internal
termination resistor.
VREF (Pin 4): Voltage Reference for Input Clamping. This
is the tap to an internal voltage divider that defi nes mid-
supply. It is normally connected to ground in dual supply,
DC coupled applications.
IN3A (Pin 5): Channel 3 Input A. This pin has a nominal
impedance of 500kΩ and does not have any internal
termination resistor.
AGND (Pin 6): Analog Ground for Isolation between IN3A
and IN1B. AGND pins have ESD protection and should not be
connected to potentials outside the power supply range.
IN1B (Pin 7): Channel 1 Input B. This pin has a nominal
impedance of 500kΩ and does not have any internal
termination resistor.
AGND (Pin 8): Analog Ground for Isolation between IN1B
and IN2B. AGND pins have ESD protection and should not be
connected to potentials outside the power supply range.
IN2B (Pin 9): Channel 2 Input B. This pin has a nominal
impedance of 500kΩ and does not have any internal
termination resistor.
AGND (Pin 10): Analog Ground for Isolation between
IN2B
and IN3B. AGND pins have ESD protection and
should not be connected to potentials outside the power
supply range.
IN3B (Pin 11): Channel 3 Input B. This pin has a nominal
impedance of 500kΩ and does not have any internal
termination resistor.
V– (Pin 12):
Negative Supply Voltage. V– pins are not in-
ternally connected to each other and must all be connected
externally. Proper supply bypassing is necessary for best
performance. See the Applications Information section.
V+ (Pins 13, 14, 24): Positive Supply Voltage. V+ pins
are not internally connected to each other and must all
be connected externally. Proper supply bypassing is
necessary for best performance. See the Applications
Information section.
V– (Pin 15): Negative Supply Voltage for Channel 3 Output
Stage. V– pins are not internally connected to each other and
must all be connected externally. Proper supply bypassing
is necessary for best performance. See the Applications
Information section.
OUT3 (Pin 16): Channel 3 Output. It is the buffered output
of the selected Channel 3 input.
V+ (Pin 17): Positive Supply Voltage for Channels 2 and
3 Output Stages. V+ pins are not internally connected to
each other and must all be connected externally. Proper
supply bypassing is necessary for best performance. See
the Applications Information section.
OUT2 (Pin 18): Channel 2 Output. It is the buffered output
of the selected Channel 2 input.
V– (Pin 19): Negative Supply Voltage for Channels 1 and
2 Output Stages. V– pins are not internally connected to
each other and must all be connected externally. Proper
supply bypassing is necessary for best performance. See
the Applications Information section.
OUT1 (Pin 20): Channel 1 Output. It is the buffered output
of the selected Channel 1 input.
V+ (Pin 21): Positive Supply Voltage for Channel 1 Output
Stage. V+ pins are not internally connected to each other and
must all be connected externally. Proper supply bypassing
is necessary for best performance. See the Applications
Information section.
SEL
⎯
A/B (Pin 22): Select Pin. This high impedance pin
selects which set of inputs are sent to the output pins.
When the pin is pulled low, the A inputs are selected. When
the pin is pulled high, the B inputs are selected.
⎯
E
⎯
N (Pin 23): Enable Control Pin. An internal pull-up resistor
of 46k defi nes the pin’s impedance and will turn the part
off if the pin is unconnected. When the pin is pulled low,
the amplifi ers are enabled.
Exposed Pad (Pin 25, QFN Only): The Exposed Pad is
V– and must be soldered to the PCB. It is internally con-
nected to the QFN Pin 4, V–.
(GN24 Package)
LT6556
8
6556f
APPLICATIO S I FOR ATIO
WUUU
Power Supplies
The LT6556 is optimized for ±5V supplies but can be op-
erated on as little as ±2.25V or a single 4.5V supply and
as much as ±6V or a single 12V supply. Internally, each
supply is independent to improve channel isolation. Do
not leave any supply pins disconnected or the part may
not function correctly!
Enable/Shutdown
The LT6556 has a shutdown mode controlled by the
⎯
E
⎯
N
pin and referenced to the DGND pin. If the amplifi er will be
enabled at all times, the
⎯
E
⎯
N pin can be connected directly
to DGND. If the enable function is desired, either driving
the pin above 2V or allowing the internal 46k pull-up
resistor to pull the
⎯
E
⎯
N pin to the top rail will disable the
amplifi er. When disabled, the output will become very
high impedance. Supply current into the amplifi er in the
disabled state will be:
IVV
k
VV
k
SEN
=+
++
–––
46 80
It is important that the following constraints on the DGND,
⎯
E
⎯
N and SEL pins are always followed:
V+ – VDGND ≥ 4.5V
-0.5V ≤ V
⎯
E
⎯
N – VDGND ≤ 5.5V
V
SEL – VDGND ≤ 8V
In dual supply cases where V+ is less than 4.5V, DGND
should be connected to a potential below ground, such as
V–. Since the ⎯E⎯N and SEL pins are referenced to DGND, they
may need to be pulled below ground in those cases. However,
in order to protect the internal enable circuitry, the ⎯E⎯N pin
should not be forced more than 0.5V below DGND.
In single supply applications above 5.5V, an additional
resistor may be needed from the
⎯
E
⎯
N
pin to DGND if the
pin is ever allowed to fl oat. For example, on a 12V single
supply, a 33k resistor would protect the pin from fl oating
too high while still allowing the internal pull-up resistor
to disable the part.
On dual ±2.25V supplies, connecting the DGND pin to V– is
the only way of ensuring that V+ – VDGND ≥ 4.5V.
The enable/disable times of the LT6556 are fast when
driven with a logic input. Turn on (from 50%
⎯
E
⎯
N
input to
50% output) typically occurs in less than 50ns. Turn off
is slower, but is typically below 500ns.
Channel Select
The SEL pin uses the same internal threshold as the
⎯
E
⎯
N
pin and is also referenced to DGND. When the pin is logic
low, the channel A inputs are passed to the output. When
the pin is logic high, the channel B inputs are passed to
the output. The pin should not be fl oated but can be tied
to DGND to force the outputs to always be channel A or
to V+ (when less than 8V) to force the outputs to always
be channel B.
Truth Table
SEL
⎯
A/B
⎯
E
⎯
N OUT
0 0 IN A
1 0 IN B
X 1 OFF
Input Considerations
The LT6556 uses input clamps referenced to the VREF pin
to prevent damage to the input stage on the unselected
channel. Three transistors in series limit the input voltage to
within three diode drops (±) from VREF. VREF is nominally
set to half of the sum of the supplies by the 40k resistors.
A simplifi ed schematic is shown in Figure 1.
VREF
40k
40k
6556 F01
V+
V–
IN
Figure 1. Simplifi ed Schematic of V
REF Pin and Input Clamping
LT6556
9
6556f
To improve clamping, the pin’s DC impedance should be
minimized by connecting the VREF pin directly to ground
in the symmetric dual supply case with a common mode
voltage of 0V. If the common mode voltage is not centered
at ground or the input voltage exceeds plus or minus three
diodes from ground, an external resistor to either supply
can be added to shift the VREF voltage to the desired level.
The only way to cover the full input voltage range of V– +
1V to V+ – 1V is to shift VREF up or down.
The VREF pin can also be directly driven with a DC source.
Figure 2 shows the effect of the clamp on input current
when sweeping input voltage with various VREF pin volt-
ages. Bypassing the VREF pin is not necessary.
INPUT VOLTAGE (V)
–4
INPUT CURRENT (μA)
0
100
4
6556 F02
–100
–250
–200
–2 02
–3 –1 13
250
200
–50
50
–150
150
TA = 25°C
VS = ±5V
VREF = 2V
VREF = 1V
VREF = 0V
VREF = –1V
VREF = –2V
The inputs can be driven beyond the point at which the
output clips so long as input currents are limited to less
than ±10mA. Continuing to drive the input beyond the
output limit can result in increased current drive and
slightly increased swing, but will also increase supply
current and may result in delays in transient response
at larger levels of overdrive.
Layout and Grounding
It is imperative that care is taken in PCB layout in order to
benefi t from the very high speed and very low crosstalk of
the LT6556. Separate power and ground planes are highly
recommended and trace lengths should be kept as short
as possible. If input traces must be run over a distance of
several centimeters, they should use a controlled imped-
ance with either series or shunt terminations (nominally
50Ω or 75Ω) to maintain signal fi delity.
Care should be taken to minimize capacitance on the
LT6556’s output traces by increasing spacing between
traces and adjacent metal and by eliminating metal planes
in underlying layers. To drive cable or traces longer than
several centimeters, using the LT6555 with its fi xed gain
of+2 in conjunction with series and load termination resis-
tors may provide better results.
A plot of AC performance driving a 1k load with various
trace lengths is shown in Figure 3. All data is from a 4-layer
board with 2oz copper, 18mil of board layer thickness to
the ground plane, a trace width of 12mils and spacing to
adjacent metal of 18mils. The 0.2cm output trace places
the 1k resistor as close to the part as possible, while the
other curves show the load resistor consecutively further
away. The worst case, 4cm, trace has almost 10pF of
parasitic capacitance.
FREQUENCY (MHz)
0.1
AMPLITUDE (dB)
6
4
2
0
–2
–4
–6 110 100 1000
6556 F03
4cm TRACE
0.2cm TRACE
2cm TRACE
VS = ±5V
VOUT = 200mVP-P
RL = 1k
TA = 25°C
Figure 3. Response vs Output Trace Length
APPLICATIO S I FOR ATIO
WUUU
Figure 2. Input Current vs Input Voltage
at Different VREF Voltages
LT6556
10
6556f
APPLICATIO S I FOR ATIO
WUUU
In order to counteract any peaking in the frequency re-
sponse from driving a capacitive load, a series resistance
can be inserted in the line at the output of the part to fl at-
ten the response. Figure 4 shows the frequency response
with the same 4cm trace from Figure 3, now with a 10Ω
series resistor inserted near the output pin of the ampli-
fi er. Note that using a 10Ω series resistor with a 1k load
only decreases the output amplitude by 0.1dB or 1% and
has a minimal effect on the bandwidth of the system. See
the graph labeled “Maximum Capacitive Load vs Output
Series Resistor” in the Typical Performance Characteristics
section for more information.
FREQUENCY (MHz)
0.1
AMPLITUDE (dB)
6
4
2
0
–2
–4
–6 110 100 1000
6556 F04
4cm TRACE
4cm TRACE
RS, OUT = 10Ω
VS = ±5V
VOUT = 200mVP-P
RL = 1k
TA = 25°C
Figure 4. Response vs Series Output Resistance
While the AGND pins on the LT6556 are not connected to
the amplifi er circuitry, tying them to ground or another
“quiet” node signifi cantly increases channel isolation
and is always recommended. The AGND pins do have
ESD protection and therefore should not be connected to
potentials outside the power supply range.
Low ESL/ESR bypass capacitors should be placed as close
to the positive and negative supply pins as possible. One
4700pF ceramic capacitor is recommended for both V+
and V–
supply busses. Additional 470pF ceramic capacitors
with minimal trace length on each supply pin will further
improve AC and transient response as well as channel
isolation. For high current drive and large-signal transient
applications, additional 1µF to 10µF tantalums should
be added on each supply. The smallest value capacitors
should be placed closest to the package.
To maintain the LT6556’s channel isolation, it is benefi cial
to shield parallel input and parallel output traces using a
ground plane or power supply traces. Vias between top-
side and backside metal may be required to maintain a
low inductance ground near the part where numerous
traces converge. See Figures 7 and 8 for photos of an
optimized layout.
Single Supply Operation
Figure 5 illustrates how to use the LT6556 with a single
supply ranging from 4.5V to 12V. Since the output range is
comparable to the input range, the DC bias point at the input
can be set anywhere between the supplies that will prevent
the AC-coupled signal from running into the output range
limits. As shown, the DC input level is mid-supply.
The only additional power dissipation in the single supply
confi guration is through the resistor bias string at the input
and through any load resistance at the output. In many
cases, the output can be used to directly drive other single
supply devices without additional coupling and without
any resistive load.
1/3
LT6556
5k
5k AGND
IN
VIN
22μF
OUT
V+
V–
4.5V TO 12V
6556 F05
Figure 5. Single Supply Confi guration, One Channel Shown
Input Expansion
In applications with more than two inputs per channel,
multiple LT6556s can be connected directly together at the
outputs. Logic circuitry can be used to drive the
⎯
E
⎯
N
pins
of each LT6556 to ensure that only one set of channels is
buffered at a time. See Figure 9 for a schematic.
Since the output impedance of a disabled LT6556 is high,
adding additional channels will not resistively load an
LT6556
11
6556f
APPLICATIO S I FOR ATIO
WUUU
enabled output. However, since the disabled LT6556 and its
traces have around 6pF of capacitance, it may be desirable
to resistively isolate the outputs of each channel to maintain
fl at frequency response as shown in the graph labeled
“Maximum Capacitive Load vs Output Series Resistor” in
the Typical Performance Characteristics section.
ESD Protection
The LT6556 has reverse-biased ESD protection diodes on all
pins. If any pins are forced a diode drop above the positive
supply or a diode drop below the negative supply, large
currents may fl ow through these diodes. If the current is
kept below 10mA, no damage to the devices will occur.
TYPICAL APPLICATIO
U
RGB Multiplexer Demo Board
The DC892A Demo Board illustrates optimal routing,
bypassing and termination using the LT6556 as an
RGB video multiplexer. The schematic is shown in Figure 6.
All inputs and outputs are routed to have a characteristic
impedance of 75Ω and 75Ω input shunt and output series
terminations are connected as close to the part as pos-
sible. The board is fabricated with four layers with internal
ground and power planes.
While the 75Ω back termination resistors at the outputs
of the LT6556 minimize signal refl ections in the output
traces and isolate the part from any capacitive loading in
those traces, they also contribute to gain error if the out-
put is not terminated with high impedance. For example,
if the output is terminated with a 1k load, the 75Ω back
termination will cause a 7% gain error. Decreasing the
value of the back termination resistors will decrease the
signal attenuation but may compromise the AC response.
However, connecting the LT6556 output pins to the output
traces on the DC892A board without some series resistance
is not recommended; 10Ω to 20Ω is generally suffi cient.
Figures 7 and 8 show the top and bottom side board layout
and placement.
Figure 6. Demo Board Schematic
5
IN1A 4
3
2
5
IN2A 4
3
2
5
IN3A 4
3
2
5
IN1B 4
3
2
5
IN2B 4
3
2
5
IN3B 4
3
2
IN1B
AGND1
IN3A
VREF
VREF
IN2A
DGND
DGND
IN1A
AGND2
6
7
8
9
4
5
3
2
1
24
23
22
14
13
12
11
10
15
16
17
18
19
20
21
V+
OUT2
V–
OUT1
IN3B
AGND3
IN2B
V–V+
V+
V–
OUT3
V+
SEL
EN
V+
U1 LT6556CUF
EXT GND
13
2
JP5
VREF
JP12
BNC × 6
DGND
1
1
1
1
1
1
L1
L1
L1
L1
L1
L1
Z = 75
Z = 75
Z = 75
Z = 75
Z = 75
Z = 75
JP13
JP14
JP5
JP6
JP7
J3
BANANA JACK
FLOAT AGND
13
2
JP2
DGND
EXT ENABLE
13
2
JP1
CONTROL 13 VCC
SEL A/B
AB
DGND
2
JP4
SEL
R7
20k
J1
50Ω BNC
EN
5432
1
R10
75Ω
R11
75Ω
R12
75Ω
R4
75Ω
R5
75Ω
R6
75Ω
2
DUAL
NOTE:
470pF BYPASS CAPACITORS LOCATED
AS CLOSE TO PINS AS POSSIBLE
SINGLE
AGND
JP3
SUPPLY
31
E1
EN
E4
SEL A/B
E2
DGND
E5
VREF
E3
AGND
R8
50Ω
OPT
Z = 50 Z = 50
EN
5
OUT1
J9
1L2
L2
L2
Z = 75
R1
75Ω
R2
75Ω
R3
75Ω
Z = 75
Z = 75
1
1
J10
J11
J4
BANANA JACK
VEE 6556 F06
4
3
2
5
OUT2
4
3
2
5
OUT3
VEE
–3.3V TO –5V
4
3
2
C1
4700pF
C10
4700pF
C7
0.33μF
10V
C2
470pF
C3
470pF
C4
10μF
16V
1206
C9
10μF
16V
1206
J2
BANANA JACK
VCC
VCC
3.3V TO 5V
C5
4700pF
C6
470pF
C8
0.33μF
10V
BNC × 3
5432
1
R9
50Ω
OPT
J8
50Ω BNC
SEL A/B
V–
25
LT6556
12
6556f
TYPICAL APPLICATIO
U
Figure 7. Demo Board Topside
(IC Removed for Clarity)
Figure 8. Demo Board Bottom Side
LT6556
13
6556f
SCHE ATIC
WW
SI PLIFIED
360Ω
100Ω
770Ω1k
V+
V+V+
V–V–
V–
INA
EN
DGND
V–
V+
SEL
TO OTHER
INPUT STAGES
VREF
VREF
40k
40k
100Ω
INB
VREF
VREF
SELECT
46k
BIAS
TO OTHER
OUTPUT
STAGES
V+
OUT
6556 SS
V–
360Ω
(One channel shown)
LT6556
14
6556f
PACKAGE DESCRIPTIO
U
.337 – .344*
(8.560 – 8.738)
GN24 (SSOP) 0204
12
345678 9 10 11 12
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
161718192021222324 15 14 13
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.0075 – .0098
(0.19 – 0.25)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.033
(0.838)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
GN Package
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
LT6556
15
6556f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTIO
U
4.00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
2423
1
2
BOTTOM VIEW—EXPOSED PAD
2.45 ± 0.10
(4-SIDES)
0.75 ± 0.05 R = 0.115
TYP
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UF24) QFN 0105
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.45 ± 0.05
(4 SIDES)
3.10 ± 0.05
4.50 ± 0.05
PACKAGE OUTLINE
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
LT6556
16
6556f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
LT/TP 0805 500 • PRINTED IN USA
PART NUMBER DESCRIPTION COMMENTS
LT1203 150MHz Single 2:1 Multiplexer Single SPDT Video Switch
LT1399 300MHz Triple Current Feedback Amplifi er 0.1dB Gain Flatness to 150MHz, Shutdown
LT1675 250MHz Triple RGB Multiplexer 100MHz Pixel Switching, 1100V/µs Slew Rate, 16-Lead SSOP
LT6550/LT6551 3.3V Triple and Quad Video Buffers 110MHz Gain of 2 Buffers in MS Package
LT6553 650MHz Gain of 2 Triple Video Amplifi er Same Pinout as the LT6554 but Optimized for Driving 75Ω Cables
LT6554 650MHz Gain of 1 Triple Video Amplifi er Performance Similar to the LT6556 with One Set of Inputs, 16-Lead SSOP
LT6555 650MHz Gain of 2 Triple Video Multiplexer Same Pinout as the LT6556 but Optimized for Driving 75Ω Cables
RELATED PARTS
TYPICAL APPLICATIO
U
×1
LT6556 #1 V+
IN1A
RED 1
GREEN 1
BLUE 1
RED 2
GREEN 2
BLUE 2
75Ω
75Ω
IN1B
×1
IN2A
75Ω
75Ω
75Ω
75Ω
IN2B
×1
IN3A
IN3B
SEL
OUT3
OUT2
OUT1
–2V GOUT
AGND
OUT1
OUT2
EN
5V
DGND
V–
VREF
×1
LT6556 #2 V+
IN1A
RED 3
GREEN 3
BLUE 3
RED 4
GREEN 4
BLUE 4
SEL0
SEL1
75Ω
75Ω
IN1B
×1
IN2A
75Ω
75Ω
75Ω
75Ω
IN2B
×1
IN3A
IN3B
SEL
OUT3
–2V
AGND
EN
5V
DGND
6556 F09
V–
VREF
ROUT
BOUT
NC7SZ14
SEL1
0
0
1
1
SEL0
0
1
0
1
OUTPUT
1
2
3
4
Figure 9. 4:1 RGB Multiplexer
