MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY DESCRIPTION M66850/851/852/853 are very high-speed and clock synchronous FIFO(First-In, First-Out) memories fabricated by high-speed GMOS technology. These FIFOs are applicable for a data buffer as networks and communications. The write operation is controlled by a write clock pin(WCLK) and two write enable pins(WEN1 ,WEN2). Data present at the data input pins(DO-D8) is written into the Synchronous FIFO on every rising write clock edge when the device is enabled for writing. The read operation is controlled by a read clock pin(RCOLK) and two read enable pins(REN1,REN2). Data is read from the Synchronous FIFO on every rising read clock edge when the device is enabled for reading. An output enable pin(GE) controls the states of the data output pins(Q0-Q8). MITSUBISHI FIFOs have four flags (EF,FF,PAE,PAF). The empty flag | EF and the full flag FF are fixed flags. The almost empty flag PAE and the almost full flag PAF are programmable flags. The programmable flag offset is initiated by the load pin(LD). FEATURES * Memory configuration 64words x 9bits (M66850J/FP) 256words x Sbits (M66851J/FP) 51 2words x Sbits (M66852J/FP) 1024words x 9bits (M66853J/FP) * Write and Read Clocks can be independent + Advanced CMOS technology * Programmable Almost-Empty and Almost-Full flags * High-speed : 25ns cycle time * Package Available : 32-pin Pastic Leaded Chip Carrier(PLOC) 32-pin Low profile Quad Flat Package(LQFP) APPLICATION * Data Buffer for networks communications. Dt ba PAF PAE GND REN RCLK REN2 OE PIN CONFIGURATION (TOP VIEW) ann t yo oOo ke Ow oOaoaqgaqagaaa ee ee O P| Fs 28) WEN1 2d WCLK 26 WEN2/LD 5] Voo 241 Q8 23) Q7 '2q] 06 at] as AEF A AEE i] we DLL LL Ls] nlc 6686 6 Outline 32P0(M66850 853J) [i 24] WENT [2 23) WCLK 3 2a] WEN2/LD PAE |4 >i] Voc c a 7 [ i or i i REN2 |s 17] a5 LILLE) IS [ti lk & a a a a Outline 32P6B(M66850 853FP) BLOCK DIAGRAM Do-De - - -0-Q -_-_- | ad pe) RESET ~7Tq RS LoGic | WCLK WEN1 , >| INPUT OFFSET WEN2 pL REGISTER REGISTER | y ' Y | WRITE READ |__| CONTROL + POINTER | { MEMORY A | ARRAY WRITE READ POINTER | CONTROL y | t AA at RCLK OUTPUT Lag RENT REGISTER og REE | | Lp Ee DEC) FLAG PAE oFO > + Logic PAF | FF _ _ _ OQ + oO _ _MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY PIN and SIGNAL DESCRIPTIONS * Voc One+5 volt power supply pin. - GND One 0 volt ground pin. + RS : Reset(INPUT) When RS is set LOW, internal read and write pointers are set to the first physical location,the output register is initialized to LOW, FF and PAF are set HIGH, EF and PAE are set LOW. A reset is required after power-up before a write operation. * WCLK : Write Clock{INPUT) Data present on DO-D8 is written into the FIFO on the rising edge of WCLK when the FIFO is enabled for writing. * ROLK : Read Clock{(INPUT) Data is read from the FIFO on the rising edge of RCLK when the FIFO is enabled for reading. * WEN : Write Enable (INPUT) If the FIFO is configured to allow loading of the offset registers, WENT is the only the write enable. When WENT is LOW, data on DO-D8 is written to the FIFO on the rising edge of WCLK. If the FIFO is configured to have two writeenables, data on DO- D8 is written to the FIFO on the rising edge of WCLK when WENT is LOW and WEN2 is High. Butif the FF is LOW, data on DO-D8 will not be written to the FIFO. * WEN2/LD : Write Enable2/Load(INPUT) The function of this signal is defined at reset. If WEN2/LD is HIGH at reset, this signal functions as a second write enable(WEN2). If WEN2/LD is LOW at reset, this signal functions as a control to load and read the offset register. If the FIFO is configured to have two write enables, data on DO- D8 is written to the FIFO on the rising edge of WCLK when WEN? is LOW and WENZ2is High. But if the FF is LOW, data on DO-D8 will not be written to the FIFO. lf the FIFO is configured to have programmable flags, it is possible to write and read from the offset registers. There are four 9-bit offset registers. Two are used to control the programmable Almost-Empty Flag and two are used to control the programmable Almost-Full Flag. Data on DO-D8 is written to an offset register on the rising edge of WCLK when WEN1 is LOW and LD is LOW. Data on DO - D8 is written to the offset registers in the following order : PAE LSB, PAE MSB, PAF LSB, PAF MSB. REN1, REN2 : Read Enable(INPUT) Data is read from the FIFO and presented Q0-8 on the rising edge of RCLK, when RENT and REN2 are LOW and output port is enabled. If either Read Enable is HIGH,the output register holds the previous data. When the FIFO is empty, the Read Enable signals are ignored. OE : Output Enable(INPUT) When OE is LOW, the output port Q0-8 is enabled for output. When OE is HIGH, the output port QO-8 is placed in a high impedance state. * DO-8 : Data Input{INPUT) DOQ-8 is the 9-bit data input port. * Q0-8 : Data Output(QUTPLUT) Q0-8 is the 9-bit data Output port. + EF : Empty Flag(OQUTPUT) The Empty flag goes LOW when the read pointer is equal to the write pointer. When EF is LOW, the FIFO is empty and further data reads from the data output are inhibited. EF is synchronized to the rising edge of RCLK. PAE : Programmable Almost-Empty Flag(QUTPUT) When PAE is LOW, the FIFO is almost empty based on the offset. The default offset is Empty+7. PAE is synchronized to the rising edge of RCLK. FF : Full Flag(OQUTPUT) When FF is LOW, the FIFO is full and further data writes into the data input are inhibited. The Full Flag goes LOW when the FIFO is full of data. FF is synchronized te the rising edge of WCLK. PAF : Programmable Almost-Full Flag(QUTPUT) When PAF is LOW, the FIFO is almost full based on the offset. The default offset is Full-7. PAF is synchronized to the rising edge of WCLK.MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY OFFSET FLAG LD | WEN1 | WCLK SELECTION LD | REN? | REN2| RCLK SELECTION i) 0 Empty Offset (LSB) i) 0 GQ Empty Cffset (LSB) Empty Offset (MSB) Empty Offset (MSB) ; Full Offset (LSB) i Full Offset (LSB) Full Offset (MSB) Full Offset (MSB) 0 1 ft No Operation 0 0 1 1 i) f No Operation 1} 0 ft Write into FIFO 1 | 4 1 1 4 No Operation 1 1 0 ft Read from FIFO Figure 1. Write Offset Register 1 0 1 1 0 f No Operation 1 1 Figure 2. Read Offset Register M66850J(64X9-bit) OFFSET REGISTERS M66852J(512X9-bit)} OFFSET REGISTERS 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 PAELSB | X X xX ES E4 3 E2 Ei E0 PAELSB | X E?7 E6 ES E4 E3 E2 E1 E0 Default Value 007H Default Value 007H PAEMSB|X X X X X X X XK xX PAEMSB|X X X X XK X X xX E8& PAFLSB | X X xX FS F4 F3 Fe Fi FO Default Value 0 Default Value 007H PAFLSB |X F7 F F5 F4 F3 F2 Fi FO PAFMSB}X X XK xX X XK X X X Default Value 007H PAFMSB|X X X X XK X X xX F8 Default Value 0 M66851J(256X9-bit) OFFSET REGISTERS 8 7 6 5 4 3 2 1 0 PAELSB | X E7Y E6 ES E4 E3 E2 E1 E0 M6853J(1024X9-bit) OFFSET REGISTERS Default Value 007H 8 7 6 56 4 3 2 1 0 PAEMSB|X X X X xX xX X xX X PAELSB | X E?Y E6 E5 E4 E38 E2 Ei E0 PAFLSB | X F?7 F F5 F4 F3 F2 Fi FO Default Value 007H Default Value 0071 PAEMSB|X X X X X X X E9 EB PAFMSB|X X X X XK X X XK X Default Value a 60 EO/FO are the least significant bits. PAF LSB | X F? F6 F5 F4 F3 F2 Fi FO X=Don't Care. Default Value 007H PAFMSB}X X XK xX X K XxX F9 F8& Default Value 0. 60Q Figure 3. Offset Regigter LocationMITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY ABSOLUTE MAXIMUM RATINGS Symbol Parameter Conditions Ratings Unit Vec Supply voltage -0.5-+47.0 Vv Vi Input voltage A value based on GND pin -0.3 Voc+0.5 Vv Vo Output voltage -0.3 Voc+0.5 Vv Pd Maximum power dissipation | Ta=70C Note mw Tstg Storage temperature -65 150 C Note : 450mW(32P6B), 550mW(32P0) RECOMMENDED OPERATING CONDITIONS Limits Symbol Parameter Min. | Tyo. | Max Vcc 45 5 5.5 GND 0 Topr ambient DC ELECTRICAL CHARACTERISTICS (Ta=0 70C, Vec=5V110%, GND=0V) . Limits ; Symbol Parameter Test conditions Min. Typ. Max. Unit ViH H"input voltage 2.0 Vv VIL "L"input voltage 0.8 Vv VOH H"output voltage loH = -1mA 24 Vv VOL "L"output voltage lol = 8mA 0.4 Vv im "H"input current Vi = Vcc, Any input 1.0 HA iL L"input current Vi= GND, Any input -1.0 HA lozH Off state "H"output current Vo = Vcc 5.0 HA loz Off state "L"output current Vo =GND -5.0 LA Icct Operating power supply current Vi= Vcc or GND, f= 40MHz, Outputs are open 70 mA loce Power supply current (Static) Vi= Vcc or GND, Outputs are open 500 HA Ci Input capacitance f= 1MHz 10 pF Co Off state output capacitance f = 1MHz 15 pFMITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY SWITCHING CHARACTERISTICS (Ta=0 70C, Vec=5V+10%, GND=0V) Limits Symbol Parameter Min. Typ. Max. Unit tac Data Access Time 3 15 ns tWFF Write Clock to Full Flag 15 ns tREF Read Clock to Empty Flag 15 ns {PAF Write Clock to Almost-Full Flag 15 ns {PAE Read Clock to Almost-Empty Flag 15 ns tOE Output Enable to Output Valid 3 13 ns toLz Output Enable to Output in Low-Z 0 ns tOHZ Output Enable to Output in High-Z 3 13 ns {RSF Reset to Flag and Output Valid time 25 ns TIMING CONDITIONS (Ta=0 70C, Vec=5V1+10%, GND=0V) Symbol Parameter Min. Max. Unit tcLK Clock Cycle Time 25 ns {GLKH Clock Pulse Width HIGH 10 ns tCLKL Clock Pulse Width LOW 10 ns tbs Data Setup Time 6 ns {DH Data Hold Time 1 ns teNS Enable Setup Time 6 ns tENH Enable Hold Time 1 ns tas Reset Pulse Width 25 ns tAss Reset Setup Time 25 ns tRSR Reset Recovery Time 25 ns tSKEW1 Skew time between Read Clock and Write Clock for Empty Flag and Full Flag 10 ns Skew time between Read Clock and Write Clock for Almost-Empty Flag and Almost-Full tSKEW2 Flag 40 ns 1.1kG AC TEST CONDITIONS In Pulse Levels GND -3.0V Input Rise/Fall Times 3ns DLT. Input Timing Reference Levels 1.5V Output Reference Levels 1.5 S800 30PF Output Load See Figure 4 Figure 4. Output Load Including Test board and scope capacitances.MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY * Reset Timing }______ iRS HH u_< _ ixsSsS oo IRSRO REN1 y > } REN2 __ ikSS Fpos iRSR -* wet XX} Or _ Rss SS RSA (1) WEN2/LD xx) OOK EF, PAE \\ <$<$<_ikRSFo __-+ RWWhQaA0 i AY aa_<___- iRSF FH FF, PAE YU Q0-8 Bin LLL wi_ (RSF -r OOVAMA\IUVUNwW NOTE: 1. I during reset WEN2/LD is HIGH, this signal functions as a second enable(WEN2). It during reset WEN2/LD is LOW this signal functions as an offset register.MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY Write Cycle Timing WCLK / DBo-Ds WEN1 WEN2/(if Applicable} RCLK REN1 REN2 NOTE: be aM@$A$ai CLK e tCLKH iCcLKL 7 |. tbs a skews () - WRF e Sk DROOL OX DATA IN VALID _ ea {ENS TENH NI Ye NO OPERATION IN MLD IN NO OPERATION A at iWEF PN NN | 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state untill the next WCLK edge.MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY * Read Cycle Timing RCLK 2/0 mim aig Dole Q0-8 WCLK WEN1 WEN2 NOTE : wi iCLK | pai tCLKH iCLKL re TENS TENH SANS V7 NO OPERATION QQ pa {REF i~ pa tREF bag AC et K VALID DATA tOHZ | t sews (1) ee ee ee NN A 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WOLK edge for EF to change during the current clock cycle. If the time between the rising edge of RGLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state untill the next ROLK edge.MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY First Data Word Latency Timing WCLK 4 Nw VN FY YN YY \_ 1DS t bo-Ds x Di x D2 x D3 x Do (First Valid) tENS WEN1 i$ Sk WEN2 x (If Applicable) tFRL CO) e TSKEW1 RK FON NY tREF EF REN1 REN2 a tAC rai 1AC 0-08 Bo D1 10LZ oc ... J NOTE : 1. When tSKEW12minimum specification, FRL maximum=tCLK+tSKEW1 . When tSKEW1=minimum specification, FRL maximum=2ICLK-+ISKEW1 or tCLK+tSKEW1.MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY * Full Flag Timing NO WRITE NO WRITE Welk SP \\N_#\_FYN 3 iSKEWI {SKEW tbs DATA WRITE D0-08 XK KAXOOKKKEK pa HWE bet tWEF ha {WEF FE WEN1 ~ WEN2 f (If Applicable) Reus NLA NY NY KI ONY tENH TENS TENS tENH REN1 REN2 fl LAC OE Low a TAC Q<8:0> DATA IN QUTPUT REGISTER x DATA READ NEXT DATA READMITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY * Empty Flag Timing wk NX NX N_ HNL \N _ DS DS i a a Bo-Ds DATA WRITE1 DATA WRITE2 x x x x x el 1ENS on 1ENS ~ WENt x] | sd - TL, ~ Y # QW | TENS mn 1ENS tENH WEN2 ae Ny < \ (If Applicable} 7 L2) peg te 1) ____J - 1SKEW!1 1SKEW1 RCLK REF EF REN1 REN2 Low OE ai AC 0-08 DATA IN OUTPUT REGISTER DATA READ NOTE : 1. When tSKEW12=minimum specification, FRL maximum=tCLK+SKEW1 . When tSKEW1<minimum specification, FRL maximum=2ICLK-+ISKEW1 or tCLK+tSKEW1.MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY * Programmable Full Flag Timing tCLKH tOLKL (4) wou BONNY NN TENS | tENH WEN 1 NS . 1 4p TENS | tENH WEN2 vo ~ XN (If Applicable) IN IPAF Full-m words in FIFO) PAF Full-(m+1) words in FIFO) ft pe IPAF skew) 1ENS | tENH REN1 LT - if, REND XQ XK 2 Ve NOTES : 1. PAF offset=m. 2. 64-m words in for M66850, 256-m words in for M66851,512-m words in for M66852, 1024-m words in for M66853. 3. tSKEW2 is the minimum time between a rising ROLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEWz, then PAF may not change state untill the next rising edge of WCLK. 4. If a write is performed on this rising edge of the write clock, there will be Full-(m-1} words in the FIFO when PAF goes LOW.MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY * Programmable Empty Flag Timing tCLKH tCLKL welK EON ONLY NY NV _Y TENS | tENH WEN AS "| HS/ fl WEN2 TENS tENH (If Applicable} = Af fz N A N. PAE n words in FIFOU) n+1 words in FIFO TPAE tskEwe () (3) RCLK tENS tENH RENt RENT Sk L7/ REN2 NOTES : 1. PAF offset=m. 2. tSKEW2 is the minimum time between a rising WCLK edge and a rising ROLK edge for PAE to change during that clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSkEWez, then PAE may not change state untill the next rising edge of RCLK. 3. If aread is performed on this rising edge of the read clock, there will be Empty+(n-1) words in the FIFO when PAE goes LOW.MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY * Write Offset Registers Timing CLK t] _tCLKH | tCLia__ Welk __7 OX ANN YNZ NN tENS | tENH i K | 7 OL LL 1ENS ~ WEN1 i I 1DS ~ 7H ON NN OS NS Do7 OOOO) PAE OFFSET PAE OFFSET PAF OFFSET PAF OFFSET (LSB) (MSB) (LSB) (MSB) * Read Offset Registers Timing | tCLKH | iCLKL wx IN NOLS TENH TENS _~ f 5| "4 \ TENS ~ REN1 wi REN2 I heag TAC 0-7 DATA IN OUTPUT REGISTER x x PAE OFFSET PAE OFFSET PAF OFFSET (LSB) (MSB) (LSB) PAF OFFSET (MSB) NOTE: Aread and write should not be performed simultaneously to the offset registers.MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY PARAMETER MEASURMENT INFORMATION 3V 11KG sw Qn Sw2 CL = 30pF : tAC, 1OEN, tODIS 680 Input Pulus Level :0-3V Input Pulus Rising time and Falling time :3ns Threshold voltage of Input / Output :1.5V But tPLZis decided at 10% of output pulse. tPHZis decided at 90% of output pulse. Output Load : Including Test board and scope capacitances. VOLTAGE WAVEFORM PROPAGATION DELAY TIMES 15V | GND | tAC tAC VOH | { 15V 15V Qn | 7 VOL 3.0V RCK 15V VOLTAGE WAVEFORM ENABLE AND DISABLE TIMES SE a 15V tPHz 4 390% Qn tPLz Item Swi swe tAc Close Close tPLZ Close Open tPHZ Open Close tPZL Close Open tPZH Open Close VOLTAGE WAVEFORM PULSE DURATION TIMES _- 7-7 3.0V ih 15V 15V High-Level | _ GND Input | tw | Low-Level | | 30V Input 15V 15V GND r TF TT TTS 3V 1.5V t GND tPZH 1sv 40 Vou }-___ | tPzL * Qn 15vV 4 _ te Le