24LC00T-E/OTVAO - Microchip

24AA00/24LC00/24C00

Device Selection Table

Features:

• Single supply with operation down to 1.7V for

24AA00 devices, 2.5V for 24 LC00 devices

• Low-power CMOS technology:

- Read current 500 μA, typical

- Standby current 100 nA, typical

• 2-wire serial interface, I2C™ compatible

• Schmitt Trigger in puts fo r noise suppression

• Output slope control to eliminate ground bounce

• 100 kHz and 400 kHz clock compatibility

• Page write time 3 ms, typical

• Self-timed erase/write cycle

• ESD protection >4000V

• More than 1 million erase/write cycles

• Data retention >200 years

• Factory programming available

• Packages include 8-lead PDIP, SOIC, TSSOP,

DFN and 5-lead SOT-23

• Pb-free and RoHS compliant

• Temperature ranges available:

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

Description:

The Microchip Technology Inc. 24AA00/24LC00/

24C00 (24XX00*) is a 128-bit Electrically Erasable

PROM memory organized as 16 x 8 with a 2-wire

serial interface. Low-voltage design permits operation

down to 1.7 volts for the 24AA00 version, and every

version maintains a maximum standby current of only

1 μA and typical active current of only 500 μA. This

device was designed for where a small amount of

EEPROM is needed for the storage of calibration

values, ID numbers or manufacturing information, etc.

The 24XX00 is available in 8-pin PDIP, 8-pin SOIC

(3.90 mm), 8-pin TSSOP, 8-pin 2x3 DFN and the 5-pin

SOT-23 packages.

Package Types

Block Diagram

Pin Function Table

Device VCC Range Temp Range

24AA00 1.7-5.5 I

24LC00 2.5-5.5 I

24C00 4.5-5.5 I,E

Name Function

VSS Ground

SDA Serial Data

SCL Serial Cloc k

VCC +1.7V to 5.5V (24AA00)

+2.5V to 5.5V (24LC00)

+4.5V to 5.5V (24C00)

NC No Internal Connec tio n

8-PIN PDIP/SOIC

8-PIN TSSOP

5-PIN SOT-23

Vss

VCC

SCL

SDA

VSS

VCC

SCL

SDA

SCL

VSS

SDA

VCC

DFN

VSS

SCL

SDA

VCC

HV Genera tor

EEPROM

Array

YDEC

XDEC

Sense AMP

R/W Cont rol

Memory

Control

Logic

I/O

Control

Logic

SDA SCL

VCC

VSS

128-Bit I2C™ Bus Serial EEPROM

*24XX00 is used in this document as a generic part number for

the 24AA00/24LC00/24C00 devices. I2C is a trademark of Philips Corporation.

24AA00/24LC00/24C00

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins..........................................................................................................................................4 kV

FIGURE 1-1: BUS TIMING DATA

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at those or any other conditions

above th ose indi cated in the opera tional li stings of this sp ecificati on is no t implie d. Exposu re to maxim um rating

conditions for extended periods may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

All Parameters apply across the

recommended operating ranges unless

otherwise noted

Industrial (I): TA = -40°C to +85°C, VCC = 1.8V to 5.5V

Automotive (E) TA = -40°C to +125°C, VCC = 4.5V to 5.5V

Parameter Symbol Min. Max. Units Conditions

SCL and SDA pins:

High-level in put voltage VIH 0.7 VCC —V(Note)

Low-level input voltage VIL —0.3 VCC V(Note)

Hysteresis of Schmitt Trigger

inputs VHYS .05 VCC —VVCC ≥ 2.5V (Note)

Low-level output voltage VOL —0.4VIOL = 3.0 mA, VCC = 4.5V

IOL = 2.1 mA, VCC = 2.5V

Input leakage current ILI —±1μAVIN = VCC or VSS

Output lea kage curre nt ILO —±1μAVOUT = VCC or VSS

Pin capacitance (all inputs/outputs) CIN,

COUT —10pFVCC = 5.0V (Note)

TA = 25°C, FCLK = 1 MHz

Operati ng current ICC Write — 2 mA VCC = 5.5V, SCL = 400 kHz

ICC Read — 1 mA VCC = 5.5V, SCL = 400 kHz

Standby current ICCS —1μAVCC = 5.5V, SDA = SCL = VCC

Note: This parameter is periodically sampled and not 100% tested.

TFTHIGH TR

TSU:STA

TLOW THD:DAT TSU:DAT TSU:STO

TBUF

TAA

TSP

SCL

SDA

OUT

THD:STA

24AA00/24LC00/24C00

TABLE 1-2: AC CHARACTERISTICS

All Parameters apply across all

recommended operating ranges

unless otherwise noted

Industrial (I): TA = -40°C to +85°C, VCC = 1.8V to 5.5V

Automotive (E): TA = -40°C to +125°C, VCC = 4.5V to 5.5V

Parameter Symbol Min Max Units Conditions

Clock frequency FCLK —

—

100

400

kHz 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.7V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

Clock high time THIGH 4000

4000

600

—

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.7V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

Clock low time TLOW 4700

4700

1300

—

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.7V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

SDA and SCL rise time

(Note 1) TR—

—

1000

300

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.7V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

SDA and SCL fall time TF—300ns(Note 1)

Start condition hold time THD:STA 4000

4000

600

—

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.7V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

Start condition setup time TSU:STA 4700

4700

600

—

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.7V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

Data input hold time THD:DAT 0—ns(Note 2)

Data input setup time TSU:DAT 250

250

100

—

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.7V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

Stop condition setup time TSU:STO 4000

4000

600

—

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.7V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

Output valid from clock

(Note 2) TAA —

—

3500

900

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.7V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

Bus free time: Time the b us must

be free before a new transmis-

sion can star t

TBUF 4700

4700

1300

—

ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)

1.7V ≤ Vcc ≤ 4.5V

4.5V ≤ Vcc ≤ 5.5V

Output fall time from VIH

minimum to VIL maximum TOF 20+0.1

CB 250 ns (Note 1), CB ≤ 100 pF

Input filter spike suppression

(SDA and SCL pins) TSP —50ns(Notes 1, 3)

Write cycle time TWC —4ms

Endurance 1M — cycles (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The co mbine d TSP and VHYS specifica tio ns are d ue to n ew Sc hm it t Trigger inp ut s w h ic h p rov id e i mp r oved

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimat es in a specific

application, please consult the Total Endurance™ Model which can be obtained at www.microchip.com.

24AA00/24LC00/24C00

2.0 PIN DESCRIPTIONS

2.1 SDA Serial Data

This is a bidirectional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pull-up

resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for

400 kHz).

For norma l data trans fer SDA is all owed to change only

during SCL low. Changes during SCL high are

reserved for indicating the Start and Stop conditions.

2.2 SCL Serial Clock

This i nput is u sed t o sy nchron ize the d ata trans fer fro m

and to the device.

2.3 Noise Protection

The SCL and SDA inputs have Schmitt Trigger and

filter circuits which suppress noise spikes to assure

proper device operation even on a noisy bus.

3.0 FUNCTIONAL DESCRIPTION

The 24XX00 supports a bidirectional 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as a transmitter, and a device

receiving data as a receiver. The bus has to be

controlled by a master device which generates the

Serial Clock (SCL), controls the bus access, and

generates the Start and Stop conditions, while the

24XX00 works as slave. Both master and slave can

operate as transmitter or receiver, but the master

device determines which mode is activated.

4.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stab le whene ver the cl ock lin e is high . Change s in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Fig ure 4-1).

4.1 Bus Not Busy (A)

Both data and clock lines remain high.

4.2 Start Data Transfer (B)

A hig h- to - lo w t ran si t i on of t h e SD A l in e whi l e t h e c lo ck

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

4.3 S top Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

4.4 Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one bit of data per

clock pulse.

Each dat a transf er is initiated w ith a S tart condition an d

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device and is

theoretically unlimited.

24AA00/24LC00/24C00

4.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this Acknowledge bit.

The device that acknowledges has to pull down the

SDA line du ring the Acknow ledge cl ock pulse in s uch a

way that the SDA line is stable low during the high

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by no t g ene rati ng an Ackno wled ge bi t on the las t

byte that has been clocked out of the slave. In this

case, the slave must leave the data line high to enable

the maste r to gen erat e the Stop condition (Figur e 4-2).

FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 4-2: ACKNOWLEDGE TIMING

Note: The 24XX00 does not generate any

Acknowledge bits if an internal program-

ming cycle is in progress.

(A) (B) (C) (D) (A)(C)

SCL

SDA

Start

Condition Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

SCL 987654321 123

Transmitter must release the SDA line at this point

allowing the Receiver to pull the SDA line low to

acknowledge the previous eight bits of data.

Receiver must release the SDA line at this point

so the Transmitter can conti nue sending data.

Data from transmitter Data from transmitter

SDA

Acknowledge

Bit

24AA00/24LC00/24C00

5.0 DEVICE ADDRESSING

After generating a Start condition, the bus master

transmits a control byte consisting of a slave address

and a Read/Write bit that indicates what type of

operatio n is to be perfo rmed. The slave add ress for the

24XX00 consists of a 4-bit device code ‘1010’ followed

by three “don’t care” bits.

The last bi t of the control byte determines the operation

to be perfo rme d. When set to a o ne a read operati on is

selected, and when set to a zero a write operation is

selected (Figure 5-1). The 24XX00 monitors the bus for

its corresponding slave address all the time. It

generate s an Ackn owledge bit if the s lave add ress was

true and it is not in a programming mode.

FIGURE 5-1: CONTROL BYTE FORMAT

6.0 WRITE OPERATIONS

6.1 Byte Write

Following the Start signal from the master, the device

code (4 bits), the “don’t care” bits (3 bits), and the R/W

bit (which is a logic low) are placed onto the bus by the

master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will

follow after it has genera ted an Acknowl edge bit durin g

the nint h clock cycl e. Therefo re, the next byte transmit-

ted by the master is the word address and will be

written into the Address Pointer of the 24XX00. Only

the low er four ad dress bits are us ed by the d evice , and

the upper four bits are “don’t cares.” The 24XX00 will

acknowledge the address byte and the master device

will then transmit the data word to be written into the

addressed memory location. The 24XX00 acknowl-

edges again and the master generates a Stop

condition. This initiates the internal write cycle, and

during this time the 24 XX00 will not ge nerate Ack nowl-

edge si gnals (Fi gure 7-2). Af ter a byte W rite comman d,

the internal address counter will not be incremented

and will point to t he same address location that was just

written. If a Stop bit is transmitted to the device at any

point in t he W rite comm and seque nce before the entire

sequence is complete, then the command will abort

and no data will be written. If more than 8 data bits are

transmitted before the Stop bit is sent, then the device

will clear the previously loaded byte and begin loading

the data buffer again. If more than one data byte is

transmitted to the device and a Stop bit is sent before a

full eight data bits have been transmitted, then the

Write command will abort and no data will be written.

The 24XX00 employs a VCC threshold detector circuit

which disables the internal erase/write logic if the VCC

is below 1.5V (24AA00 and 24LC00) or 3.8V (24C00)

at nominal conditions.

1010xxxSACKR/W

Device Select

Bits Don’t Care

Bits

Slave Address

Acknowledge Bit

Start Bit

Read/Write Bit

24AA00/24LC00/24C00

7.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the Stop condition for a Write

comma nd has been is sued from the master , the device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the master

sending a Start condition followed by the control byte

for a Write command (R/W = 0). If the device is still

busy with the write cycle, then no ACK will be returned.

If no AC K is retu rned, then the S t art bit and cont rol byte

must be re-sent. If the cycle is complete, then the

device will return the ACK and the master can then

proceed with the next Read or Write command. See

Figure 7-1 for flow diagram.

FIGURE 7-1: ACKNOWLEDGE

POLLING FLOW

FIGURE 7-2: BYTE WRITE

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

Yes

BUS ACT I VITY

MASTER

SDA LINE

BUS ACTIVITY

Control

Byte Word

Address Data

10 x10 xxx

x = “don’t care” bit

xxx

24AA00/24LC00/24C00

8.0 READ OPERATIONS

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one. Ther e are three ba sic types

of read operat ions: current add ress read , rand om rea d

and sequential read.

8.1 Current Address Read

The 24XX00 contains an address counter that main-

tains the address of the last word accessed, internally

incremented by one. Therefore, if the previous read

access was to address n, the next current address read

operatio n wou ld acc ess dat a fr om add ress n + 1. U pon

receipt of the slav e address w ith the R/W b it set to one,

the device issues an acknowledge and transmits the

eight-bit data word. The master will not acknowledge

the transfer , but do es generate a S top condition and the

device discontinues transmission (Figure 8-1).

8.2 Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this typ e of re ad ope ration, first the wo rd address mus t

be set. This is done b y sending the word address to the

device as part of a write operation.

After the word address is sent, the master generates a

Start condition following the acknowledge. This termi-

nates the write operation, but not before the internal

Address Pointer is set. Then the master issues the

control byte again, but with the R/W bit set to a one.

The 24XX00 will the n issue an a cknowled ge and trans -

mits the eight bit data word. The master will not

acknowledge the transfer, but does generate a Stop

condition and the device discontinues transmission

(Figure 8-2). After this command, the internal address

counter will point to the address location following the

one that was jus t read.

8.3 Sequentia l Read

Sequential reads are initiated in the same way as a

random read except that after the device transmits the

first data byte, the master issues an acknowledge as

opposed to a Stop condition in a random read. This

directs the device to transmit the next sequentially

addressed 8-bit word (Figure 8-3).

To provide sequential reads the 24XX00 contains an

internal Address Pointer which is incremented by one

at th e co mplet ion o f eac h r ead o peratio n. Thi s Add ress

Pointer allows the entire memory contents to be serially

read during one operation.

FIGURE 8-1: CURRENT ADDRESS READ

BUS ACT IV IT Y

MASTER

SDA LINE

BUS ACT IV IT Y

Control

Byte

TData

1100xxx1

x = “don’t care” bit

24AA00/24LC00/24C00

FIGURE 8-2: RANDOM READ

FIGURE 8-3: SEQUENTIAL READ

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

Control

Byte

Word

Address(n) Control

Byte

TData (n)

x xxx

S1100xxx0 S110 0xxx1

x = “don’t care” bit

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

Control

Byte

Data n Data n + 1 Data n + 2 Data n + x

24AA00/24LC00/24C00

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

XXXXXXXX

T/XXXNNN

YYWW

8-Lead PDIP (300 mil) Example:

8-Lead SOIC (3.90 mm) Example:

XXXXXXXT

XXXXYYWW

NNN

8-Lead TSSOP Example:

24LC00

I/P 13F

0527

24LC00I

SN 0527

13F

XXXX

TYWW

NNN

4L00

I527

13F

5-Lead S OT-23 Example:

XXNN M03F

8-Lead 2x3 DFN Example:

204

527

XXX

YWW

24AA00/24LC00/24C00

Part Number

1st Line Marking Codes

TSSOP SOT-23 DFN

I Temp. E Temp. I Temp. E Temp.

24AA00 4A00 B0NN — 201 —

24LC00 4L00 M0NN — 204 —

24C00 4C00 D0NN E0NN 207 208

Note: NN = Alphanumeric traceability code

Legend: XX...X Part number or part number code

T Temperature (I, E)

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week c ode (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event th e full Mi croch ip pa rt numbe r canno t be ma rked on one line , it wil

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.

*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.

24AA00/24LC00/24C00

8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP]

otes:

. Pin 1 visual index feature may vary, but must be located with the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e .100 BSC

Top to Seating Plane A – – .210

Molded Package Thickness A2 .115 .130 .195

Base to Seating Plane A1 .015 – –

Shoulder to Shoulder Width E .290 .310 .325

Molded Package Width E1 .240 .250 .280

Overall Length D .348 .365 .400

Tip to Seating Plane L .115 .130 .150

Lead Thickness c .008 .010 .015

Upper Lead Width b1 .040 .060 .070

Lower Lead Width b .014 .018 .022

Overall Row Spacing § eB – – .430

NOTE 1

Microchip Technology Drawing C04-018

24AA00/24LC00/24C00

8-Lead Plastic Small Outl ine (SN or OA) – Narrow, 3.90 mm Body [SOIC]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Ref erence Dimen sion, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 1.27 BSC

Overall Height A – – 1.75

Molded Package Thickness A2 1.25 – –

Standoff §A1 0.10 – 0.25

Overall Width E 6.00 BSC

Molded Package Width E 1 3.90 BSC

Overall Length D 4.90 BSC

Chamfer (optional) h 0.25 – 0.50

Foot Length L 0.40 – 1.27

Footprint L1 1.04 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.17 – 0.25

Lead Width b 0.31 – 0.51

Mold Draft Angle Top α5° – 15°

Mold Draft Angle Bottom β5° – 15°

NOTE 1

12 3

Microchip Technology Drawing C04-057

24AA00/24LC00/24C00

8-Lead Plastic Thin Shri nk Small Outline (ST) – 4.4 mm Body [TSSOP]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 0.65 BSC

Overall Height A – – 1.20

Molded Package Thickness A2 0.80 1.00 1.05

Standoff A1 0.05 – 0.15

Overall Width E 6.40 BSC

Molded Package Width E1 4.30 4.40 4.50

Molded Package Length D 2.90 3.00 3.10

Foot Length L 0.45 0.60 0.75

Footprint L1 1.00 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.09 – 0.20

Lead Width b 0.19 – 0.30

NOTE 1

L1 L

Microchip Technology Drawing C04-086

24AA00/24LC00/24C00

8-Lead Plastic Dual Fla t, No Lead Package (MC) – 2x3x0.9 mm Body [DFN]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Package may have one or more exposed tie bars at ends.

. Package is saw singulated.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 0.50 BSC

Overall Height A 0.80 0.90 1.00

Standoff A1 0.00 0.02 0.05

Contact Thickness A3 0.20 REF

Overall Length D 2.00 BSC

Overall Width E 3.00 BSC

Exposed Pad Length D2 1.30 – 1.75

Exposed Pad Width E2 1.50 – 1.90

Contact Width b 0.18 0.25 0.30

Contact Length L 0.30 0.40 0.50

Contact-to-Exposed Pad K 0.20 – –

NOTE 1

EXPOSED PAD

NOTE 1

A3A1

NOTE 2

BOTTOM VIEW

TOP VIEW

Microchip Technology Drawing C04-123

24AA00/24LC00/24C00

5-Lead Plastic Small Outl ine Transistor (OT or CT) [SOT-23]

otes:

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 5

Lead Pitch e 0.95 BSC

Outside Lead Pitch e1 1.90 BSC

Overall Height A 0.90 – 1.45

Molded Package Thickness A2 0.89 – 1.30

Standoff A1 0.00 – 0.15

Overall Width E 2.20 – 3.20

Molded Package Width E1 1. 30 – 1.80

Overall Length D 2.70 – 3.10

Foot Length L 0.10 – 0 .60

Footprint L1 0.35 – 0.80

Foot Angle φ0° – 30°

Lead Thickness c 0.08 – 0.26

Lead Width b 0.20 – 0.51

123

A2 c

Microchip Technology Drawing C04-091

24AA00/24LC00/24C00

APPENDIX A: REVISION HISTORY

Revision E

Added DFN package.

Revision F (02/2007)

Revised Device Selection Table; Features Section;

Changed 1.8V to 1.7V; Revised Tables 1-1, 1-2;

Revised Product ID System; Replaced Package

Drawings; Replac ed On-line Supp ort page.

Revision G (03/2007)

Replaced Package Drawings (Rev. AM).

24AA00/24LC00/24C00

NOTES:

24AA00/24LC00/24C00

THE MICROCHIP WEB SITE

Microc hip pro vides onl ine s upport v ia our W WW site at

www.microchi p.c om . Thi s web si te i s us ed as a m ean s

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

•Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

docume nts , latest softw are releas es and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online dis cu ss io n gr oups, Micro chi p con sul tant

program member listing

•Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of sem i nar s and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specif ied produ ct family or develo pment tool of interes t.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Development Systems Information Line

Customers should contact their distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical s upport is a vailable through the web site

at: http://support.microchip.com

24AA00/24LC00/24C00

READER RESPONSE

It is ou r intentio n to provide you with the b es t do cument a t ion po ss ib le to e ns ure suc c es sfu l u se of y ou r M icr oc hip pro d-

uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, subj ect matte r , and ways i n which o ur docum entatio n

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager

RE: Reader Response Total Pages Sent ________

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS21178G24AA00/24LC00/24C00

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

24AA00/24LC00/24C00

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

X/XX

PackageTemperature

Range

Device

Device: 24AA00: = 1.7V, 128 bit I2C™ Serial EEPROM

24AA00 T: = 1.7V, 128 bit I2C Serial EEPROM

(Tape and Reel)

24LC00: = 2.5V, 128 bit I2C Serial EEPROM

24LC00T: = 2.5V, 128 bit I2C Serial EEPROM

(Tape and Reel)

24C00: = 5V, 128 bit I2C™ Serial EEPROM

24C00T: = 5V, 128 bit I2C™ Serial EEPROM

(Tape and Reel)

Temperature

Range: I = -40°C to +85°C

E = -40°C to +125°C

Package: P = Plastic DIP (300 mil body), 8-lead

SN = Plastic SOIC (3.90 mm body ), 8-lead

ST = Plastic TSSOP (4.4 mm), 8-lead

OT = S OT-23, 5-lead (Tape and Reel only)

MC = 2x3 DFN, 8-lead

Examples:

a) 24AA00-I/P: Industrial Temperature,1.8V

PDIP package

b) 24AA00-I/SN: Industrial Temperature,

1.8V, SOIC package

c) 24AA00T-I/OT: Industrial Temperature,

1.8V, SOT- 23 package, tape and reel

d) 24LC00-I/P: Industrial Temperature,

2.5V, PDIP package

e) 24C00-E/SN: Extended Temperature,

5V, SO IC packa g e

f) 24LC00T-I/OT: Industrial Temperature,

2.5V, SOT- 23 package, tape and reel

24AA00/24LC00/24C00

NOTES:

Information contained in this publication regarding device

applications a nd the lik e is provid ed only for your c on ve nience

and may be supers eded by u pdates. I t is y o u r r es ponsibil i ty to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmic ro, PI C START, PRO MATE, PowerSmart, rfP IC, and

SmartShunt are registered trademark s of Microchip

Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable

Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor

and The Embedded Control Solutions Company are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,

MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInf o, PowerMate, PowerTool, REAL ICE , rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporat ed in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that it s family of products is one of the most secure families of it s kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microchip are commit ted to continuously improving the code protect ion featur es of our

products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

T empe, Arizona, Gresham, Oregon and Mountain View , California. The

Company’s quality system processes and procedures are for its PIC®

MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

AMERICAS

Corporate Office

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Web Address:

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WORLDWIDE SALES AND SERVICE

12/08/06