SST32HF32A1-70-4C-LSE - Silicon Storage Technology

S71260-01-000 5/05

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF+ and ComboMemory are trademarks of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Preliminary Specificat ions

FEATURES:

• ComboMemories organized as:

– 2M x16 Flash + 1024K x16 PSRAM

• Single 2.7-3.3V Read and Write Operations

• Concurrent Operation

– Read from or Write to PSRAM while

Erase/Program Flash

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Ret ention

• Low Power Consumption:

– Active Current: 15 mA (typical) for

Flash or PSRAM Read

– Standby Current: 60 µA (typical)

• Fle xible Erase Capabilit y

– Uniform 2 KWord sectors

– Uniform 32 KWord size blocks

• Erase-Suspend/Erase-Resume Capabilities

• Security-ID Feature

– SST: 128 bits; User: 128 bits

• Hardware Block-Protection/WP# Input Pin

– Bottom Block-Protection (b ot tom 32 KWord)

for SST32HF3 2A1

• Fast Read Access Times:

– Flash: 70 ns

– PSRAM: 70 ns

• Latched Address and Data for Flash

• Flash Fast Erase and Word-Program:

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 40 ms (typical)

– Word-Program Time: 7 µs (typical)

• Flash Automatic Erase and Program Timing

– Internal VPP Generation

• Flash End-of-Write Detection

– Toggle Bit

– Data# Po lling

• CMOS I/O Compatibility

• JEDEC Standard Command Set

• Package Available

– 63-ball LFBGA (8mm x 10mm x 1.4mm)

– 62-ball LFBGA (8mm x 10mm x 1.4mm)

• All non-Pb (lead-free) de vices are RoHS compliant

PRODUCT DESCRIPTION

The SST32HF32A1 ComboMemory devices integrate a

CMOS flash memor y bank with a CMOS Pseu doSRAM

(PSRAM) memory bank in a Multi-Chip Package (MCP),

manufactured with SST’s proprietary, high-performance

SuperFlash technology.

Featuring high-performance Word-Program, the flash

memory bank provides a maximum Word-Progra m t ime of

7 µsec. To protect against inadvertent flash write, the

SST32HF32A1 devices contain on-chip hardw are and soft-

ware data protection schemes. The SST32HF32A1

devices offer a guaranteed endurance of 10,000 cycles.

Data retention is rat ed at greater than 100 y ears.

The SST32HF32A1 devices consist of two independent

memory banks with respective bank enable signals. The

flash and PSRAM memory banks are superimposed in the

same memory address space. Both memory banks share

common address lines, data lines, WE# and OE#. The

memory bank selection is done by memory bank enable

signals. The PSRAM bank enable sign al, BES# selects the

PSRAM bank. The flash memory bank enable signal,

BEF# selects the f lash memory bank. The WE# signal has

to be used with Softw are Data Prot ection (SDP) command

sequence when controlling the Erase and Program opera-

tions in the flash memory bank. The SDP command

sequence protects the data stored in the flash memory

bank from accidental alter ation.

The SST32HF32A1 provide the added functionality of

being able to simultaneously read from or write to the

PSRAM bank while erasing or programming in the flash

memory bank. The PSRAM memor y bank can be read or

written while the flash memory bank performs Sector-

Erase, Bank-Erase, or Word-Program concurrently. All

flash memory Erase and Program operations will automati-

cally latch the in put address and data signals and complete

the operation in background without further input stimulus

requirement. Once the internally controlled Erase or Pro-

gram cycle in the flash bank has commenced, the PSRAM

bank can be a ccessed f or Read or Write .

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

SST32HF32A1 32Mb Flash + 4Mb SRAM, 32Mb Flash + 8Mb SRAM

(x16) MCP Com boMemori es

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

The SST32HF32A1 de vices are suited f or applicat ions that

use both flash memory and PSRAM memory to store code

or data. For systems requiring low power and small form

factor, the SST32HF32A1 devices significantly improve

perf ormance and reliability, while low ering power consump-

tion, when compared with multiple chip solutions. The

SST32HF32A1 inherently use less energy during erase

and program than alternative flash technologies. The total

energy consumed is a function of the applied voltage, cur-

rent, and time of application. Since for any given voltage

range , the SuperFlash technology uses less current to pro-

gram and has a shor ter erase time, the total energy con-

sumed during any Erase or Pr ogr am operat ion is less than

alternative flash technologies .

The SuperFlash technology provides fixed Erase and Pro-

gram ti mes, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardw are does no t ha v e t o be modified or de-r ated as is

necessary with alternative flash technologies , whose Erase

and Program times increase with accumulated Erase/ Pro-

gram cycles.

Device Operation

The SST32HF32A1 use BES1#, BES2 and BEF# to con-

trol operation of either the flash or the PSRAM memory

bank. When BEF# is low, the flash bank is activated for

Read, Program or Erase operation. When BES1# is low,

and BES2 is high the PSRAM is activated for Read and

Write operation. BEF# and BES1# cannot be at low level,

and BES2 cannot be at high level at the same time. If all

bank enable signals are asserted, bus contention will

result and the device may suffer permanent damage.

All address, d ata, and control line s are shared b y flash an d

PSRAM memory banks which minimizes po w er consump-

tion and loading. The device goes into standby when BEF#

and BES1# bank enab les are raised to VIHC (Logic High) or

when BEF# is high and BES2 is low.

Concurrent Read/Write Operation

The SST32HF32A1 provide the unique benefit of being

able to read from or wr ite to PSRAM, while simultaneously

erasing or programming the flash. This allows data alter-

ation code to be executed from PSRAM, while altering the

data in flash. See Figure 26 for a flowchar t. The following

table lists all valid states .

The devic e will ignore all SDP commands when an Erase

or Program operation is in progress. Note that Product

Identification commands use SDP; therefore, these com-

mands will also be ignored while an Erase or Program

operatio n is in progress .

Flash Read Operation

The Read oper ation of the SST32HF32 A1 devices is con-

trolled by BEF# and OE#. Both have to be low, with WE#

high, f or the system to obtain data from the outputs. BEF#

is used for flash memory bank selection. When BEF# is

high, the chip is deselected and only standby power is

consumed. OE# is the output contro l and is used to gate

data from the ou tput pins. The data bus is in high imped-

ance state when OE# is high. Refer to Figure 6 for further

details.

CONCURRENT READ/WRITE STATE TABLE

Flash PSRAM

Program/Erase Read

Program/Erase Write

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

Flash Word-Program Operation

The flash memory bank of the SST32HF32A1 devices is

programmed on a word-by-word basis. Before Program

operatio ns, the memory must be er ased first. The Progr am

operatio n consists of three steps . The first step is the t hree-

byt e load sequence for Software Data Protect ion. The sec-

ond step is to load w ord address and w ord data. During the

W ord-Program oper ation, the addresses are latched on the

falling edge of either BEF# or WE#, whichever occurs last.

The data is latched on the rising edge of either BEF# or

WE#, whichever occurs last. The third step is the internal

Progra m operation which is initiat ed after the rising edge of

the four th WE# or BEF#, whichever occurs first. The Pro-

gram operation, once initiated, will be completed, within 10

µs. See Figures 7 and 8 f or WE# and BEF# contro lled Pro-

gram operation timing diagrams and Figure 21 for flow-

charts. During the Program operation, the only valid flash

Read operations are Data# Polling and Toggle Bit. During

the internal Program operation, the host is free to perform

additional tasks. During the command sequence, WP#

should be statically held high or low. Any SDP commands

loaded during the internal Program operation will be

ignored.

Flash Sector/Block-Erase Operation

The Flash Sector/Bloc k -Erase oper ation allo ws the system

to erase the device on a sector-by-sector (or block-by-

block) basis. The SST32HF32A1 offer both Sector-Erase

and Block-Erase mode. The sector architecture is based

on uniform sector size of 2 KWord. The Bloc k-Erase mode

is based on unifor m block size of 32 KWord. The Sector-

Erase operation is initiated by executing a six-byte com-

mand sequence with Sector-Erase command (30H) and

sector address (SA) in the last b us cycle. The address lines

AMS-A11 are used to determine the sector address. The

Block-Erase operation is initiated by executing a six-byte

command sequence with Block-Erase command (50H)

and block address (BA) in the last bus cycle. The address

lines AMS-A15 are used to determine the block address.

The sector or b lock address is lat ched on the f alling edge of

the sixth WE# pulse, while the command (30H or 50H) is

latched on the rising edge of the sixth WE# pulse. The

internal Erase operation begins after the sixth WE# pulse.

The End-of-Erase operation can be determined using

either Data# Polling or Toggle Bit methods . Se e Figures 12

and 13 f or timing wa vef orms. Any commands issued during

the Sector- or Block-Erase operation are ignored, WP#

should be statically he ld high or lo w .

Erase-Suspend/Erase-Resume Commands

The Erase-Suspend operation temporarily suspends a

Sector- or Block-Erase operation thus allowing data to be

read from any memor y location, or program data into any

sector/block that is not suspended for an Erase operat ion.

The operation is executed by issuing one byte command

sequence with Erase-Suspend command (B0H). The

device automatically enters read mode typically within 20

µs after the Erase-Suspend command had been issued.

Valid data can be read from any sector or block that is not

suspended from an Erase operation. Reading at address

location within erase-suspended sectors/blocks will output

DQ2 toggling and DQ6 at “1”. While in Erase-Suspend

mode, a Word-Program operation is allowed except for the

sector or b loc k selected for Erase-Suspend.

To resume Sector-Erase or Block-Erase operation which has

been suspended the system must issue Erase Resume

command. The operation is executed by issuing one byte

command sequence with Erase Resume command (30H)

at any address in the last Byte sequence.

Flash Chip-Erase Operation

The SST32HF32A1 provide a Chip-Erase operation,

which allows the user to erase the entire memory array to

the “1” state . This is useful when the ent ire de vice must be

quickly erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command

(10H) at address 5555H in the last byte sequence. The

Erase operation begins with the rising edge of the sixth

WE# or BEF#, whichever occurs first. During the Erase

operation, the only v alid read is Toggle Bit or Data# P olling.

See Tab le 5 f or t he command sequence , Figure 1 0 f or tim-

ing diagram, and Figure 25 for the flowchart. Any com-

mands issued during the Chip-Erase operation are

ignored.

Write Operation Status Detection

The SST32HF32A1 provide two software means to detect

the completion of a write (Prog ram or Era se) cycle, in order

to optimize the system Write cycle time. The software

detection includes tw o stat us bits: Data# Polling (DQ7) and

Toggle Bit (DQ6). The End-of-Write detection mode is

enabled after the rising edge of WE#, which initiates the

internal Program or Er ase operation.

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

The actual completion of the nonvolatile wr ite is asynchro-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the Write cycle. If this occurs, the system may possibly

get an erroneous result, i. e., valid data may appear to con-

flict with either DQ7 or DQ6. In order to prevent spurious

rejection, if an err oneous result occurs , the softw are routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the Write cycle, otherwise the rejec-

tion is v alid.

Flash Data# Polling (DQ7)

When the SST32HF32A1 flash memory banks are in the

internal Program operation, any attempt to read DQ7 will

produce the complement of the true data. Once the Pro-

gram operation is completed, DQ7 will produce true data.

Note that even though DQ7 may have valid data immedi-

ately following the completion of an internal Write opera-

tion, the remaining data outputs may still be invalid: valid

data on the entire data bus will appear in subsequent suc-

cessive Read cycles after an interval of 1 µs. Dur ing inter-

nal Erase operation, any attempt to read DQ7 will produce

a ‘0’. Once the internal Erase operation is completed, DQ7

will produce a ‘1’. The Data# Polling is valid after the rising

edge of the f ourth WE# (or BEF#) pulse f or Program opera-

tion. For Sector- or Block-Erase, the Data# Polling is valid

after the rising edg e of the sixth WE# (or BEF#) pu lse. See

Figure 9 f or Data# Polling timing diagr am and Figure 22 for

a flowcha rt.

Toggle Bits (DQ6 and DQ2)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating “1”s

and “0”s, i.e., toggling between 1 and 0. When the inter nal

Program or Erase operation is completed, the DQ6 bit will

stop toggling. The device is then ready for the next opera-

tion. F or Sector-, Bloc k-, or Chip-Erase , the toggle bit (DQ6)

is valid after the r ising edge of sixth WE# (or BEF#) pulse.

DQ6 will be set to “1” if a Read operation is attempted on an

Erase-Suspended Sector/ Block. If Progr am operation is ini-

tiated in a sector/block not selected in Erase-Suspend

mode, DQ6 will toggle.

An additional Toggle Bit is available on DQ2, which can be

used in conjunction with DQ6 to check whether a pa rticular

sector is being activ ely erased or erase-suspended. Table 1

shows detailed status bits information. The Toggle Bit

(DQ2) is valid after the rising edge of the last WE# (or

BEF#) pulse of Write operation. See Figure 10 for Toggle

Bit timing diagr am and Figure 22 f or a flo wchart.

Note: DQ7 and DQ2 require a valid address when reading

status information.

Flash Memory Data Protection

The SST32HF32A1 flash memory bank provides both

hardware and software features to protect nonvolatile data

from inadv ertent writes.

Flash Hardware Data Protection

Noise/Glitch Protection: A WE# or BEF# pulse of less than

5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#

high will inhibit the flash Write operation. This prevents

inadv ertent writes during pow er-up or po wer-do wn.

TABLE 1: WRITE OPERATION STATUS

Status DQ7DQ6DQ2

Normal

Operation Standard

Program DQ7# Toggle No Toggle

Standard

Erase 0 Toggle Toggle

Erase-

Suspend

Mode

Read from

Erase-Suspended

Sector/Block

1 1 Toggle

Read from

Non- Erase-Suspended

Sector/Block

Data Data Data

Program DQ7# Toggle N/A

T1.0 1260

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

Hardware Block Protection

The SST32HF32A1 support bottom hardware block pro-

tection, which protects the bottom 32 KWord block of the

device. The Boot Block address is 000000H-007FFFH.

Program and Erase operations are prevented on the 32

KWord when WP# is low. If WP# is left floating, it is inter-

nally held high via a pull-up resistor, and the Boot Block is

unprotected, enabling Program and Erase operations on

that b loc k.

Hardware Reset (RST#)

The RST# pin provides a hardw are method of resetting the

device to read array data. When the RST# pin is held low

f or at least TRP, an y in-progress operation will terminate and

return to Read mode. When no internal Program/Erase

operation is in progress, a minimum period of TRHR is

required after RST# is driven high before a valid Read can

tak e place (see Figure 17).

The Erase or Program operation that has been interrupted

needs to be reinitiated after the device resumes normal

operatio n mode to ensure data integrity.

Flash Software Data Protection (SDP)

The SST32HF32A1 provide the JEDEC appro ved software

data protection scheme for all flash memory bank data

alteration operations, i.e., Program and Erase. Any Pro-

gram operation requires the inclusion of a series of three-

byte sequence. The three byte-load sequence is used to

initiate the Program operation, providing optimal protecti on

from inadver tent Write operations, e.g., during the system

power-up or power-down. Any Erase operation requires the

inclusion of six-byte load sequence. The SST32HF32A1

devices are shipped with the software data protection per-

manently enabled. See Table 5 for the specific software

command codes . During SDP command sequence , in valid

commands will abort the de vice to Read mode , within TRC.

The cont ents of DQ15-DQ8 can be VIL or VIH, but no other

v alue, during any SDP command sequence .

PSRAM Read

The PSRAM Read operation of the SST 32 HF3 2A 1 is con -

trolled by OE# and BES1#, both have to be low with WE#

and BES2 high fo r the system to obtain data from the out-

puts. BES1# and BES2 are used for PSRAM bank selec-

tion. OE# is the output control and is used to gate data from

the output pins. The data bus is in high impedance state

when OE# is high. Ref er to the Read cycle timing diag ram,

Figure 3, f or further details.

PSRAM Write

The PSRAM Write operation of the SST32HF32A1 is con-

trolled by WE# and BES1#, both have to be low, BES2

must be high f or t he system to write to the PSRAM. During

the Word-Write operation, the addresses and data are ref-

erenced to the rising edge of either BES1#, WE#, or the

falling edge of BES2 whichever occurs first. The write time

is measured from the last falling edge of BES#1 or WE# o r

the rising edge of BES2 to the first rising edge of BES1#, or

WE# or the falling edge of BES2. Refer to the Write cycle

timing diagr ams, Figures 4 and 5, f or further details.

Product Identification

The Product Identification mode identifies the devices as

the SST32HF32A1 and manufacturer as SST. This mode

may be accessed by software operations only. The

hardware device ID Read operation, which is typically

used by programmers, cannot be used on this device

because of the shared lines between flash and PSRAM

in the multi-chip package. Therefore, application of

high voltag e to pin A9 may damag e this device . Users

may use the software Product Identification operation to

identify the part (i.e., using the device ID) when using multi-

ple manufacturers in the same socket. For details, see

Tables 4 and 5 for software operation, Figure 14 for the

software ID entry and read timing diagram and Figure 23

f or the ID entry command sequence fl owchart.

TABLE 2: PRODUCT IDENTIFICATION

Address Data

Manufacturer’ s ID 0000H BFH

Device ID

SST32HF32A1 0001H 235BH

T2.1 1260

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

Product Identification Mode Exit/Reset

In order to return to the standard read mode, the Software

Product Identification mode must be exited. Exiting is

accomplished by issuing the Exit ID command sequence,

which returns the device to the Read operation. Please

note that the softw are rese t command is ignore d during an

internal Program or Erase operation. This command may

also be used to reset the device to Read mode after any

inadver tent transient condition that apparently causes the

device to behave abnormally, e.g. not read correctly. See

Table 5 for software command codes, Figure 15 for timing

wa v ef orm and Figure 23 f or a flo wchart.

Security ID

The SST32HF32A1 devices offer a 256-bit Security ID

space. The Secure ID space is divided into two 128-bit seg-

ments - one factory programmed segment and one user

programmed segment. The first segment is programmed

and loc ked at SST with a rando m 128-bit number . The user

segment is left un-programmed for the customer to pro-

gram as desire d.

To program the user segment of the Security ID, the user

must use the Security ID Word-Program command. To

detect end-of-write for the SEC ID, read the toggle bits. Do

not use Data# Polling. Once this is complete, the Sec ID

should be locked using the User Sec ID Program Lock-Out.

This disables any future corruption of this space. Note that

regardless of whether or not the Sec ID is locked, neither

Sec ID segment can be erased.

The Secure ID spa ce can be queried b y ex ecuting a three-

byte command sequence with Enter Sec ID command

(88H) at address 5555H in the last byte sequence. To exit

this mode, the Exit Sec ID command should be exec uted.

Ref er to Table 5 for more details .

Design Considerations

SST recommends a high frequency 0.1 µF cer amic capac-

itor to be placed as close as possible between VDD and

VSS, e.g., less than 1 cm away from the VDD pin of the

device. Additionally, a low frequency 4.7 µF electrolytic

capacitor from VDD to VSS should be placed within 1 cm of

the VDD pin.

I/O Buffers

1260 B1.1

Address Buffers

DQ15 - DQ

MS-A0WE1#

SuperFlash

Memory

PSRAM

Control Logic

BES1#

BES2

BEF#

OE1#

RESET#

WP#

Address Buffers

& Latches

LBS#

UBS#

DQ7 - DQ

Notes: 1. For LS package only: WE# = WEF# and/or WES#

OE# = OEF# and/or OES#

FUNCTIONAL BLOCK DIAGRAM

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

FIGURE 1: PIN ASSIGNMENTS FOR 62-BALL LFBGA (8MM X 10MM)

FIGURE 2: PIN ASSIGNMENTS FOR 63-BALL LFBGA (8MM X 10MM)

1260 62-tfbga LS P1.4

A20

A16

WEF#

VSSS

WP#

LBS#

A18

A11

RST#

UBS#

A17

A15

A10

A19

OES#

A14

DQ11

A13

DQ15

DQ13

DQ12

DQ9

BEF#

A12

WES#

DQ6

BES2

DQ10

DQ8

VSSF

DQ14

DQ4

VDDS

DQ2

DQ0

OEF#

DQ7

DQ5

VDDF

DQ3

DQ1

BES1#

A B C D E F G H J K

TOP VIEW (balls facing down)

SST32HF32A1

1260 63-tfbga LFS P2.2

A11

WE#

WP#

LBS#

A15

A12

A19

BES2

RST#

UBS#

A13

A20

A18

A14

A10

A17

A16

DQ6

DQ1

VSS

DQ15

DQ13

DQ4

DQ3

DQ9

OE#

BEF#

VSS

DQ7

DQ12

VDDS

VDDF

DQ10

DQ0

BES1#

DQ14

DQ5

DQ11

DQ2

DQ8

A B C D E F G H J K

TOP VIEW (balls facing down)

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

TABLE 3: PIN DESCRIPTION

Symbol Pin Name Functions

AMS1 to A0Address Inputs To provide flash address, AMS-A0.

To provide PSRAM address, AMS-A0

DQ15-DQ0Data Inputs/Outputs To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a flash Erase/Program cycle. The outputs are

in tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high.

BEF# Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low

BES1# PSRAM Memory Bank Enable To activate the PSRAM memory bank when BES1# is low

BES2 PSRAM Memory Bank Enable To activate the PSRAM memory bank when BES2 is high

OEF#2Output Enable To gate the data output buffers fo r Flash 2 only

OES#2Output Enable To gate the data output buffers for PSRAM2 only

WEF#2Write Enable To control the Wri te operations for Flash2 only

WES#2Write Enable To control the Wri te operations for PSRAM2 only

OE# Output Enable To gate the data output buffers

WE# Write Enable To control the Write operations

UBS# Upper Byte Control (PSRAM) To enable DQ15-DQ8

LBS# Lower Byte Control (PSRAM) To enable DQ7-DQ0

WP# Write Protect To protect and unprotect sectors from Erase or Program operation

RST# Reset To Reset and return the device to Read mode

VSSF2Ground Flash2 only

VSSS2Ground PSRAM2 only

VSS Ground

VDDFPower Supply (Flash) 2.7-3.3V Po wer Supply to Flash only

VDDSPower Supply (PSRAM) 2.7-3.3V Power Supply to PSRAM only

NC No Connection Unconnected pins

T3.1 1260

1. AMS = Most Significant Address

AMS = A20 for SST32HF32A1

2. LS package only

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

TABLE 4: OPERATIONAL MODES SELECTION1

Mode BEF# BES1# BES22OE#3WE#3LBS# UBS# DQ0-7 DQ8-15

Full Standby VIH VIH XXXXXHIGH-ZHIGH-Z

IL XXXX

Output Disable VIH VIL VIH VIH VIH XXHIGH-Z HIGH-Z

VIL VIH XXV

IH VIH

VIL VIH XV

IH VIH XXHIGH-ZHIGH-Z

Flash Rea d VIL VIH XV

IL VIH XXD

OUT DOUT

Flash Write VIL VIH X VIH VIL XXD

IN DIN

Flash Erase VIL VIH XV

IH VIL XX X X

PSRAM Read VIH V

IL VIH VIL VIH VIL V

IL DOUT DOUT

VIH VIL HIGH-Z DOUT

VIL VIH DOUT HIGH-Z

PSRAM Write VIH VIL VIH XV

IL VIL VIL DIN DIN

VIH VIL HIGH-Z DIN

VIL VIH DIN HIGH-Z

Product

Identification4VIL VIH X VIL VIH X X Manufacturer’s ID5

Device ID5

T4.1 1260

1. X can be VIL or VIH, but no other value.

2. Do not apply BEF# = VIL, BES1# = VIL and BES2 = VIH at the same time

3. OE# = OEF# and OES#

WE# = WEF# and WES# for LS package only

4. Software mode only

5. With AMS-A1 = 0;SST Manufacturer’s ID = 00BFH, is read with A0=0,

SST32HF32A1 Device ID = 235BH, is read with A0=1.

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

TABLE 5: SOFTWARE COMMAND SEQUENCE

Command

Sequence 1st Bus

Write Cycle 2nd Bus

Write Cycle 3rd Bus

Write Cycle 4th Bus

Write Cycle 5th Bus

Write Cycle 6th Bus

Write Cycle

Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2

Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA3Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX430H

Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX450H

Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Erase-Suspend XXXXH B0H

Erase-Resume XXXXH 30H

Query Sec ID55555H AAH 2AAAH 55H 5555H 88H

User Security ID

Word-Program 5555H AAH 2AAAH 55H 5555H A5H WA6Data

User Security ID

Program Lock-Out 5555H AAH 2AAAH 55H 5555H 85H XXH60000H

Software ID Entry7,8 5555H AAH 2AAAH 55H 5555H 90H

Software ID Exit9,10

/Sec ID Exit 5555H AAH 2AAAH 55H 5555H F0H

Software ID Exit9,10

/Sec ID Exit XXH F0H

T5.1 1260

1. Address format A14-A0 (Hex).

Addresses A15-A20 can be VIL or VIH, but no other value, for Command sequence for SST32HF32A1.

2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence

3. WA = Program Word address

4. SAX for Sector-Erase; uses AMS-A11 address lines

BAX, for Block-Erase; uses AMS-A15 address lines

AMS = Most significant address

AMS = A20 for SST32HF32A1

5. With AMS-A4 = 0; Sec ID is read with A3-A0,

SST ID is read with A3 = 0 (Address range = 000000H to 000007H),

User ID is read with A3 = 1 (Address range = 000010H to 000017H).

Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.

6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H.

7. The device does not remain in Software Product ID Mode if powered down.

8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0,

SST32HF32A1 Device ID = 235BH, is read with A0=1.

AMS = Most significant address

AMS = A20 for SST32HF32A1

9. Both Software ID Exit operations are equivalent

10. If users never lock after programming, Sec ID can be programmed o ver the previously unprogr ammed bits (data=1) using the Sec ID

mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are from 000000H-000007H and

000010H-000017H.

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V

Transient Voltage (<20 ns) on Any Pin to Ground Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V

Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Solder Reflo w Temperature2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. VDD = VDDF and VDDS

2. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.

Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.

3. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.3V

Extended -20°C to +85°C 2.7-3.3V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF

See Figures 19 and 20

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

TABLE 6: DC OPERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V)

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Active VDD Current Address input = VILT/VIHT, at f=5 MHz,

VDD=VDD Max, all DQs open

Read OE#=VIL, WE#=VIH

Flash 18 mA BEF#=VIL, BES1#=VIH, or BES2=VIL

PSRAM 30 mA BEF#=VIH, BES1#=VIL , BES2=VIH

Concurrent Operation 40 mA BEF#=VIH, BES1#=VIL , BES2=VIH

Write1WE#=VIL

Flash 35 mA BEF#=VIL, BES1#=VIH, or BES2=VIL, OE#=VIH

PSRAM 30 mA BEF#=VIH, BES1#=VIL , BES2=VIH

ISB Standby VDD Current 110 µA VDD = VDD Max, BEF#=BES1#=VIHC, BES2=VILC

IRT Reset VDD Current 30 µA Reset=VSS±0.3V

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max

VIH Input High Voltage 0.7 VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOLF Flash Output Low Voltage 0.2 V IOL=1 00 µA, VDD=VDD Min

VOHF Flash Output High Voltage VDD-0.2 V IOH=-10 0 µA, VDD=VDD Min

VOLS PSRAM Output Low Voltage 0.4 V IOL =1 mA, VDD=VDD Min

VOHS PSRAM Output High Voltage 2.2 V IOH =-500 µA, VDD=VDD Min

T6.1 1260

1. IDD active while Erase or Program is in progress.

TABLE 7: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Erase Operation 100 µs

T7.0 1260

TABLE 8: CAPACITANCE (TA = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 12 pF

T8.0 1260

TABLE 9: FLASH RELIABILITY CHARACTERISTICS

Symbol Para meter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T9.0 1260

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Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

AC CHARACTERISTICS

TABLE 10: PSRAM READ CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TRCS Read Cycle Time 70 ns

TAAS Address Access Time 70 ns

TBES Bank Enable Access Time 70 ns

TOES Output Enable Access Time 35 ns

TBYES UBS#, LBS# Access Time 70 ns

TBLZS1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

BES# to Active Output 0 ns

TOLZS1Output Enable to Active Output 0 ns

TBYLZS1UBS#, LBS# to Active Output 0 ns

TBHZS1BES# to High-Z Output 25 ns

TOHZS1Output Disable to High-Z Output 0 25 ns

TBYHZS1UBS#, LBS# to High-Z Output 35 ns

TOHS Output Hold from Address Change 10 ns

T10.1 1260

TABLE 11: PSRAM WRITE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TWCS Write Cycle Time 70 ns

TBWS Bank Enable to End-of-Write 60 ns

TAWS Address Valid to End-of-Write 60 ns

TASTS Address Set-up Time 0 ns

TWPS Write Pulse Width 60 ns

TWRS Write Recovery Time 0 ns

TBYWS UBS#, LBS# to End-of-Wri te 60 ns

TODWS Output Disable from WE# Low 30 ns

TOEWS Output Enable from WE# High 0 ns

TDSS Data Set-up Time 30 ns

TDHS Data Hold from Write Time 0 ns

T11.1 1260

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Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

TABLE 12: FLASH READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V

Symbol Parameter Min Max Units

TRC Read Cycle Time 70 ns

TCE Chip Enable Access Time 70 ns

TAA Address Access Time 70 ns

TOE Output Enable Access Time 35 ns

TCLZ1BEF# Low to Active Output 0 ns

TOLZ1OE# Low to Active Output 0 ns

TCHZ1BEF# High to High-Z Output 20 ns

TOHZ1OE# High to High-Z Output 20 ns

TOH1Output Hol d from Address Change 0 ns

TRP1RST# Pulse Width 500 ns

TRHR1RST# High before Read 50 ns

TRY1,2 RST# Pin Low to Read Mode 20 µs

T12.1 1260

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. This parameter applies to Sector-Erase, Block-Erase and Program operations.

This parameter does not apply to Chip-Erase operations.

TABLE 13: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TBP Word-Program Time 10 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 30 ns

TCS WE# and BEF# Setup Time 0 ns

TCH WE# and BEF# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP BEF# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High 30 ns

TCPH1BEF# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 50 ms

T13.0 1260

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

FIGURE 3: PSRAM READ CYCLE TIMING DIAGRAM

DDRESSES AMSS-0

DQ15-0

UBS#, LBS#

OE#

BES1#

BES2

TRCS

TAAS

TBES

TOES

TBLZS

TOLZS

TBYES

TBYLZS TBYHZS

D ATA V ALID

TOHZS

TBHZS

TOHS

1260 F03.0

TBES

Note: AMSS = Most Significant PSRAM Address

AMSS = A19 for SST32HF32A1

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Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

FIGURE 4: PSRAM WRITE CYCLE TIMING D IAGRAM (WE# CONTROLLED)1

TAWS

DDRESSES AMSS3-0

BES1#

BES2

WE#

UBS#, LBS#

TWPS TWRS

TWCS

TASTS

TBWS

TBYWS

TODWS TOEWS

TDSS TDHS

1260 F04.

NOTE 2

DQ15-8, DQ7-0 VALID DATA IN

Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. If BES1# goes Low or BES2 goes high coincident with or after WE# goes Low, the output will remain at high impedance.

If BES1# goes High or BES2 goes low coincident with or before WE# goes High, the output will remain at high impedance.

Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.

3. AMSS = Most Significant PSRAM Address

AMSS = A19 for SST32HF32A1

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

FIGURE 5: PSRAM WRITE CYCLE TIMING D IAGRAM (UBS#, LBS# CONTROLLED)1

DDRESSES AMSS3-0

WE#

BES1#

BES2

TBWS

TAWS

TWCS

TWPS TWRS

TASTS TBYWS

DQ15-8, DQ7-0 VALID DATA IN

NOTE 2 NOTE 2

TDSS TDHS

UBS#, LBS#

1260 F05.0

Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.

3. AMSS = Most Significant PSRAM Address

AMSS = A19 for SST32HF32A1

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

FIGURE 6: FLASH READ CYCLE TIMING DIAGRAM

FIGURE 7: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

1260 F06.0

DDRESS AMS-0

DQ15-0

WE#

OE#

BEF# TCE

TRC TAA

TOE

TOLZVIH

HIGH-Z TCLZ TOH TCHZ HIGH-Z

D ATA V ALIDD ATA V ALID

TOHZ

Note: AMSF = Most Significant Flash Address

AMSF = A20 for SST32HF32A1

1260 F07.0

DDRESS AMS-0

DQ15-0

TDH

TWPH

TDS

TWP

TAH

TAS

TCH

TCS

BEF#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

XXAA XX55 XXA0 DATA

INTERNAL PROGRAM OPERATION STARTS

WORD

(ADDR/DATA)

OE#

WE#

TBP

Note: AMSF = Most Significant Flash Address

AMSF = A20 for SST32HF32A1

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence

X can be VIL or VIH, but no other value

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

FIGURE 8: BEF# CONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM

FIGURE 9: FLASH DATA# POLLING TIMING DIAGRAM

1260 F08.0

DDRESS AMS-0

DQ15-0

TDH

TCPH

TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

XXAA XX55 XXA0 DATA

INTERNAL PROGRAM OPERATION STARTS

WORD

(ADDR/DATA)

OE#

BEF#

TBP

Note: AMSF = Most Significant Flash Address

AMSF = A20 for SST32HF32A1

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence

X can be VIL or VIH, but no other value

1260 F09.0

DDRESSES AMSF-0

DQ7Data Data# Data# Data

WE#

OE#

BEF#

TOEH

TOE

TCE

TOES

Note: AMSF = Most Significant Flash Address

AMSF = A20 for SST32HF32A1

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

FIGURE 10: FLASH TOGGLE BIT TIMING DIAGRAM

FIGURE 11: WE# CONTROLLED FLASH CHIP-ERASE TIMING DIAGRAM

1260 F10.0

DDRESSES AMSF-0

DQ6 and DQ2

WE#

OE#

BEF#

TOETOEH

TCE

TOE

TWO READ CYCLES

WITH SAME OUTPUTS

Note: AMSF = Most Significant Flash Address

AMSF = A20 for SST32HF32A1

1260 F11.0

DDRESS AMS-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX10XX55XXAA XX80 XXAA

5555

OE#

BEF#

SIX-BYTE CODE FOR CHIP-ERASE

SCE

TWP

Note: AMSF = Most Significant Flash Address

AMSF = A20 for SST32HF32A1

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence

This device also supports BEF# controlled Chip-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 13)

X can be VIL or VIH, but no other value.

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

FIGURE 12: WE# CONTROLLED FLASH BLOCK-ERASE TIMING DIAGRAM

Note: AMSF = Most Significant Flash Address

AMSF = A20 for SST32HF32A1

This device also supports BEF# controlled Block-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 13.)

BAX = Block Address

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence

X can be VIL or VIH, but no other value.

1260 F12.0

DDRESS AMS-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX50XX55XXAA XX80 XXAA

BAX

OE#

BEF#

SIX-BYTE CODE FOR BLOCK-ERASE

TWP

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

FIGURE 13: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM

1260 F13.0

DDRESS AMS-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX30XX55XXAA XX80 XXAA

SAX

OE#

BEF#

SIX-BYTE CODE FOR SECTOR-ERASE

TWP

Note: AMSF = Most Significant Flash Address

AMSF = A20 for SST32HF32A1

This device also supports BEF# controlled Sector-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 13.)

SAX = Sector Address

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence

X can be VIL or VIH, but no other value.

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

FIGURE 14: SOFTWARE ID ENTRY AND READ

FIGURE 15: SOFTWARE ID EXIT AND RESET

1260 F14.0

DDRESS A14-0

TIDA

DQ15-0

WE#

SW0 SW1 SW2 MFG ID

5555 2AAA 5555 0000 0001

OE#

BEF#

THREE-WORD SEQUENCE FOR

SOFTWARE ID ENTRY

TWP

TWPH TAA

00BF

DEVICE ID

XX55XXAA XX90

Note: X can be VIL or VIH, but no other value.

Device ID - See Table 2 on page 5

1260 F15.0

DDRESS A14-0

DQ15-0

TIDA

TWP

TWHP

WE#

SW0 SW1 SW2

5555 2AAA 5555

THREE-WORD SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

BEF#

XXAA XX55 XXF0

Note: X can be VIL or VIH, but no other value.

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Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

FIGURE 16: FLASH SEC ID ENTRY

1260 F16.0

DDRESS AMSF-0

TIDA

DQ15-0

WE#

SW0 SW1 SW2

5555 2AAA 5555

OE#

BEF#

THREE-BYTE SEQUENCE FOR

SEC ID ENTRY

TWP

TWPH TAA

XX55XXAA XX88

Note: AMSF = Most Significant Flash Address

AMSF = A20 for SST32HF32A1

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

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Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

FIGURE 17: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS)

FIGURE 18: RST# TIMING DIAGRAM (DURING PROGRAM OR ERASE OPERATION)

1260 F17.0

RST#

EF#/OE#

TRP

TRHR

1260 F18.0

RST#

EF#/OE#

TRP

TRY

End-of-Write Detection

(Toggle-Bit)

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

FIGURE 19: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 20: A TEST LOAD EXAMPLE

1260 F19.0

REFERENCE POINTS OUTPUTINPUT VIT

IHT

VILT

VOT

A C test inputs are driv en at VIHT (0. 9 VDD) f or a logic “1” and VILT (0.1 VDD) f or a log ic “0”. Measurement reference points

f or inputs and outputs are VIT (0.5 VDD) and V OT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Test

VOT - VOUTPUT Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1260 F20.0

T O TESTER

O DUT

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Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

FIGURE 21: WORD-PROGRAM A LGORITHM

1260 F21.

Start

Write data: XXAAH

Address: 5555H

Write data: XX55H

Address: 2AAAH

Write data: XXA0H

Address: 5555H

Write Word

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

ote: X can be VIL or VIH, but no other valu

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Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

FIGURE 22: WAIT OPTIONS

1260 F22.0

W ait TBP,

TSCE, or TBE

Program/Erase

Initiated

Internal Timer Toggle Bit

Yes

Program/Erase

Completed

Does DQ6

match?

Read same

word

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read word

Is DQ7 =

true data?

Read DQ7

Program/Erase

Initiated

Program/Erase

Initiated

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Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

FIGURE 23: SEC ID/SOFTWARE ID COMMAND FLOWCHARTS

X can be VIL or VIH, but no other value

1260 F23.

Load data: XXAAH

Address: 5555H

Software Product ID Ent

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX90H

Address: 5555H

W ait TIDA

Read Software ID

Load data: XXAAH

Address: 5555H

Sec ID Query Entry

ommand Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX88H

Address: 5555H

W ait TIDA

Read Sec ID

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Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

FIGURE 24: SOFTWARE ID/SEC ID COMMAND FLOWCHARTS

1260 F24.0

Load data: XXAAH

Address: 5555H

Software ID Exit/Sec ID Exit

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XXF0H

Address: 5555H

Load data: XXF0H

Address: XXH

Return to normal

operation

W ait TIDA

Return to normal

operation

X can be VIL or VIH, but no other value

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Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

FIGURE 25: ERASE COMMAND SEQUENCE

1260 F25.

Load data: XXAAH

Address: 5555H

Chip-Erase

ommand Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX10H

Address: 5555H

Load data: XXAAH

Address: 5555H

W ait TSCE

Chip erased

to FFFFH

Load data: XXAAH

Address: 5555H

Sector-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX30H

Address: SAX

Load data: XXAAH

Address: 5555H

W ait TSE

Sector erased

to FFFFH

Load data: XXAAH

Address: 5555H

Block-Erase

Command Sequenc

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX50H

Address: BAX

Load data: XXAAH

Address: 5555H

W ait TBE

Block erased

to FFFFH

Note: X can be VIL or VIH, but no other value.

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

FIGURE 26: CONCURRENT OPERATION FLOWCHART

1260 F26.0

Load SDP

Command

Sequence

Concurrent

Operation

Flash

Program/Erase

Initiated

Wait for End of

Write Indication

Flash Operation

Completed

End Concurrent

Operation

Read or Write

SRAM

End

Wait

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

PRODUCT ORDERING INFORMATION

Valid combinations for SST32HF32A1

SST32HF32A1-70-4C-LS SST32HF32A1-70-4C-LFS

SST32HF32A1-70-4C-LSE SST32HF32A1-70-4C-LFSE

SST32HF32A1-70-4E-LS SST32HF32A1-70-4E-LFS

SST32HF32A1-70-4E-LSE SST32HF32A1-70-4E-LFSE

Note: Valid combination s are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine avai lability of new combinations.

Device Speed Suffix1 Suffix2

SST32HFxxxx - XXX -XX-XXX X

Environmental Attribute

E1 = non-Pb

Package Modifier

FS = 63 ball positions

S = 62 ball positions

Package Type

L = LFBGA (8mm x 10mm x 1.4mm, 0.40mm ball size)

Temperature Range

C = Commercial = 0°C to +70°C

E = Extended = -20°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

Hardware Block Protection

1 = Bottom Boot Block

PSRAM Density

A = 16 Mbit

Flash Density

32 = 32 Mbit

Voltage

H = 2.7-3.3V

Product Series

32 = MPF+ + PSRAM ComboMemory

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

PACKAGING DIAGRAMS

62-BALL L OW-PROFILE, FINE-PITCH B ALL GRID ARRAY (LFBGA) 8MM X 10MM

SST PACKAGE C ODE: LS

A1 CORNER

K J H G F E D C B A

A B C D E F G H J K

BOTTOM VIEWTOP VIEW

8.00 ± 0.20

0.40 ± 0.0

(62X)

A1 CORNER

10.00 ± 0.20

0.80

5.60

0.80

7.20

62-lfbga-LS-8x10-400mic-

ote: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.32 mm (± 0.05 mm)

1mm

SIDE VIEW

SEATING PLANE 0.32 ± 0.05

1.30 ± 0.10

0.12

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Preliminary Specifications

Multi-Purpose Flash Plus + PSRAM ComboMemory

SST32HF32A1

63-BALL L OW-PROFILE, FINE-PITCH B ALL GRID ARRAY (LFBGA) 8MM X 10MM

SST PACKAGE C ODE: LFS

TABLE 14: REVISION HISTORY

Number Description Date

00 •Initial Release Jun 2004

01 •Changed IDD test condition for frequency specification from 1/TRC Min to 5 MHz

Table 6 on page 12

•Added the so lder reflo w temp eratu re to the “Absolute Maxim um Str ess Ratings” on

page 11.

•Added RoHS compliance information on page 1 and page 33

•Changes to the “Pr odu c t Or de ring Inform ation” on page 33

– Removed all 90 ns information and associated MPNs

– Added non-Pb MPNs for all devices

– Remo ved SST32HF64A1/B1 commercial temperature devices and MPNs

– Moved SST32HF64A1/B1 extended temperature MPNs to S71299 data sheet

May 2005

A1 CORNER

K J H G F E D C B A

A B C D E F G H J K

BOTTOM VIEW

TOP VIEW

8.0 ± 0.1

0.40 ± 0.0

(63X)

A1 CORNER

10.0 ± 0.1

0.80

5.60

0.80

7.20

63-lfbga-LFS-8x10-400mic-1

ote: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size: 0.32 mm (± 0.05 mm)

1mm

SIDE VIEW

SEATING PLANE 0.32 ± 0.05

1.3 ± 0.1

0.12

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94 086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

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