NJU6356
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■TREMINAL DESCRIPTION
No. SYMBOL FUNCTION
1 I/O Input/Output Select Terminal for DATA Terminal
"H" : Input, "L" : Output
During the CE terminal is "L", the DATA terminal is high impedance.
2 XT
3 XT Quartz Cry stal Connecting Terminal (f=32.768kHz)
Refer to the line-up table for internal Cg, Cd value.
5 CE
Chip Enable Input Terminal (with Pull-down Resistance)
"H" : DATA input/output is available.
"L" : DATA terminal is high impedance.
When the CE signal is which rising edge or falling edge,
the CLK signal should be fixed to "L".
6 CLK Clock Input Terminal
The DATA input/output is synchronized this clock.
When the CE terminal is "L" the DATA terminal is high impedance.
I/O CE DATA
H H Input
L H Output
H L High Impedance
L L High Impedance
7 DATA
Serial Timer Data Input/Output Terminal
8 V
DD
Power Su pply
4 V
SS
GND
■FUNCTIONAL DESCRIPTION
1. Timer Data Structure
The NJU6356 using BCD code which consisting of 4 bits per 1 digit. The calender function including the last
date of each month and the leap year calculation is executed automatically. The unused bit for the timer data is
“0”.
Timer Data Bit Map
MSB LSB Range
Second 0 S6 S5 S4 S3 S2 S1 S0 0 to 59
Minute 0 m6 m5 m4 m3 m2 m1 m0 0 to 59
Hour 0 0 H5 H4 H3 H2 H1 H0 0 to 23
Days of Week 0 W2W1W0 1 to 7
Day 0 0 D5D4D3D2D1D0 1 to 31
Month 0 0 0 M4 M3 M2 M1 M0 1 to 12
Year Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 0 to 99
NJU6356
-3-
2. Timer Data Reading
W hen the I/O termianl is "L" and th e CE tarminal is "H", timer data ca n r e ad ou t. The outp ut is LS B f irs t and the
output data strings is shown below.
The timer data is transferred from timer counter to shift register at rising edge of the chip enable on the CE
terminal, and output the LSB of the timer data from the DATA terminal.
Afterward the timer data in the shift register shift by synchronized at the falling edge of clock signal on the CLK
terminal and output from the DATA terminal.
If the timer data is updated in the data output, there are one second difference between timer data and output
data.
Type E
Year Month Day Days of
Week Hour Minute Second
The data is read out from LSB of Year, and first 52-bit is effective.
If the lo w vo ltage detec tor detect the lo w battery, (E E)
H
is wri tten into each digit of tim er data and r ead o ut. T he
code of (EE)
H
is a warning for the broken.
< Read Out Timing >
Year Second
CLK
CE
I/O
Data
Output
Shift
Register
(1) (2) The time r data is transf erred to the shift register at ri sing edge of the CE (1)
and LSB of the timer data is output to the DATA terminal. Afterward the
timer data in the shift register shift by synchronized at falling edge of the
CLK (2) th en outp ut to t he DATA term ina l time-to-time.
1 2
3
4 5 6 7 3 4 5
6
7
0
1 2
3
4 5 6 7 3 4 5
6
7
0
Note) When the CE signal is which rising edge or falling edge,
the CLK signal should be fixed to “L”. And so, before t he
CE signal is raised, the I/O signal should be fixed to “L”.
NJU6356
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3. Timer Data Writing
When both of the I/O terminal and the CE terminal are "H", update is stopped, the oscillator divider is cleared,
and the timer data can be wri tten to the NJU6356.
The timer data is written into the shift register from the DATA terminal by synchronized with rising edge of the
clock signal input from the CLK terminal, and the data is transferred from the shift register to the timer counter by
synchronized with falling edge of the CE signal. In thi s time the s econd-counter is c leared to "0", and the oscillator
divider start the operation.
The input data strings are LSB first of each digit as shown below.
Type E
Year Month Day Days of
Week Hour Minute Second
The data is read out from LSB of Year, and last 44-b it is effective.
< Write Down Timing >
4. Low Vo ltage Detector
The NJU6356 series incorporate the low battery detector. If the supply voltage reduce to the detection level,
(EE)
H
is writte n into each digit of the shift register as warning c ode for the CPU.
5. Data Access
The NJU6356 s eries can o perate f rom 2.0V t o 5 .5V. However, it is n ot al low the data ac ces s out of th e ra nge of
5V±10%. It may be broken the data unles s 5V±10%.
Thus, wh en the data ac cess, the CE terminal shoul d be "H " after the po wer s upp ly rise to 5V±10%, the n start the
operation.
CLK
CE
I/O
The data is input into the shift
register at rising edge of the
CLK.
The data in the shift register is
transf erred to the tim er counter at this
falling edge of the CE, then the
oscill ator divi de r sta rt t he o peration.
Year
1 2
3
4 5 6 7 3 4 5
6
7
0
1
2
3
4 5 6 70
3 4 5
6
7
Minute
Data
Input
Shift
Register
Note) When the CE signal is which rising edge or falling edge,
the CLK si gnal s houl d be fixed to "L". And so, before the
CE signal is raised, the I/O signal should be fixed to "H".
NJU6356
- 6 -
■
APPLICATION CIRCUIT
t
CS
t
DS
t
CH
t
DH
CLK
CE
I/O
(out)
t
WDS
80%
t
WDH
tr
CLK
Input D ata
tf
Vss
Vss
20%
80%
20%
t
CWL
80%
t
CWH
CLK
O utput Data
20% 50%
20%
50%
80%
20%
50%
t
RDD
XT XT
CE
CLK
I/O
DATA
V
DD
V
SS
NJU6356
V
DD
CPU
Main Power
Supply
t
CS
t
DS
t
CH
t
DH
CLK
CE
I/O
(in)
[CAUTION]
The specifications on thi s data book are only
given for information , without any guarantee
as regards either mistakes or omissions.
The application circuits in this data book are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
