HUF76121P3, HUF76121S3S Data Sheet 47A, 30V, 0.021 Ohm, N-Channel, Logic Level UltraFET Power MOSFETs These N-Channel power MOSFETs are manufactured using the innovative UltraFETTM process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable and battery-operated products. January 2003 Features * Logic Level Gate Drive * 47A, 30V * Ultra Low On-Resistance, rDS(ON) = 0.021 * Temperature Compensating PSPICE(R) Model * Temperature Compensating SABER(c) Model * Thermal Impedance SPICE Model * Thermal Impedance SABER Model * Peak Current vs Pulse Width Curve * UIS Rating Curve Formerly developmental type TA76121. * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards" Ordering Information Symbol PART NUMBER PACKAGE BRAND HUF76121P3 TO-220AB 76121P HUF76121S3S TO-263AB 76121S D G NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-263AB variant in tape and reel, e.g., HUF76121S3ST. S Packaging JEDEC TO-220AB JEDEC TO-263AB SOURCE DRAIN GATE DRAIN (FLANGE) GATE DRAIN (FLANGE) SOURCE (c)2003 Fairchild Semiconductor Corporation HUF76121P3, HUF76121S3S Rev. C1 HUF76121P3, HUF76121S3S Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified UNITS Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 30 V Drain to Gate Voltage (R GS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 30 V Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS 20 V Drain Current Continuous (TC = 25oC, VGS = 10V) (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM 47 25 24 Figure 4 A A A Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Figures 6, 17,18 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 0.6 W W/oC Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -40 to 150 oC Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300 260 oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TA = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 30 - - V - - 1 A - - 250 A VGS = 20V - - 100 nA OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current BVDSS IDSS ID = 250A, VGS = 0V (Figure 12) VDS = 25V, VGS = 0V VDS = 25V, VGS = 0V, TC Gate to Source Leakage Current IGSS = 150oC ON STATE SPECIFICATIONS Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250A (Figure 11) 1 - 3 V Drain to Source On Resistance rDS(ON) ID = 47A, VGS = 10V (Figures 9, 10) - 0.015 0.021 ID = 25A, VGS = 5V (Figure 9) - 0.019 0.028 ID = 24A, VGS = 4.5V (Figure 9) - 0.021 0.031 THERMAL SPECIFICATIONS Thermal Resistance Junction to Case R JC (Figure 3) - - 1.66 oC/W Thermal Resistance Junction to Ambient RJA TO-220 and TO-263 - - 62 oC/W VDD = 15V, ID 24A, RL = 0.63, VGS = 4.5V, RGS = 10.0 (Figures 15, 21, 22) - - 265 ns - 15 - ns tr - 160 - ns td(OFF) - 14 - ns tf - 31 - ns tOFF - - 70 ns SWITCHING SPECIFICATIONS (VGS = 4.5V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time (c)2003 Fairchild Semiconductor Corporation tON td(ON) HUF76121P3, HUF76121S3S Rev. C1 HUF76121P3, HUF76121S3S Electrical Specifications TA = 25oC, Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - - 80 ns - 6 - ns tr - 47 - ns td(OFF) - 47 - ns tf - 42 - ns tOFF - - 135 ns - 24 30 nC - 13 16 nC - 1.0 1.2 nC SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time tON Turn-On Delay Time td(ON) Rise Time Turn-Off Delay Time Fall Time Turn-Off Time VDD = 15V, ID 47A, RL = 0.32, VGS = 10V, RGS = 12.5 (Figures 16, 21, 22) GATE CHARGE SPECIFICATIONS Total Gate Charge Qg(TOT) Gate Charge at 5V Qg(5) Threshold Gate Charge Qg(TH) VGS = 0V to 10V VDD = 15V, ID 25A, RL = 0.6 VGS = 0V to 5V Ig(REF) = 1.0mA (Figures 14, 19, 20) VGS = 0V to 1V Gate to Source Gate Charge Qgs - 2.50 - nC Gate to Drain "Miller" Charge Qgd - 7.80 - nC - 850 - pF CAPACITANCE SPECIFICATIONS Input Capacitance CISS Output Capacitance COSS - 465 - pF Reverse Transfer Capacitance CRSS - 100 - pF MIN TYP MAX UNITS ISD = 25A - - 1.25 V trr ISD = 25A, dISD/dt = 100A/s - - 65 ns QRR ISD = 25A, dISD/dt = 100A/s - - 100 nC VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage VSD Reverse Recovery Time Reverse Recovered Charge TEST CONDITIONS Typical Performance Curves 50 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 0.2 0 40 VGS = 10V 30 VGS = 4.5V 20 10 0 0 25 50 75 100 125 TA , AMBIENT TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE (c)2003 Fairchild Semiconductor Corporation 150 25 50 75 100 125 150 TC, CASE TEMPERATURE (oC) FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE HUF76121P3, HUF76121S3S Rev. C1 HUF76121P3, HUF76121S3S Typical Performance Curves (Continued) 2 ZJC, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC SINGLE PULSE 0.01 10-5 10 -4 10-3 10-2 10 -1 10 0 101 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE I DM, PEAK CURRENT (A) 1000 TC = 25oC VGS = 10V FOR TEMPERATURES ABOVE 25 oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 150 - TC 125 VGS = 5V 100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 40 10 -5 10-4 10 -3 10-2 10 -1 100 101 t, PULSE WIDTH (s) FIGURE 4. PEAK CURRENT CAPABILITY 500 TJ = MAX RATED TC = 25oC 100 I AS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 1000 100s 1ms 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10ms If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 100 STARTING TJ = 25oC 10 STARTING TJ = 150oC BVDSS MAX = 30V 1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 1 0.001 0.01 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100 NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 5. FORWARD BIAS SAFE OPERATING AREA (c)2003 Fairchild Semiconductor Corporation FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY HUF76121P3, HUF76121S3S Rev. C1 HUF76121P3, HUF76121S3S Typical Performance Curves (Continued) 100 100 VGS = 10V VGS = 5V -40oC 80 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 25 oC 150oC 60 40 20 VGS = 4.5V 80 VGS = 4V 60 VGS = 3.5V 40 VGS = 3V 20 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 0 0 0 1 2 3 4 0 5 1 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 7. TRANSFER CHARACTERISTICS PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) ID = 47A 35 ID = 28A 30 25 20 ID = 15A 15 1.6 4 5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 47A 1.4 1.2 1.0 0.8 10 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) -60 10 0 60 120 180 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. SOURCE TO DRAIN ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1.2 1.0 0.8 0.6 -60 0 60 120 180 TJ, JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE (c)2003 Fairchild Semiconductor Corporation NORMALIZED DRAIN TO SOURCE BREAKOWN VOLTAGE 1.2 VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE 3 FIGURE 8. SATURATION CHARACTERISTICS NORMALIZED DRAIN TO SOURCE ON RESISTANCE 40 2 VDS, DRAIN TO SOURCE VOLTAGE (V) ID = 250A 1.1 1.0 0.9 -60.0 0.0 60.0 120 180 TJ , JUNCTION TEMPERATURE (oC) FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE HUF76121P3, HUF76121S3S Rev. C1 HUF76121P3, HUF76121S3S 1200 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS C DS + CGD CISS C, CAPACITANCE (pF) (Continued) 900 COSS 600 300 CRSS 10 VGS , GATE TO SOURCE VOLTAGE (V) Typical Performance Curves 8 6 4 WAVEFORMS IN DESCENDING ORDER: I D = 47A I D = 28A I D = 15A 2 VDD = 15V 0 0 0 5 10 15 20 25 VDS , DRAIN TO SOURCE VOLTAGE (V) 0 30 5 10 15 Qg, GATE CHARGE (nC) 20 25 NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 500 200 VGS = 10V, VDD = 15V, ID = 47A, RL = 0.32 400 SWITCHING TIME (ns) SWITCHING TIME (ns) VGS = 4.5V, VDD = 15V, ID = 24A, RL = 0.63 tr 300 200 td(OFF) tf td(OFF) 150 tf 100 tr 50 100 td(ON) td(ON) 0 0 0 10 20 30 40 0 50 RGS, GATE TO SOURCE RESISTANCE () 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE () FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS tP + RG VDS IAS VDD VDD - VGS DUT 0V tP IAS 0 0.01 tAV FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT (c)2003 Fairchild Semiconductor Corporation FIGURE 18. UNCLAMPED ENERGY WAVEFORMS HUF76121P3, HUF76121S3S Rev. C1 HUF76121P3, HUF76121S3S Test Circuits and Waveforms (Continued) VDS VDD RL Qg(TOT) VDS VGS = 10V VGS Qg(5) + - VDD VGS = 5V VGS DUT VGS = 1V Ig(REF) 0 Qg(TH) IgREF) 0 FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS VDS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + VGS - VDD 10% 0 10% DUT RGS VGS 90% VGS 0 FIGURE 21. SWITCHING TIME TEST CIRCUIT (c)2003 Fairchild Semiconductor Corporation 10% 50% 50% PULSE WIDTH FIGURE 22. SWITCHING TIME WAVEFORM HUF76121P3, HUF76121S3S Rev. C1 HUF76121P3, HUF76121S3S PSPICE Electrical Model .SUBCKT HUF76121 2 1 3 ; rev March 1998 CA 12 8 1.2e-9 CB 15 14 1.23e-9 CIN 6 8 7.6e-10 LDRAIN DPLCAP DRAIN 2 5 10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD ESLC 11 - EBREAK 11 7 17 18 33.4 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE GATE 1 + 50 - LDRAIN 2 5 1e-9 LGATE 1 9 3.57e-9 LSOURCE 3 7 4.25e-9 EVTEMP RGATE + 18 22 9 20 21 EBREAK 17 18 DBODY - 16 MWEAK 6 MMED MSTRO RLGATE LSOURCE CIN 8 SOURCE 3 7 RSOURCE MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RLSOURCE S1A 12 RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 2.5e-3 RGATE 9 20 4 RLDRAIN 2 5 10 RLGATE 1 9 35.7 RLSOURCE 3 7 42.5 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 10e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B DBREAK + RSLC2 5 51 IT 8 17 1 RLDRAIN RSLC1 51 S2A 13 8 14 13 S1B CA RBREAK 15 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 - - IT 14 + + VBAT 5 8 EDS - + 8 22 RVTHRES 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*181),4))} .MODEL DBODYMOD D (IS = 4e-13 RS = 6.3e-3 TRS1 = 1e-3 TRS2 = 3e-6 CJO = 1.33e-9 TT = 2.8e-8 M = 0.4 XTI = 4.3 N = 0.95 IKF = 5) .MODEL DBREAKMOD D (RS = 1.05e-1 TRS1 = 0 TRS2 = 2.5e-5) .MODEL DPLCAPMOD D (CJO = 7.8e-10 IS = 1e-30 N = 10 M = 0.63) .MODEL MMEDMOD NMOS (VTO = 1.8 KP = 3.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 4) .MODEL MSTROMOD NMOS (VTO = 2.08 KP = 65 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.54 KP = 0.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 40 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 9.7e-4 TC2 = 7e-7) .MODEL RDRAINMOD RES (TC1 = 1.6e-2 TC2 = 4e-5) .MODEL RSLCMOD RES (TC1 = 5e-3 TC2 = 8e-6) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC = -1.7e-3 TC2 = -4e-6) .MODEL RVTEMPMOD RES (TC1 = -1.2e-3 TC2 = 1e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -5 VOFF= -3) VON = -3 VOFF= -5) VON = -0.5 VOFF= 2) VON = 2 VOFF= -0.5) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. (c)2003 Fairchild Semiconductor Corporation HUF76121P3, HUF76121S3S Rev. C1 HUF76121P3, HUF76121S3S SABER Electrical Model REV March 1998 template huf76121 n2, n1, n3 electrical n2, n1, n3 { var i iscl d..model dbodymod = (is = 4e-13, xti = 4.3, cjo = 1.33e-9, tt = 2.8e-8, n = 0.95, m = 0.4) d..model dbreakmod = () d..model dplcapmod = (cjo = 7.8e-10, is = 1e-30, n = 10, m = 0.63) m..model mmedmod = (type=_n, vto = 1.8, kp = 3.5, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.08, kp = 65, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.54, kp = 0.1, is = 1e-30, tox = 1) DPLCAP sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5, voff = -3) 10 sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3, voff = -5) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 2) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 2, voff = -0.5) DRAIN 2 RLDRAIN RSLC1 51 RDBREAK RSLC2 c.ca n12 n8 = 1.2e-9 c.cb n15 n14 = 1.23e-9 c.cin n6 n8 = 7.6e-10 72 ISCL RDRAIN 6 8 ESG EVTHRES + 19 8 + i.it n8 n17 = 1 LGATE GATE 1 EVTEMP RGATE + 18 22 9 20 21 MWEAK DBODY EBREAK + 17 18 MMED MSTRO RLGATE res.rbreak n17 n18 = 1, tc1 = 9.7e-4, tc2 = 7e-7 res.rdbody n71 n5 = 6.3e-3, tc1 = 1e-3, tc2 = 3e-6 res.rdbreak n72 n5 = 1.05e-1, tc1 = 0, tc2 = 2.5e-5 res.rdrain n50 n16 = 2.5e-3, tc1 = 1.6e-2, tc2 = 4e-5 res.rgate n9 n20 = 4 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 35.7 res.rlsource n3 n7 = 42.5 res.rslc1 n5 n51 = 1e-6, tc1 = 5e-3, tc2 = 8e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 10e-3, tc1 = 0, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -1.2e-3, tc2 = 1e-6 res.rvthres n22 n8 = 1, tc1 = -1.7e-3, tc2 = -4e-6 71 11 16 6 CIN m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u RDBODY DBREAK 50 - d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 3.57e-9 l.lsource n3 n7 = 4.25e-9 LDRAIN 5 - 8 LSOURCE SOURCE 3 7 RSOURCE RLSOURCE S1A 12 S2A 13 8 14 13 S1B CA RBREAK 15 17 18 RVTEMP S2B 13 CB 6 8 - - IT 14 + + EGS 19 VBAT 5 8 EDS - + 8 22 RVTHRES spe.ebreak n11 n7 n17 n18 = 33.4 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc = 1 equations { i (n51->n50) + = iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/181))** 4)) } } (c)2003 Fairchild Semiconductor Corporation HUF76121P3, HUF76121S3S Rev. C1 HUF76121P3, HUF76121S3S SPICE Thermal Model th JUNCTION REV March 1998 HUF76121 CTHERM1 th 6 1.1e-3 CTHERM2 6 5 2.9e-3 CTHERM3 5 4 3.2e-3 CTHERM4 4 3 1.5e-2 CTHERM5 3 2 3.9e-1 CTHERM6 2 tl 2.2 RTHERM1 RTHERM1 th 6 1.0e-4 RTHERM2 6 5 2.0e-3 RTHERM3 5 4 3.4e-1 RTHERM4 4 3 4.6e-1 RTHERM5 3 2 1.8e-1 RTHERM6 2 tl 7.0e-2 RTHERM2 CTHERM1 6 CTHERM2 5 RTHERM3 CTHERM3 SABER Thermal Model Saber thermal model HUF76121 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 1.1e-3 ctherm.ctherm2 6 5 = 2.9e-3 ctherm.ctherm3 5 4 = 3.2e-3 ctherm.ctherm4 4 3 = 1.5e-2 ctherm.ctherm5 3 2 = 3.9e-1 ctherm.ctherm6 2 tl = 2.2 rtherm.rtherm1 th 6 = 1.0e-4 rtherm.rtherm2 6 5 = 2.0e-3 rtherm.rtherm3 5 4 = 3.4e-1 rtherm.rtherm4 4 3 = 4.6e-1 rtherm.rtherm5 3 2 = 1.8e-1 rtherm.rtherm6 2 tl = 7.0e-2 } 4 RTHERM4 CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl (c)2003 Fairchild Semiconductor Corporation CASE HUF76121P3, HUF76121S3S Rev. C1 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM FACTTM ActiveArrayTM FACT Quiet SeriesTM BottomlessTM FAST(R) CoolFETTM FASTrTM CROSSVOLTTM FRFETTM DOMETM GlobalOptoisolatorTM EcoSPARKTM GTOTM E2CMOSTM HiSeCTM I2CTM EnSignaTM Across the board. Around the world.TM The Power FranchiseTM Programmable Active DroopTM ImpliedDisconnectTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC(R) OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench(R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SILENT SWITCHER(R) SMART STARTTM SPMTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic(R) TruTranslationTM UHCTM UltraFET(R) VCXTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I2