81 GHz to 86 GHz, E-Band Power Amplifier
With Power Detector
Data Sheet HMC8142
Rev. A Document Feedback
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FEATURES
Gain: 21 dB typical
Output power for 1 dB compression (P1dB): 25 dBm typical
Saturated output power (PSAT): 26 dBm typical
Output third-order intercept (OIP3): 29 dBm typical
Input return loss: 12 dB typical
Output return loss: 8 dB typical
DC supply: 4 V at 450 mA
No external matching required
Die size: 3.039 mm × 1.999 mm × 0.05 mm
APPLICATIONS
E-band communication systems
High capacity wireless backhaul radio systems
Test and measurement
GENERAL DESCRIPTION
The HMC8142 is an integrated E-band gallium arsenide (GaAs),
pseudomorphic high electron mobility transistor (pHEMT),
monolithic microwave integrated circuit (MMIC), medium power
amplifier with a temperature compensated on-chip power detector
that operates from 81 GHz to 86 GHz. The HMC8142 provides
21 dB of gain, 25 dBm of output power at 1 dB compression,
29 dBm of output third-order intercept, and 26 dBm of saturated
output power at 20% power added efficiency (PAE) from a 4 V
power supply. The HMC8142 exhibits excellent linearity and is opti-
mized for E-band communications and high capacity wireless
backhaul radio systems. The amplifier configuration and high gain
make it an excellent candidate for last stage signal amplification
before the antenna. All data is taken with the chip in a 50 Ω test
fixture connected via a 3 mil wide × 0. 5 mil thick × 7 mil long
ribbon on each port.
FUNCTIONAL BLOCK DIAGRAM
48
5
24 22 20 18 16 15
911710
6
3
1
25 23 21 19
213
17
12
14
V
DD1
V
DD2
RFIN
V
GG1
V
GG2
V
GG3
RFOUT
V
DD3
V
DD4
V
GG4
V
REF
V
DET
HMC8142
13425-001
Figure 1.
HMC8142 Data Sheet
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Interface Schematics..................................................................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 12
Applications Information .............................................................. 13
Typical Application Circuit ....................................................... 13
Assembly Diagram ..................................................................... 14
Mounting and Bonding Techniques for Millimeterwave
GaAs MMICs .................................................................................. 15
Handling Precautions ................................................................ 15
Mounting ..................................................................................... 15
Wire Bonding .............................................................................. 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
2/16—Revision A: Initial Version
Data Sheet HMC8142
Rev. A | Page 3 of 16
SPECIFICATIONS
TA = 25°C, VDDx = 4 V, IDD = 450 mA, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit
OPERATING CONDITIONS
Radio Frequency (RF) Range 81 86 GHz
PERFORMANCE
Gain 19 21 dB
Gain Variation over Temperature 0.02 dB/°C
Output Power for 1 dB Compression (P1dB) 22.5 25 dBm
Saturated Output Power (PSAT ) 26 dBm
Output Third-Order Intercept (OIP3) at Maximum Gain1 29 dBm
Input Return Loss
12
dB
Output Return Loss 8 dB
POWER SUPPLY
Total Supply Current (IDD)2 450 mA
1 Data taken at output power (POUT) = 12 dBm/tone, 1 MHz spacing.
2 Adjust VGGx from −2 V to 0 V to achieve the total drain current, IDD = 450 mA.
HMC8142 Data Sheet
Rev. A | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Drain Bias Voltage (VDD1 to VDD4) 4.5 V
Gate Bias Voltage (VGG1 to VGG4) −3 V to 0 V
Maximum Junction Temperature (to
Maintain 1 Million Hours Mean Time to
Failure (MTTF))
175°C
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −55°C to +85°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Table 3. Thermal Resistance
Package Type θJC1 Unit
25-Pad Bare Die [CHIP] 48.33 °C/W
1 Based on ABLETHERM® 2600BT as die attach epoxy with thermal
conductivity of 20 W/mK.
ESD CAUTION
Data Sheet HMC8142
Rev. A | Page 5 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
4 8
5
24 22 20 18 16 15
911710
6
3
1
25 23 21 19
213
17
12
14
V
DD1
GND GND GND GND
V
DD2
RFIN
V
GG1
V
GG2
V
GG3
RFOUT
V
DD3
V
DD4
V
GG4
V
REF
V
DET
GND
GND
GND GND GNDGND GND
GND
GND
HMC8142
TOP VIEW
(Not to Scale)
13425-002
Figure 2. Pad Configuration
Table 4. Pad Function Descriptions
Pad No. Mnemonic Description
1, 3, 4, 6, 8, 10, 12, 14,
17, 19, 21, 23, 25
GND Ground Connection (See Figure 3).
2 RFIN RF Input. AC couple RFIN and match it to 50 Ω (See Figure 4).
5, 7, 9, 11 VDD1 to VDD4 Drain Bias Voltage for the Power Amplifier (See Figure 5).
13 RFOUT RF Output. AC couple RFOUT and match it to 50 Ω (see Figure 6).
15 VDET Detector Voltage for the Power Detector (See Figure 7). VDET is the dc voltage representing the RF
output power rectified by the diode, which is biased through an external resistor. Refer to the
typical application circuit for the required external components (see Figure 40).
16 VREF Reference Voltage for the Power Detector (See Figure 7). VREF is the dc bias of diode biased through
an external resistor used for the temperature compensation of VDET. Refer to the typical application
circuit for the required external components (see Figure 40).
18, 20, 22, 24 VGG4 to VGG1 Gate Bias Voltage for the Power Amplifier (See Figure 8). Refer to the typical application circuit for
the required external components (see Figure 40).
Die Bottom GND Ground. The die bottom must be connected to the RF/dc ground (see Figure 3).
HMC8142 Data Sheet
Rev. A | Page 6 of 16
INTERFACE SCHEMATICS
G
ND
13425-003
Figure 3. GND Interface
RFIN
13425-004
Figure 4. RFIN Interface
V
DD1 TO VDD4
13425-005
Figure 5. VDD1 to VDD4 Interface
RFOUT
13425-006
Figure 6. RFOUT Interface
V
REF
, V
DET
13425-007
Figure 7. VDET, VREF Interface
V
GG4
TO V
GG1
13425-008
Figure 8. VGG4 to VGG1 Interface
Data Sheet HMC8142
Rev. A | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
30
25
20
15
10
5
0
–5
–10
–15
–2079 80 81 82 83 84 85 86 87 88
RESPONSE (dB)
FRE Q UE NCY ( GHz)
GAIN
INPUT RETURN L OSS
OUTPUT RE TURN L OSS
13425-009
Figure 9. Broadband Gain and Return Loss Response vs. Frequency,
Drain Current (IDD) = 450 mA
25
24
23
22
21
20
19
18
17
16
15
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
GAI N (dB)
FRE Q UE NCY ( GHz)
I
DD
= 350mA
I
DD
= 400mA
I
DD
= 450mA
13425-010
Figure 10. Gain vs. Frequency at Various Drain Currents (IDD)
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RET URN LOS S ( dB)
FRE Q UE NCY ( GHz)
T
A
= +85°C
T
A
= +25°C
T
A
= –55° C
13425-011
Figure 11. Output Return Loss vs. Frequency at Various Temperatures,
Drain Current (IDD) = 450 mA
25
24
23
22
21
20
19
18
17
16
15
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
GAI N (dB)
FRE Q UE NCY ( GHz)
T
A
= +85°C
T
A
= +25°C
T
A
= –55° C
13425-012
Figure 12. Gain vs. Frequency at Various Temperatures,
Drain Current (IDD) = 450 mA
–5
–7
–9
–11
–13
–15
–17
–19
–21
–23
–25
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
RET URN LOS S ( dB)
FRE Q UE NCY ( GHz)
T
A
= +85°C
T
A
= +25°C
T
A
= –55° C
13425-013
Figure 13. Input Return Loss vs. Frequency at Various Temperatures,
Drain Current (IDD) = 450 mA
–44
–46
–48
–50
–52
–54
–56
–58
–60
–62
–64
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
ISOLATION (dB)
FRE Q UE NCY ( GHz)
T
A
= +85°C
T
A
= +25°C
T
A
= –55° C
13425-014
Figure 14. Reverse Isolation vs. Frequency at Various Temperatures,
Drain Current (IDD) = 450 mA
HMC8142 Data Sheet
Rev. A | Page 8 of 16
30
29
28
27
26
25
24
23
22
21
20
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
P1d B ( dBm)
FRE Q UE NCY ( GHz)
T
A
= +85°C
T
A
= +25°C
T
A
= –55° C
13425-015
Figure 15. Output P1dB vs. Frequency at Various Temperatures,
Drain Current (IDD) = 450 mA
30
29
28
27
26
25
24
23
22
21
20
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
P
SAT
(d Bm)
FRE Q UE NCY ( GHz)
T
A
= +85°C
T
A
= +25°C
T
A
= –55° C
13425-016
Figure 16. PSAT vs. Frequency at Various Temperatures,
Drain Current (IDD) = 450 mA
35
34
33
32
31
30
29
28
27
26
25
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
IP3 (dBm)
FRE Q UE NCY ( GHz)
T
A
= +85°C
T
A
= +25°C
T
A
= –55° C
13425-017
Figure 17. Output IP3 vs. Frequency at Various Temperatures,
Drain Current (IDD) = 450 mA, POUT/Tone = 12 dBm
30
29
28
27
26
25
24
23
22
21
20
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
P1d B ( dBm)
FRE Q UE NCY ( GHz)
I
DD
= 350mA
I
DD
= 400mA
I
DD
= 450mA
13425-018
Figure 18. Output P1dB vs. Frequency at Various Drain Currents (IDD)
30
29
28
27
26
25
24
23
22
21
20
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
P
SAT
(d Bm)
FRE Q UE NCY ( GHz)
I
DD
= 350mA
I
DD
= 400mA
I
DD
= 450mA
13425-019
Figure 19. PSAT vs. Frequency at Various Drain Currents (IDD)
35
34
33
32
31
30
29
28
27
26
25
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
IP3 (dBm)
FRE Q UE NCY ( GHz)
I
DD
= 350mA
I
DD
= 400mA
I
DD
= 450mA
13425-020
Figure 20. Output IP3 vs. Frequency at Various Drain Currents (IDD),
POUT/Tone = 12 dBm
Data Sheet HMC8142
Rev. A | Page 9 of 16
35
34
33
32
31
30
29
28
27
26
25
81.0 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0
IP3 (dBm)
FRE Q UE NCY ( GHz)
12dBm
14dBm
16dBm
13425-021
Figure 21. Output IP3 vs. Frequency at Various POUT/Tones,
Drain Current (IDD) = 450 mA
8 9 10 11 12 13 14 15 16
POUT/TONE (dBm)
35
34
33
32
31
30
29
28
27
26
25
IP3 (dBm)
IDD = 350mA
IDD = 400mA
IDD = 450mA
13425-022
Figure 22. Output IP3 vs. POUT/Tone at Various Drain Currents (IDD)
at RF = 83.5 GHz
350 400 450
I
DD
(mA)
30
29
28
27
26
25
24
23
22
21
20
GAI N (dB) , P1dB (d Bm) , P
SAT
(d Bm)
GAI N (dB)
P1d B ( dBm)
P
SAT
(dBm)
13425-023
Figure 23. Gain, Output P1dB, and PSAT vs. Drain Current (IDD)
at RF = 81 GHz
8 9 10 11 12 13 14 15 16
POUT/TONE (dBm)
35
34
33
32
31
30
29
28
27
26
25
IP3 (dBm)
IDD = 350mA
IDD = 400mA
IDD = 450mA
13425-024
Figure 24. Output IP3 vs. POUT/Tone at Various Drain Currents (IDD)
at RF = 81 GHz
8 9 10 11 12 13 14 15 16
P
OUT
/TONE (dBm)
35
34
33
32
31
30
29
28
27
26
25
IP3 (dBm)
I
DD
= 350mA
I
DD
= 400mA
I
DD
= 450mA
13425-025
Figure 25. Output IP3 vs. POUT/Tone at Various Drain Currents (IDD)
at RF = 86 GHz
350 400 450
I
DD
(mA)
30
29
28
27
26
25
24
23
22
21
20
GAI N (dB) , P1dB (d Bm) , P
SAT
(d Bm)
GAI N (dB)
P1d B ( dBm)
P
SAT
(dBm)
13425-026
Figure 26. Gain, Output P1dB, and PSAT vs. Drain Current (IDD)
at RF = 83.5 GHz
HMC8142 Data Sheet
Rev. A | Page 10 of 16
350 400 450
IDD ( mA)
30
29
28
27
26
25
24
23
22
21
20
GAI N (dB) , P1dB (d Bm) , PSAT ( dBm)
GAI N (dB)
P1d B ( dBm)
PSAT (dBm)
13425-027
Figure 27. Gain, Output P1dB, and PSAT vs. Drain Current (IDD)
at RF = 86 GHz
28
24
20
16
12
8
4
0
–15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11
P
OUT
(dBm), GAIN ( dB), PAE ( %)
INPUT POWE R ( dBm)
580
560
540
520
500
480
460
440
P
OUT
GAIN
PAE
I
DD
I
DD
(mA)
13425-028
Figure 28. POUT, Gain, PAE, and IDD vs. Input Power at RF = 83.5 GHz,
Drain Current (IDD) = 450 mA
28
24
20
16
12
8
4
0
–15 –13 –11 –9 –7 –5 –3 –1 1357911
P
OUT
(dBm), GAIN ( dB), PAE ( %)
INPUT POWE R ( dBm)
560
530
500
470
440
410
380
350
P
OUT
GAIN
PAE
I
DD
I
DD
(mA)
13425-029
Figure 29. POUT, Gain, PAE, and IDD vs. Input Power at RF = 81 GHz,
Drain Current (IDD) = 350 mA
28
24
20
16
12
8
4
0
–15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11
P
OUT
(dBm), GAIN ( dB), PAE ( %)
INPUT POWE R ( dBm)
P
OUT
GAIN
PAE
I
DD
580
560
540
520
500
480
460
440
I
DD
(mA)
13425-030
Figure 30. POUT, Gain, PAE, and IDD vs. Input Power at RF = 81 GHz,
Drain Current (IDD) = 450 mA
28
24
20
16
12
8
4
0
–15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11
P
OUT
(dBm), GAIN ( dB), PAE ( %)
INPUT POWE R ( dBm)
P
OUT
GAIN
PAE
I
DD
580
560
540
520
500
480
460
440
I
DD
(mA)
13425-031
Figure 31. POUT, Gain, PAE, and IDD vs. Input Power at RF = 86 GHz,
Drain Current (IDD) = 450 mA
28
24
20
16
12
8
4
0
–15 –13 –11 –9 –7 –5 –3 –1 1357911
P
OUT
(dBm), GAIN ( dB), PAE ( %)
INPUT POWE R ( dBm)
P
OUT
GAIN
PAE
I
DD
560
530
500
470
440
410
380
350
I
DD
(mA)
13425-032
Figure 32. POUT, Gain, PAE, and IDD vs. Input Power at RF = 83.5 GHz,
Drain Current (IDD) = 350 mA
Data Sheet HMC8142
Rev. A | Page 11 of 16
28
24
20
16
12
8
4
0
–15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11
P
OUT
(dBm), GAIN ( dB), PAE ( %)
INPUT POWE R ( dBm)
560
530
500
470
440
410
380
350
P
OUT
GAIN
PAE
I
DD
I
DD
(mA)
13425-033
Figure 33. POUT, Gain, PAE, and IDD vs. Input Power at RF = 86 GHz,
Drain Current (IDD) = 350 mA
3.0
2.5
2.0
1.5
1.0
0.5
0
–15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7
POWER DISSIPATI O N (W)
INPUT POW E R ( dBm)
81GHz
82GHz
83GHz
84GHz
85GHz
86GHz
13425-034
Figure 34. Power Dissipation vs. Input Power at Various Frequencies,
Drain Current (IDD) = 450 mA, TA = 85°C
10
1
0.1
0.01
–16 –11 –6 –1 4 9 14 19 24 29
OUTPUT VOLTAGE (V)
OUTPUT P OW E R ( dBm)
T
A
= +85°C
T
A
= +25°C
T
A
= –55° C
13425-035
Figure 35. Detector Output Voltage (VOUT) vs. Output Power at Various
Temperatures, Drain Current (IDD) = 450 mA, RF = 81 GHz
50
45
40
35
30
25
20 8 9 10 11 12 13 14 15 16
IM D3 ( dBc)
POUT/TONE (dBm)
81GHz
82GHz
83GHz
84GHz
85GHz
86GHz
13425-036
Figure 36. Output IMD3 vs. POUT/Tone at Various Frequencies,
Drain Current (IDD) = 450 mA
3.0
2.5
2.0
1.5
1.0
0.5
0
–15 –13 –11 –9 –7 –5 –3 –1 13 5 7
POWER DISSIPATI O N (W)
INPUT POW E R ( dBm)
81GHz
82GHz
83GHz
84GHz
85GHz
86GHz
13425-037
Figure 37. Power Dissipation vs. Input Power at Various Frequencies,
Drain Current (IDD) = 350 mA, TA = 85°C
10
1
0.1
0.01
–16 –11 –6 –1 4 9 14 19 24 29
OUTPUT VOLTAGE (V)
OUTPUT P OW E R ( dBm)
T
A
= +85°C
T
A
= +25°C
T
A
= –55° C
13425-038
Figure 38. Detector Output Voltage (VOUT) vs. Output Power at Various
Temperatures, Drain Current (IDD) = 450 mA, RF = 86 GHz
HMC8142 Data Sheet
Rev. A | Page 12 of 16
THEORY OF OPERATION
The architecture of the HMC8142 power amplifier is shown in
Figure 39. The HMC8142 uses four cascaded gain stages to form an
amplifier with a combined gain of 21 dB and saturated output
power (PSAT) of 26 dBm. At the output of the last stage, a coupler
taps off a small portion of the output signal. The coupled signal
is presented to an on-chip diode detector for external monitoring of
the output power. A matched reference diode is included to help
correct for detector temperature dependencies. See the application
circuit shown in Figure 40 for further details on biasing the
different blocks and using the detector features.
13425-043
VREF VDET
RFOUT
RFIN
Figure 39. Power Amplifier Circuit Architecture
Data Sheet HMC8142
Rev. A | Page 13 of 16
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
A typical application circuit for the HMC8142 is shown in
Figure 40. Combine supply lines as shown in the application
circuit schematic to minimize external component count and
simplify power supply routing.
The HMC8142 uses several amplifier, detector, and attenuator
stages. All stages use depletion mode pHEMT transistors. It is
important to follow the following power-up bias sequence to
ensure transistor damage does not occur.
1. Apply a −2 V bias to the VGG1 to VGG4 pads.
2. Apply 4 V to the VDD1 to VDD4 pads.
3. Adjust VGG1 to VGG4 between −2 V and 0 V to achieve a
total amplifier drain current of 450 mA.
To power dow n t he HMC8142, follow the procedure in reverse.
For additional guidance on general bias sequencing, see the
MMIC Amplifier Biasing Procedure application note.
4 6 8 10
5 7 911
12
13
14
3
1
2
25 222324 21 181920 151617
V
DD1
,
V
DD2
, V
DD3
, V
DD4
V
GG1
, V
GG2
, V
GG3
, V
GG4
V
OUT
= V
REF
– V
DET
V
DD1
V
GG1
V
GG2
V
GG3
V
GG4
V
REF
V
DET
V
DD2
V
DD3
V
DD4
120pF
RFIN RFIN RFOUT RFOUT
120pF 120pF 120pF
4.7µF 0.01µF
120pF 120pF 120pF 120pF +5V +5V
–5V
4.7µF 0.01µF
100kΩ100kΩ
10kΩ
10kΩ
SUGGESTED INTERFACE CIRCUIT
10kΩ
10kΩ
13425-040
Figure 40. Typical Application Circuit
HMC8142 Data Sheet
Rev. A | Page 14 of 16
ASSEMBLY DIAGRAM
1
2
3
14
13
12
4769811105
25 222324 21 181920 17 1516
120pF 120pF120pF120pF
120pF 120pF120pF120pF
0.01µF
0.01µF
4.7µF
50Ω TRANSMISSION LINE
3
MIL WIDE GOLD RIBBON
(WEDGE BOND)
3 MIL WIDE GOLD RIBBON
(WEDGE BOND)
6 MIL NOMINAL GAP
4.7µF
13425-041
Figure 41. Assembly Diagram
Data Sheet HMC8142
Rev. A | Page 15 of 16
MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GAAS MMICS
Attach the die directly to the ground plane eutectically or with
conductive epoxy.
To bring RF to and from the chip, use 50 Ω microstrip trans-
mission lines on 0.127 mm (5 mil) thick alumina thin film
substrates (see Figure 42).
RF GROUND P LANE
0.05mm ( 0.002") T HICK GaAs MMI C
RIBBO N BOND
0.127mm ( 0. 005") THI CK ALUMI NA
THIN FILM SUBSTRATE
0.076mm
(0.003")
13425-042
Figure 42. Routing RF Signals
To minimize bond wire length, place microstrip substrates as
close to the die as possible. The typical die to substrate spacing
is 0.076 mm to 0.152 mm (3 mil to 6 mil).
HANDLING PRECAUTIONS
To avoid permanent damage, adhere to the precautions in the
following sections.
Storage
All bare die ship in either waffle or gel-based ESD protective
containers, sealed in an ESD protective bag. After opening the
sealed ESD protective bag, all die must be stored in a dry
nitrogen environment.
Cleanliness
Handle the chips in a clean environment. Never use liquid
cleaning systems to clean the chip.
Static Sensitivity
Follow ESD precautions to protect against ESD strikes.
Transients
Suppress instrument and bias supply transients while bias is
applied. To minimize inductive pickup, use shielded signal and
bias cables.
General Handling
Handle the chip on the edges only using a vacuum collet or with
a sharp pair of bent tweezers. Because the surface of the chip
has fragile air bridges, never touch the surface of the chip with a
vacuum collet, tweezers, or fingers.
MOUNTING
The chip is back metallized and can be die mounted with gold/tin
(AuSn) eutectic preforms or with electrically conductive epoxy.
The mounting surface must be clean and flat.
Eutectic Die Attach
It is best to use an 80% gold/20% tin preform with a work
surface temperature of 255°C and a tool temperature of 265°C.
When hot 90% nitrogen/10% hydrogen gas is applied, maintain
tool tip temperature at 290°C. Do not expose the chip to a
temperature greater than 320°C for more than 20 sec. No more
than 3 sec of scrubbing is required for attachment.
Epoxy Die Attach
ABLETHERM 2600BT is recommended for die attachment.
Apply a minimum amount of epoxy to the mounting surface so
that a thin epoxy fillet is observed around the perimeter of the
chip after placing it into position. Cure the epoxy per the schedule
provided by the manufacturer.
WIRE BONDING
RF bonds made with 3 mil × 0.5 mil gold ribbon are recom-
mended for the RF ports. These bonds must be thermosonically
bonded with a force of 40 g to 60 g. DC bonds of 1 mil
(0.025 mm) diameter, thermosonically bonded, are recommended.
Create ball bonds with a force of 40 g to 50 g and wedge bonds
with a force of 18 g to 22 g. Create all bonds with a nominal
stage temperature of 150°C. Apply a minimum amount of
ultrasonic energy to achieve reliable bonds. Keep all bonds as
short as possible, less than 12 mil (0.31 mm).
HMC8142 Data Sheet
Rev. A | Page 16 of 16
OUTLINE DIMENSIONS
07-15-2015-A
0.191
0.014
0.114
0.106
0.09
0.003 TOP VIEW
(CIRCUIT SIDE)
SIDE VIEW
0.05
1.999
3.039
810 11
12
13
14
151617
18192021
22232425
1
3
2
45679
0.764
0.764
0.130
0.130
0.168
0.089
0.600
0.600 0.2000.2000.2000.200
0.200
0.200 0.200 0.200 0.200 0.200
0.600 0.200 0.2000.200
0.600
Figure 43. 25-Pad Bare Die [CHIP]
(C-25-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option2
HMC8142 −55°C to +85°C 25-Pad Bare Die [CHIP] C-25-2
HMC8142-SX −55°C to +85°C 25-Pad Bare Die [CHIP] C-25-2
1 The HMC8142-SX consists of two pairs of the die in a gel pack for sample orders.
2 This is a waffle pack option; contact Analog Devices, Inc., sales representatives for additional packaging options.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13425-0-2/16(A)
